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2013International Conference on Compound Semiconductor Manufacturing Technology

May 13th - 16th, 2013Register Online atwww.csmantech.org

Hilton New Orleans Riverside New Orleans, Louisiana, USA

http://www.csmantech.org/

CONFERENCE AT A GLANCESUNDAY, May 12th5:00 PM – 8:00 PM REGISTRATION

3rd Floor Registration

MONDAY, May 13th 7:00 AM – 7.00 PM REGISTRATION

3rd Floor Registration Counters

7:00 AM – 8:30 AM BREAKFAST FOR WORKSHOPS

Belle Chase8:50 AM – 5:00 PM CS MANTECH WORKSHOPS

Jefferson8:15 AM – 4:45 PM ROCS WORKSHOP

Versailles12:00 PM –1:00 PM LUNCHEON FOR

WORKSHOPSBelle Chase

6:00 PM – 9:00 PM EXHIBITS RECEPTIONHilton Exhibition Center

TUESDAY, May 14th7:00 AM – 5:00 PM REGISTRATION 3rd Floor Registration

Counters7:00 AM – 8:30 AM Continental Breakfast

Hilton Exhibition Center8:00 AM – 8:30 AM OPENING CEREMONIES

Jefferson8:30 AM – 10:10 AM SESSION 1: Plenary I

Jefferson10:00 AM – 5:30 PM EXHIBITS OPEN

Hilton Exhibition Center10:10 AM –10:40 AM BREAK Hilton Exhibition Center10:40 AM –12:00 PM SESSION 2: Plenary II

Jefferson

12:00 PM – 1:20 PM EXHIBITS LUNCH Hilton Exhibition Center

1:20 PM – 3:00 PM SESSION 3: Optoelectronic Technology

Jefferson3:00 PM – 3:30 PM BREAK Hilton Exhibition Center3:30 PM – 4:50 PM SESSION 4a: Process -

BacksideJefferson

3:30 PM – 4:50 PM SESSION 4b: Process - Lithography

Napoleon

2 2013 Intl. Conf. Compound Semicond. Manuf. Technol.

4:50 PM – 5:10 PM EXHIBITORS FORUM RECEPTION

Hilton Exhibition Center

TUESDAY, May 14th5:10 PM – 6:40 PM EXHIBITORS’ FORUMS

Rosedown/Elmwood/Magnolia5:10 PM – 6:40 PM STUDENT FORUM Belle Chase7:00 PM –10:00 PM INTERNATIONAL RECEPTION Steamboat Natchez

WEDNESDAY, May 15th 7:00 AM – 5:00 PM REGISTRATION

3rd Floor Registration Counters

7:00 AM – 8:30 AM EXHIBITS BREAKFAST Hilton Exhibition Center7:00 AM – 10:30 AM EXHIBITS OPEN

Hilton Exhibition Center8:00 AM – 9:50 AM SESSION 5a: RF GaN

ProducibilityJefferson

8:00 AM – 9:50 AM SESSION 5b: Epitaxy & Materials

Napoleon9:50 AM – 10:20 AM BREAK

Hilton Exhibition Center10:20 AM – 12:00 PM SESSION 6a: GaN Process,

Device & CircuitsJefferson

10:20 AM – 12:00 PM SESSION 6b: Manufacturing, Test & Characterization

Napoleon

12:00 PM – 1:30 PM OPEN LUNCH BREAK

1:30 PM – 3:20 PM SESSION 7a: Thermal Design I

Jefferson1:30 PM – 3:20 PM SESSION 7b:

Traps & TransientsNapoleon

3:20 PM – 3:40 PM BREAKCourt Assembly

3:40 PM – 5:20 PM SESSION 8a: Thermal Design II

Jefferson3:40 PM – 5:20 PM SESSION 8b: Process – Metal

Napoleon5:20 PM – 5:50 PM RUMP SESSION RECEPTION

Court Assembly5:50 PM – 6:50 PM RUMP SESSIONS A-D Belle Chase, Elmwood,

Oak Alley, Rosedown


7:00 PM – 9:00 PM SEMI Standards Meeting Melrose

THURSDAY, May 16th7:00 AM – 9:30 AM REGISTRATION 3rd Floor Registration

Counters7:00 AM – 8:30 AM CONTINENTAL BREAKFAST

Court Assembly8:00 AM – 9:50 AM SESSION 9a:

WBG Power DevicesJefferson

8:00 AM – 9:50 AM SESSION 9b: LED Outlook and Technology

Napoleon9:50 AM –10:10 AM BREAK

Court Assembly

10:10 AM –11:50 AM SESSION 10a: Materials – GaN Epi

Jefferson10:10 AM –11:50 AM SESSION 10b:

Process – IntegrationNapoleon

11:50 AM – 1:10 PM CS MANTECH LuncheonHilton Exhibition Center A

1:10 PM – 3:00 PM SESSION 11a: GaN Gate Dielectrics

Jefferson1:10 PM – 3:00 PM SESSION 11b:

Yield Enhancement and Manufacturing

Napoleon3:00 PM – 4:00 PM POSTER SESSION

Breezeway4:00 PM – 4:30 PM CLOSING RECEPTION

Breezeway

MESSAGE FROM THE CONFERENCE CHAIR:

Sharing Ideas Throughout the Industry!

And where else would one rather share their ideas and technical advances than in one of the world’s most fascinating cities, New Orleans! On behalf of 2013 CS ManTech conference Technical Program Committee and Executive Committee, I invite you to partake and discuss the future of compound semiconductor manufacturing. On May 13 - 16, CS professionals from all over the world


will gather at the Riverside Hotel to share ideas with new and old acquaintances. This will be our 27th year and our third conference in the entertaining city of New Orleans.

After a flat year in 2012, will the forecasts show a much healthier growth in handsets and power amplifiers in 2013? If the financial cliff continues to loom, how will the CS industries survive? Which CS technology or CS sector will thrive in 2013? These are some of the questions and concerns that CS ManTech will be addressing. The opening session leads off with a focus on understanding the GaAs market, hearing CS Industry leaders share their perspectives on the status of the CS business in 2013. Throughout the week, there will be presentations on a broad array of technologies and application, including photonics, optoelectronics, LEDs, and power devices, along with special sessions devoted to to all aspects of volume manufacturing with GaAs, GaN, SiC, and other compound semiconductors.

This is THE annual event where our industry comes together. CS ManTech’s mission has always been to foster communication between participants from academia, industry, and government. We are quite famous for our love of social networking events and this year will be no exception. These gatherings start with the Exhibitor’s Reception on Monday evening; include a Steamboat Cruise for the International Reception Tuesday night; return with the always popular (and often lively) Rump sessions on Wednesday; and finally wrap things up with the Closing Reception on Thursday. These informal gatherings are perfect for catching up with old friends and making new ones, as well as networking with colleagues from all over the world. Our technical sessions will offer the most current state of the art in device technology, reliability, processing and materials across the broad compound semiconductor industry. This is sure to be a conference to remember, so please make plans to share your ideas and become part of THE event. I hope to see you there!

Karen RenaldoNorthrop Grumman (ES)Chair, 2013 CS ManTech Conference


2013 CONFERENCE SPONSORS(Partial list as of February 15, 2013)

CS ManTech is an independent not-for-profit organization whose mission is to promote technical discussion and scientific education in the compound semiconductor manufacturing industry. The continued success of the conference is enabled by donations from corporate sponsors. The 2013 CS ManTech Conference Committee gratefully acknowledges the support from our sponsors.

Platinum Sponsors:Materion CorporationPlasma-Therm LLC

RF Micro DevicesSkyworks Solutions, Inc.

WIN Semiconductor

Gold Sponsors:Accel-RF AXT

Brewer Science FreibergerHitachi Cable MAX IEG

TriQuint Semiconductor Virginia Diode

Silver Sponsors:AIXTRON SE

Northrop Grumman ESM/A-COM Technology Solutions

2012 CONFERENCE SPONSORSWe would again like to thank our 2012 sponsors!

Platinum Sponsors:AIXTRON SE Plasma-Therm LLC

RFMD Skyworks Solutions, Inc.Sumitomo Electric

Gold Sponsors:AXT Booz Allen Hamilton

Hitachi Cable KopinTriQuint Semiconductor VEM

WIN Semiconductor Corp.

Silver Sponsors:Accel-RF Brewer Science

Cree FreibergerNorthrop Grumman OEM Group

Veeco


2013 CONFERENCE HIGHLIGHTS

The 2013 CS ManTech program begins on Monday, May 13th with a series of tutorial workshops. This year’s program, organized by Russ Kremer of Freiberger Compound Materials USA, is one of the most exciting and practical for our industry that we’ve offered in many years! It will focus on various aspects of the ubiquitous handset power amplifier. Throughout the workshop, the noted speakers will examine the many factors that are important to business and engineering aspects of the PA industry, including the customer motivation, the design, and major manufacturing processes that yield a finished, packaged die. Participants will now finally understand the overall picture of why we do what we do.

CS ManTech is again fortunate to host the internationally-acclaimed ROCS (Reliability of Compound Semiconductors) Workshop which will be held on the opening day (Monday 5/13). The 28th ROCS Workshop will provide an agenda that is packed with industry, government and university professionals and comprise the latest results of all phases of Compound Semiconductor Reliability (see http://www.jedec.org/home/gaas/ for details). This meeting is sponsored by the JEDEC JC-14.7 Committee on GaAs Reliability and Quality Standards and the EIA.

Festivities of the conference kick off on Monday evening with the traditional Exhibits Reception. By Monday evening, most of the attendees will have arrived and the exhibits space will be open. The CS ManTech exhibits are an excellent opportunity to view suppliers of materials, services and tools from around the globe. This is a great time to renew old relationships and establish new ones while getting your first taste of New Orleans cuisine, great food and drinks.

The CS ManTech Conference formally opens on Tuesday morning with a brief overview of the conference and the awards presentation for the best papers from the 2012 conference and our most loyal sponsors. This is immediately followed by the two Opening Sessions of invited speakers which will cover overviews of the GaAs Industry and Photonics IC Industry from prominent CEOs and companies within the United States, Canada, Taiwan and Europe.

For lunch on Tuesday we welcome all our guests to the Exhibits Hall. Afterwards, we’ll return to a 3rd very prominent session of invited talks on manufacturing and technology advances in the optoelectronics industry. We expand the program at this stage to two parallel sessions on important manufacturing topics covering backside processes and photolithography.


http://www.jedec.org/home/gaas/

The Tuesday technical session will conclude with both the Exhibitors’ Forum and Student Forum. The student forum provides an opportunity for students to explore career options through networking and interactions with members of the CS community in academia, industry, and government laboratories. Later on Tuesday evening, conference attendees and guests will join together in the spirit of Mark Twain, William Faulkner, Bob Dylan, John Fogerty, Louis Armstrong and many other storytellers on the “Mighty Mississipp’.” We will hold the CS ManTech International Reception on the Steamboat NATCHEZ with food, music, camaraderie and a view of the better side of New Orleans.

The sessions on Wednesday morning will start early with breakfast in the Exhibition Center where attendees and vendors can continue to foster new relationships. The technical sessions start promptly thereafter in order to accommodate a full schedule of world-class technical topics. The two parallel sessions of Wednesday morning focus on extremely important topics like manufacturing, materials, process and test. Wednesday lunch will be open to explore the many opportunities for fine local fare in the French Quarter within walking distance from the hotel. The Wednesday afternoon sessions are particularly special, hosting TWO sessions that address modern advances in thermal design for high-power devices, a session on all things temporal and the all-important session on metals.

Wednesday evening brings the highly-anticipated Rump Sessions where deliberation and debate stir the soul of any ManTech attendee! We eat, drink and argue our case in the atmosphere of healthy competition. Attendees may join any or all of the four parallel topics, where moderators will encourage informal, lively, and highly-interactive discussions.

We continue the excellent series of technical sessions on Thursday morning. Two parallel sessions will encompass optoelectronics, wide-bandgap power devices, III-nitride epitaxy and advances in process integration. The Thursday lunch will allow you to combine the taste of excellent food with networking and discussions around the table. Thursday afternoon will include our closing two sessions on yield enhancement in parallel with advanced gate dielectrics for GaN devices. A new format for the Interactive Forum will be introduced in 2013 where traditional poster papers will be presented. This poster session includes papers that were accepted especially for interactive presentation. Attendees will have the opportunity to meet with authors to discuss their papers in detail. Attendees of the Interactive Forum will vote for the best poster, and the winning author will receive the Best Poster Award.

The celebratory Conference Closing Reception will follow the Poster Session and signifies a reemergence of


a favorite conference-closing contest – The Ugly Picture Contest. Our closing reception will also feature a drawing for a valuable prize. All those who complete and submit their Feedback Forms will have a chance to win!

CS MANTECH WORKSHOP

Every year, CS ManTech offers a Monday Workshop, in conjunction with the Technical Program. The topics for these workshops have varied widely, but always are of relevance to the compound semiconductor industry. Recent Workshops have focused on Green Energy involving compound semiconductors, the manufacturing processes used to move from process to product, and an overview of compound semiconductor device processing. These workshop talks are presented by leaders in our community.

This year, the Workshop will single out one particular device, the power amplifier, at least one of which goes into every mobile phone. We will examine the motivation behind the PA, its design, and carefully study each major manufacturing process along the way to a finished, packaged die.

The Workshop will begin with a presentation by James Eastham from TriQuint Semiconductor discussing how mobile phones work, and the various standards that are currently in use. While it is clear how a call to a land line reaches its intended destination, it is much less clear how a call to a mobile number can find the correct handset, no matter where in the world that handset may be at the moment. In addition, all calls use only a limited bandwidth of frequencies. James will also describe the multiplexing schemes that allow multiple calls to utilize the same frequency.

The second talk will be by Pete Zampardi, from RF Micro Devices. Pete will discuss the process whereby a device manufacturer takes a specification from a handset manufacturer, and converts that into a design for a power amplifier that is both technically compliant with the spec and manufacturable in a cost-effective manner. To accomplish this in a finite time frame, extensive simulation must be done, using standard models for the parameters and processes involved. Only after the modeling indicates that the design is close to optimum, can actual building of the circuits begin.

The first step in producing an HBT power amp is to grow the epitaxial layer structure necessary. Wayne Johnson, from IQE KC, will describe how the specification from a device manufacturer gets translated into a specific stack of epi layers. Layer thickness, dopant type and concentration, and interfaces between layers must all be carefully considered. And, of course, each layer must be thoroughly tested and characterized.


Wayne's presentation will describe both the design and testing of the epi wafer.

After the epi wafer is produced, the process moves back to the device manufacturer. Will Snodgrass from Avago Technologies will discuss the processes necessary to convert the epi wafer into first, and HBT, and second, into a power amplifier. Material must be etched away, and metal and dielectrics deposited, and in a very precise manner. Will's presentation will discuss the details of these processes, and describe the evaluation and testing that must happen at each step of the way. And, as with all other processes, high yields and low costs must be maintained.

The final presentation will be by Dean Monthei from TriQuint Semiconductor. Dean's talk will describe how the finished amplifier must be packaged. The packaging will not only protect the power amp, but will also determine how it interfaces with the other components of the handset. Since there are many different ways to package semiconductor devices, it is critical to select the best one to optimize both performance and cost.

2013 ROCS WORKSHOP

Reliability of Compound Semiconductors

Monday, May 13th, 2013Hilton Riverside HotelRoom: Versailles8:15 a.m. - 4:45 p.m.

The 28th annual ROCS Workshop - formerly known as the GaAs Rel Workshop - will be held in conjunction with the CS ManTech Conference on Monday May 13th, 2013, at the Hilton Riverside Hotel, New Orleans, LA. This meeting is sponsored by the JEDEC JC-14.7 Committee on GaAs Reliability and Quality Standards and the EIA.

The ROCS Workshop brings together researchers, manufacturers and users of compound semiconductor materials, devices and circuits. Papers presenting latest results, including work-in-progress and new developments in all aspects of compound semiconductor reliability will be presented. Potential authors are invited to submit an electronic copy of a one to two page comprehensive summary, suitable for a 15 minute presentation, to: Peter Ersland, [email protected], (978)-656-2817. The deadline for receipt of submissions is February 25th, 2013; late papers of significant interest may be considered up to the date of the Workshop. The Advanced Program will be published at http://www.jedec.org/home/gaas/ approximately one month prior to the meeting.

Advance registration for the workshop is $100 for students, $200 for JEDEC members, and $225 for non-


members; on-site registration is $250. Registration includes a full day of ROCS presentations, two breaks, a luncheon and a copy of the Proceedings. Late registration will be available starting at 7:30 a.m. on the morning of the workshop. For further information or to register on-line (through April 29, 2013), visit our web site at http://www.jedec.org/home/gaas/, or contact: Peter Ersland, Workshop Technical Program Chair, M/A-COM Technology Solutions, 100 Chelmsford Street, Lowell, MA 01851, (978) 656-2817, [email protected].

INTERNATIONAL RECEPTION

Join us for a fun-filled evening aboard the Steamboat NATCHEZ, the last authentic steamboat cruising in New Orleans.

She’s the ninth steamer to bear the name NATCHEZ. It was her predecessor, NATCHEZ VI, that raced the ROBERT E. LEE in the most famous steamboat race of all time. True to tradition in every detail, boarding the NATCHEZ makes you feel as if you have entered another era. The captain barks his orders through an old-time hand-held megaphone. The calliope trills a melody into the air while the great wheel, 25 tons of white oak, churns the heavy waters of the Mississippi. Her powerful antique steam engines were built in 1925 and are still on view today from the engine room.

Drinks and a New Orleans-style dinner will be served accompanied by live local music. As always, this reception provides an excellent opportunity to meander around to renew old acquaintances and make new ones in a unique social setting. Come aboard and enjoy New Orleans hospitality….. Steamboat Style!

CS ManTech extends an invitation to family and friends that may be accompanying you at the Conference to join us at this special event Tuesday night. Guest tickets are $50 each. We strongly encourage you to purchase guest tickets at the time of your registration to ensure space at the reception.

INDUSTRY EXHIBITS

The Industry Exhibits at CS ManTech offer participating companies a unique opportunity to reach out and interact with representatives from across the compound semiconductor industry with a real interest in exhibitor offerings. The Exhibits at CS ManTech are a forum for companies to showcase their products and services for the compound semiconductor community. This provides excellent visibility to a wide range of CS-focused participants from around the globe and offers a good return on investment.


mailto:[email protected]

The Exhibits will kick off on Monday evening with the Exhibits Reception. Food and drinks will be served in the Exhibits Hall, where friends, colleagues, suppliers, and even competitors will gather to catch up on the first full evening of the conference. The Exhibits Reception is an excellent occasion for networking and a chance to meet and greet the assembling conference attendees.

On Tuesday there are a number of opportunities for exhibitors to interact with attendees starting with a continental Breakfast in the Exhibits Hall at 7:00 am. Extended coffee breaks between technical sessions and a buffet-style Exhibits Lunch will also both be served in the Exhibits Hall. Following the technical sessions on Tuesday, exhibitors will give short presentations introducing or highlighting new products in the popular Exhibitors’ Forum.

The Exhibits will open again on Wednesday morning with a continental breakfast at 7:00 am. The Wednesday morning session provides an ideal opportunity for both conference attendees and participating Exhibitors to follow up on interest generated earlier, both in the technical program and at the Exhibitors’ Forum.

Several factors make exhibiting at CS ManTech attractive. A combination of practical technical sessions and workshops draws representatives from across the compound semiconductor industry. The exhibits are integral to the conference with several events, including the Exhibits Reception, Lunch, and Coffee Breaks hosted in the exhibition hall. These events provide extended opportunities for exhibitors to interact with conference attendees to seek out new customers, maintain person-to-person rapport with existing customers, and advance public relations with the compound semiconductor industry in general.

Exhibitor information and on-line registration can be found on the Exhibitor Link on the CS ManTech website (http://csmantech.org/exhibitors/exhibitors.html). Please remember to sign up for the Exhibitors’ Forum if interested. Exhibitor Forum slots are on a first-come-first-served basis and the number of slots are limited!

For any questions related to Exhibiting at CS ManTech, please contact the 2013 Exhibits Chair, David Via, 937.307.7445, [email protected].



2013 EXHIBITORS LIST(Partial list as of February 15, 2013)

Accel-RF Instruments Corp.AIXTRON SECS MagazineAXT, INC.

Brewer Science, Inc.Cree Inc.

CS CLEAN SYSTEMSEpiWorks, Inc.

Evans Analytical GroupEVATEC NA

Freiberger USAHUETTINGER Electronic, Inc.

Insaco, IncIQE

JST Manufacturing, Inc.KITEC microelectronic technologie

GmbHKLA-Tencor

MicroChem CorpMomentive

Oxford InstrumentsPlasma-ThermProton Onsite

PVA TePla America Inc.RIBER INC

SAES Pure GasSAMCO

Semiconductor TodayShin-Etsu MicroSi

Soitec USASolid State Equipment LLC

SPTS TechnologiesSumika Electronic Materials, Inc.Vacuum Engineering & Materials

Virginia Diodes Inc.Visual Photonics Epitaxy Co., Ltd

Wafer World Inc.YOLE DEVELOPPEMENT


Special Thanks to our 2012 Exhibitors!

Accel-RFAIXTRON SE

AXT, INCBrewer Science, Inc

BridgestoneCentrotherm Thermal Solutions

China Crystal TechnologiesCompound Semiconductor

Compugraphics-PhotomasksCree, Inc.

CS Clean Systems, Inc.Dow Electronic Materials

EpiWorks, IncEvans Analytical Group

EvatecFerrotec USA Corp

Freiberger Compound MaterialsHitachi Cable, Ltd

INNOViONInsaco, Inc.

Intelligent Epitaxy TechnologyIQE

JST ManufacturingKITEC Microelectronic Technology

KLA-TencorKopin Corporation

Lehighton ElectronicsMaterion CorporationMersen Midland Inc

MicroChem CorpMomentive Performance Materials

Nanotronics ImagingOxford Instruments

Plasma-ThermPower + Energy, Inc

Proton OnSitePVA TePla America, Inc

SAFC HitechSAMCO Inc

Semiconductor TodayShin-Etsu MicroSi

Sigma TechSoitec

SPTS TechnologiesSumika Electronic MaterialsVacuum Barrier Corporation

VeecoVirginia Diodes Inc

Visual photonics Epitaxy Co. LtdWafer World Inc

WBG Materials, A Division of II-VI IncYole Developpement


2012 BEST PAPER AWARDS

CS ManTech tradition is to formally recognize the authors of the best paper and best student paper of the previous conference, as determined from the conference attendee votes tallied from your feedback forms. These awards will be presented during the conference introductions on Tuesday, May 14th.

The conference Best Paper Award is named in honor of Dr. He Bong Kim, the founder of the International Conference on Compound Semiconductor Manufacturing Technology. The He Bong Kim award winner for the 2012 Conference is:

Improving Front Side Process Uniformity by Back-Side MetallizationKezia Cheng, Skyworks Solutions, Inc.

The Best Student Paper for the 2011 Conference, for which the principal student author will receive a special cash award of $1000, is:

Impact of step edges on trapping behavior in N-polar GaN HEMTsNicole Killat1, Michael J. Uren1, Seshadri Kolluri2, Stacia Keller2, Umesh K. Mishra2, and Martin Kuball1, 1University of Bristol, 2University of Santa Barbara California

The committee also wishes to award a Best Student – Honorable Mention where the principal student author will receive a special cash award of $500:

Non-Linearity Characterization of Submicron Type-I InP/InGaAs/InP and Type-I/II AlInP/GaAsSb/InP DHBTsHuiming Xu, Eric Iverson, K.Y. (Donald) Cheng, Mark Stuenkel and Milton Feng, University of Illinois at Urbana-Champaign

Congratulations to these award winning teams for their excellent presentation and technical contribution to our field.

SEMI STANDARDS MEETING

The SEMI Standards meeting is scheduled for Wednesday, May 15th, from 7:00 pm to 9:00 pm (immediately following the Rump Sessions. The SEMI Compound Semiconductor (GaAs, InP and SiC) Committee invites CS ManTech Conference attendees interested in the development of internationally approved


standards for wafer specifications to attend this meeting. Topics being addressed are GaAs, InP, and SiC dimensions/orientations and electrical properties, epitaxial layer specifications (which properties should be specified, and how they are to be verified), and non-destructive test methods.

Based in San Jose, CA, SEMI is an international trade association serving more than 2,400 companies participating in the semiconductor and flat panel display equipment and materials markets. SEMI maintains offices in Brussels, Moscow, Tokyo, Seoul, Hsinchu, Beijing, Singapore, Austin, Boston and Washington, DC. For additional information, please contact co-chairs James Oliver of Northrop Grumman at 410-765-0117 or [email protected]; or Russ Kremer of Freiberger Compound Materials at 937-291-2899 or [email protected]; or SEMI Standards contact Paul Trio at 408-943-6900 or [email protected].

UGLY PICTURE CONTEST

After a brief break, and back by popular demand, CS ManTech is reintroducing the ugly photo contest! Bring in your ugly photos from daily work, please leave the old aunt Gertrude polaroids at home. We are an equal opportunity contest; bring the wafer map plots, FIB cross-sections, reliability failures, yield loss analysis, experiments gone awry, you name it - we’ll judge it. Don’t be shy, we all have them saved on our computer or pinned to the wall, just print something out and tack it up on the board we will provide, please just select one entry per person.

So get creative and post your photos for judging! As reward for participating, we will award an ugliest photo prize that will definitely be worth your trouble.

CONFERENCE CLOSING RECEPTION

The Conference Closing Reception will bring the 2013 edition of CS ManTech to an end. It will immediately follow the Poster Session. Drinks and snacks will be provided to foster a congenial final opportunity to exchange business cards, ideas, and experiences.

Returning this year is a Feedback Form Raffle. Your opinion on the Feedback Form is very valuable to the CS ManTech committees in structuring the conference and programs year-to-year and in choosing the best paper awards. This year, when you turn in your Feedback Form you enter a raffle for a prize. It’s as simple as that! The drawing will be held at the Conference Closing Reception, though you need not be present to win. In addition, votes






will be tallied and the Best Poster presentation and best Ugly Picture award winners will be announced.


2013 EXECUTIVE COMMITTEEConference Chair

Karen Renaldo*, Northrop Grumman ES

Board of Directors ChairCelicia Della-Morrow*, TriQuint Semiconductor

SecretaryScott Davis*, Sumitomo Electric

TreasurerChris Santana*, IQE North Carolina

Technical Program ChairScott Sheppard, Cree, Inc.

Publication ChairDrew Hanser, Veeco Instruments, Inc.

Local Arrangements ChairPaul Cooke*, IQE RF

Exhibits ChairDave Via, Air Force Research Laboratory

Workshop ChairRuss Kremer, Freiberger Compound Materials USA

Publicity ChairThorsten Saeger, TriQuint Semiconductor

Sponsorship ChairAndy Souzis, II-VI

Local Arrangements Vice-ChairAlex Smith, Brewer Science

International LiaisonsEurope: Andreas Eisenbach, IQE plc

Asia: Chang-Hwang Hua, WIN Semiconductors Corp

Registration ChairsSharon Woodruff, Northrop Grumman ESTravis Abshere, TriQuint Semiconductor

Web ChairMike Sun, Skyworks Solutions,

Inc.

University LiaisonPatrick Fay, University of

Notre Dame

International Reception Chair

Kevin Stevens, Kopin Corporation

Information ChairPeter Ersland, M/A-COM

Technology Solutions

Budget Event ChairGeorge Henry, Northrop

Grumman ES

Audio Visual ChairRuediger Schreiner, AIXTRON

SE

Committee MembersMike Barsky*, Northrop Grumman ASMarty Brophy*, Avago Technologies

Mariam Sadaka*, Soitec USA

Executive Advisory BoardSteve Mahon*, Cascade Microtech

Scott Davis*, Sumitomo ElectricYohei Otoki*, Hitachi Cable Ltd.

Chairman EmeritusHe Bong Kim, GaAstronics

* Member, Board of Directors


TECHNICAL PROGRAM COMMITTEEJon Abrokwah, Avago TechnologiesKamal Alavi, Raytheon Hani Badawi, AXT Inc.Zaher Bardai, IMN.Epiphany.comJohn Blevins, AFRL/RYDKarlheinz Bock, Fraunhofer Institute Michelle Bourke, Oxford Instruments Plasma TechnologyJeff Brown, RFMDShawn Burnham, HRL LaboritoriesArnold Chen, AurrionMike Clausen, The Centre for Process InnovationSuzanne Combe, TriQuint SemiconductorJim Crites, CobhamMonte Drinkwine, CobhamStefan Eichler, Freiberger Compound Materials GmbHMilton Feng, University of IllinoisCharlie Fields, AgilentPat Fowler, ManufacturingAllen Hanson, M/A-COM Technology SolutionsQuesnell Hartmann, EpiWorksGeorge Henry, Northrop Grumman ESShelia Hurtt, TriQuint SemiconductorMing-Yih Kao, TriQuint SemiconductorHidetoshi Kawasaki, SonyGene KoharaRussell Kremer, Freiberger Compound Materials GmbHJudy Kronwasser, NOVASiCMartin Kuball, University of BristolBarbara Landini, Sumika Electronic MaterialsChun-Lim Lau, Booz Allen HamiltonAmy Liu, IQE Inc.Tom Low, Agilent TechnologiesEarl Lum, EJL Wireless ResearchDavid Meyer, Naval Research LabGreg Mills, AXRTECHEizo Mitani, Sumitomo Electric Device Innovations, IncBob Mohondro, Plasma-Therm, LLCKaren Moore, FreescaleCorey Nevers, TriQuint SemiconductorChanh Nguyen, Teledyne ScientificYogi Ota, Panasonic CorporationTed Pappas, Vacuum Engineering & Materials Co.William Quinn, WEQ Consulting, LLCKelli Rivers, MaterionThomas Roedle, NXP SemiconductorsRobert Sadler, Global Communications Semiconductors, LLCKeith Salzman, TriQuint Semiconductor TexasShyh-Chiang Shen, Georgia TechKevin Speer, SemiSouth LaboratoriesJoerg Splettstoesser, United Monolithic Semiconductor Andrew Stoltz, US Army, Night Vision LaboratoryOded Tal, Max IEGShiban Tiku, Skyworks Solutions, Inc.Naveen Tipirneni, Texas InstrumentsJansen Uyeda, Northrop Grumman ASKevin Vargason, IntelliEPIDavid Wang, Global Communication SemiconductorsRuss Westerman, Plasma-Therm, LLCVictoria Williams, Cree, Inc.Chris Youtsey, Microlink DevicesGuoliang Zhou, Skyworks Solutions, Inc.


TECHNICAL PROGRAM

Monday, May 13th

CS MANTECH WORKSHOPSChair: Russ Kremer, Freiberger USA

7:00 AM Registration

8:50 AM Welcome and Introductions

9:00 AM Workshop Session 1How do calls reach my cell phone regardless of where I'm located? And how can thousands of people talk on the same band of frequencies? James Eastham, TriQuint Semiconductor

10:15 AM BREAK

10:30 AM Workshop Session 2 Once I know what the handset manufacturers need for a PA, how can I convert than into a spec?Pete Zampardi, RF Micro Devices

12:00 PM WORKSHOP LUNCH (CS MANTECH WORKSHOP & ROCS)

1:00 PM Workshop Session 3 Given a PA spec, how do I determine the exact epi layer stack needed? And how can I test each layer? Wayne Johnson, Kopin Corporation

2:15 PM Workshop Session 4 Here's a great epiwafer. How do I convert that into a PA module? Will Snodgrass, Avago Technologies

3:30 PM BREAK

3:45 PM Workshop Session 5 What a nice PA! How should I package it so it works optimally? Dean Monthei, TriQuint Semiconductor

6:00 PM EXHIBITS RECEPTION

ROCS WORKSHOPChair: Peter Ersland, M/A-COM Technology

Solutions


7:30 AM ROCS Registration- 8:30 AM

8:15 AM ROCS Workshop Sessions- 4:45 PM

12:00 PM WORKSHOP LUNCH (CS MANTECH & ROCS)

Tuesday, May 14th

8:00 AM Conference OpeningKaren Renaldo, Northrop GrummanConference Chair

8:10 AM 2012 Conference Best Paper AwardsYohei Otoki, Hitachi Cable

8:20 AM Technical Program HighlightsScott Sheppard, Cree, Inc.Technical Program Chair

SESSION 1:PLENARY I –GaAs INDUSTRY OVERVIEW

Chair: Scott Sheppard, Cree, Inc.

8:30 AM Invited Presentation1.1 Challenges of Short Lifecycle Commercial Products in Compound Semiconductor Manufacturing Howard S. Witham, TriQuint Semiconductor

8:55 AM Invited Presentation1.2 GaAs Foundry: Challenges and FutureDavid Danzilio, WIN Semiconductors Corp.

9:20 AM Invited Presentation1.3 A Co-operative Business Model for Advancing Compound Semiconductor TechnologyJerry Curtis, Global Communication Semiconductors

9:45 AM Invited Presentation1.4 GaAs Industry Overview and Forecast: 2011 – 2016 AbstractEric Higham, Strategy Analytics, Inc.

10:10 AM BREAK


SESSION 2: PLENARY II –PHOTONICS IC VOLUME MANUFACTURING

Chair: David Wang, Global Communication Semiconductors

10:40 AM 2.1 Manufacturing Progress for InP-based 500 Gbps Photonic Integrated CircuitsRichard P. Schneider, Jr., Jacco L. Pleumeekers, Damien J. H. Lambert, Peter W. Evans, Andrew G. Dentai, Paul Liu, Jon Rossi, Scott Craig, Margherita Lai, Vikrant Lal, Naksup Kim, Eva Strzelecka, Pavel Studenkov, Adam James, Scott Corzine, Kuan-Pei Yap, Peter Debackere, Shashank Agashe, Jeffrey Glick, Christopher Hill, Quisheng Chen, Wayne Williams, Sanjeev Murthy, Ranjani Muthiah, Mark Missey, Scott DeMars, Mehrdad Ziari, Masaki Kato, Radhakrishnan Nagarajan, Arnold Chen, Sheila Hurtt, Fred Kish, Infinera Corporation

11:05 AM Invited Presentation2.2 Multi-Guide Vertical Integration in InP – A Regrowth-Free PIC Technology for Optical CommunicationsValery Tolstikhin, OneChip Photonics, Inc.

11:30 AM Invited Presentation2.3 Heterogeneous Integration as a Manufacturing Platform for Photonic Integrated CircuitsEric Hall, Jae Shin, Gregory Fish, Aurrion, Inc.

11:55 AM EXHIBITS LUNCH

SESSION 3: OPTOELECTRONICS TECHNOLOGIES

Chair: Yohei Otoki, Hitachi Cable, Ltd.

1:20 PM Invited Presentation 3.1 The Latest Progress of Nitride-based

Visible LEDs and Laser diodes Shuji Nakamura, University of California,

Santa Barbara

1:45 PM Invited Presentation3.2 The Discovery of III-V Oxidation, Device Progress, and Application to Vertical-Cavity Surface-Emitting LasersJ. M. Dallesasse, University of Illinois at Urbana-Champaign


2:10 PM Invited Presentation3.3 Non-850nm Vertical Cavity Laser Applications and Manufacturing Technology Klein Johnson, Vixar, Inc.

2:35 PM Invited Presentation3.4 AlInGaN Based Deep Ultraviolet Light Emitting Diodes and Their Applications Technology Asif Khan, University of South Carolina

3:00 PM BREAK

SESSION 4a: PROCESS – BACKSIDEChair: Michelle Bourke, Oxford Instruments Plasma

Technology

3:30 PM 4a.1 Advances in Back-side Via Etching of SiC for GaN Device ApplicationsAnthony Barker1, Kevin Riddell1, Huma Ashraf1 & Dave Thomas1, Chia-Hao Chen2, Yi-Feng Wei2, I-Te Cho2 & Walter Wohlmuth2, 1SPTS Technologies, 2WIN Semiconductors Corp.

3:50 PM 4a.2 Meeting the Fabrication Challenges For Backside Processing on Thin Substrates with Ultrahigh Device Topography

Pavan Bhatia1, Roberta Hawkins1, Jan Campbell1, Martin Ivie1, Alex Smith2, Mark Privett2, Gary Brand2, 1TriQuint Semiconductor,2Brewer Science, Inc.

4:10 PM 4a.3 Wafer-level Backside Process Technology for Forming High-density VIAs and Backside Metal Patterning for 50-µm-thick InP Substrate

Takuya Tsutsumi, Toshihiko Kosugi, and Hideaki Matsuzaki, NTT Photonics Laboratories, NTT Corporation

4:30 PM Student Presentation4a.4 Full-Wafer, Small-Area Via-Hole Fabrication Process Development for Indium-Bearing III-V Heterostructure DevicesYuning Zhao, Patrick Fay, University of Notre Dame


SESSION 4b: PROCESS – LITHOGRAPHYChairs: Robert Mohondro, Plasma-Therm, LLC

Kamal Alavi, Raytheon

3:30 PM 4b.1 Thick Film Photo Resist Application Spun on Application v. Dry Film LaminationSuzanne Combe, TriQuint Semiconductor

3:50 PM 4b.2 The Effect of Exposure Mode on Feature Resolution and Film Thickness for Thick (>10 µm) BCB

J. Parke, A. Gupta, J. Mason, K. Renaldo, Northrop Grumman Electronic Systems

4:10 PM 4b.3 Final Module Yield Improvement by Increasing the Adhesion of SU8 to Microelectronic Devices using a DMAIC approach

Jan Campbell, Martin Ivie, Qizhi He, TriQuint Semiconductor

4:30 PM 4b.4 Automated Skiplot Sampling for Photoresist Thickness MeasrurementDavid Punsalan, Donald Pursley, Christopher Roper, TriQuint Semiconductor

4:50 PM BREAK

5:10 PM EXHIBITORS’ FORUMS (Rosedown/ Elmwood/Magnolia) - Please refer to the posted placards in the exhibit area for forum participants and scheduled presentations.

5:10 PM STUDENT FORUM (Belle Chase)

7:00 PM INTERNATIONAL RECEPTION

Wednesday, May 15th

SESSION 5a: RF GaN PRODUCIBILITYChair: David Meyer, US Naval Research

LaboratoryGlen “David” Via, Air Force Research Laboratory

8:00 AM Invited Presentation5a.1 Recent Defense Production Act Title III Investments In Compound Semiconductor Manufacturing Readiness


Gene Himes1, David Maunder2, Bruce Kopp2, 1Air Force Research Laboratory, 2David P. Maunder Consulting

8:30 AM 5a.2 Title III Gallium Nitride (GaN) on Silicon Carbide (SiC) X-band MMIC ProductionJoseph Smolko, Colin Whelan, Christopher Macdonald, Joshua Krause, Bradley Mikesell, Michael Benedek, Raytheon Corp.

8:50 AM 5a.3 Achieve Manufacturing Readiness Level 8 of high-power, high efficiency 0.25-µm GaN on SiC HEMT ProcessC. Della-Morrow, C. Lee, K. Salzman, TriQuint Semiconductor

9:10 AM 5a.4 GaN-on-SiC MMIC Production for S-Band and EW-Band ApplicationsRyan Fury, Scott Sheppard, Jeffrey B. Barner, Bill Pribble, Jeremy Fisher, Donald A. Gajewski, Fabian Radulescu, Helmut Hagleitner, Dan Namishia, Zoltan Ring, Jennifer Gao, Sangmin Lee, Jim Milligan and John Palmour, Cree, Inc.

9:30 AM 5a.5 GaN-based Components for Transmit/Receive Modules in Active Electronically Scanned ArraysMike Harris, Robert Howard and Tracy Wallace, Georgia Tech Research Institute

SESSION 5b: EPITAXY & MATERIALSChairs: Guoliang Zhou, Skyworks Solutions, Inc.

Paul Pinsukanjana, IntelliEPI

8:00 AM Invited Presentation5b.1 A Comparison of MOVPE and MBE Growth Technologies for III-V Epitaxial StructuresRodney Pelzel, IQE Wireless

8:30 AM 5b.2 Impact of crystal-quality improvement of epitaxial wafers on RF and power switching devices by utilizing VAS-method grown GaN substrates with low-density and uniformly distributed dislocationsYohei Otoki1, Takeshi Tanaka1, Hiroyuki Kamogawa1, Naoki Kaneda1, Tomoyoshi Mishima1,Unhi Honda2,and Yutaka Tokuda2,1Hitachi Cable, Ltd, 2Aichi Institute of Technology


8:50 AM Student Presentation5b.3 Fe-doped AlGaN/GaN HEMTs: Kink-Effect Screening using Yellow Luminescence?Nicole Killat1, Michael J. Uren1, David J. Wallis2, Trevor Martin3, and Martin Kuball1, 1University of Bristol, 2University of Cambridge, 3IQE PLC

9:10 AM 5b.4 Performance and Reliability of AlGaN/GaN HEMT on 100-mm SiC Substrate with Improved Epitaxial Growth UniformitySangmin Lee, Tim Kennedy, Christer Hallin, Helder Antunes, Brian Fetzer, Scott T. Sheppard, Al Burk, Don A. Gajewski, Rick McFarland, Jim Milligan and John Palmour, Cree, Inc.

9:30 AM 5b.5 Development of an Epitaxial Growth Process on European SiC Substrates for a Low Leakage GaN HEMT Technology with Power Added Efficiencies Around 65%P. Waltereit1, S. Müller1, L. Kirste1, S. Storm2, A. Weber2, J. Splettstößer3, B. Schauwecker3, 1Fraunhofer Institute for Applied Solid State Physics, 2SiCrystal AG, 3United Monolithic Semiconductors GmbH

9:50 AM BREAK

SESSION 6a: GaN PROCESS, DEVICE, & CIRCUITS

Chairs: Karen Moore, Freescale Semiconductor, Inc.Ming-yi Kao, TriQuint Semiconductor

10:20 AM 6a.1 An Optical 0.25-μm GaN HEMT Technology on 100-mm SiC for RF Discrete and Foundry MMIC ProductsSimon M. Wood, Scott T. Sheppard, Fabian Radulescu, Don A. Gajewski, Bill Pribble, Donald Farrell, Ulf Andre Jeffrey B. Barner, Jim Milligan and John Palmour, Cree, Inc.

10:40 AM Student Presentation6a.2 Effect of sputtered SiN passivation on current collapse of AlGaN/GaN HEMTsMd. Tanvir Hasan, Toshikazu Kojima, Hirokuni Tokuda, and Masaaki Kuzuhara, University of Fukui


11:00 AM 6a.3 Investigation of AlGaN/GaN HEMTs Passivated by AlN Films Grown by Atomic Layer EpitaxyA.D. Koehler1, N. Nepal1, T.J. Anderson1, M.J. Tadjer2, K.D. Hobart1, C.R. Eddy, Jr.1, F.J. Kub1, 1Naval Research Laboratory, 2Universidad Politécnica de Madrid

11:20 AM Student Presentation6a.4 Fabrication Technology of GaN/AlGaN HEMT Slanted Sidewall Gates Using Thermally Reflowed ZEP Resist and CHF3/SF6 Plasma EtchingK. Y. Osipov, W. John, N. Kemf, S. A. Chevtchenko, P. Kurpas, M. Matalla, O. Krüger, and J. Würfl, Ferdinand-Braun-Institut

11:40 AM 6a.5 Development and Control of a 0.25μm Gate Process Module for AlGaN/GaN HEMT ProductionWei-Chou Wang, Chia-Hao Chen, Jhih-Han Du, Ming Hung Weng, Che-Kai Lin, Willie Huang, Ricky Chang, Shih-Hui Huang, Yi-Feng Wei, Stanley Hsieh, Michael Casbon, Paul J. Tasker, Wen-Kai Wang, I-Te Cho, Walter Wohlmuth, WIN Semiconductor Corp.

SESSION 6b: MANUFACTURING: TEST & CHARACTERIZATION

Chairs: Peter Ersland, M/A-COM Technology SolutionsHidetoshi Kawasaki, Sony

10:20 AM 6b.1 Low Turn-On Voltage Schottky Diode in InGaP/GaAs HBT/BiFET ProcessesCristian Cismaru and Peter J. Zampardi, Skyworks Solutions, Inc.

10:40 AM 6b.2 Device Characteristics Analysis of GaAs/InGaP HBT Power Cells Using Conventional Through Wafer Via Process and Copper Pillar Bump ProcessHsiu-Chen Chang, Shu-Hsiao Tsai, Cheng-Kuo Lin, Tim Hsiao, Steven Chou, Chen, Pi-Hsia Wang, and Dennis WilliamsJu-Yung, WIN Semiconductors Corp.

11:00 AM 6b.3 Improved Vertical Probe Technology for Production Probing on Cu Pillar BumpsMartin J. Brophy, Chin-Shun Chen, Keith Quick, Avago Technologies


11:20 AM 6b.4 Real-time Validation of Probe Contact Quality in GaAs PCM TestingMartin J. Brophy, Phil Marsh, Anthony Martinkus, and Judy Huggenberger, Avago Technologies

11:40 AM 6b.5 Real Time Dynamic Application of Part Average Testing (PAT) at Final TestDouglas Pihlaja, TriQuint Semiconductor

12:00 PM OPEN LUNCH

SESSION 7a: THERMAL DESIGN IChair: John Blevins, Air Force Research Laboratory

1:30 PM Invited Presentation7a.1 DARPA’s Intra/Interchip Embedded Cooling (ICECool) ProgramAvram Bar-Cohen¹, Joseph J. Maurer², Jonathan G. Felbinger², 1Defense Advance Research Projects Agency, 2Booz Allen Hamilton

2:00 PM 7a.2 GaN HEMT Near Junction Heat Removal Rajinder Sandhu1, Vincent Gambin1, Benjamin Poust1, Ioulia Smorchkova1, Gregg Lewis1, Raffi Elmadjian1, Danny Li1, Craig Geiger1, Ben Heying1, Mike Wojtowicz1, Aaron Oki1, Tatyana Feygelson2, Karl Hobart3, Bradford Pate3, Joe Tabeling4, Elah Bozorg-Grayeli5, Kenneth Goodson5, 1Northrop Grumman Aerospace Systems, 2SAIC, 3Naval Research Laboratory, 4Applied Diamond, Inc., 5Stanford University

2:20 PM 7a.3 New High Power GaN HEMT with Low Temperature Bonded Diamond Substrate Technology P.C. Chao, K. Chu and C. Creamer, BAE Systems

2:40 PM 7a.4 Improved Near Junction Thermal Transport Using GaN on DiamondM.Tyhach1, D. Altman1, S. Bernstein1, R. Korenstein1, F. Ejeckam2, D. Francis2, K. Goodson3, S. Graham4, 1Raytheon Co., 2Group4Labs, 3Stanford University, 4Georgia Tech University


3:00 PM 7a.5 Gallium Nitride Power Amplifier, Near Junction Thermal Transport, Cooling ModuleStan Weaver1, Gary Mandrusiak1, David Lin1, Eric Browne1, Nannan Chen1, Oliver Boomhower1, Joleyn Brewer1 and Rama Vetury2, 1General Electric Global Research, 2RF Micro Devices

SESSION 7b: TRAPS & TRANSIENTSChairs: Tom Low, Agilent Technologies

Chang-Hwang Hua, WIN Semiconductors Corp.

1:30 PM Invited Presentation7b.1 Correct Determination of Trap Densities at High-k/III-V InterfacesR. Engel-Herbert, Pennsylvania State University

2:00 PM 7b.2 Temporal Characterization of Defects and Evolution of Strain in AlGaN/GaN HEMTs Under Bias H. Ghassemi1, A. Lang1, C. Johnson2, R. Wang3, B. Song3, H. Xing3, and M. L. Taheri1, 1Dept. of Materials Science and Engineering, Drexel University, 2Centralized Research Facilities, Drexel University, 3University of Notre Dame

2:20 PM Student Presentation7b.3 Interfacial Charge Properties of ALD/III-Nitride Interfaces Ting-Hsiang Hung, Michele Esposto, Digbijoy Neelim Nath, Sriram Krishnamoorthy,Pil Sung Park and Siddharth Rajan, Dept. of Electrical and Computer Engineering, The Ohio State University

2:40 PM 7b.4 GaN Buffer Design: Electrical Characterization and Prediction of the Effect of Deep Level Centers in GaN/AlGaN HEMTsM. Silvestri1, M. J. Uren1, D. Marcon2, and M. Kuball1, 1University of Bristol, 2IMEC

3:00 PM 7b.5 Ultra Fast Switching Speed FET Technology DevelopmentJerod Mason, Guoliang Zhou, Joe Bulger, Jay Yang, David Petzold, Dylan Bartle, Skyworks Solutions, Inc.


3:20 PM BREAK

SESSION 8a: THERMAL DESIGN IIChairs: Andy Souzis, II-VI

Martin Kuball, University of Bristol

3:40 PM 8a.1 Process Improvements for an Improved Diamond-capped GaN HEMT DeviceT.J. Anderson1, A.D. Koehler1, M.J. Tadjer2, K.D. Hobart1, T.I. Feygelson3, B.B. Pate1, F.J. Kub1, 1Naval Research Laboratory, 2Universidad Politécnica de Madrid, Spain, 3SAIC, Inc.

4:00 PM 8a.2 Ag/Diamond Composite Shims for HPA Thermal ManagementJason H. Nadler, Keri A. Ledford, H. Michael Harris and Brent K. Wagner, Georgia Tech Research Institute

4:20 PM 8a.3 Thermal and Mechanical Sensors for Advancement of GaN RF MMIC TechnologiesB. Wagner1, H.M. Harris1, M. King1, H. Chan1, N. Minor2 and L. B. Burns2, 1Georgia Tech Research Institute, 2PEO Integrated Warfare Systems, Naval Sea Systems Command

4:40 PM 8a.4 GaN HEMTs for Power Switching Applications: from Device to System-Level Electro-Thermal ModelingNicola Delmonte, Paolo Cova, and Roberto Menozzi, University of Parma

5:00 PM 8a.5 InGaP/GaAs HBT Safe Operating Area and Thermal Size EffectNick GM Tao, Chien-Ping Lee, Tony St. Denis and Tim Henderson, TriQuint Semiconductor, Inc.

SESSION 8b: PROCESS – METALChairs: Suzanne Combe, TriQuint Semiconductor

Jansen Uyeda, Northrop Grumman AS

3:40 PM 8b.1 High Precision Thin Metal Film Measurement by Optical TransmissionKezia Cheng, and Bing Hui Li, Skyworks Solutions, Inc.


4:00 PM 8b.2 SiN/Ge Lift-off: A Method for Patterning Films Deposited at High TemperatureD. J. Meyer1, D. A. Deen2, B. P. Downey1, D. S. Katzer1, D. F. Storm1, and S. C. Binari1, 1Naval Research Laboratory, 2University of Minnesota

4:20 PM 8b.3 Palladium Diffusion Barrier Grown by Electoplating for Backside Cu Metallization of GaAs devicesDaisuke Tsunami, Koichiro Nishizawa, Toshihiko Shiga, Tomoki Oku and Masayoshi Takemi, Mitsubishi Electric Corporation

4:40 PM 8b.4 Optimization of Electroplating Processes for Copper BumpsElizabeth Tan Calora and Travis Abshere, TriQuint Semiconductor

5:00 PM 8b.5 Back Metal Optimization for PbSn Die Attach AssemblyJose Suarez, Jason Fender, and Jenn-Hwa Huang, Freescale Semiconductor

5:20 PM RUMP SESSION RECEPTION

5:50 PM RUMP SESSIONSChair: Karen Moore, Freescale Semiconductor, Inc.

This year’s rump sessions should continue the ManTech tradition of lively discussions among peers helped along by snacks and beers. Please join us for animated-to-heated conversation and debate of some of your favorite hot buttons in the compound semiconductor industry.

SESSION A: Keep your pointy probes off of my wafers, you vulture!Moderator: Marty Brophy, Avago Technologies, Fort Collins, CO, USA

If you work in in-process, PCM, or die sort test, or use test, you have heard it or said it before. “Test? There’s no value added there, you just add to my costs. Go away and leave my poor wafers alone. All you want to do is scrap them, and what did they ever do to you?”

Is this true? Are we over-testing? Many will tell you “No way!” But some people may think differently, poor misguided souls that they are, probably under-loved as children or something…. Come by and argue your point of view with those of us who “really know!” If no one takes the opposing point of view, it will just encourage us, so


best that you come along and argue your side… and remember – probe engineers can smell fear!

SESSION B: GaN wants to be a Billionaire? Who will call to assist the answer?Moderator: Toshi Kikkawa, Fujitsu Laboratories

Mass-production of GaN for RF application has already been launched. However, the business areas and opportunities are still restricted, and GaN for power conversion is still small in market size. In this rump session, we would like to discuss what needs to be done for nitrides to join the “big leagues” and really enjoy large scale financial success. We will “Ask the Audience,” “Ask and Expert,” and, if necessary, “Phone a Friend” to find some correct “Final Answers” to large scale production success for GaN device technologies, both present and future.

SESSION C: What are the real chances of success for GaN on Si? Can you show me some data?Moderator: Russ Westerman, Plasma-Therm LLC

GaN-on-Si devices have demonstrated high performance capabilities with the promise of realizing mainstream Si manufacturing costs and efficiencies. Enter commercial reality - mainstream silcon-based technologies have set market expectations for devices with near perfect reliability and have the data to prove it. While the initial performance of GaN-on-Si is enticing –is the technology truly mature enough in terms of reliability for commercial applications? Though Deming only trusts God & data – we’re interested in your opinions! (but feel free to bring your favorite (biased) data). What’s holding GaN-on-Si back and (when) will it take over the world?

SESSION D: SOI switches are killing GaAs PHEMT's. Will CMOS PA's follow the same path and kill GaAs HBT's? CMOS PA vs GaAs PA - CMOS go homeModerators: Mike Sun and Shiban Tiku, Skyworks Inc.

A Tale of Two ArchersSir MOSalot and Sir GaAsahad were participating in a contest to see who would be crowned champion of the apple picking contest held by the King. Most people bet on Sir MOSalot who had won numerous contests. Sir GaAsahad only entered very specific contests. Archers had to hit the bulls-eye to win, but they could move closer to the target after each shot that hit the target and shoot again. Sir MOSalot used very expensive 12 inch arrows that were slow to fabricate and modify, while Sir GaAshad used cheap 6 inch arrows that were quickly improved. Sir


MOSalot took his first shot and missed, and proceeded to prepare for the next shot. Sir MOSalot finally got his turn again and was lining up the shot, but the king moved the target. Sir MOSalot hurled his bow like a javelin into black sand nearby. Sir GaAsahad took multiple shots, was able to move closer to the target and hit the bull’s eye, and won the contest, receiving the magic tablet. Astonishingly, the supporters of Sir MOSalot still picked him up on their shoulders and carried him to the next contest...

Adapted from “A tale of Two Archers” by Mack Javelly , IEEE microwave magazine, Nov./Dec. 2012

This is an ancient story. Does CMOS still mean “Can’t Meet Our Schedule” today? Come to this rump session and find out.

7:00 PM SEMI STANDARDS MEETING

Thursday, May 16th

SESSION 9a: WIDE BANDGAP POWER DEVICESChairs: Toshihide Kikkawa, Fujitsu Laboratories

Shyh-Chiang Shen, Georgia Tech

8:00 AM Invited Presentation 9a.1 High Temperature (> 200 °C), High

Frequency (> 1 MHz) Multi-Chip Power Modules

Ty McNutt, Brandon Passmore, Zach Cole, Bret Whitaker, Adam Barkley, Alex Lostetter, Arkansas Power Electronics International, Inc.

8:30 AM 9a.2 Emerging Applications for GaN Transistors

David Reusch, Alex Lidow, Johan Strydom, Michael de Rooij, Efficient Power Conversion Corporation

8:50 AM Student Presentation9a.3 600 V High-Performance AlGaN/GaN HEMTs with AlN/SiNx Passivation

Zhikai Tang, Sen Huang, Qimeng Jiang, Shenghou Liu, Cheng Liu and Kevin J. Chen, The Hong Kong University of Science and Technology

9:10 AM 9a.4 600V-900V GaN-on-Si Process Technology for Schottky Barrier Diodes


and Power Switches Fabricated in a Standard Si-Production FabJ.J.T.M. Donkers1, S.B.S. Heil2, G.A.M. Hurkx1, H. Broekman3, R. Delhougne1, J.A. Croon2, D. Gravesteijn1, J. Šonský1, 1NXP Semiconductors Research, Belgium, 2NXP Semiconductors Research, High Tech Campus, The Netherlands, 3NXP Semiconductors Nijmegen, The Netherlands

9:30 AM 9a.5 182W L-band GaN High Power Module with 66% Power Added Efficiency Based on European Technologies

Stéphane Rochette1, Olivier Vendier1, Dominique Langrez1, Jean-Louis Cazaux1, Michael Buchta2, Martin Kuball3, Alain Xiong4, 1Thales Alenia Space, 2UMS GmbH, 3University of Bristol, 4AMCAD Engineering

9:50 AM BREAK

SESSION 9b: LED OUTLOOK & TECHNOLOGYChairs: Ruediger Schreiner, Aixtron SE

Gene Kohara

8:10 AM Invited Presentation 9b.1 Low-Cost High-Efficiency GaN LEDs

on Large-Area Silicon Substrates Sir Colin J. Humphreys, University of

Cambridge

8:40 AM Invited Presentation9b.2 How GaN-on-Si Could Disrupt the Current Equilibrium of the Booming LED Industry

Philippe Roussel, Yole Développement

9:10 AM 9b.3 Improvement of LED Luminance Efficiency by Sapphire Nano PSS Etching

H. Ogiya, T. Nishimiya, M. Hiramoto, S. Motoyama, O. Tsuji, and P. Wood, Samco, Inc.

9:30 AM Student Presentation9b.4 The Effects of Light Output via Inductively Coupled Plasma (ICP) and Wet Chemical Etch on Distributed Bragg Reflectors in Resonant Cavity Light Emitting TransistorsMong-Kai Wu, Michael Liu, and Milton Feng, University of Illinois at Urbana-Champaign


9:50 AM BREAK

SESSION 10a: MATERIALS: GaN EPIChairs: Judy Kronwasser, NOVASiC

Robert Sadler, Global Communications Semiconductors, LLC

10:10 AM 10a.1 MOCVD Growth of AlGaN/GaN Heterostructures on 6 inch Silicon Jie Su, Hongwei Li, Seungjae Lee, Balakrishnan Krishnan, Dong Lee, George Papasouliotis, and Ajit Paranjpe, Veeco MOCVD Operations

10:30 AM 10a.2 Uniformity Studies of AlGaN/GaN HEMTs on 8-in Diameter Si(111) Substrate S. Arulkumaran1, G. I. Ng2, S. Vicknesh1, C.M. Manojkumar1, K.S. Ang1, H. Wang2, M.J. Anand2, K. Ranjan1, S. L. Selvaraj3, W. Z. Wang3, G.-Q. Lo3, S. Tripathy4, 1Temasek Laboratories, Nanyang Technological University, 2School of Electrical and Electronics Engineering, Nanyang Technological University, 3Institue of Microelectronics, A*star, 4Institute of Materials Research and Engineering, A*star

10:50 AM 10a.3 High Voltage GaN-on-Silicon HEMTs T. Boles1, C. Varmazis1, D. Carlson1, L. Xia1, D. Jin1, T. Palacios2, G. W. Turner3, R. J. Molnar3, 1M/A COM Technology Solutions, 2Massachusetts Institute of Technology, 3Massachusetts Institute of Technology, Lincoln Laboratory

11:10 AM 10a.4 High Voltage GaN-on-Silicon Schottky DiodesT. Boles1, C. Varmazis1, D. Carlson1, L. Xia1, D. Jin1, T. Palacios2, G. W. Turner3, R. J. Molnar3, 1M/A COM Technology Solutions, 2Massachusetts Institute of Technology, 3Massachusetts Institute of Technology, Lincoln Laboratory

11:30 AM Student Presentation10a.5 Comparison of Schottky Diodes on Bulk GaN substrates & GaN-on-Sapphire Pei Zhao, Amit Verma, Jai Verma, Huili Xing and Debdeep Jena, University of Notre Dame

SESSION 10b: PROCESS – INTEGRATION


Chair: Steve Mahon, Cascade Microtech, Inc.

10:10 AM 10b.1 Layout Practices for Die Size Reduction on InGaP/GaAs HBT MMICs for Handset Power Amplifier ApplicationsShu-Hsiao Tsai, Rong-Hao Syu, Yu-Ling Chen, Wen-Fu Yu, Cheng-Kuo Lin, and Dennis Williams, WIN Semiconductors Corp.

10:30 AM 10b.2 Evaluation of Material and Process Contributions to BiFET Variation Using Design of Experiments Peter J. Zampardi, Bin Li, Cristian Cismaru, Hal Banbrook, and Andre Metzger, Skyworks Solutions, Inc.

10:50 AM 10b.3 Bulk Acoustic Wave Technology AdvancesG. Fattinger, R. Aigner, P. Stokes, A. Volatier, F. Dumont, TriQuint Semiconductor

11:10 AM 10b.4 Heterointegration Technologies for High Frequency Modules Based on Film Substrates Karlheinz Bock, Erwin Yacoub-George, Henry Wolf, Christof Landesberger, Gerhard Klink, and Horst Gieser, University of Berlin

11:30 AM 10b.5 Passivation Stress versus Top Metal Profiles by 3D Finite Element Modeling Xiaokang Huang, Liping Zhu, Bang Nguyen, Van Tran, Harold Isom, TriQuint Semiconductor

11:50 AM LUNCH by CS MANTECH

SESSION 11a: GaN GATE DIELECTRICSChair: Patrick Fay, University of Notre Dame

1:10 PM Invited Presentation11a.1 Characterization and Control of Insulated Gate Interfaces on GaN-Based HeterostructuresTamotsu Hashizume1,2 and Masamichi Akazawa1, 1Hokkaido University, 2JST-CREST

1:40 PM Student Presentation11a.2 A Study on Al2O3 Deposition by Atomic Layer Deposition for III-Nitride Metal-Insulator-Semiconductor Field Effect Transistors


Yi-Che Lee, Tsung-Ting Kao, and Shyh-Chiang Shen, Georgia Tech University

2:00 PM 11a.3 Thermal Oxidization of MIS Interface between Etched GaN and ALD-Al2O3 Tetsuya Fujiwara1, Minoru Akutsu1, Norikazu Ito1, Junichi Kashiwagi1, Kentaro Chikamatsu1, Ken Nakahara1, and Masaaki Kuzuhara2, 1ROHM Co., Ltd., 2University of Fukui

2:20 PM Student Presentation11a.4 High Performance Enhancement-Mode AlGaN/GaN MOSHEMT using Bimodal-Gate-Oxide and Fluoride-Based Plasma TreatmentLiang Pang and Kyekyoon Kim, University of Illinois at Urbana-Champaign

2:40 PM 11a.5 Performance and Reliability of GaN MISHEMTs and MMICs Fabricated From GaN Grown on High Resistance <111> Si Substrates by Molecular Beam EpitaxyJeffrey LaRoche, William Hoke, David Altman, James McClymonds, Paul Alcorn, Kurt Smith, Eduardo Chumbes, Jeff Letaw, and Thomas Kazior, Raytheon IDS Microelectronics

SESSION 11b: YIELD ENHANCEMENT AND MANUFACTURING

Chair: Marty Brophy, Avago Technolgies

1:10 PM Invited Presentation11b.1 Challenges of Equipment Support in a Factory with a Diverse Multigenerational ToolsetDavid W. Brindza, Travis A. Abshere, TriQuint Semiconductor

1:40 PM 11b.2 Factory Automation for Overall Fab EfficiencyNirav Thakkar, Skyworks Solutions

2:00 PM 11b.3 Optimizing Staff Levels Using Linear ProgrammingMarino Arturo and Ariel Meyuhas, MAX I.E.G.

2:20 PM 11b.4 Yield Learning of a GaAs-Based High-Throw-Count Switch for Handset Applications


Tertius Rivers, Corey Nevers, Chi-hing Choi, Hui Liu, TriQuint Semiconductor

2:40 PM 11b.5 Combining Visual Inspection and Bare Die Packaging for High Volume ManufacturingChang’e Weng and Thorsten Saeger, TriQuint Semiconductor

SESSION 12: POSTER SESSIONChairs: Kelli Rivers, Materion

Corey Nevers, TriQuint SemiconductorJansen Uyeda, Northrop Grumman AS

3:00 PM 12.1 How Mask Data Error Rate - 4:00 PM Maintained at below 0.1% While Volume

Increased 2+ Folds – Through AutomationSusie Ross, Tin Ko, Jianli Fu, Hongxiao Shao, Skyworks Solutions, Inc.

Student Presentation12.2 Yield Improvement in Fabrication of Edge Emitting Transistor Lasers by optimized BCB planarizationRohan Bambery and Milton Feng, University of Illinois at Urbana-Champaign

12.3 Development of PVD-AlN Buffer Process for GaN-on-SiFrank Cerio, Arindom Datta, Adrian Devasahayam, Boris Druz, Veeco Instruments

Student Presentation12.4 GaN MOSHEMT Using Sputtered-Gate-SiO2 and Post-Annealing TreatmentLiang Pang1, Yaguang Lian1, Dong-Seok Kim2, Jung-Hee Lee2, and Kyekyoon Kim1, 1University of Illinois at Urbana-Champaign, 2Kyungpook National University, Korea

12.5 Process-Reliability Relationships in GaN and GaAs Field Effect Transistors and HFETsA. Christou, University of Maryland

12.6 Formation of slanted gates for GaN-based HEMTs by combined plasma and wet chemical etching of silicon nitrideA. Thies, N. Kemf, S.A. Chevtchenko, and O. Krüger, Ferdinand-Braun-Institut-Berlin


12.7 Deposition control during GaN MOVPED. Fahle1, T. Krücken2, M. Dauelsberg2, R. Schreiner2, H. Kalisch1, M. Heuken1,2 and A. Vescan1, 1RWTH Aachen University, 2AIXTRON SE

12.8 Heterogeneous Integration Schemes of Compound Semiconductors for Advanced CMOS and More-than-Moore ApplicationsT. Uhrmann, T. Matthias, T. Glinsner, V. Dragoi, T. Plach, E. Pabo, M. Wimplinger and P. Lindner, EV Group

Student Presentation12.9 Methods of Improving GaN-Based LED Luminous EfficiencyLiang-Yu Su and JianJang Huang, National Taiwan University

Student Presentation12.10 Current Gain Enhancement of Light-Emitting Transistors Under Different Ambient TemperaturesWen-Chung Tu and Chao-Hsin Wu, National Taiwan University

12.11 BCB Encapsulation for High Power AlGaN/GaN-HFET TechnologyP. Kurpas, O. Bengtsson, S. A. Chevtchenko, I. Ostermay, R. Zhytnytska, W. Heinrich, J. Würfl, Ferdinand-Braun-Institut-Berlin

12.12 Recent Developments in Real-Time Thickness Control of Plasma Deposited Thin Film Dielectrics Using Optical Emission InterferometryKenneth D. Mackenzie, David J. Johnson, Christopher W. Johnson, and Linnell Martinez, Plasma-Therm, LLC

12.13 Reducing Defects Using a 5x Stepper in Pattering 80 µm SU8 on MEMS DevicesJean-François Bédard, Jan Campbell, Martin Ivie, Elda Clarke and Gary Head, TriQuint Semiconductor

12.14 Back to the Future: How Implementing Retro-Style Processing Can be an ImprovementMartin Ivie, Jan Campbell, Qizhi He, TriQuint Semiconductor


Student Presentation12.15 Growth and Characterization of Band Gap Engineered InGaAs/InAlAs/ GaAs High Electron-Mobility Quantum Well Structure Towards Low Leakage VLSI ApplicationsU. P. Gomes1, Y. Chen2, Y.K.Yadav1, S. Ghosh1, S. Chowdhury1, P. Mukhopadhyay1, P. Chow2 and D. Biswas1, 1Indian Institute of Technology Kharagpur, 2SVT Associates

12.16 Developing a Fundamental Understanding of Gold Spitting During EvaporationAlan Duckham1, Lawrence Luke2, Robert Sprague2, 1Materion Microelectronics & Services, 2Materion Barr Precision Optics & Thin Film Coatings

12.17 Estimating the Energy Output of Multi-junction Solar Cell WafersOnur Fidaner and Michael W. Wiemer, Solar Junction Corporation

12.18 Integrating a Control Plan Methodology into an MES System to Enhance Ease of Process ControlLesley Cheema, Jason Welter, Nicolas Awad, TriQuint Semiconductor

4:00 PM CONFERENCE CLOSING RECEPTION


TECHNICAL SESSIONS

SESSION 1: PLENARY I –GaAs INDUSTRY OVERVIEW

Chair: Scott Sheppard, Cree, Inc.

Technology built with compound semiconductor GaAs and related materials is chief in our industry and the major contributor of papers and attendees at our conference. Therefore, it is with great pleasure that we open the conference with an overview of several facets of this industry. The conference starts with the Vice President of Operations at TriQuint Seminconductor in Texas, Dr. Howard S. Witham, who will share his expertise on the challenges of short-lifecycle products and manufacturing operation’s role in fast-paced product launch. This is an extremely valuable presentation for future winners in the market of increasing RF content in high-volume commercial electronics. As the consumer demands newer generations of electronics at a higher rate, the operations branch must have systems in place for near instantaneous ramp with minimum cycle time and high yield. Complementary to Integrated Device Manufacturing in our industry are the companies for whom their product is the pure-play manufacturing processes only. Component and MMIC foundry services enable high-flexibility and broad-based innovation of new RF products across the entire industry with high-quality, low-cost and short cycle times. Two top-level reviews of GaAs foundry business models and their future will be given by Mr. David Danzilio, Senior VP of Technology at WIN, and Mr. Jerry Curtis, CEO of Global Communication Semiconductors. Both of these invited speakers will discuss current and future challenges of this indispensable part of the overall RF semiconductor supply chain, especially as the GaAs content in mobile devices will continue to increase. An added advantage lies with the foundry offering that can accommodate small-volume custom products that leverage cost infrastructure alongside high-volume manufacturing and technical expertise of pure-play. Finally, this opening session of the conference finishes with a GaAs industry overview and forecast through 2016 by Eric Higham of Strategy Analytics, Inc. His paper focuses on the review of 2011 GaAs substrate and component markets, but will also give insight into the projected trends, drivers and estimated market performance of GaAs through 2016.

SESSION 2: PLENARY II –PHOTONICS IC VOLUME MANUFACTURING

Chairs: David Wang, Global Communication SemiconductorsArnold Chen, Aurrion


With insatiable demands for instant access to information and data, the global IP traffic is forecast to grow at 32% CAGR from 2012 to 2015 (from LightCounting presentation at OFC 2012). As one of its beneficiaries, the optoelectronic components industry is experiencing an explosive growth from the increasing use of FTTX access systems, optical interfaces/interconnects, and continuing transition to higher data rates.

In order to meet the optical systems’ requirements for complexity, performance, volume, and cost, optoelectronic components are following the footsteps of digital IC and MMIC to evolve from discrete components/hybrid assembly into photonic IC (PIC) technology, where active and passive optical components, and even electronic ICs are fabricated on a single semiconductor chip.

Infinera Corporation is the leader in PIC technology and has commercialized 50-100 Gbps InP-based large-scale PICs since 2004, with 860 million field hours without a single failure. Rick Schneider will give an introduction of PICs and describe the manufacturing status of Infinera’s 3rd generation LS-PICs.

OneChip Photonics has developed an InP-based Multi-Guide Vertical Integration (MGVI) technology, which is a versatile and cost-efficient regrowth-free PIC platform that allows for decoupling of epitaxial growth and wafer fabrication, thereby enabling for outsourcing manufacturing to separate commercial foundries. Valery Tolstikhin will describe fundamentals and applications of the MGVI technology and report on manufacturing and performance of the PIC products for cost-sensitive telecom and datacom markets.

Aurrion Inc. has developed a Si-based Heterogeneous PIC platform, which adds InP functionality to the underlying Si photonic circuits. This technology can leverage the best-in-class performance from III-V active devices and low-cost Si-based passive optical components as well as advanced electronic device for drivers. Eric Hall will describe this Heterogeneous PIC technology and present some example products.

SESSION 3: OPTOELECTRONICS TECHNOLOGIES

Chair: Yohei Otoki, Hitachi Cable, Ltd.

Revolutionary optoelectronic devices, such as high-performance LDs, LEDs and sensors, have been continuously developed in the past several decades, changing our life style. These devices have been realized by hard and continuous efforts for developing new processes and innovative device designs using various compound semiconductor materials. This session introduces recent progress in these areas from four famous


invited speakers. Prof. Shuji Nakamura of UCSB talks about the latest progress of GaN LEDs and blue/green LDs grown on nonpolar/semipolar GaN-substrates, demonstrating excellent performance. Prof. John M. Dallesasse from the University of Illinois reviews application of lateral growth oxide layers coming from AlAs/GaAs layers, enabling both current and optical confinement and better reliability. This technology also has been applied to vertical cavity surface emitting laser (VCSEL) diodes. Dr. Klein Johnson from Vixar presents the great evolution of the VCSEL diode using AlGaAs, AlInGaP, InGaAs materials, ranging from infrared to red wavelengths and across applications from well-known communication systems to biomedical. Finally, newly developed deep ultraviolet (250-300 nm) LEDs using AlInGaN materials on AlN substrates are introduced by Prof. Asif Khan of University of South Carolina. He will highlight the latest material and process developments resulting in improve device efficiency and reliability that could enable the replacement of mercury lamps.

SESSION 4a: PROCESS – BACKSIDEChair: Michelle Bourke, Oxford Instruments Plasma

Technology

The backside processing session this year considers the formation of vias in SiC, GaAs and InP. The session begins with a joint paper from SPTS Technologies and WIN Semiconductors. This paper will focus on the development of an 85μm diameter, 100μm deep SiC backside via etch process on 100mm SiC/GaN wafers bonded to carriers. The results will show SiC etch rates >1.3μm/min. The second paper in this session is a joint paper from TriQuint Semiconductor (Texas) and Brewer Science. This paper will discuss the development of a mounting process that enables the thinning of the substrate to the required thickness for such devices is presented with consideration to critical process requirements including total thickness variation (TTV), grind thickness uniformity, damage removal, etch resistance, and electrical parameters. Following on from a backside process relating to GaAs, the third paper in this session is from NTT Photonics Laboratories, NTT Corporation. This paper will discuss a backside process for thinning 3-inch InP substrates down to 50μm, forming dense vias with good uniformity across the whole substrate, and backside-metal patterning, which is applicable for up to Y-band SMMICs. The final paper is this session is a joint paper from the Department of Electrical Engineering, University of Notre Dame and MicroLink Devices. This paper will compare several process alternatives for forming small-area, high-density vias in Indium-bearing III-V materials by dry etching.


Three different chemistries will be considered, Cl2/Ar, BCl3/Cl2/Ar, and SiCl4/Ar.

SESSION 4b: PROCESS – LITHOGRAPHYChairs: Robert Mohondro, Plasma-Therm, LLC

Kamal Alavi, Raytheon

This session has four papers that deal with practical aspects of thick photo resist and BCB in the backend manufacturing of compound semiconductors. The first paper from Triquint discusses tradeoffs between spun on vs. dry film lamination of thick photo resist. The second paper, from Northrop Grumman, deals with the effect of exposure mode on feature resolution for >10 um thick BCB. The third paper, from Triquint, shows a new method for “Automated Skiplot Sampling for Photoresist Thickness Measurements”, which aids in productivity. The last paper, also from Triquint, discusses how use of DMAIC (Define, Measure, Analyze, Improve and Control) method results in enhanced adhesion of SU8 and thus improves the final module yield.

SESSION 5a: RF GaN PRODUCIBILITYChairs: David Meyer, US Naval Research

LaboratoryGlen “David” Via, Air Force Research Laboratory

Gallium Nitride (GaN) device and Monolithic Microwave Integrate Circuit (MMIC) technology for RF applications has matured significantly over the last decade. Major efforts, such as the Defense Advanced Research Projects Agency (DARPA) sponsored Wide Band Semiconductors for RF applications (WBGS-RF) program and the multinational Key Organization for Research in Integrated Circuits in GaN Technology (KORRIGAN) initiative, a large-scale European joint Research and Technology Project performed within the European Union, have helped establish substrate and epitaxial growth capability along with advancing fabrication processes. Programs such as these, along with a myriad of other academic and industrial efforts, have been instrumental in demonstrating the art of the possible by pushing device and circuit performance limits and evaluating intrinsic reliability, but have often focused on “hero” results. This session will describe current efforts to establish large-scale GaN MMIC production capability and discuss potential applications for these mature circuits. The session will open with an invited talk from the Defense Production Act Title III program office. This talk will provide an overview of Title III mission and describe the Manufacturing Readiness Assessment (MRA) process. Key Performance Parameters (KPPs) or objectives for current efforts will


also be reviewed. The following three talks will come from industry performers describing their Title III efforts and highlighting benchmarked performance levels, maturation process, yield, and reliability. The first of these performer talks will be from Raytheon (Andover, MA), who will discuss their efforts to optimize their production released coplanar waveguide (CPW) 28V X-band GaN MMIC process. The next two talks, one from TriQuint (Richardson, TX) and the other from Cree (Durham, NC), will describe their respective efforts on maturing their S-band and Wideband GaN MMIC process capabilities. Each performer will discuss current process status with respect to program baselines and provide examples of process centering activities. The final talk of the session comes from the Georgia Tech Research Institute (GTRI) and will describe the benefits and challenges of using GaN-based components in next generation transmit/receive (T/R) modules for active electronically scanned arrays (AESAs).

SESSION 5b: EPTIAXY & MATERIALSChairs: Guo-liang Zhou, Skyworks Solutions

Paul Pinsukanjana, IntelliEPI

Epi material is the foundation of compound semiconductor devices. This session focuses on epitaxial growth techniques and its process improvement. The session begins with an invited paper from Rodney Pelzel of IQE on the pros and cons of MOVPE vs. MBE growth technology for III-V epitaxial structures. The strength and limitations of each technology will be discussed from both technical and commercial aspects based on their first-hand experiences. The second paper from Yohei Otoki et al. of Hitachi Cable presents the results of GaN-HEMT and GaN p-n diode structure grown on low defect VAS (Void Associated Separation)-GaN substrates. The potential device performance improvement for GaN on VAS-GaN substrates vs. GaN grown on SiC substrates will be discussed. Nicole Killat et al. of University of Bristol investigated the correlation between the kink-effect of Fe-doped AlGaN/GaN HEMTs and the yellow luminescence (YL) from the correspondent epitaxial structure to explore the possible route for “kink-screening”. In this third paper, they conclude that the kink effect is resulted from a more complex trapping mechanism and is not solely related to YL defect states. Therefore, YL analysis does not present a suitable method for “kink screening”. The fourth paper presented by Sangmin Lee et al. of Cree focuses on thickness uniformity improvement of AlGaN epitaxial layer grown on 100-mm SiC substrate by improving the gas flow of their MOCVD reactor. They report a 25% improvement in the standard deviation of VT with no sacrifice of device performance and reliability. The final paper is presented by P. Waltereit et al. of Fraunhofer


Institute for Applied Solid State Physics on development of an epitaxial growth process on European SiC substrates. They evaluated material quality both at epiwafer level, as well as, at transistor level for the growth process on semi-insulating 6H-SiC(0001) substrates, and compared the results with the growth process on 4H-SiC(0001) substrates.

SESSION 6a: GaN PROCESS, DEVICE, & CIRCUITS

Chairs: Karen Moore, Freescale Semiconductor, Inc. Ming-yi Kao, TriQuint Semiconductor

The GaN Process, Devices, and Circuits session will span a range of topics for GaN process and device technology. One of the highlights of this session is that Cree and WIN Semiconductor will both present their new processes for 0.25 µm optical gate GaN HFET’s. The WIN paper will also feature their field plate process that is run with the 0.25 µm flow. These are particularly noteworthy as this is the first time Cree has presented its 0.25 µm production technology, and this is the first GaN paper presented by WIN.

We will also have three papers featuring use of dielectrics in GaN devices and processes. Koehler et al. from the Naval Research Laboratory and Universidad Politécnica de Madrid will discuss their investigation of Atomic Layer Epitaxy (ALE) AlN as a passivation layer for GaN devices, showing improvements in pulsed IV results and better performance than for PECVD SiN passivation. Md. Hasan from University of Fukui will share his results on the effect of sputtered SiN on the current collapse of GaN HEMTs, including the impact of both deposition temperature and anneal temperature on interface trap density. Finally, Osipove et al. from Ferdinand-Braun-Institut in Berlin will discuss their process for using thermally reflowed ZEP520A and CHF3/SF6 plasma etching for the formation of slanted gate trenches in SiN. A slanted gate profile has the potential to both improve metal conformality and to improve DC device performance via a slant field plate.

SESSION 6b: MANUFACTURING: TEST & CHARACTERIZATION

Chairs: Peter Ersland, M/A-COM Technology SolutionsHidetoshi Kawasaki, Sony

This Test and Characterization Session includes five papers covering a diverse range of measurement topics. We start with a paper from Skyworks which describes the electrical characteristics of a new Schottky diode implemented in their HBT and BiFET processes. Using


TaN for the anode contact they are able to achieve a significantly lower turn-on voltage than with traditional Ti/Pt/Au contacts. A thorough characterization of this new device will be presented. Staying with the characterization theme, the authors of our second paper have employed both electrical measurements and infrared (IR) microscopy to compare the thermal performance of flip-chip assembly to traditional backside die-attach in an HBT process. This paper from WIN Semiconductor shows roughly a 25% reduction in transistor self-heating when using copper pillars connected directly to the emitter fingers. The next three papers focus on improving production test effectiveness. Paper three of the session comes from Avago, and describes how the correct choice of DC probe hardware has resulted in both reduced probe damage of copper pillar bumps, and a reduction of false test failures during DC die sort testing of these circuits. The next paper in the session, also from Avago, presents a technique for assessing the level of probe contact resistance during PCM testing. An existing TLM structure is used to determine whether a specific probe card is capable of providing valid, low contact-resistance measurements. This in situ measurement validation technique eliminates questions of whether poor probe contact is the cause of wafer PCM test failure, thereby reducing the need for engineering intervention and re-testing of wafers. The final paper in this session comes from TriQuint Semiconductor, and offers a technique for dynamically setting pass/fail limits during final product test. This approach uses a robust moving mean and standard deviation to identify parts that meet the device specification limits, but are clearly outside the distribution of the tested population. Identifying an outlier immediately after it is tested allows the device to be sorted to the correct output bin, where it can be later analyzed to offer greater understanding of the cause for variation.

SESSION 7a: THERMAL DESIGN IChair: John Blevins, Air Force Research Laboratory

This session contains five exciting papers aimed at improving the thermal management of next generation gallium nitride power amplifiers. The first paper is an invited talk from DARPA highlighting their Intra/Interchip Embedded Cooling (ICECool) Program. Subsequent papers will present results achieved under DARPA’s Near Junction Thermal Transport (NJTT) Program. The NJTT Program is investigating thermal management approaches at the transistor level. The second paper by Northrop-Grumman explores the use of diamond filled vias for near junction cooling. The third and fourth papers are presented by BAE and Raytheon respectively who are pursuing techniques to integrate diamond films in close proximity to


the gallium nitride transistor active channel. Finally General Electric is investigating the formation of channels etched into silicon carbide substrates for active cooling of gallium nitride transistors.

SESSION 7b: TRAPS & TRANSIENTSChairs: Tom Low, Agilent Technologies

Chang-Hwang Hua, WIN Semiconductors Corp.

Traps continue to play an essential role in defining and constraining the performance of electronic devices fabricated in III-V and GaN based compound semiconductors. These traps include a wide variety deep level point defects which form at dielectric-semiconductor interfaces and semiconductor hetero-interfaces, as well as within the bulk of semiconductor active layers, buffer layers, and substrates. The energies, concentrations, and occupancies of these traps control “pinning” and determine device operating characteristics like FET I(V)’s and parasitic resistances. Moreover, changes in occupancy of charged trap states during device operation often dominate the transient and noise performance of FET devices.

This session contains an exciting collection of papers on the important topic of traps. The first is an invited paper by Prof. Roman Engel-Herbert describing and comparing various quantitative methods to measure the interface trap densities (Dit) at high-k/III-V interfaces using admittance measurements of MOS capacitor devices. The second paper, a collaboration between Drexel U., and U. of Notre Dame, shifts the focus from III-V’s to AlGaN/GaN HEMTs, and presents a study of evolution of strain and defect generation during the HEMT operation using analysis of HRTEM images in order more clearly understand reliability failure mechanisms in these devices. The third paper, a student paper from Ohio State, presents C(V) and I(V) data from ALD/AlGaN/GaN FET-like test structures which show correlations between dielectric-semiconductor charge density, channel mobility and conductivity, and gate leakage currents for very thin (6nm to 18 nm AlGaN layers which will be of interest for future MISHEMTs. The fourth paper, which continues on the AlGaN/GaN HEMT topic, is from the U of Bristol, and presents characterization data and simulation results for deep centers in the GaN buffer beneath the HEMT channel, and their relationship to time dependent HEMT characteristics, including both low frequency noise between 1Hz and 1000Hz, as well as dispersion in transconductance over the same low frequency range. The last paper in the session is from Skyworks MA and presents a pulsed I-V study in which their PHEMT switch technology was optimized to achieve remarkably fast 15nsec off -on transitions by appropriate choice of epi


design (varying trap density), gate recess dimensions, pre-passivation treatments of dielectric-semiconductor interfaces, and dielectric deposition conditions. This final paper is an excellent example of applying an understanding how traps produce transients in FETs and switching ICs to enable acceptable switching speed for the real world demands of time division TD based transceivers.

SESSION 8a: THERMAL DESIGN IIChairs: Andy Souzis, II-VI

Martin Kuball, University of Bristol

This session will continue the theme of the Thermal Design I session, in exploring improvements in thermal device management as well as thermal limitations to device operation. We focus on novel thermal design concepts, including further diamond materials integration on chip, device packaging and advanced thermal simulations developments and applications. Naval Research Laboratory reports on the benefits of diamond capping GaN electronics for heat sinking the devices, and challenges in device fabrication to consider. A further application of diamond, namely its use not in chip but in metal-diamond composites is explored by Georgia Tech, looking at benefits of these composites for example for die attached HPAs. In a further presentation the development of diagnostic structures particularly suited for GaN devices as test and evaluation tools is discussed to reduce packaging and thermal management system development cycles. University of Parma reports on thermal simulation development focused on that modeling cannot be confined to the device alone needing to consider also package, the heat sink, and finally the board, making a finite element model rather large. A lumped-element thermal model is developed to enable improved and simplified device simulations. Finally, TriQuint reports on the impact of the temperature non-uniformity within the finger on the InGaP/GaAs HBT safe operating area and on thermal “runaway”.

SESSION 8b: PROCESS – METALChairs: Suzanne Combe, TriQuint Semiconductor

Jansen Uyeda, Northrop Grumman AS

At the heart of the CS ManTech is the sharing of advancements in process methods, tools, metrology, and test that result in low cost manufacturing solutions for current and emerging compound semiconductor device technologies. Advancement is the outcome of thinking out-of-the-box and challenging conventional methods to achieve unique solutions. This is evident in this session for Process – Metals where we have five contributing papers;


two are focused on frontside metallization and three are focused on backside metal and bump processes. We begin with a paper from Skyworks Solutions which discusses advances in metrology for thin metal film characterization. During the transfer of Skyworks Solutions E-mode pHEMT technology to production, they applied an optical transmission technique to accurately characterize and match their critical gate metal deposition thickness on multiple e-beam evaporation systems. The second paper covers a novel lift-off approach developed by the Electronics Science and Technology Division of the Naval Research Laboratory (NRL) for selective patterning of material films deposited at high temperatures. NRL has circumvented the low temperature limitations of conventional photoresist methods by employing a bi-layer structure composed of silicon nitride (SiN) and germanium (Ge). NRL is exploring this novel in-organic lift-off approach for selective epilayer regrowth that will enable reduced contact resistances for GaN transistors. The third paper discusses demonstration of an electroless plating technique for palladium (Pd) with a crystalline adjuster. The authors are from the High Frequency & Optical Device Works group of Mitsubishi Electric Corporation. This technique enables an effective Pd diffusion barrier for backside copper (Cu) metallization on GaAs devices that is uniform and thermally stable. This work makes it possible to replace Au with the more cost-effective Cu for GaAs backside metallization. The fourth paper from TriQuint Semiconductor discusses a systematic approach they used to optimize their Cu bump process to address yield limiters identified during their production ramp-up. The authors review their work on optimizing their plating bath solution stability and plating bath hardware configurations, methods for operator training using videos, and implementation of 3-D automated optical inspection. We conclude the session with a paper from Freescale Semiconductor which discusses how they addressed challenges of transferring their GaAs RF power amplifier process to a different fab with different tool sets. The worked presented in this paper focuses on issues the authors observed with die bond voiding in their PbSn die attach assembly. They describe how they optimized their backmetal process and discuss related findings.

SESSION 9a: WIDE BANDGAP POWER DEVICESChairs: Toshihide Kikkawa, Fujitsu Laboratories

Shyh-Chiang Shen, Georgia Tech

This session will start with a discussion on SiC-based high-temperature, high frequency multi-chip power modules presented by Arkansas Power Electronics International. High-speed full H-bridge power modules were developed to exploit the advantages of wide bandgap


devices, power packaging, gate drivers and bus work for power systems. The session will continued with a discussion of emerging applications for GaN transistors in high-frequency electronics that can potentially offer an alternative technology platform that is currently dominated by silicon power MOSFETs from Efficient Power Conversion Corp. The presentation will be followed by a discussion of high-performance 600-V AlGaN/GaN high electron mobility transistors (HEMTs) developed by researchers at the Hong Kong University of Science and Technology. The GaN-on-silicon platform has been a center of research effort. Another paper from NXP semiconductor Research in Belgium will also present their work on GaN-based Schottky diodes and power switches fabricated in a Si-production Fab for 600-900 V operations. The session will conclude with a presentation on a high-power (180 W) L-band GaN-HEMT power amplifier module with 66% power added efficiency presented by colleagues from the Thales Alenia Space.

SESSION 9b: LED OUTLOOK & TECHNOLOGYChairs: Ruediger Schreiner, Aixtron SE

Gene Kohara, Marubeni Corporation

Manufacturing of Light Emitting Diodes (LEDs) has a long tradition for the semiconductor industry reaching back more than 35 years. The range of available wavelengths or colours, respectively as well as applications, however, has been accelerating incredibly over the last 5 to 10 years. This session will provide an outlook on some further aspects for LED manufacturing including cost reduction, improved performance or new applications. The first contribution, an invited paper presented by Sir Colin Humphreys from Cambridge University, will describe advantages and challenges from a technology and cost point-of-view as well as the realisation of LEDs manufactured by depositing GaN-based structures on 6 inch size Silicon substrates. Following this path, silicon established processing and automation can provide a significant improvement regarding achievable yields and related cost reduction in comparison to the use of Sapphire and SiC substrates. As the second invited contribution on this subject, Philippe Roussel from Yole will compare different paths to overcome challenges that have to be faced considering the growth of GaN-on-Si LED-structures by MOCVD. This includes the stress management between GaN and Silicon, materials of different lattice parameters and thermal expansion coefficient, the use of patterned Silicon substrates, as well as the application of nanoscale LED formation, including benefits and drawbacks for each of those approaches. A deeper insight into the potential from epitaxial growth of GaN-related LEDs on patterned sapphire substrates (PSS) versus flat ones will be given by


the presentation of H. Ogiya from Samco. Precise and reproducible formation for the requested hill-like pattern can be achieved using the plasma dry-etch process versus wet etching. Selection of appropriate preparation and fixture of the silicon substrate for the dry-etch process step as well as proceeding from micro- to nano-patterning (for example, from 1.8 µm to 200 nm pattern-/hill-height) allows one to significantly increase the total internal and external efficiency. The session will be concluded by a student presentation provided by Mong-Kai Wu from the University of Illinois. Hetero-junction bipolar light-emitting transistor (HBLET) demonstrates a unique three-terminal device that can simultaneously produce both electrical and optical output. The quantum wells (QWs) inserted in the base region remove slow carriers enabling high speed modulation up to 7 GHz. This paper reports about details on the further development of this device to a resonant cavity light-emitting transistor (RCLET), adding distributed Bragg Reflectors to sandwich the QWs which narrows the spectra and allows enhanced spontaneous emission.

SESSION 10a: MATERIALS: GaN EPIChairs: Judy Kronwasser, NOVASiC

Robert Sadler, Global Communications Semiconductors, LLC

This session reviews recent progress in the development of GaN HEMTs and diodes on a variety of epitaxial materials.

The first paper, by Veeco, looks at the use of low-cost silicon as the substrate for AlGaN/GaN HEMTs. They describe the layers of the heterostructure MOCVD growth that result in crack-free pseudomorphic growth on 6” silicon. They present the quality of the AlGaN barrier and the 2DEG performance.

In the next paper, Temasek Laboratories, et. al. of Singapore presents their study of the uniformity of sub-micron gate AlGaN/ GaN HEMTs on quarters of 8” (200-mm) silicon wafers. They conclude that their demonstrated results show the feasibility of achieving high uniformity on full 8” silicon wafers, for low-cost, high-power switching device applications.

The next two papers in this session are from collaborations between M/A-COM Technology Solutions and laboratories affiliated with MIT. They describe the development of two- and three-terminal high-voltage/high-current switching devices utilizing GaN on silicon. The first of these two papers describes the improvement of breakdown voltage for HEMT devices built on GaN on silicon, looking at the effect of gate-to-drain spacing and field plate design on both normally-off and normally-on devices. Results for GaN on silicon are compared to those


for other materials. The second of these papers reports double-field-plated Schottky diodes with up to 5000-V reverse breakdown voltage developed under a program sponsored by the U.S. Department of Energy.

The session concludes with a student paper from the University of Notre Dame. This work compares the results of GaN Schottky diodes on bulk GaN substrates with GaN on sapphire, specifically looking at the effect of dislocations on reverse leakage current and breakdown.

SESSION 10b: PROCESS – INTEGRATIONChair: Steve Mahon, Cascade Microtech, Inc.

Device and process technology is all well and good but if it doesn’t integrate into the environment or the system it has little chance of success. This session on Process Integration looks at a few perspectives of bringing it all the elements together.

We lead off the session with a paper from Taiwan, where a team from WIN, the world’s biggest GaAs foundry, describes layout practices for HBT circuits that can shrink die size and the performance tradeoffs involved in the various options. It is classic process and device layout integration to be used for getting more die and dollars out for every wafer.

Next, Skyworks reports an investigative look at the process and materials interaction on BiFET variation. The authors investigate FET geometry, using DOE, to flesh out the source of deviant FETs and its interaction with the process and material set.

The next two papers look outside the integrated circuit with filter elements and packaging technologies that provide the full integration that is driving our industry’s growth. The filter group at TriQuint gives us an update on the tremendous progress in performance of Bulk Acoustic Wave (BAW) filters that is making it the preeminent filter technology for mobile devices. This paper will also present the advanced wafer-level-packaging (WLP) that allows BAW devices and CS devices to be compactly integrated. Dr. Karlheinz Bock looks further out on the possibility of the integration of our high frequency CS devices with flexible circuits and flexible interconnect. These low cost techniques open the window to even higher volume in the future.

We bring it all home with a paper that tackles the long-standing problem of hermetic coating of CS devices. An author at TriQuint uses finite element analysis to model the proper conditions for crack free nitride passivation – a classic problem.

This not-to-miss session is sure to have something for everyone!


SESSION 11a: GaN GATE DIELECTRICSChair: Patrick Fay, University of Notre Dame

In this session, insulated-gate GaN FETs and the properties of the insulator/nitride interface are the focal point. The session opens with an invited talk by Prof. Hashizume of Hokkaido University on the characterization and control of interfaces between insulator and GaN-based materials for FET applications. This is followed by a student paper from Georgia Tech describing recent results on ALD-deposited Al2O3 films for use as gate dielectrics in III-N devices. The third paper, by authors from ROHM and the Univ. of Fukui, describes the use of thermal oxidation to control interface state densities between etched GaN surfaces and ALD-deposited Al2O3. A student paper from the Univ. of Illinois describes the performance obtained in a fluorine-treated AlGaN/GaN insulated-gate HEMT with a two-layer gate oxide based on Al2O3 and SiO2. The session finishes with a paper from Raytheon describing the performance and reliability of insulated-gate HEMTs and MMICs fabricated on Si substrates.

SESSION 11b: YIELD ENHANCEMENT AND MANUFACTURING

Chair: Marty Brophy, Avago Technologies

Session 11b covers Yield Enhancement and Manufacturing, which are two topics that are near and dear to all our hearts! A big part of svelte manufacturing is making your equipment behave itself, so the session starts out with an invited talk from Dave Brindza and Travis Abshere from TriQuint Oregon, one of the biggest GaAs fabs in the world. They discuss the challenges of taking care of the mix of new and old tools many of our CS fabs have. Shiny new tools, tried and true workhorse tools, and the old usually cantankerous legacy tools all need their own kind of hand-holding, which the authors discuss with specific details from their experience. Come and learn some of the hard-won lessons from these very experienced engineers!

Next, we learn from Nirav Thakkar how the Skyworks fab in Newbury Park has used factory automation software for everything from tracking use of precious metals to attending to equipment, to spare parts control, recipe downloading, Cpk monitoring, and even ESD control. This promises to be a good talk from which to gather concepts to take home and try out for yourself.

A proper staff level for the mission is as important as documentation, SPC, training, utilization and a good operations manager. To illustrate this, MAX I.E.G. will present a case study to optimize the direct labor (DL) staffing level at a medium size semiconductor fab that


resulted in a 5% reduction in DL costs while maintaining or improving tool utilization.

We finish with two more yield improvement talks from TriQuint Oregon. Tertius Rivers and his team describe how they used application-specific DC die sort test and concentrated yield analysis to find and root out sources of die scrap in a 1 pole, 7 throw PHEMT switch. That RF part was seen to have defect-limited yields, a first in TriQuint’s long history of fabricating GaAs IC’s. Automated Optical Inspection and other methodologies to measure then reduce defect densities paved the way for high yielding switches. And this very interesting session ends with Weng and Saeger, also from TriQuint, discussing how they have been able to do both front- and back-side automated visual inspection of Cu Pillar Bump die after singulation. The inspection occurs during the die pick-and-place to tape-and-reel, at minimal cost and low increase to cycle time. Cheap and fast, something sure to make your management happy!

SESSION 12: INTERACTIVE FORUMChairs: Kelli Rivers, Materion

Corey Nevers, TriQuint SemiconductorJansen Uyeda, Northrop Grumman AS

Following the tradition initiated in 1994, the Interactive Forum is a session devoted to promoting the open exchange of ideas and information. This session allows for discussions and face-to-face meetings between the authors and conference attendees. In 2013, the Interactive Forum will change slightly in that it will feature only authors presenting their original material outside of an oral session-think of it as an Interactive Poster Forum. Historically, all oral session presenters were also asked to also be available with a poster during this time, but not this year. All attendees and presenters are heartily invited to come and review a select group of papers in this session, where one can enjoy a beverage and spend some time really discussing the work presented. This will take place in a relaxed setting with room to move, where the authors will be available and show their work on 4’x6’ boards – a nice way to start winding down from a busy CS ManTech week.

This Forum will be the only time at the conference where papers that have been selected for the Interactive Forum only will be displayed. These papers demonstrate in a beautiful way the true nature of CS ManTech as the integrative conference in compound semiconductors: participants from industry and academia; from Asia, Europe and North America; presenting their valuable results generated from basic GaN process development, defect reduction, transistor lasers, process monitoring,


evaporation improvements, process monitoring and a few papers on uses of BCB. In short: CS ManTech at its best!

Attendees of the Interactive Poster Forum will enjoy a unique way to view research, catch up with colleagues, perhaps solve a few problems and also vote for the best poster. The winning author will receive the Best Poster Award and also a nice prize to boot!

GENERAL INFORMATION

2013 International Conference on Compound Semiconductor Manufacturing Technology

May 13th - 16th, 2013Hilton New Orleans Riverside

2 Poydras Street New Orleans, LA 70130

REGISTRATION INFORMATION (US$)

For Advanced Conference Registration, register online at our Web Site by April 22rd.

www.csmantech.org

On or before Apr. 22 After Apr. 22Full Conference Registration $580 $680Student Conference Registration $125 $125Government Conference Registration $580 $580One-Day Conference Registration $300 $300** New Low Price **Workshop Registration $175 $275Government Workshop Registration $175 $175

Payment of the full, student, or government conference registration fee includes one copy of the printed Conference Digest (if desired), one copy of the Conference Digest on a USB memory stick, and admission to all sessions and the exhibits. It also includes the International Reception, Exhibits Reception, Exhibits Luncheon, Rump Session Reception, Interactive Forum Reception, continental breakfasts, and refreshment breaks. Additional copies of the Conference Digest may be purchased at $140 each. Additional copies of the Conference Digest on a USB memory stick may be purchased for $50 each.

The one-day registration includes admission to all sessions for that day, admission to the Exhibits Hall, buffet breakfast, break refreshments, and lunch. The Rump Session Reception or Interactive Forum Reception is included on Wednesday and Thursday, respectively. It also includes a printed Conference Digest and a Conference Digest on a USB memory stick. The one-day registration does not include admission to the International Reception. The one-day option can be taken only once during the


conference.Payment of workshop registration includes one copy of

the Workshop Digest, continental breakfast, Workshop Luncheon and break refreshments. Additional copies of the Workshop Notes may be purchased at $100.

Registrants may pay by check, money order, bank draft or credit card. Make checks payable in U.S. dollars drawn on a U.S bank to: “GaAs ManTech, Inc.” Your name and address must appear on checks, money order or bank drafts. The only acceptable credit cards are Master Card, VISA, and American Express. REGISTRATION FORMS SENT WITHOUT PAYMENT WILL NOT BE ACCEPTED. All refund requests must be received by Chris Santana at the CS MANTECH office shown below by April 10th for a full refund less a $25 processing fee. NO REFUNDS AFTER APRIL 10, 2013.

CS MANTECH14525 SW Millikan Way #26585 Beaverton, Oregon 97005-2343

For Advanced Conference Registration, register online at our Web Site by April 22nd.

www.csmantech.org

HOTEL RESERVATIONS

CS ManTech has arranged for a discounted nightly rate at the Hilton New Orleans Riverside. This rate is available for CS ManTech participants and their guests. For single or double occupancy, rooms maybe reserved as follows:

-Prepaid, non-refundable at $197/night ($20/night saving)-Guaranteed by Credit Card at $217/night

The CS ManTech rate includes free guest room internet access, a 50% discount on Health club access and discounted Hotel parking. State and local occupancy taxes (currently 13% and $3, respectively) will be added to these rates. For those wishing to extend their stay, a limited number of rooms are available at the group rate before and after the conference on a first come, first served basis.

Please note that if guaranteed by credit card, one night’s room and tax will be charged if the reservation is cancelled less than 72 hours prior to arrival. Also, the Hilton will assess an early departure fee of $90 for any guests electing to check out ahead of their planed stay.

Hotel reservations may be made through either:


o The CS ManTech website www.csmantech.org o Calling toll free: 1-800-HILTONS within North

America. o Calling the Hilton Riverside Directly.

When calling either the toll free reservations number or the Hotel directly, please request the CS ManTech group rate. To receive the CS ManTech rate, Hotel reservations must be received BEFORE April 11 th , 2013. Reservations made after this date will be subject availability and to the prevailing rates at the Hilton.

If you require the US Government rate (ID required) please call the Hilton Riverside directly and notify them you are attending CS ManTech.

The discounted rate is subject to availability, so please MAKE YOUR RESERVATION EARLY!

We ask you to please support CS ManTech and to enjoy all of the conference activities by staying at our official 2013 location, the Hilton New Orleans Riverside.

CONFERENCE REGISTRATION & INFO CENTER

Conference registration will open at on the 3rd floor of the Hilton Exhibition Center on Sunday night and will be open Monday through Thursday. Please refer to the “Conference At A Glance” for specific hours of operation. A Conference Attendee list will be available at the Registration Center on Thursday, May 16th.

MESSAGE BOARD

A Conference Message Board will be maintained at the Registration & Information Center during registration hours. Please advise callers who wish to reach you during the day to ask the hotel operator to deliver a message to the CS ManTech Conference Registration Desk. Please check the message board periodically.

THE CONFERENCE HOTEL

The Hilton New Orleans Riverside is located in a prime downtown location on the banks of the Mississippi River, adjacent to the Ernest Morial Convention Center. The Hotel features over 1600 guestrooms, all with convenient and immediate access to the conference meeting rooms. The Hilton features one of the most expansive and best


http://www.csmantech.org/

equipped, health clubs in New Orleans, including 2 heated outdoor pools. A number of dining options are available within the Hotel, including Drago’s, one of New Orleans best known Seafood restaurants. Penfield’s Business Center offers round-the-clock email, fax and photocopying facilities. A full concierge service is available to assist booking tours and events in New Orleans

The Hilton is connected to the Riverwalk Marketplace, featuring over 100 distinctive New Orleans shops and eateries. It is within easy walking distance of the fabled French Quarter with its world renowned selection of music, dining and nightlife venues. Harrah’s casino is immediately adjacent to the Hilton and offers round-the- clock entertainment opportunities. The Audubon Aquarium, Zoo and Insectarium are a short walk away. Royal Carriage tours and Riverboat tours are also within easy reach.

TRANSPORTATION TO THE HOTEL

The Hilton Riverside can be reached by car, taxi or shuttle bus from New Orleans Airport:

Taxi: Taxis are available at the airport. Taxi rates from the airport to the Hilton Riverside are approximately $35.00 one way for up to 2 people. Each additional person is $14.

Car: The Hilton has ample parking. The CS ManTech reduced rate is $28 per night.

Shuttle bus: Downtown New Orleans is served by Airport Shuttle. One way fare is $20 and Advance reservations are highly recommended. Reservations can be made at www.airportshuttleneworleans.com or by calling 504-522-3500

FINANCIAL ASSISTANCE

CS ManTech encourages presentations and participation by academic delegates. To support this participation, limited funding is available to support travel and conference attendance by student presenters. Please see http://www.csmantech.org/students/students.html for details on applying for financial assistance.


http://www.csmantech.org/students/students.html

http://www.airportshuttleneworleans.com/

HILTON NEW ORLEANS RIVERSIDE LOCATION ANDMEETING ROOM LAYOUT


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