doc.: ieee 15-05-0451-00-004a submission july 2005 slide 1 sait/ire project: ieee p802.15 working...

July 2005

Slide 1

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)

Submission Title: Test Results of Low Clock Rate Non-coherent Chaotic Ranging SystemDate Submitted: July 2005

Source: (1) Young-Hwan Kim, Jae-Hyon Kim, Chia-Chin Chong, Su Khiong Yong, Seong-Soo Lee, (2) Haksun Kim, Kwang Doo Lee, Chang Soo Yang, (3) Hyung Soo Lee, (4) Kyung Sup Kwak, (5) Jaesang Cha, (6) A. S. Dmitriev, A. I. Panas, S. O. Starkov, Yu. V. Andreyev, E. V. Efremova, L. V. Kuzmin

Company: (1) Samsung Electronics Co., Ltd. (Samsung Advanced Institute of Technology (SAIT)), (2) Samsung Electro-Mechanics Co., Ltd. (SEM), (3) Electronics and Telecommunications Research Institute (ETRI), (4) UWB-ITRC, Inha University, (5) Seokyeong Univ.,(6) Institute of Radio Engineering and Electronics (IRE),

E-Mail: [email protected]

Re: [Response to IEEE 802.15.4a Call for Proposals (04/380r2)]Abstract: [Proposal for the IEEE 802.15.4a PHY standard based on the chaotic UWB system technology.]Purpose: [Proposal for the IEEE 802.15.4a PHY standard.]

Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein.Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15.

July 2005 doc.: IEEE 15-05-0451-00-004a

Slide 2Submission

SAIT/IRE

Test Results of Low Clock Rate Non-coherent Chaotic Ranging System

Presented by: Jae-Hyon Kim

Samsung Advanced Institute of Technology (SAIT)Institute of Radio Engineering and Electronics (IRE)

July 2005

Slide 3

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Objective

• To provide the real hardware test results of non-coherent ranging system based on chaotic signal

• To show the low cost solution using low rate clock (2.500 MHz) for non-coherent ranging system

• To show the low hardware complexity of chaotic source when it is implemented in CMOS

July 2005

Slide 4

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Chaotic Signal• Chaotic signal is flexible enough to accommodate to Burst PPM

or Burst OOK non-coherent ranging system

Chaotic PPM

Burst OOK

Option-I (Burst PPM)

Chaotic OOK

ChaoticSource(option)

Impulse

July 2005

Slide 5

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Video Recording of Experiments

July 2005

Slide 6

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Direct Chaotic UWB System

Chaos Generator

Microwave Amplifier

DemodulatorLow noise amplifier

Digital Board

Inverter 1

Inverter 2

Modulator and

Switch

Input PC signal

Output signal to PC

No need Conventional UWB RF Devices nano scale time synchronization

Up/Down Mixer , PLL

July 2005

Slide 7

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Tx= (N3+0.5N2)/f1 – (N1+0.5N2)/f0

distanceS = 0.5*c*(Tx-0)

N1, N2, N3 – pulse numbers

0 – retranslation timet0 t1t2 t3

С1

С2

C3: Ref clock

Tx

N1

N2

N3

Operation time of counters C1,C2,C3.

t**

Low Clock Rate Ranging Method

Delayed pulse Reference pulse

This ranging algorithm can be applied to a system that compare the reference clock and the received waveform or only by comparison of two different rate of clock waveform

delayed pulses(2.500 MHz) and reference pulses(2.5025 MHz)

July 2005

Slide 8

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Low Clock Rate

• Implementation example of two synchronized clocks with 2.500 MHz and 2.5025 MHz rates

Programmable Waveform Generator

Clock source

CPLD

20 MHz

2.500 MHz

2.5025 MHz

Control unit (Digital Block )

AD9833

Programmable Waveform Generator can be implemented by means of AD9833 chip (Analog Devices)

July 2005

Slide 9

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Cable Experiment

Target

RF cableTRF TLF+

- Propagation delay through the RF cableTRFTLF - Propagation delay through the LF wire

July 2005

Slide 10

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Mean-Square Error <σ> = 1.3 ns

Test Results of Cable Experiment

July 2005

Slide 11

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

TransceiverTarget

LF wire

TRF TLF+

- Propagation delay through free spaceTRF

TLF - Propagation delay through the LF wire

Wireless experiment

July 2005

Slide 12

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Error RMS = 0.6 ns (0.18 m)

Test Results of Wireless Experiment

July 2005

Slide 13

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Features of Chaotic UWB Technology

Feature Chaotic UWB Non-coherent Pulse UWB

1. Power consumption ▲

2. Simplicity realization ×

3. Synchronization ×

4. Critical to antenna ×

5. Multipath immunity ▲ ▲

6. Location ▲ ▲

7. Distance

8. Data rate, scalability

- Better ▲ - Even ×-Worse

Low Power Consumption ( 10mW )

Simplicity of Hardware Structure ( Low Cost Realization )

Easy Synchronization ( Low Cost Realization )

Not critical to antenna performance

July 2005

Slide 14

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Chaotic Generator (CMOS IC)

vo

chotic_Filter2X26

RR94R=50 Ohm

RR91R=15 kOhm

V_DCSRC17Vdc=1.8 V

CC51

tsmc018_rfpmos2vrfpmos2v21

tsmc018_rfnmos2vrfnmos2v22

gnd

mimcap_shield_TTX22

BottomTop

Shield

RR92

RR85

RR86



RR90 gnd

mimcap_shield_TTX24

Bott

omTo

p

Shield

RR87



gnd

mimcap_shield_TTX23

Bott

omTo

p

Shield

RR88



RR83

RR84

RR89




RR95

CMOS IC (On Chip)

BPF (Off Chip)

Power Consumption:6.4mW(3.6mA, 1.8V)

Very Simple Architecture Without Inductors

• 5stage Ring Oscillator

July 2005

Slide 15

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Chaotic Generator (CMOS IC)

300um

200um

• Layout of the 5stage Ring Type Generator

July 2005

Slide 16

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Conclusion• Chaotic system is a low cost, low power solution for

non-coherent communications and ranging system • Easy to synchronize and it is not critical to antenna

performance

• The simulation results against multipath will be provided soon.

Note:Please refer to Appendix A and B for more information related to the ranging error estimation and the Chaotic source implementation in CMOS respectively.

July 2005 doc.: IEEE 15-05-0451-00-004a

Slide 17Submission

SAIT/IRE

Appendix A

Ranging Error Estimation

July 2005

Slide 18

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

(Appendix A) Ranging (1)

10

11

ff 5.20 f

5025.21 f

Error estimation concerning the generator frequency drift

Basic assumptions:• Two pulse sequences are generated, the first one is video pulses andthe second one is chaotic;• The generator has some frequency drift;• As two sequences have one origin, their frequency drifts are synchronized;• The frequency drift depends linearly on the time;• There is constant error in time estimation because of finite resolution of the generator;

MHz - frequency of the chaotic pulses sequence

MHz - frequency of the video pulses sequence

4.0Error from the finite resolution ns

July 2005

Slide 19

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE


a

nnd

21 2

21

Synchronized drift: T2=T1(1+a), a=const.

T1 – period of the video pulse sequence, T2 – period of the chaotic pulse sequence

Periods are changed linearly (according to basic concepts);

T1=T10+d1n, T2=T20+d2n,

n – the number of pulses, d1, d2 – drifts of sequence periods

For the time error estimation because of drift we have the formula

According to model: a~10-3; n~103

For drift D = 20 ppm, d1 = 2T1D×10-12 = 2*400×20×10-12 = 16×10-9 ns

Then the error is = 8×10-6 ns

Example of calculation:

July 2005

Slide 20

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE


ppm 2 5 10 20

Δτ, ns 8×10-7 2×10-6 4×10-6 8×10-6

dl, m 0 0 0 0

Dependence of the time and distance errors on the drift of the generator frequency

July 2005

Slide 21

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

(Appendix A) Ranging (1)Derivation of drift error estimate

Periods of the two sequences: T1=T10+d1n, T2=T20+d2n;

Basic expressions for time estimation: n1T1 = + n2T2 (1) with drift

n1T10 = 0 + n2T20 (2) without drift

The sequences are synchronized, then d2=d1+a;

T1,T2 are arithmetical progressions, then in n1 and n2 steps (1) is

Subtracting (2) from (3), we have the error

For majority of distances (0-60 m): n1=n2+1, then

2122

1

221

22

1

2

2

22

1

2

1

2)1(

11

2ndan

d

nondan

da

nn

d

0 ))1(( 2

221 nan

)3(22

22202

11101

ndTn

ndTn

July 2005

Slide 22

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

(Appendix A) Ranging (2)Derivation of drift

The period of the sequence is T1n=T10+d1n

If generator drift is D ppm (D pulses per million pulses), then for million original pulses there is (106-D) drifting pulses, so

but 106 T10 = (106-D)(T10 + dT10(106-D)/2)

Hence, d 2DT10×10-12

July 2005 doc.: IEEE 15-05-0451-00-004a

Slide 23Submission

SAIT/IRE

Appendix B

Chaotic Generator and Receiver

July 2005

Slide 24

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Contents

System Spec.

Frequency Plan

System Link Budget

Transmitter Block Design

Receiver Block Design

July 2005

Slide 25

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Parameter Specification

Bandwidth(3dB BW ) 494 MHz

Center Frequency(MHz) Band1: 3458, Band2: 3952, Band3: 4446(Option)

Tx Out Power -41.3dBm/MHz (FCC UWB Emission Mask)

Tx Power Consumption 20 mW (11mA)

Rx Sensitivity -70dBm

Rx Power Consumption 23 mW (13mA)

Die Size 2mm X 2mm

Data rates 1024 kb/s

Modulation Direct Chaotic-OOK + 15Chips spreading

Demodulation Envelope Detection / Non-Coherent

System SpecificationSystem Specification

July 2005

Slide 26

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Band No. 3 dB BW

(MHz)

Low Freq.

(MHz)

Center Freq.

(MHz)

High Freq.

(MHz)

1 494 3211 3458 3705

2 (mandatory) 494 3705 3952 4199

3 494 4199 4446 4693

4 1482 3211 3952 4693

3 4 5 GHz3.5 4.53.25 3.75 4.25 4.75

Note: This plan has almost double margin to 4.9 GHz as compared to 3.1 GHz

1 2 3

Band No. 4

207MHz

111MHz

Proposed Frequency Plan

July 2005

Slide 27

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

IEEE802.15.4a System PHY StructureSystem PHY Structure

Chaotic RF Receiver

Chaotic RF Transmitter Digital Modulator

Control Logic & Resisters

MAC H/W

Ranging Detection

Digital Demodulator

RF System Block MODEM System Block

DC Power Control

Wake-up Receiver

July 2005

Slide 28

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Chaotic Transceiver Block Diagram

A

B

E

C

D HF G

A

H

GE F

B

C

D

Modem

July 2005

Slide 29

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Pramerer Value

Peak payloard Bit Rate(Rb) X0=1024Kb/s

Bandwidth 500MHz

Average Tx power(PT) -14.3dBm

Tx antenna Gain(GT) 0dBi

Center frequency(MHz) 2458

Path Loss at 1 meter (L1) 44.43dB

Path loss at d=30m (L2) 29.54dB

Rx antenna Gain(GR) 0dBi

Rx power (PR= PT + GT + GR -L1-L2 (dB)) -88.3dBm

Average noise power per bit (N=-174+10*log(Rb) -113.9dBm

Rx Noise Figure(NF) 7dB

Average noise power per bit (PN=N+NF) -106.9dBm

Minimum Eb/N0(S) 15.5dB

Implementaion Loss(I) 3

Link Margin (M=PR-PN-S-I) 0.1dB

Proposed Min.Rx Sensitivity Level -88.4 dBm

System Link Budget & Sensitivity500MHz Bandwidth

July 2005

Slide 30

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

ChaoticGenerator

Antenna

Mod(OOK)

ChaoticGEN

Power Amp Chaotic

Mod(OOK)

Power Amp

Tx_Data_in

BPF0 1 0 1 0 1 0

Modulator

Chaotic Transmitter

0

1

0

1

0

1

0

1

0

1

0

1

3 0 0 4 0 0 5 0 0 6 0 0 7 0 02 0 0 8 0 0

- 0 . 5

0 . 0

0 . 5

- 1 . 0

1 . 0

t i m e , n s e c

vo

, V

Ou

tpu

t(V

)

Time(nS)Performance of Transmitter Defend on Chaotic Signal Characteristics

Poor Isolation of Modulators Can limit a Dynamic Range of Chaotic signals

July 2005

Slide 31

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

vo

chotic_Filter2X26

RR94R=50 Ohm

RR91R=15 kOhm

V_DCSRC17Vdc=1.8 V

CC51



gnd

mimcap_shield_TTX22

BottomTop

Shield

RR92

RR85

RR86



RR90 gnd

mimcap_shield_TTX24

Bott

omTo

p

Shield

RR87



gnd

mimcap_shield_TTX23

Bott

omTo

p

Shield

RR88



RR83

RR84

RR89




RR95

CMOS IC (On Chip)

BPF (Off Chip)


Very Simple Architecture Without Inductors

• 5stage Ring Oscillator

Chaotic Source (II) Chaotic Generator (I)

July 2005

Slide 32

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

5 10 150 20

-150

-100

-200

-50

freq, GHz

dbm

(fs(v

o))

100 200 300 400 500 600 7000 800

-10

-5

0

5

10

-15

15

time, nsec

vo, m

VChaotic Source (II)

Chaotic Generator (I)Simulation Result

Chaotic Signal in Frequency Chaotic Signal in Frequency DomainDomain

Chaotic Signal in Time DomainChaotic Signal in Time Domain

July 2005

Slide 33

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

300um

200um

Layout of Chaotic Source (II)

• Layout of the 5stage Ring Type GeneratorChaotic Generator (I)

July 2005

Slide 34

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

• Block Diagram of Advanced Chaotic Generator

BPF Vout

Mixer

C1 C2R1 R2

R3 R4 R5


Chaotic Signal Generation by Mixing Pulse Signals

Very Stabile Chaotic Signal Generation

Chaotic Source (III)

Out_VOut_V

In_VIn_V

Chaotic Generator (II)

July 2005

Slide 35

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

50 100 150 200 250 300 3500 400

-10

-5

0

5

10

-15

15

time, nsec

vo, m

V

5 10 15 20 25 30 35 400 45

-150

-100

-50

-200

0

freq, GHz

dbm

(fs(

vo))

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00.1 1.1

0.1

0.2

0.3

0.4

0.0

0.5

a5

in2

Ou

t_V

In_V

75.0 75.5 76.0 76.5 77.0 77.5 78.0 78.574.5 79.0

-6

-4

-2

0

2

4

6

-8

8

time, nsec

vo, m

V


Simulation Result

Chaotic Phase PortraitChaotic Phase Portrait

Chaotic Generator (II)Chaotic Signal in Frequency Chaotic Signal in Frequency

DomainDomain

Chaotic Signal in Time DomainChaotic Signal in Time Domain

July 2005

Slide 36

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE


Very Sensitive to the Current and Impedance

BPF acts on Chaotic Mode Resonator and

Band Selection Filter

• Colpitts Chaotic Generator

ColpittsColpitts

C1C2

RL

RS

L

VDD

BPF

Out

R1

R2

iD

iBPF

iG

1 2

1 2

1

2resof

C CLC C

July 2005

Slide 37

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

C41

L1 L2 L3

C1 C2 C3

C4 C5

C6

R1 R2

VDD

INput

OUTput

Power Amplifier

-70 -60 -50 -40 -30 -20 -10-80 0

-40

-30

-20

-10

0

10

-50

20

Pin

dBm

(Out

put[:

:,1])

2 3 4 5 6 71 8

-10

0

10

20

30

40

-20

50

freq, GHz

dB

(S(2

,1))

3stage Cascode Power Amplifier

Gain: 35dB, P1dB: 10dBm

Power Consumption:14.4mW(8mA, 1.8V)

R-C Shunt Feedback to Improve Stability and

Wideband Frequency

July 2005

Slide 38

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Tunable Piconet Filter

2.5 3.0 3.5 4.0 4.5 5.0 5.52.0 6.0

-50

-40

-30

-20

-10

-60

0

freq, GHzdB

(S(1

,2))

.

3 Band(BW:500MHz) Tunable Interdigital Filter

Capacitance Varied by Voltage in Varactors

Due to the Parasitic of the Varactor, Implementation is

Very Difficult

Port1

Port2 Varactor Varactor

0 V 0 V 0.7 V 0.7 V

1.5V 1.5V

July 2005

Slide 39

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Chaotic Receiver

TunablePiconet Filter

Antenna

Detector

A/D

LPF

Rx_Data_outLNASwitch

RSSIA/D

AGC AmpTunable

Piconet FilterAntenna

Detector

A/D

LPF

Rx_Data_outLNA

RSSIA/D

Non-Coherent Receiver

Direct Digital Communication in Air Using a Stream Chaotic Radio Pulses

Robustness against Internal System Noise

Design Goal: Low Cost and Low Power Consumption

July 2005

Slide 40

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Low Noise Amplifier

L1 L2 L3 L4

C3 C5 C7AMP1 AMP2 AMP3 AMP4C1

C_total C_total C_total C_total

IN OUT

4stage Low Noise Amplifier Functioning as BPF of 4 Poles

Gain: 48dB, P1dB: 9dBm, Noise Figure: 2.6dB

Power Consumption:19.8mW(11mA, 1.8V)

Due to the BPF Characteristics, Architecture of Receiver can be Simple

Due to the poor sensitivity of detector, it is required to get enough gain at the front end of receiver.

July 2005

Slide 41

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

2 3 4 5 6 71 8

-10

0

10

20

30

40

-20

50

freq, GHz

dB

(S(2

,1))

2 3 4 5 6 7 8 91 10

4

6

8

10

2

12

freq, GHz

nf(2

)

-90 -80 -70 -60 -50 -40-100 -30

-40

-20

0

-60

20

Pin

dBm

(Out

put[:

:,1])

Low Noise AmplifierSimulation Result

GainNoise Figure (dB)

Out Power

July 2005

Slide 42

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

C1 R1

R2

VDD

INput-V

+V

OUT

-IN

+IN

OUTput

R3

R4

R5

Schottky Diode

300 400 500 600 700200 800

0

200

400

-200

600

time, nsec

vo2,

mV

300 400 500 600 700200 800

0.5

1.0

1.5

0.0

2.0

time, nsec

Vou

t4, V

300 400 500 600 700200 800

-1.0

-0.5

0.0

0.5

-1.5

1.0

time, nsec

vo, V

Envelope DetectorSignal Waveforms

July 2005

Slide 43

doc.: IEEE 15-05-0451-00-004a

Submission

SAIT/IRE

Conclusion RemarksNon-Coherent CMOS Transceiver IC Design

. 3 Type Chaotic Generator

. Piconet Band Pass Filter

. Power Amplifier

. Low Noise Amplifier

. Envelope Detector

We have Proposed the Power Consumption and Chip Size of the Chaotic UWB Transceiver

The Feasibility of Chaotic CMOS Implementation was Proved by Simulation

We are going to test CMOS Chip of Chaotic UWB Transceiver from now on

doc.: ieee 15-05-0451-00-004a submission july 2005 slide 1 sait/ire project: ieee p802.15 working...

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