dmaps (depleted cmos pixels) development and results at the … · 2018. 11. 19. · dmaps...
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DMAPS (Depleted CMOS Pixels) development and resultsat the University of Bonn
Norbert Wermes
[email protected] AIDA-2020 – Annual Meeting- DESY - 15.06.2016
High Luminosity LHC Environment - Requirements
[email protected] AIDA-2020 - Marseille - 13.05.2016
ATLAS Phase II Letter of Intent
Oc
cu
pa
nc
y [
%]
Inner layer1. Low power2. Low material3. Occupancy4. Resolution
1. Low cost2. Low power3. Low material4. Resolution
outer
Inner
Outer layer
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[email protected] AIDA-2020 - Marseille - 13.05.2016
Hybrid Pixel Detectors Monolithic Pixels
Hybrid Monolithic
charge collection time fast (drift) slow (diffusion)
cost high low
material high low
pixel size medium small
radiation resistance high low/medium
signal high low
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[email protected] AIDA-2020 - Marseille - 13.05.2016
Hybrid Pixel Detectors Depleted Monolithic Pixels
Hybrid Depleted Monolithic
charge collection time fast mainly diffusion fast
cost high low
material high low
pixel size medium small
radiation resistance high low/medium high
signal high low high
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[email protected] AIDA-2020 - Marseille - 13.05.2016
Bulk process options (simple options, n-on-p)
Electronics inside charge collection well
Collection node with large fill factor rad. hard
Large sensor capacitance (DNW/PW junction!) x-talk, noise & speed (power) penalties
Full CMOS with isolation between NW and DNW
Electronics outside charge collection well
Very small sensor capacitance low power
Potentially less rad. hard (longer drift lengths)
Full CMOS with additional deep-p implant
p-substrate
Deep n-well
P+ p-well
Charge signal
Electronics (full CMOS)
P+nw
p-substrate
n+ p-well
Charge signal
Electronics (full CMOS)
n+nw
deep p-well
- -
larger capacitance makes it more difficult for the readout -> more power
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[email protected] AIDA-2020 - Marseille - 13.05.2016
Fill Factor influence at 1015 neq/cm2
NW: 20VPW: 0V
Substrate:2k Ohm cmDose: 1015 neq/cm2
Electron Velocity
fill factor = 15% fill factor = 75%
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[email protected] AIDA-2020 - Marseille - 13.05.2016
Summary
% of collected charge in first 10ns
no radiation
1013
neq/cm2
1014
neq/cm2
1015
neq/cm2
substrateresistivity[Ohm cm]
Bias [V]
Fill Factor[%]
10 1 15
10 20 15
2k 1 15
2k 20 15
2k 20 750
10
20
30
40
50
60
70
80
90
100
5x1015
neq/cm2
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[email protected] AIDA-2020 - Marseille - 13.05.2016
ESPROS Photonic CMOS™
Chip size: 1.4×1.4 mm2
OHC15L • 150 nm process (deep N-well/P-well)• Up to 7 metal layers• Resistivity of wafer (n-type): >2000 Ω·cm• Backside processing• 50um thin
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[email protected] AIDA-2020 - Marseille - 13.05.2016
EPCB01 Fe55/Laser
Gain: ~ 100 µV/e (200 mV ~ 2 ke)Power: ~5uWPeaking time: <25nsSahping time: ~200ns-2us (for continous reset)
Fe55 and baseline spectrum (single pixel 40x40um) Backside laser scans (@~12V)
T. Obermann, Bonn
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[email protected] AIDA-2020 - Marseille - 13.05.2016
Capacitance
CAP1Diode bias D2
CAP3Diode bias D1
CAP4Dummy cell
[fF] 8.6 11 3.2
[fF] 6.8 11.1 -
T. Obermann, Bonn
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XFAB XT180
XT180: • XFab 180 nn HV-SOI• Up to 7 metal layers• Resistivity of wafer: 100 Ω·cm
XTB01 and XT02 prototypes: • Pixel pitch: 15, 50, 100um• Chip size: 2.5 mm x 5 mm
AIDA-2020 - Marseille - 13.05.2016 18
XT02
[email protected] AIDA-2020 - Marseille - 13.05.2016
TCT, I. Mandić, B. Hiti et al.,Jožef Stefan Institute, Ljubljana, Slovenia
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LFoundry LF150
LFA150: • L-Foundry 150 nm process (deep N-well/P-well)• Up to 7 metal layers• Resistivity of wafer: >2000 Ω·cm• Small implant customization• Backside processing
CCPD_LF prototype: • Pixel size: 33um x 125 um (6 pix =2 pix of FEI4)• Chip size: 5 mm x 5 mm (24 x 114 pix) • Bondable to FEI4• 300um and 100um version• Bonn + CCPM +KIT
AIDA-2020 - Marseille - 13.05.2016 22
[email protected] AIDA-2020 - Marseille - 13.05.2016
Passive LFCMOS sensor prototype
• LFoundry 150 nm CMOS technology
• 2 k-cm p-type bulk, 8“
• 300 µm thick, backside processed
• Bump bonded to the ATLAS FE-I4
• Pixel size: 50 µm x 250 µm
• Matrix size: 16 x 36 pixels (1.8 mm x 4 mm)
• Bonn + MPI
AC-coupled pixelsResistive bias
30 µm implants
DC-coupled pixelsPunch through bias
30 µm implants
30 µm
25 µm
20 µm
15 µm
n-implant widths:[30, 25, 20, 15] µm
30 µm
25 µm
20 µm
15 µm
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[email protected] AIDA-2020 - Marseille - 13.05.2016
LF CMOS Passive – IV and noise
• Room temperature, ATLAS FE-I4 on, configured and idle, not irradiated
• Break down: > 160 V
• Leakage: 28 uA / cm³ (200 um depletion depth assumed)
• IBL planar sensor design: 15 uA / cm³ (200 um depletion depth assumed)
• IBL CNM 3D sensor design: 45 uA / cm³ (230 um depletion depth assumed)
• Measured with a threshold scan, IBL like tuning: „1500 e“ threshold
• AC couples pixels: (133 ± 1) e
• DC couples pixels: (117 ± 1) e
• IBL n-in-n planar pixel: (125 ± 5) e, 117 fF
• IBL 3D pixel: ~ 150 e, 180 fF
D. Pohl, Bonn
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[email protected] AIDA-2020 - Marseille - 13.05.2016
BV reality -> EMMI (emission microscopy)
J. Segal, SLAC
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[email protected] AIDA-2020 - Marseille - 13.05.2016
Fill factor dependent Efficiency (BEFORE radiation)
• Idea: reduce pixel capacitance for power density reduction
• Only a few pixels can be used for this, since they are at the edge
• Efficiency drops 0.1 % per 1 um n-implant width-reduction
97.5
98
98.5
99
99.5
100
10 15 20 25 30 35
Effi
cie
ncy
[%
]
n-implant width [um]
D. Pohl, Bonn
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[email protected] AIDA-2020 - Marseille - 13.05.2016
CCPDLF/LFB01
Process: LFoundry 150nm, 4-6 Aluminum Metal layers, 1.8 VSubstrate: CZ, p-type bulk, >2kOhm-cmPost processing: Thinning 100/300um, p-type implant, annealing, metallization
PW
P
P-substrate
DNWELL
NW
N
P+
GND
+-
N N NP P
NW
PSUB
VDD
PW
NI
NW
NI
P
GND
PWPW
5x5 mm2
24 x 114 pixels
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[email protected] AIDA-2020 - Marseille - 13.05.2016
CCPD-LF
Beam spectrum
T. Hirono, Bonn
Sensor reverse current
1013neq/cm2 1015neq/cm2
0neq/cm2
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[email protected] AIDA-2020 - Marseille - 13.05.2016
CCPD-LF – Radiation damage
Collection with (edge-TCT) Sepctrum of 55Fe and 241Am after 1015neq/cm2
TCT, I. Mandić, B. Hiti et al.,Jožef Stefan Institute, Ljubljana, Slovenia
T. Hirono, Bonn
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[email protected] AIDA-2020 - Marseille - 13.05.2016
100um CCPD
IV
Fe5
5fr
on
t/b
ack
30
0u
mFe
55
fro
nt/
bac
k 1
00
um
T. Hirono, Bonn 30
[email protected] AIDA-2020 - Marseille - 13.05.2016
RD53A – Next Hybrid Pixel Readout Performance
Parameter Value
Pixel size 50x50 or 25x100 µm2`
Analog power 4-5 µA/pixel -> 160-200 mA/cm2 (40-50 fF)
Digital power 4 µA/pixel -> 160 mA/cm2
Analog Threshold 500 e-
Charge Resolution 4-5 bits
Timing Resolution 25 ns
Hit Rate 3-4 Ghits/cm2
Trigger Rate 1-2 MHz
Trigger Latency 12.5 µs
Output Data Rata 5 Gbit/s
Powering schema serial
Size 400x400 pixels (2x2 cm2)
Analog power scales with input capacitanceDigital power scales with rate
...it is not linear
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Thank you
[email protected] AIDA-2020 - Marseille - 13.05.2016
[email protected] AIDA-2020 - Marseille - 13.05.2016
Hybrid pixel sensor input capacitance
250µm x 50µm sensors:
“Measurement of pixel sensor capacitances with sub-femtofarad precision”, M. Havranek, F. Hügging, H. Krüger, N. Wermes – NIMA 714 (2013), 83-89
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CMOS Pixel Demonstrator Effort
In July 2014 the CMOS Pixel Demonstrator WG has been launched to demonstrate the suitability of CMOS Pixels for ATLAS under HL-LHC conditions. The WG is chaired by Sasha Rozanov and Norbert Wermes.
MAPS CMOS Pixels employing CMOS camera technologies with charge collection in an epitaxial layer have been successfully developed (> 10 years) into pixel detectors for comparatively low rate and low radiation environments (STAR/RHIC, ALICE phase 1).
Can CMOS pixels be made HL-LHC suitable and improve the physics performance?
A word about NAMING (my view)
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CMOS pixels = pixel detectors using any CMOS technology
MAPS = monolithic CMOS pixels which are not (much) depleted
DMAPS or depleted MAPS = depleted CMOS pixels for LHC high rate high
radiation applications
HV-MAPS is a term used already since in 2007 when in particular the HV
add-on of the AMS technology was a key point.
HV/HR or HR/HV - MAPS is an extension to the label HV-MAPS when
the HV/HR approach to achieve a depleted region is jointly employed.
“Smart CMOS pixels” = CMOS pixel sensors including an amplification and
discrimination stage ... usually coupled (DC or AC) to FE-chip (AC -> CCPD)
Key points
Technology key points for CMOS Pixels at LHC
HV add-ons
HR wafers
Multiple wells (≥4)
(back side processing)
Design key points
optimize cell geometry for speed and radiation tolerance
- reasonably large signal at low noise, sufficiently fast time stamping, homogeneous response
cope with additional inter-well capacitances
cope with cross talk (from digital activity) into sensor
Module key points
can one exploit the CMOS technology on module level to gain in physics performance?
e.g. can cooling be applied more directly and efficiently (thus saving material)?
can the module assembly be made less involved (less process steps, less human labour)?-> better overall yield?
can the overall material budget be reduced?
Goals of the demonstrator program
1. First Prototypes: Characterization of different technology features together with design approaches by dedicated prototypes (smart sensors) that could be characterized “stand alone” or “bonded to FE-I4”.
1. “Demonstrators”: Larger area (~1cm2) prototypes in few selected technologies.To avoid the (initially believed too challenging) on-chip R/O architecture, these prototypes were requested to be characterizable “stand alone” AND “bonded to FE-I4”.
2. Fully monolithic depleted CMOS pixel chips includingthe R/O architecture on-chip (FE-I3-like or different)
TID/fluence target at first:outer pixel layers (r > 25 cm)100 Mrad / 1015 neq/cm2
CMOS demonstrator program thus far
Technology comments Groups involved indesign (D) & characterization
prototypes demonstra-tor
monolithic
AMS 350/180 nmHV, 20-1000 Ωcm
3-well processextensive tests
Karlsruhe (D), GVA, Liverpool (D), CPPM, Glasgow, Oxford, Barcelona (D), BN, CERN,
✓ CCPDv1 – v4(180nm) + FE-I4
✓ H35_DEMO 350 nm (back 1/2016)
H35_DEMO hasmonolithic part
Global Foundry130 nmHR: 3 kΩcm
huge vendor CPPM (D), Karlsruhe (D), Geneva, Bonn, CERN
✓ HV2FEI4_GF
Tower Jazz 180 nm, 1-3 kΩcm, epi
little dedicatedattention so far
Bonn (D), Strasbourg (D) ✓ ? Pegasus_1&2stand alone, monolithic
ESPROS150 nmHR: 2 kΩcm
back contact in process, genericdesign not forLHC
Bonn (D), Prague (D) ✓ EPCB01, EPCB02stand alone
XFAB 130 nm0.1 – 1 kΩSOI
SOI technology Bonn (D), CERNCPPM
✓ XTB01, XTB01 planned ?! planned ?!
Toshiba130 nm3 kΩcm
designs not yetthoroughly tested
Bonn (D) ✓ TSB01
LFoundry130 nm2-3 kΩcm
extensive tests Bonn (D), CPPM (D), IRFU (D)SLAC (D), CERN, Glasgow
✓ CCPD_LFCCPD_LF + FI-I4
✓ CCPD (CPPM, IRFU, Bonn)(subm. Feb. 16)
MONOPIX_01 (5/2016)(Bonn, CPPM, IRFU)COOL_01 (SLAC)
ST-M (BCD8)160 nmselectable kΩcm
bipolar+CMOS+DMOSepi selectable
INFNMilano (D), Genova, Bologna, IIT Mandi
✓ KC53AB Testchip planned TPM139
CMOS demonstrator program thus far
Technology comments Groups involved indesign (D) & characterization
prototypes demonstra-tor
monolithic
AMS 350/180 nmHV, 20-1000 kΩcm
3-well processextensive tests
Karlsruhe (D), GVA, Liverpool (D), CPPM, Glasgow, Oxford, Barcelona (D), BN, CERN,
✓ CCPDv1 – v4(180nm) + FE-I4
✓ H35_DEMO 350 nm (back 1/2016)
H35_DEMO hasmonolithic part
Global Foundry130 nmHR: 3 kΩcm
huge vendor CPPM (D), Karlsruhe (D), Geneva, Bonn, CERN
✓ HV2FEI4_GF
Tower Jazz 180 nm, 1-3 kΩcm, epi
little dedicatedattention so far
Bonn (D), Strasbourg (D) ✓ ? Pegasus_1&2stand alone, monolithic
ESPROS150 nmHR: 2 kΩcm
back contact in process, genericdesign not forLHC
Bonn (D), Prague (D) ✓ EPCB01, EPCB02stand alone
XFAB 130 nm0.1 – 1 kΩSOI
SOI technology Bonn (D), CERNCPPM
✓ XTB01, XTB01 planned ?! planned ?!
Toshiba130 nm3 kΩcm
designs not yetthoroughly tested
Bonn (D) ✓ TSB01
LFoundry130 nm2-3 kΩcm
extensive tests Bonn (D), CPPM (D), IRFU (D)SLAC (D), CERN, Glasgow
✓ CCPD_LFCCPD_LF + FI-I4
✓ CCPD (CPPM, IRFU, Bonn)(subm. Feb. 16)
MONOPIX_01 (5/2016)(Bonn, CPPM, IRFU)COOL_01 (SLAC)
ST-M (BCD8)160 nmselectable kΩcm
bipolar+CMOS+DMOSepi selectable
INFNMilano (D), Genova, Bologna, IIT Mandi
✓ KC53AB Testchip planned TPM140
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Two reasoning categories:
1. “use cases” what physics benefits will result from CMOS layers?
- e.g. better b-tagging performance
- less material
- ...
2. “project cases”which benefits might come from a new detector development?
- e.g. better technical performance
- easier production
- opening up new directions (sic!)The decision to use 3D-Si detectors in the IBL is the best and a very direct example in ATLAS how important this is!
Why do this R&D in the context of the ITk?
1. The “fun” argumentCMOS pixels are the “future”. They will come anyway – perhaps not in time for HL-LHC, but may be yes?
2. The cost argument
8” or even 12” commercial technology -> very likely much cheaper than planar or 3D sensors + R/O chip
no bumping, no flip-chipping -> this is the cost driver for hybrid pixels
exploit industrial (wafer scale/reticule scale) machinery
3. The simplicity argumentMultiple gains possible in assembly process: less steps, better yield, etc.
4. The sociological argument Pixel groups are “very keen to realize it”
5. The “who knows” argumentAt the moment nobody considers to use pixels in the very outer ITkregions ... but who knows ... it might become a “physics use case”
Project cases
2. Use cases ...
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• Assume only 5 (pixel) layers as debatable terrain ...
• Power, pixel size, speed ... are NO use cases ... hybrid pixels are perhaps better in some aspects ...
• Money is not a “use case” ... assume it is there ... so what is left?
Possible benefits
1. Ease of assembly => better final yield => use selected “perfect” modules => fewer failures => better coverage (not clear, could be opposite)
2. Better cooling efficiency because of thinner and monolithic sensors (is this true? to be studied) -> would translate into material reduction (!!)
3. For inner layers (with hybrid option: smart CMOS pixel + FE65) 25×50 µm2 pixels via in-pixel en/de-coding demonstrated (in principle)
4. For outer layers: If pixels are small enough (50x50?) such that there is only one hit per column => need only simple hit R/O to EOC => not an unmanageable data volume => excellent two track separation.
Given the present schedule (2025) there are of course also some risks.
Way to the TDR (2017) ...
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• I believe that a “sort-of” functioning monolithic “full scale” prototype chipwill be the “door opener” DMAPS an option for the HL-LHC
– (almost) in-time efficient
– rad. tolerant to 100 Mrad and 1015 neq/cm2
– can cope with readout traffic along the columns
• first monolithic submissions will be characterized by the end of 2016
• second COMMON approach is launched today and could be submitted in fall/winter
• needed: common evaluation and performance understanding
• needed: CMOS-taylored module concepts
• needed: simulation of (i) R/O architecture (on-chip), (ii) potential performance gain