dld course file
TRANSCRIPT
PRRM ENGINEERING COLLEGESHABAD-509 217.
Course file
Class : II B.Tech.
Semester : I Semester.
Branch : Computer Science and Engineering.
Name of Faculty : V. Rajesh M.Tech.
Department : Electronics and Communication Engineering.
Designation : Asst. Professor.
Subject name : Digital Logic Design.
Subject code : 53024.
PRRM ENGINEERING COLLEGESHABAD-509217
Course file contents
Time Table Copy
Syllabus Copy
Academic Calendar Copy for Semester
Lesson Plan Sheets
Course Notes
Previous Question Papers-
i) Internal Unit Test Papers
ii) University External Examination Papers
Student Previous Marks Analysis Sheets
PRRM ENGINEERING COLEGESHABAD 509 217
Department of Electronics and Communication Engineering
Personal Time Table
Class : II B.Tech.
Semester : I-Semester.
Branch : Computer Science and Engineering.
Subject : Digital Logic Design.
Subject code : 07A4EC09.
Name of the Staff member : V. Rajesh M.Tech.
PRRM ENGINEERING COLEGESHABAD 509 217
Department of Computer Science and Engineering
Time Table
DAY I II II IV V VI VII
MON
TUE
WED
THUR
FRI
SAT
Class : II B.Tech.
Semester : II Semester.
Branch : Computer Science and Engineering.
CSE-ADAY I II II IV V VI VII
MON
TUE
WED
THUR
FRI
SAT
CSE-BDAY I II III IV V VI VII
MON
TUE
WED
THUR
FRI
SAT
Jawaharlal Nehru Technological University Hyderabad
II-year B.Tech CSE-I Sem L T/P/D C
4 1/-/- 3
DIGITAL LOGIC DESIGN (53024)
UNIT-I
BINARY SYSTEMS: Digital system, Binary number, Number base conversion, Octal and Hexadecimal Numbers, complements, signed binary numbers, Binary storage and Registers.
UNIT-II
BOOLEAN ALGEBRA AND LOGIC GATES: Basic Definitions, Axiomatic definitions of Boolean Algebra, basic theorems and properties of Boolean Algebra, Boolean functions canonical and standard forms, other logical operation, Digital logic gates, integrated circuits.
UNIT-III
GATE-LEVEL MINIMIZATION: The map method, Four-variable map, Five- variable map, product of sums simplification, Don’t care conditions, NAND and NOR implementation other Two-level implementations, Exclusive-Or function, Hardware Description language (HDL).
UNIT-IV
COMBINATIONAL LOGIC: Combinational Circuits, Analysis procedure, Design procedure, Binary Adder-Subtractor, Decimal Adder, Binary multiplier, magnitude comparator, Decoders, Encoders, Multiplexers, HDL for Combinational circuits.
UNIT-V
SYNCHRONOUS SEQUENTIAL LOGIC: Sequential circuits, latch, Flip-Flops Analysis of clocked sequential circuits, HDL for sequential circuits, State Reduction and Assignment, Design Procedure.
UNIT-VI
Registers, shift Registers, Ripple counters synchronous counters, other counters, HDL for Registers and counters.
UNIT-VII
Introduction, Random-Access Memory, Memory Decoding, Error Detection and correction Read only memory, Programmable logic Array programmable Array logic, Sequential Programmable Devices.
UNIT-VIII
ASYNCHRONOUS SEQUENTIAL LOGIC: Introduction, Analysis procedure, Circuits with latches, Design Procedure, Reduction of state and Flow Tables, Race-Free state Assignment Hazards, Design Example.
TEXT BOOKS:
1. Digital Design – Morris mano, PHI,3rd Edition, 2006.2. Fundamentals of logic Design- charles h. Roth, Thomson publications 5th Edition, 2004.
REFERANCES:
1. Switching & Finite Automata Theory –Zvi kohavi, TMH, 2nd edition.2. Switching and Logic Design, C.V.S.Rao, Pearson Education
3. Digital Principles Design – Donald D. Givone, Tata McGraw Hill, Edition.4. Fundamentals of Digital Logical & Micro Computer Design, 5TH Edition, M Rafiquzzaman John
Wiley.
PRRM ENGINEERING COLLEGESHABAD-509 217.
Class: II B.Tech (CSE) I- Semester. Synopsis for: Digital Logic Design.
Lecturer: V. Rajesh M.Tech.
Required No of
Starting & Ending
Sl. No Unit-No. Contents Classes dates Remarks
1 Unit-I Binary Systems 8
2 Unit-II Boolean Algebra and Logic Gates
9
3 Unit-III Gate Level Minimization 8
4 Unit-IV Combinational Logic 8
5 Unit-V Synchronous Sequential Logic
8
6 Unit-VI Registers & Counter 7
7 Unit-VII Memory Devices 8
8 Unit-VIII Synchronous Sequential Logic
8
PRRM ENGINEERING COLLEGESHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech
Sem.: I-Sem
Branch : CSE
Page number: 1/8.
Name of faculty:V. Rajesh M.Tech.
Department: ECE.
Designation: Asst. Prof.
Subject Title:
Digital Logic Design
Unit Number : I
Unit title: Binary Systems.Objective: To brief study about Number system, number converstion.
S.No. Subject Topics Periods Reference material
1
2
3
4
Digital system & Binary number.
Number base conversion, Octal and Hexadecimal Numbers.
Complements & signed binary numbers.
Binary storage and Registers.
2
2
2
2
1
1
1
2
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition.
1 to 3
4
Teaching aids: S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
3 & 4NilNil
PRRM ENGINEERING COLLEGESHABAD-509 217
Class: II B.Tech
Sem.: I-Sem
Branch : CSE
Lesson Plan Subject code: 53024.
Page number: 2/8.
Name of faculty:V. Rajesh M.Tech.
Department: ECE.
Designation: Asst. Prof.
Subject Title:
Digital Logic Design
Unit Number : II
Unit title: Boolean Algebra and Logic Gates. Objective: Introduction about Boolean theorems and properties, Logic Gates.
S.No. Subject Topics Periods Reference material
1
2
3
4
Basic Definitions, Axiomatic definitions of Boolean Algebra.
Basic theorems and properties of Boolean Algebra.
Boolean functions canonical and standard forms, other logical operation,
Digital logic gates, integrated circuits.
2
2
3
2
2
2
1 & 2
2
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition.
2. Digital Design – Morris Mano, PHI, 3rd Edition.
3 & 5
1 to 4
PRRM ENGINEERING COLLEGESHABAD-509 217
Lesson Plan Subject code: 53024.
Teaching aids: S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
2NilNil
Class: II B.Tech
Sem.: I-Sem
Branch : CSE
Page number: 3/8.
Name of faculty:V. Rajesh M.Tech.
Department: ECE.
Designation: Asst. Prof.
Subject Title:
Digital Logic Design
Unit Number : III
Unit title: GATE-LEVEL MINIMIZATION.Objectives: To study about Map & Tabulation methods, Prime Implicants & Essential PI.
S.No. Subject Topics Periods Reference material
1
2
3
4
The map method, Four-variable map & Five- variable map,
Product of sums simplification, Don’t care conditions.
NAND and NOR implementation other Two-level implementations.
Exclusive-Or function, Hardware Description language (HDL).
2
2
2
2
1
1
1 & 3
1
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition.
1 to 4
3
PRRM ENGINEERING COLLEGESHABAD-509 217
Lesson Plan Subject code: 53024.
Teaching aids: S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
NilNilNil
Class: II B.Tech
Sem.: I-Sem
Branch : CSE
Page number: 4/8.
Name of faculty:V. Rajesh M.Tech.
Department: ECE.
Designation: Asst. Prof.
Subject Title:
Digital Logic Design
Unit Number : IV
Unit title: Combinational Logic. Objective: The study of different Multivibrators.
S.No. Subject Topics Periods Reference material1
2
3
4
5
Combinational Circuits, Analysis procedure.
Design procedure, Binary Adder-Subtractor.
Decimal Adder, Binary multiplier, magnitude comparator.
Decoders, Encoders, Multiplexers.
HDL for Combinational circuits.
1
2
2
2
1
1
1
1
2 & 3
2 & 3
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition.
3. Modern Digital Logic Design- R.P. Jain.
1, 2 & 5
3 & 4
3 & 4
Teaching aids S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
NilNilNil
PRRM ENGINEERING COLLEGESHABAD-509 217
Lesson Plan Subject code: 53024.
Page number: 5/8.
Unit title: SYNCHRONOUS SEQUENTIAL LOGIC.Objective: Introduction about flip-flops.
S.No. Subject Topics Periods Reference material
1
2
3
4
Sequential circuits, latch.
Flip-Flops, Analysis of clocked sequential circuits.
HDL for sequential circuits.
State Reduction and Assignment, Design Procedure.
2
2
1
3
1
1 & 2
2
1 & 2
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition.
1, 2 & 5
2 & 4
Teaching aids: S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
5NilNil
PRRM ENGINEERING COLLEGESHABAD-509 217
Class: II B.Tech
Sem.: I-Sem
Branch : CSE
Lesson Plan Subject code: 53024.
Page number: 6/8.
Name of faculty:V. Rajesh M.Tech.
Department: ECE.
Designation: Asst. Prof.
Subject Title:
Digital Logic Design
Unit Number : VI
Unit title: Sequential Circuits-I.Objective: To study Sequential circuits like flip-flops, Counters.
S.No. Subject Topics Periods Reference material
1
2
3
Registers & shift Registers.
Ripple counters synchronous counters, other counters.
HDL for Registers and counters.
3
3
1
1
1
1 & 2
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition.
1 to 4
4 & 5
Teaching aids: S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
3NilNil
PRRM ENGINEERING COLLEGESHABAD-509 217
Class: II B.Tech
Sem.: I-Sem
Branch : CSE
Lesson Plan Subject code: 53024.
Page number: 7/8.
Name of faculty:V. Rajesh M.Tech.
Department: ECE.
Designation: Asst. Prof.
Subject Title:
Digital Logic Design
Unit Number : VII
Unit title: Sequential Circuits-II.
Objective: Mealy and Moore machines, Merger chart, Concept of minimal cover table.
S.No. Subject Topics Periods Reference material
1
2
3
4
5
Introduction, Random-Access Memory, Memory Decoding.
Error Detection and correction Read only memory.
Programmable logic Array.
Programmable Array logic.
Sequential Programmable Devices.
2
3
1
1
1
1
1 & 2
2
2
2
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition.
1& 2
2 to 4
PRRM ENGINEERING COLLEGESHABAD-509 217
Class: II B.Tech
Sem.: I-Sem
Branch : CSE
Lesson Plan Subject code: 53024.
Page number: 8/8.
Name of faculty:V. Rajesh M.Tech.
Department: ECE.
Designation: Asst. Prof.
Subject Title:
Digital Logic Design
Unit Number : VIII
Unit title: ASYNCHRONOUS SEQUENTIAL LOGIC.Objective: Introduction about .
Teaching aids: S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
6NilNil
S.No. Subject Topics Periods Reference material1
2
3
4
Introduction, Analysis procedure, Circuits with latches.
Design Procedure, Reduction of state and Flow Tables.
Race-Free state Assignment Hazards,
Design Example.
2
2
3
1
1
1 & 2
1
1
Suggested referencesName of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition
1 to 3
2
Teaching aids: S.No.
1. O.H.P.2. Models.3. Simulation by Computer.
2NilNil
Prepared by Checked by Approved by
Signature
Name
Designation
Date