Implications of Capacitor Voltage Imbalance on theOperation of the Semi-Full-Bridge Submodule

Stefanie Heinig, Student Member, IEEE, Keijo Jacobs, Student Member, IEEE, Kalle Ilves, Member, IEEE,Luca Bessegato, Student Member, IEEE, Panagiotis Bakas, Student Member, IEEE, Staffan Norrga, Member, IEEE,

and Hans-Peter Nee, Fellow IEEE

Parts of the paper have been presented at EPE’17 ECCE Europe (see end of introduction).

Abstract—Future meshed high-voltage direct current grids re-quire modular multilevel converters with extended functionality.One of the most interesting new submodule topologies is thesemi-full-bridge because it enables efficient handling of DC-sideshort circuits while having reduced power losses compared toan implementation with full-bridge submodules. However, thesemi-full-bridge submodule requires the parallel connection ofcapacitors during normal operation which can cause a highredistribution current in case the voltages of the two submodulecapacitors are not equal. The maximum voltage difference andresulting redistribution current have been studied analytically, bymeans of simulations and in a full-scale standalone submodulelaboratory setup. The most critical parameter is the capacitancemismatch between the two capacitors. The experimental resultsfrom the full-scale prototype show that the redistribution currentpeaks at 500A if the voltage difference is 10V before parallelingand increases to 2500A if the difference is 40V. However,neglecting very unlikely cases, the maximum voltage differencepredicted by simulations is not higher than 20-30V for theconsidered case. Among other measures, a balancing controller isproposed which reduces the voltage difference safely if a certainmaximum value is surpassed. The operating principle of thecontroller is described in detail and verified experimentally ona down-scaled submodule within a modular multilevel converterprototype. It can be concluded that excessively high redistributioncurrents can be prevented. Consequently, they are no obstacle forusing the semi-full-bridge submodule in future HVDC converters.

Index Terms—AC-DC power conversion, HVDC converters,HVDC transmission, Power transmission, Fault tolerance, Powersystem faults.

I. INTRODUCTION

THERE is a clear trend towards extremely demandingnew applications for power electronic converters like

high-voltage direct current (HVDC) grids. Integrated HVDCmultiterminal overlay grids may be appearing sooner thanexpected. The start of the rise of HVDC grids can be seen bothin the developments in the German and Chinese networks [1].

Two of the most important components of such futureHVDC supergrids are the power converters and DC circuit

Manuscript sent April 3, 2018; revised August 21, 2018; accepted Decem-ber 17, 2018.

S. Heinig (corresponding and main author), K. Jacobs, K. Ilves,L. Bessegato, P. Bakas, S. Norrga, and H.-P. Nee are with the Royal Instituteof Technology (KTH), Stockholm 10044, Sweden (e-mail: sheinig@kth.se,keijoj@kth.se, ilves@kth.se, lucabe@kth.se, pbakas@kth.se, norrga@kth.se,hansi@kth.se).

breakers [2], [3]. Several new features have to be introducedin order to meet the demands that are imposed by networks ofHVDC converters. Those new requirements as well as optionsfor future advanced converters have been summarized in [4].Reduced power loss is of paramount commercial importance.In addition, electronic failure management, small footprint, andlower semiconductor expenditure will play important roles.However, cost and performance have to be analyzed from asystems point of view in future HVDC grid applications.

During recent years viable candidate technologies for powerconverters and DC circuit breakers have been proposed. In thecase of power converters, the preferred converter is the modularmultilevel converter (MMC), first presented by Marquardt etal. [5]–[8], and in the case of DC circuit breakers varioushybrid electronic/mechanical concepts have been reviewed in[9]–[11]. Both the converter and the DC circuit breaker arecostly and voluminous to such an extent that the introduction ofHVDC supergrids may be delayed unless more cost-effectiveand compact solutions are found. The cost of circuit breakerscould be reduced by using power converters that are able tocontrol the DC-side current in the event of a short circuit onthe DC-side, because DC circuit breakers may not have to beinstalled in every single node if such converters are used [12].

Fast protection of the converters and associated equipmentmust be ensured throughout the whole network. ElectronicDC-side current limitation and control by the converter itself,also referred to as full-bridge functionality [4], could be aparticularly good alternative for meshed transmission systemswith overhead lines where the probability of DC line faults ismuch higher due to lightning strikes or bad weather conditions.A variety of submodule topologies that fulfill this criterionare discussed in [13]. The full-bridge (FB) submodule belongsto this group. However, an MMC employing FB submodulesutilizes twice the number of semiconductor switches in com-parison to one with half-bridge (HB) submodules. This leadsto high conduction losses which represents a severe drawbackof the general use of FB submodules. The double-clampsubmodules (DCS) [14], on the other hand, offers reducedlosses but can only provide DC-side current blocking. It is notcapable to control the fault current and, hence, cannot supportthe AC grid during DC short circuit faults.

In order to balance power loss, semiconductor cost andfunctionality, mixed cell MMC topologies with both HB andFB submodules have been proposed [15]–[17]. The combineduse of these two basic cell types constitutes an improved

compromise, though particular attention has to be paid toenable successful voltage balancing at low values of theDC-side voltage. FB MMCs can also be utilized in hybridconfigurations where they are combined with line-commutatedconverters (LCC). These concepts enable the operation of anLCC at leading power angles. A review of several possibletopologies is presented in [18].

Regarding the physical volume of the MMC itself, it is foundthat a major contributor is the submodule capacitance [19]–[22]. The cell capacitors occupy more than half of the submod-ule volume. One alternative approach to realize submoduleswith a smaller capacitance is the concept of hybrid voltagesource converter (VSC) topologies. Hybrid VSCs mix elementsof the classic VSC and the MMC. They have been mainlyproposed in order to reduce the converter footprint, whichthey achieve by requiring fewer submodules with a smallercapacitance. One of the most prominent representatives of thisapproach is the alternate arm converter (AAC) [23]. Differentmodes of operation have been presented in [24], [25]. Yet, theresearch and development phase of the AAC is still ongoingand no commercial application has been reported so far.

It can be noted that the search for new MMC submoduletopologies remains important. The goal is to find topologieswhich enable efficient handling of DC-side short circuits,reduction of power loss, and lower submodule capacitance.The semi-full-bridge (SFB) submodule, presented in [26], isa very interesting topology from this point of view and wasidentified to be one of the most promising candidates forHVDC grid applications by leading research experts in thefield [27]. Based on this, the authors of this paper concludethat the SFB submodule topology and its operation is a relevanttopic and should be investigated in detail.

The SFB allows to insert negative voltages in the converterarms. It was shown that the ripple voltage across the sub-module capacitor could be reduced by 59% compared to thecase when only positive voltages were used [26]. The samenegative voltages are also necessary in order to set up a voltageagainst the AC-side voltage in case of a DC-side short circuit.Moreover, the use of SFB instead of FB submodules reducesthe number of components in an MMC, while still providingfault current limitation and bipolar voltage capability. Anotherinteresting feature of this submodule topology is that the twosubmodule capacitors in the circuit can be connected eitherin series or in parallel when inserting positive voltages inthe arm. In the latter case, the submodule capacitors canshare the arm current such that the corresponding voltagedeviation across the submodule capacitors is reduced by 50%during a conduction interval [26]. The parallel connectionmay, however, be problematic in case the two capacitorvoltages are not equal. Due to the low impedance of thecircuit, an initial voltage imbalance may give rise to excessiveredistribution currents and depending on the damping of thecircuit subsequent oscillations between the two capacitors mayoccur. A new HB topology was recently proposed which usesclamping diodes and buffer inductors to keep the submodulecapacitor voltages balanced [28]. This topology forms the samebalancing loop between two submodules as is the case of theSFB. However, this approach increases the complexity and cost

of the converter.This paper presents a detailed study of the phenomenon of

transient redistribution currents in the SFB and is structuredas follows. In Section II, the basic switching operations ofthe SFB submodule are discussed with focus on the possiblecapacitor voltage imbalance and an analytical calculation ofthe redistribution current. A parameter study of the maximumdifference in the capacitor voltages is presented in Section III.A balancing controller that limits the divergence of the capac-itor voltages and thus the redistribution currents is proposed inSection IV. Two control methods are explained and theoreticalanalysis is provided in this part of the paper. In Section V,the simulation environment is described. Simulation resultsof the redistribution current are shown and verified againstanalytical calculations. Moreover, the new balancing controlleris simulated and its impact on the submodule performanceis analyzed. Fina lly, measurement data from two differentexperimental setups, a full-scale and down-scaled laboratoryprototype of the SFB submodule, are presented in Section VI.Finally, a discussion is provided about various options on howa voltage imbalance between the two submodule capacitors canbe handled without impairing the operation of the converter.

Note that part of this paper has been published in theProceedings of the 2017 19th European Conference on PowerElectronics and Applications (EPE’17 ECCE Europe), War-saw, 11-14 Sep., 2017 [29]. However, the parameter studyof the maximum difference in the capacitor voltages hasbeen considerably extended and twice as much measurementresults are presented in this paper. Moreover, the proposedcontrol mechanism to balance the capacitors, its analysis andexperimental verification is entirely new.

II. SEMI-FULL-BRIDGE SUBMODULE

A. Operating PrinciplesThe operation principles of the SFB and its energy fluctu-

ation have been studied in [26]. The SFB can be consideredas an extension of the DCS as presented in [14]. The maindifference between the DCS and the SFB is that two diodeshave been replaced by active switches which changes the func-tion and operating principles of the submodule. A schematicdiagram of the SFB is shown in Fig. 1, where iarm denotesthe arm current. The proposed SFB submodule contains twocapacitors, C1 and C2, which can be bypassed, connected inparallel, or in series. Thus, one SFB replaces two conventionalsubmodules which are equipped with only one capacitor each.For evaluation purposes, the SFB submodule should thereforebe compared to two series-connected HB or FB submodules.

Only two out of several possible switching states are relevantfor this investigation. They are illustrated in Fig. 2. Switched-off devices are indicated with gray color. Using the parallelstates of the SFB, i.e. controlling the submodule in such waythat devices S3 and S5 are conducting in parallel, offers severalbenefits compared to the case of operating the bridge legsindependently. Firstly, S3 and S5 must only be rated for half ofthe arm current. Thus, in terms of combined power rating ofthe semiconductors, the seven devices in the SFB correspondto six devices rated for the full arm current. Accordingly, the

S1

S2

S3

S4

S5 S7

S6

C1

C2

iarm

A

B

Fig. 1: Schematic diagram of the proposed semi-full-bridgesubmodule.

S1

S2

S3

S4

S5 S7

A

B

S6

(a) Capacitors inserted in series.

S2

S1

S4

S3

S5 S7

S6

A

B

(b) Capacitors inserted in parallel.

Fig. 2: Switching states of the SFB submodule [29].

combined power rating of the devices in the SFB is 25%lower compared to a full-bridge submodule, and 50% highercompared to a half-bridge submodule. Secondly, advantagesas regards the energy balancing at modulation indices aboveunity can be achieved. If the parallel states were not used, theoperation of the SFB would in most aspects be equivalent to thecombination of one half-bridge and one full-bridge submodule.However, such a mixed cell, or hybrid, configuration, is limitedin its operating range due to the energy balancing betweenhalf-bridge and full-bridge submodules. As regards the SFB,the energy between the two capacitors can be easily balancedby utilizing the negative parallel state at any operating pointup to modulation index M = 3.

B. Capacitor Voltage ImbalanceIt can be assumed that the capacitance values of C1 and

C2 differ slightly due to manufacturing tolerances. After some

time in operation the capacitance of film capacitors may alsohave decreased due to aging effects and their self-healing orclearing functionality. At the position of a local defect, a smallpart of the stored energy punctures the film and evaporatesthe thin metal layer. Hence, the local defect is disconnectedsimilar to the function of a fuse [30]. Consequently, thetwo capacitors charge differently when they are inserted inseries, although both are subjected to the same arm current.This results in different voltages across C1 and C2 whichhas been analytically derived in [26]. This voltage differenceis balanced out when the switching state is changed fromseries- to parallel-connection of the capacitors. The equivalentcircuit valid during the transient is illustrated in Fig. 3. Themain elements of this circuit are the two capacitances C1and C2, the stray inductance Lσ, and the voltage drop dueto the IGBT Vth,IGBT and diode Vth,D. Moreover, the circuitcontains several resistive elements, i.e. the ON-state resistancesof IGBT and diode, the resistance of the busbar system aswell as the equivalent series resistance (ESR) of the capacitors.The respective values of the full-scale prototype are listed inTable I. The values for IGBT, diode and busbars have beenmeasured at 400A, while the ESR value is obtained from thedatasheet [31].

TABLE I: Resistive elements in the circuit and prototypevalues.

Parameter Symbol Value

IGBT ON-state resistance RIGBT 3.75mΩ

Diode ON-state resistance RD 2.6mΩ

Busbar resistance Rbus 1.5mΩ

Capacitor ESR ESRC < 0.15mΩ

The resulting resistance can be expressed as

Rres = 2ESRC +RIGBT +RD +Rbus . (1)

All these elements together form a damped resonant circuit,whereby the damping may vary considerably depending on thecircuit design as well as the choice of power semiconductorsand capacitors. The redistribution current ird is superposedon the arm current during the capacitor voltage balancingprocess. However, the arm current is assumed to be zero inthe following analytical study corresponding to the conditionsof the performed experiments, see Section VI. Thus, the sumof both currents determines the current direction in S3 and S5and, in consequence, whether IGBT or diode are conducting.Since it is possible to control the SFB in such a way thatthose devices are always conducting in parallel they couldtheoretically be rated only for half of the arm current [26].

C. Redistribution Current

In case of a voltage difference between the two capacitorsin the SFB submodule there will be a current flowing whenthe capacitors are connected in parallel. This current redis-tributes charge from one capacitor to the other such that thetwo voltages become almost equal after a certain time. The

Lσ

Rbus

Vth,D

Vth,IGBT

RD

RIGBT

C2

C1

ESRC1

ESRC2

ird

ird

Fig. 3: Parasitic elements in the current path [29].

analytical calculation of the current is based on the equivalentcircuit presented in Fig. 3. It is assumed that the capacitorshave different capacitances C1 and C2. Initially, the voltage VC2is higher than the voltage VC1 such that shortly after time zerothe redistribution current is flowing in the direction indicatedin Fig. 3. The analysis of ird reveals that

ird(t) =∆VC−Vth,D−Vth,IGBT√Lσ

(1

C1+

1C2

)− R2

res

4

e− t/τ sin(ω t) , (2)

where ∆VC is given by the voltage difference between thecapacitors

∆VC =VC2−VC1 , (3)

with τ referring to the time constant that is given by

τ =2Lσ

Rres(4)

and with ω describing the angular frequency that is given by

ω =

√1

Lσ

C1 +C2

C1 C2− 1

4

(Rres

Lσ

)2

. (5)

The transients in the capacitor voltages can be described asfollows

vC1(t) =V0 +∆VC−∆VC C2

C1 +C2[ 1−e− t/τ (cos(ω t)

+1

τωsin(ω t)

)] (6)

vC2(t) =V0 +∆VC C1

C1 +C2[ 1−e− t/τ (cos(ω t)

+1

τωsin(ω t)

)] (7)

where V0 is the nominal capacitor voltage.It should be noted from (2) that the redistribution current

is determined by the voltage difference ∆VC and not by theabsolute voltages VC1 and VC2.

III. ANALYSIS OF THE MAXIMUM DIFFERENCE INCAPACITOR VOLTAGES

An analytical study has been conducted in order to evaluatethe influence of various MMC parameters on the maximumdifferences in the capacitor voltages ∆VC,max for a realisticSFB submodule in an HVDC application. The impact of thefollowing parameters has been studied: switching frequency,arm current iarm, phase angle ϕ as well as capacitance C andits associated tolerances k. Phase-shifted carrier pulsewidthmodulation (PSC-PWM) has been chosen to determine therequired switching state of the SFB, i.e. whether it shallbe inserted in series, parallel or bypassed. The state whichgenerates negative terminal voltages is not part of this studysince this state does not create any voltage imbalance amongthe two capacitors. Fig. 4 shows an example of a reference armvoltage vref, arm currents of different phase shifts, and PWMcarriers during one fundamental cycle.

How the capacitor voltages would develop in this case isillustrated in Fig. 5. Since a capacitance tolerance of k=±10%has been assumed in this example, the capacitor voltagesdiverge during their series connection, highlighted in gray, andare balanced out as soon as they are connected in parallel.It becomes clear that the longer the capacitors are connectedin series the greater will be the resulting voltage difference,provided that the current is not changing direction during thattime. Consequently, the voltage difference is inversely relatedto the carrier frequency. It can also be seen that the seriesconnection of the capacitors coincides with low arm currentsfor active power transfer which reduces ∆VC,max. ∆VC,max willbe larger for increased load angles since the arm current isthen higher during series connection.

Fig. 6 presents the results of a parameter study for ∆VC,max.A reference case has been assumed, where the peak armcurrent Iarm = 900A, ϕ = 0 , C = 4mF and k = ±5%. Avariation of the parameters ϕ, k, Iarm, and C is presented in the

0 0.005 0.01 0.015 0.02

Time [s]

0

0.2

0.4

0.6

0.8

1

Vo

ltag

e [p

.u.]

-1000

-500

0

500

1000

Cu

rren

t [A

]

PWM carriers

vref

iarm

( = 0°)

iarm

( = 30°)

iarm

( = 90°)

0 0.005 0.01 0.015 0.02

Time [s]

0

0.2

0.4

0.6

0.8

1

Vo

ltag

e [p

.u.]

-1000

-500

0

500

1000

Cu

rren

t [A

]

PWM carriers

vref

iarm

( = 0°)

iarm

( = 30°)

iarm

( = 90°)

ϕ

ϕ

ϕ

Fig. 4: Reference arm voltage and currents [29].

0 0.005 0.01 0.015 0.02

Time [s]

-600

-400

-200

0

200

Volt

age

dev

iati

on [

V]

C1 & C2 in series

vC1,2

( = 0°)

vC1,2

( = 30°)

vC1,2

( = 90°)

ϕ

ϕ

ϕ

Fig. 5: Capacitor voltages during one fundamental cycle [29].

subplots as a function of the switching frequency. The otherparameters are unchanged according to the reference case. Theinsets show a zoom to low switching frequencies as they arethe most relevant for MMC applications.

All plots of Fig. 6 confirm the mentioned inverse relation-ship between ∆VC,max and the switching frequency. It is alsoshown that the spread in ∆VC,max is greatest for low switchingfrequencies and that it converges to a small value for highswitching frequencies. Fig. 6a illustrates that the phase anglehas a minor impact, in particular for small values of ϕ, whereasthe capacitance tolerance k is critical concerning the amountof ∆VC,max as shown in Fig. 6b. However, the (dotted) casewhere the capacitance of one capacitor is 10 % above itsnominal value and the capacitance of the other capacitor is10 % below its nominal value is highly unlikely. It can insteadbe reasonably assumed that the capacitances of a batch ofnew capacitors have similar values which are probably slightlyabove their rated values. The influence of the arm current Iarmis shown in Fig. 6c. It can be seen that ∆VC,max increases withincreased arm current. Finally, Fig. 6d illustrates the impact ofthe capacitance C on ∆VC,max. It can be seen that the smallerthe capacitance, the greater the difference between the twocapacitor voltages.

Fig. 6 shows that, except for the extreme case of k =±10%,∆VC,max is lower than 30V for switching frequencies greaterthan 100Hz and lower than 20V for switching frequenciesgreater than 150Hz. Immediately after parallelization of thecapacitors, ∆VC will translate into a certain peak value of theredistribution current. This peak value can be calculated with(2) provided that the circuit parameters are known, and shouldbe kept within the safe operating area (SOA) of the employedsemiconductor devices.

A mathematical expression for the voltage imbalance be-tween the two capacitors ∆VC has been recently presentedin [32]. As discussed there, this voltage difference can beexpressed as

0 500 1000 1500 2000 2500

Switching frequency [Hz]

0

10

20

30

40

50

VC

,max

[V]

= 0°

= 30°

= 90°

50 100 150 200 25010

20

30

40

50

ϕ

ϕ

ϕ

(a) Phase angle ϕ

0 500 1000 1500 2000 2500Switching frequency [Hz]

0

20

40

60

80

VC

,max

[V]

k = ± 2.5 %k = ± 5 %k = ± 10 %

50 100 150 200 2500

20

40

60

80

(b) Capacitance tolerance k

0 500 1000 1500 2000 2500Switching frequency [Hz]

0

10

20

30

40

50

VC

,max

[V

]

50 100 150 200 2500

1020304050

(c) Arm current Iarm

0 500 1000 1500 2000 2500Switching frequency [Hz]

0

10

20

30

40

50

VC

,max

[V

]

C = 5 mFC = 4 mFC = 3 mF

50 100 150 200 2500

1020304050

(d) Capacitance C

Fig. 6: Parameter study of the maximum difference in thecapacitor voltages.

∆VC

V0=

TQ 2(1+m√

32 )(1+δ)

mτ

(2k

1− k2

). (8)

Equation (8) takes the arm current, carrier frequency, phaseangle, capacitance values, and capacitance tolerances intoaccount. TQ describes the charge transferred to the capacitorsduring the series-connected switching state which is expressedas coulombs per ampere alternating current. TQ is a functionof the modulation index, carrier frequency, and power angleand has to be pre-calculated numerically. According to (8),the voltage difference ∆VC is proportional to the nominal sub-module voltage V0 and inversely proportional to the normalizedenergy storage τ.

IV. BALANCING CONTROLLER

In this section, two control methods for limiting the redis-tribution currents in the SFB submodule to an uncritical levelare presented. In general, this can be achieved by balancingthe capacitor voltages before their difference exceeds a certainthreshold voltage. The proposed control methods allow such avoltage balancing, while preventing the parallel connection ofthe two capacitors. The fundamental principle of both controlmethods is that only one capacitor is inserted, allowing the armcurrent to either discharge the capacitor with higher voltage orcharge the one with lower voltage.

The first method makes use of an inherent self-balancingmechanism of the SFB submodule and is described in Sec-tion IV-A. The advantage of this method is that the submodulechanges automatically into the parallel state as soon as thebalancing process is completed. It is, so to say, a passivemethod since the controller does not need to be activelydeactivated. However, this methods requires the arm currentto be negative. Hence, it is particularly suitable for a converteroperating in inverter mode, i.e. when the peak value of thearm voltage coincides with the negative peak value of thearm current. This operation mode corresponds to converteroperation with active power transfer. In this case, the switchingstate when both capacitors are inserted in series and mightdiverge, that is close to the peak of the arm voltage, coincideswith negative arm current values.

The second method, on the other hand, enables the capacitorvoltage balancing also for positive arm currents. However, itrequires an active change of switching states after the balancinghas been accomplished. For that reason, this control methodis called “active balancing control”. Further information isprovided in Section IV-B.

The duration of the balancing process depends among otherthings on the magnitude of the current at the instant when thisprocess is activated. Analytical calculations of the balancingtime are derived in Section IV-C.

A. Self-Balancing ControlThe self-balancing control method ensures to temporarily

turn off S4 during the series-connected switching state, pro-vided that the arm current is negative. Thus, the arm currentis redirected either through the diode of S3 or S5 depending

on which one is forward-biased by the capacitor voltagedifference. Fig. 7 shows the equivalent circuit for the self-balancing mechanism.

VC1

VC2

S3

S5

iarm< 0

Fig. 7: Equivalent circuit for self-balancing mechanism.

The two possible current paths, depending on which capac-itor has a higher voltage, are illustrated in red colour in Fig. 8.Fig. 8a illustrates the case when the voltage of capacitor C2is greater than that of C1. The opposite situation is shown inFig. 8b. Only one capacitor is inserted in either case. It shouldbe noted that the capacitor with the higher voltage gets insertedby switching off S4 and that this capacitor gets discharged dueto the negative arm current. As soon as the voltages are equal,both diodes conduct and the switching state changes safely tothe parallel state without redistribution current.

An illustration of the voltages and currents during the self-balancing mechanism is given in Fig. 9. In this case, thecapacitance of C1 has been chosen lower than the capacitance

A

B

S1

S2

S3

S4

S5 S7

S6

C1

C2

(a) Current path for VC1 <VC2. Discharge VC2.

A

B

S1

S2

S3

S4

S5 S7

S6

C1

C2

(b) Current path for VC1 >VC2. Discharge VC1.

Fig. 8: Current path during self-balancing control, iarm < 0.

0 2 4 6 8

Time [ms]

Volt

age

[V]

vC2

vC1

vC2

- vC1

(a) Difference in capacitor voltages.

0 2 4 6 8

Time [ms]

Cu

rren

t [A

]

iS4,IGBT

iS4,Diode

iS3,Diode

(b) Currents through the SFB submodule.

Fig. 9: Exemplary illustration of the self-balancing mechanism.

of C2, which means that during series connection C1 dischargesfaster due to the negative arm current. Both capacitor voltagesas well as their difference are shown in Fig. 9a. The currentsflowing through the semiconductors of interest are shown inFig. 9b. In this example, the controller is activated after 5ms,when the voltage difference exceeds the defined thresholdvoltage. It can be seen that the current gets redirected fromthe IGBT of S4 to the diode of S3, because S4 is turned off.According to Fig. 8a, only C2 is inserted, which dischargesdue to the negative arm current. It can be observed thatwhen the controller is activated the difference in the capacitorvoltages drops to zero. Simulation results and an analysis of theimpact of the self-balancing control method on the harmonicperformance of an SFB submodule is presented in Section V.

B. Active Balancing Control

This control method should be applied if the arm currentis positive. In contrast to the self-balancing control method,the switching state has to be actively changed by switchingeither the left or right half-bridge of the SFB submodule. Theactive balancing method ensures to only insert the capacitorwith lower voltage in order to charge it to the same levelas the second capacitor, see Fig. 10. As soon as the twovoltages are equal, the switching state of the submodule can beeither changed back to series-connected or to parallel insertedstate which would not cause a redistribution current since thevoltages are balanced. As mentioned above, the duration of thebalancing process can be calculated analytically and is derivedin the following section.

In principle, it is possible to operate the SFB without usingthe positive and negative parallel states. The bridge legs of thesubmodule can be controlled separately. However, it shouldbe noted that a path for the redistribution current might becreated when inserting a single capacitor with negative polarity(via the switches that are in ON-state and the free-wheelingdiodes). Without using the positive parallel state, there mightbe a voltage imbalance between the two capacitors when atransition from the bypass state to the negative state is required.Furthermore, the advantages of the parallel states, which aredescribed in Section II-A, would be lost if the bridge legsoperate independently without a parallel connection of thecapacitors.

A

B

S1

S2

S3

S4

S5 S7

S6

C1

C2

(a) Current path for VC1 <VC2. Charge VC1.

A

B

S1

S2

S3

S4

S5 S7

S6

C1

C2

(b) Current path for VC1 >VC2. Charge VC2.

Fig. 10: Current path during active balancing control, iarm > 0.

C. Balancing TimeThe starting point for the calculation of the balancing time

is the expression for the capacitor voltage vC when subjectedto the current iarm, i.e.

vC(t) =1C

∫iarm dt + vC(t0) , (9)

where C is the capacitance and vC(t0) is the initial voltage.

Using iarm = idc +is2

cos(ω t−ϕ) yields

vC(t) =1C

∫ (idc +

is2

cos(ω t−ϕ)

)dt + vC(t0) , (10)

where idc is a third of the dc-side current for the three-phaseinverter case. The controller gets activated at time t = t0 andthe balancing process shall be finished at t = tend. Solving theintegral in (10) for these limits yields

C (vC(tend)− vC(t0)) = idc (tend− t0)+is

2ω(sin(ω tend−ϕ)

− sin(ω t0−ϕ)) .(11)

Equation (11) can be solved numerically for the balancingtime, tbal = tend− t0. An analytical expression can be foundby applying the first-order Taylor polynomial of sin(ω t−ϕ),which gives a linear approximation around the starting pointt = t0.

tbal =C ∆VC,max

idc +is2

cos(ω t0−ϕ)

. (12)

∆VC,max is the voltage difference before the balancing processstarts which corresponds to the maximum allowed voltagedifference. It can be observed that the denominator of (12)is the arm current value at the starting time of the controller.A more accurate expression for the balancing time can befound by applying the second-order Taylor polynomial forsin(ω t − ϕ) around t = t0. We obtain tbal by solving theresulting quadratic equation. That is

tbal =−b±

√b2−4ac

2a, (13)

with the coefficients a,b,c given by

a =is4

ωsin(ω t0−ϕ) , (14a)

b =−(

idc +is2

cos(ω t0−ϕ)

), (14b)

c =C ∆VC,max . (14c)

V. SIMULATION RESULTS

A. Uncontrolled Balancing Process of the Capacitor VoltagesThe characteristics of the redistribution current in the SFB

submodule are validated by simulations in LTspice R©. Theequivalent circuit is shown in Fig. 11, where the current pathand its direction are indicated in red color.

S3

S5

VC

ird

L

Rres

VC+ΔVC

ird

Fig. 11: Current path during the redistribution transient [29].

Ideal components are chosen and a voltage difference of40V is assumed. A first assessment of the overall resistanceRres in the current path has been calculated based on measure-ments of the static characteristics of the semiconductor devicesand copper busbars that are used in the experimental setup,see Section VI. The results show that the ON-state resistancesof the IGBT modules, RIGBT and RD, follow the 125Ccharacteristic given in their datasheet [33], and thus have asignificant contribution to the overall resistance, whereas themeasured resistance of the busbar system Rbus is comparablysmall. The values used for Rres and the stray inductance Lσ

have been obtained from a curve fit of the current measurementdata in MATLAB based on (2). The fitted parameters for thesimulation with LTspice R© are listed in Table II together withother specifications of the simulated circuit.

TABLE II: Simulation parameters.

Parameter Symbol Value

Voltage difference ∆VC 40VSubmodule capacitance C 4mFStray inductance Lσ 230nHEquivalent resistance Rres 7.85mΩ

Simulation time step ∆ t 1µs

Fig. 12 shows how the simulated redistribution currentcompares to the measurement. The inductance value of 230nHcoincides with calculations that have been performed on thebasis of measurements at a high-power IGBT module [34]and according to [35]. Moreover, the resulting resistance of7.85mΩ shows a good agreement with the measured value.

From the measured current waveform shown in Fig. 12 itcan be seen that the circuit is lower damped than critical. Withthe parameters given in Table II, the damping factor ζ can becalculated by

0 0.05 0.1 0.15 0.2 0.25 0.3Time [ms]

-1000

-500

0

500

1000

1500

2000

2500

3000C

urre

nt [

A]

ird, meas

ird, sim

Fig. 12: Measurement data (blue) and simulation result (red)of the redistribution current [29].

ζ =Rres

2

√C/2Lσ

. (15)

In this case it occurs that ζ = 0.37, which confirms that thisis an underdamped system.

Fig. 13 illustrates the charge balancing process between thetwo capacitors. Their voltages converge after 0.3ms in theanalytical calculation based on (2) but do not converge inthe simulation. LTspice R© takes the forward voltage drop ofthe semiconductor devices into account which is neglected inthe analytical calculations. The oscillation stops as soon as theremaining voltage difference is less than the combined forwardvoltage drop over IGBT and diode.

B. MMC Test System and Balancing ControllerThe functionality of the SFB as well as the proposed

balancing controller are validated by simulating a three-phaseMMC in the software PSCAD/EMTDC. The MMC is equippedwith five SFB submodules per arm and is feeding a passiveload. The parameters of the test case are summarized inTable III.

In the simulation, PSC-PWM is employed with four carriersto account for all available voltage levels. The internal arm-balancing control, including circulating-current and voltagecontrol, is implemented based on [36]. Fig. 14 shows theintended effect of the balancing controller. It can be seen thatthe capacitor voltages are limited to a specified critical value∆VC,max. The self-balancing mechanism is triggered wheneverthe voltage difference reaches the threshold level.

It is worth noting that the number of balancing actionsshould be minimized because only one voltage level is insertedfor a short time instead of two and additional switchinglosses are introduced. A conservative analysis of the balancing

0 0.05 0.1 0.15 0.2 0.25 0.3Time [ms]

0

10

20

30

40

50

Vol

tage

[V

]

vC1,anal

vC1,sim

vC2,anal

vC2,sim

Fig. 13: Analytical calculation (solid) and simulation result(dashed) of the two capacitor voltages [29].

TABLE III: Parameters of simulation test case.

Parameter Symbol Value

Converter power S 18MVADC-side voltage (pole-pole) Vdc 30kVModulation index M 0.9Fundamental frequency f0 50HzCarrier frequency fc 80HzSubmodules per arm Nsub 5Capacitors per arm Ncap 10Submodule capacitance C 4mFPassive load Rload 11Ω

Simulation time step ∆ t 1µs

control algorithm was conducted on submodule level. For thispurpose, the capacitance values of the two capacitors in oneconverter submodule were changed by ±10% (C1 = 3.6mF,C2 = 4.4mF). Furthermore, in order to avoid averaging ef-fects, only five fundamental cycles were analyzed because theswitching pattern repeats after that time. The analysis includesan evaluation of the number of balancing switchings, theaverage switching frequency per device favg, and the maximumarm current prior a balancing action |iarm,balance|. These armcurrent values are of interest because the redistribution currentsuperposes the normal load current and the IGBT moduleshave to withstand the sum of both. The results for various casesof maximum allowed capacitor voltage difference ∆VC,max arepresented in Table IV.

TABLE IV: Analysis of balancing controller (T = 0.1s,k =±10%).

∆VC,max 10V 20V 30V 40V

No. balancing switchings 22 13 6 2favg [Hz] 257 241 236 229|iarm,balance| [A] 372 376 366 306

0.028 0.029 0.03 0.031 0.032 0.033 0.034

Time [s]

0

5

10

15

20

25

30

35

40

vca

p[V

]

Vc

= 40V

Vc

= 30V

Vc

= 20V

Vc

= 10V

Fig. 14: Simulation results of the balancing controller fordifferent levels of ∆VC,max.

The number of control actions increase with a more stringentlimit for the voltage difference. Accordingly, the averageswitching frequency is higher for these cases as well. More-over, a fast Fourier transform (FFT) analysis of the terminalvoltage of the respective SFB submodule was conducted,whereby the impact of the balancing controller on arm andconverter level was not considered explicitly. The FFT analysiswas not only conducted for the described capacitance differ-ence of ±10%, but also for the more realistic case of ±5%.The results are plotted in Fig. 15 which illustrates the deviationof the voltage spectra for two different values of ∆VC,max froma reference spectrum without applied balancing control.

The magnitudes of the harmonic components differ consid-erably. A capacitance difference of±10% results in a relativelylarge number of balancing actions as stated in Table IV becausethe voltage difference can be up to 60V, cf. Fig. 6b. It canbe observed in Fig. 15a that the DC components and thefundamental components are reduced in this case. This effectis explained by the fact that less voltage is inserted thandemanded by the voltage controller. Any deviations from thedemanded voltage can be compensated in the modulator byincreasing the reference value of the inserted arm voltageby a value corresponding to one capacitor voltage. A fastresponse from the modulator can be reasonably expected sothat it is likely that the activated balancing control has only anegligible effect on the transient performance of the MMC. Acompensation in the modulator was, however, not implementedin these simulations. Any remaining error in the DC componentof the inserted voltage will eventually be taken care of by thecirculating-current controller which adjusts the insertion in-dices of the arms [37]. An error in the fundamental componentwill be visible in the AC output voltage. The AC output currentcontroller takes care of this error and also adjusts the insertionindices accordingly [36]. In addition, it can be seen in Fig. 15athat the second- and third-order harmonic components areincreased due to the additional switching actions. The rest ofthe spectrum is randomly affected by the control mechanism,

0 1 2 3 4 5 6 7 8 9 10Harmonic order

-8

-6

-4

-2

0

2

4

6

8

|Vh|

[%]

Vmax

= 20V

Vmax

= 30V

(a) Capacitance difference of ±10% (C1 = 3.6mF, C2 = 4.4mF).

0 1 2 3 4 5 6 7 8 9 10Harmonic order

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

|Vh|

[%]

Vmax

= 20V

Vmax

= 30V

(b) Capacitance difference of ±5% (C1 = 3.8mF, C2 = 4.2mF).

Fig. 15: Deviation of voltage spectra with balancing controllerfrom reference case without balancing controller.

whereas the largest deviations appear at subharmonics thatconstitute multiples of the carrier frequency and their relatedsidebands. It is an important finding of this analysis that theimpact of the balancing controller is almost negligible if thecapacitance difference is ±5%, see Fig. 15b. The reason isthat the amount of balancing switchings is very small. Fig. 6bshows that the difference in capacitor voltage is at most 30Vfor this case. By comparing the black and orange bars inFig. 15 it can be further concluded that the discussed deviationsof the harmonics are significantly reduced if the parameter∆VC,max of the proposed balancing controller is increased. Dueto the fact that the deviations in the FFT spectrum are verysmall for the case with a capacitance difference of ±5% andthese deviations can be compensated for with the modulator itwas chosen to not further elaborate on the FFT spectra of thealternating voltage.

The influence of the balancing controller on the outputac voltage and current waveforms has been analysed and isshown in Fig. 16. The simulation model has been modifiedin order to account for the realistic scenario of a capaci-tance mismatch in more than one submodule per arm. Twodifferent cases have been simulated. In the first case, thefive submodules per arm have ±10%,±8%,±6%,±4%,±2%difference, respectively, and in the second case they have±5%,±4%,±3%,±2%,±1%, respectively. The capacitor

0 0.005 0.01 0.015 0.02-20

0

20

Outp

ut

volt

age

[kV

]

0 0.005 0.01 0.015 0.02

Time [s]

-1

0

1

Outp

ut

curr

ent

[kA

]

Fig. 16: Influence of balancing controller on output ac volt-age and current for k = ±10, . . . ,2% (dashed, orange) andk =±5, . . . ,1% (dash-dotted, green).

voltage difference is strictly limited to ∆VC,max = 20V in bothcases. The balancing actions triggered in the first case inducea slight deviation in the output waveforms, whereas there is nodifference visible for the second case with lower capacitancedifference.

The insertion indices of the five submodules, n1−5, areadjusted by the implemented control scheme. They are shownin Fig. 17 for the reference case with equal capacitances, i.e.no controller activation, and for the case where the submoduleshave up to ±10% capacitance difference. It can be seenthat the insertion indices are adjusted around the peak ofthe modulation reference, which is reasonable since the self-balancing control gets activated during the series-connection ofthe capacitors when the highest arm voltage is required. Theinsertion indices are generally increased to compensate for thelower than requested voltage that is inserted by some of thesubmodules in consequence of the control actions.

In summary, if there is a major mismatch between the capac-itances of the two capacitors in one submodule (k = ±10%),care should be taken that the voltage limit is not selected toostringent. It has been shown that the number of balancingactions and, hence, the deviation in the FFT spectrum can besignificantly reduced by choosing a higher threshold voltage.However, a major mismatch between the capacitances mightoccur only after several years of operation and can be easilyavoided with a capacitance monitoring scheme. The impact ofthe balancing controller on the output waveforms is small, evenfor a major capacitance mismatch in several submodules perarm and no compensation in the modulator. If the differenceis ±5% or lower, the impact is negligible. Therefore, it can beconcluded that the proposed balancing controller is a promisingmethod to keep the capacitor voltage difference in the SFBbelow a defined limit. This means that the redistributioncurrents can be controlled to an uncritical level, which is alsoexperimentally verified in Section VI-B.

0 0.005 0.01 0.015 0.02Time [s]

0

0.2

0.4

0.6

0.8

1

Inse

rtio

n in

dice

s

Fig. 17: Insertion indices of arm submodules with equalcapacitances (solid, black) and unequal capacitances (dashed,orange).

VI. EXPERIMENTAL RESULTS

A. Full-scale Submodule Prototype

The described phenomenon of transient redistribution cur-rents due to a voltage imbalance between the two capacitors ofthe SFB has been investigated experimentally on a full-scaleprototype. A drawing of the setup is shown in Fig. 18a anda photograph of the realized implementation is presented inFig. 18b.

The SFB submodule has been equipped with five3300V/1200A (MBN1200E33E) and two 3300V/800A(MBN800E33E) IGBT modules, both types manufactured byHITACHI. However, for the tests conducted for this publicationonly two of the lower rated IGBT modules are needed. Thetwo capacitors, manufactured by VISHAY, have a rated directvoltage of 2650V and a nominal capacitance of 4 mF with atolerance of ±5% as stated in the datasheet [31].

Fig. 19 shows the results of the current and voltage measure-ment. An important finding is that the circuit is highly dampedand the oscillations cease quickly. The peak of the current-spike scales with the amount of voltage difference betweenthe two submodule capacitors and varies between 500A if∆VC = 10V and 2500A if ∆VC = 40V . The peak current valuesmeasured in the 30V and 40V experiment exceed the repetitivepeak collector current rating of the used 3300V/800A IGBTmodule, which is 1600A according to the datasheet [33]. Oneshould bear in mind that the IGBT modules have to withstandthe sum of redistribution current and normal load current,whereas the load current is not included in the experiments.Thus, in order to calculate the total current through the devicesS3 and S5, the load current before paralleling the capacitors hasto be added as an offset to the redistribution currents that areshown in Fig. 19a. The maximum load current that adds tothe redistribution current has been quantified for the presentedsimulation case in Table IV of Section V.

(a) CAD drawing of the SFB submodule.

(b) Photograph of the laboratory prototype.

Fig. 18: Experimental setup of the full-scale prototype of theSFB submodule [29].

B. Down-Scaled Submodule Prototype

The proposed balancing control technique is implementedon a down-scaled MMC prototype with FB submodules toverify its functionality experimentally. It is worth rememberingthat the purpose of the balancing controller is the reduction ofthe redistribution current, while limiting the capacitor voltagedifference is a means of achieving this. An SFB submoduleis formed by reconnecting two FB submodules that have beencustomized with different capacitance values in order to causevoltage imbalance. The original switching signals generatedfor the two FB submodules are re-mapped in order to operatethe SFB submodule properly. Finally, the balancing controlleris implemented in the MMC control structure and tested.Before discussing the details of the SFB balancing controllerexperiments, the structure of the current MMC prototypeis described briefly. The prototype used in the experimentemploys a total of 30 FB submodules, i.e. five submodulesper arm. The converter submodules are implemented on printed

0 0.05 0.1 0.15 0.2Time [ms]

-1000

-500

0

500

1000

1500

2000

2500

3000

Cur

rent

[A

]

Vc = 40V

Vc = 30V

Vc = 20V

Vc = 10V

(a) Redistribution currents.

0 0.05 0.1 0.15 0.2Time [ms]

0

5

10

15

20

25

30

35

40

45

50

Vol

tage

[V

]

Vc = 40V

Vc = 30V

Vc = 20V

Vc = 10V

(b) Capacitor voltages.

Fig. 19: Measurement results for various voltage differences∆VC between the two capacitors.

circuit boards (PCBs), which are inserted in the subracks andconnected to a backplane, which provides the submodules withauxiliary power supply and control signals. The structure ofthe experimental setup together with a photograph is shown inFig. 20.

The down-scaled MMC prototype has a rated power of10 kW and its control system is based on Xilinx Zynq-7000system-on-chip, which integrates a programmable logic witha processing system. The programmable logic performs low-

ZynqZynq

arm

inductors

lower

arms

main

controller

and auxiliary

boards

upper

arms

Resistive

load

Fig. 20: Structure and photograph of the MMC prototype.

level control, i.e. modulation and communication with thesubmodules. The implemented modulation scheme is PSC-PWM, which ensures the balancing of the individual capacitorvoltages within the arm [37]. The prototype is operated ininverter mode (dc-ac conversion) with a symmetrical three-phase resistive load. A detailed description of the down-scaled MMC prototype is presented in [38]. The experimentis designed as follows. The MMC prototype is adapted tothis study by reconnecting two FB submodules to one SFBsubmodule, while operating the rest of the converter with FBsubmodules. The arm that contains the two reconnected FBsubmodules is illustrated in Fig. 21.

The schematic diagram of the SFB configuration as it isused in the experiments along with measurement points isshown in Fig. 22. The implemented PSC-PWM modulationscheme has been adapted for the SFB submodule. The PWMscheme provides switching signals to the four HB legs of thetwo FB submodules which are configured to one SFB, seeFig. 22. Those PWM signals are re-mapped in order to insertthe corresponding output voltage according to

VSFB =VFB1 +VFB2. (16)

Finally, the desired VSFB is implemented ensuring that onlyviable switching states of the SFB submodule are used. The re-mapping algorithm is designed as described in Table V, where’0’ stands for lower switch ON, ’1’ stands for higher switchON, and ’X’ stands for disabled bridge.

TABLE V: Signal re-mapping.

SFB output voltage FB1 FB2VSFB HB1 HB2 HB1 HB2

−VC 0 1 0 10 0 0 1 1

VC 1 1 0 02VC 1 0 X 0

CFB2

SFB FB1

FB2

CFB1

+

+

+

-

-

FB1

FB2

FB3 FB4 FB5

SFB-

SFB submodule

(a) Schematic of reconnected phase arm.

SM-

C-

SM+

C+

MOSFET

MOSFET

(b) Description of power connectors (left) and photograph of recon-nected phase arm (right).

Fig. 21: Configuration of one phase arm for the SFB balancingcontroller experiment.

S1

S2

S3

S4

S5 S7

S6

C1

C2S'4

A

HB1 HB2

HB1 HB2

A

FB1

FB2

SFB+

V

SFB-

iarm

SFBV

Fig. 22: Schematic diagram of the SFB configuration. Pointsof voltage and current measurements are illustrated.

Furthermore, one of the FB submodules forming the SFBhas been customized by removing three out of the ten elec-trolytic capacitors that are mounted on each PCB. In thisway, a capacitance difference between the two capacitors ofthe SFB is achieved, which is a necessary precondition for avoltage imbalance between them. Fig. 23 shows a photographof the customized PCB of FB1 with three removed capacitors.Table VI lists important parameters for the SFB balancingcontroller experiment.

The carrier frequency is comparatively high, but it has notbeen feasible to change it without any major adjustments andadaptation efforts in the implemented MMC control struc-ture. A high carrier frequency, respectively a high switchingfrequency, has implications on the duration of the switching

TABLE VI: MMC parameters - Balancing controller experi-ment.

Parameter Symbol Value

DC-side voltage (pole-pole) Vdc 100VAC-side voltage amplitude vs 49.5VFundamental frequency f0 50HzArm inductance Larm 5.7mHArm resistance Rarm 0.55Ω

Resistive load Rload 7.35Ω

Submodules per arm N 5Modulation index M 0.99Carrier frequency fc 763HzFB capacitance C 2.7mFSFB capacitance C1 1.9mFSFB capacitance C2 2.7mFMaximum capacitor voltage difference ∆VC,max 0.2V, 0.4V

states and hence the maximum capacitor voltage difference asdiscussed in Section III. Simulations of the MMC prototypewith the given parameter set in MATLAB/Simulink revealthat the maximum time of series connection is approximately400µs and the maximum voltage difference is low (< 1V)despite the relatively large difference in capacitance. In a realconverter the relative capacitance difference would be muchlower, but in the presented fast switching MMC prototypea higher difference for the capacitance is needed to createthe investigated effect. Moreover, it could be observed inthis experiment that due to the given modulation scheme,the voltage drifting phenomenon results from a cumulativedrifting effect caused by the fast transition of parallel andseries states, where the capacitor voltages diverge during theseries state and converge during the parallel state. However,this does not imply any restrictions on the verification ofthe proposed control method, since its effectiveness can beobserved in the measured redistribution currents, or in thelow-pass filtered voltage difference, where the high-frequencyswitching operations are neglected. Since the MMC prototypeoperates in inverter mode, the self-balancing control method ofthe proposed balancing controller is applied, see Section IV-A.The control mechanism activates when three conditions aremet: 1) the SFB operates in series-connected switching state; 2)the arm current is negative; 3) the capacitor voltage differenceis higher than a specified threshold value, which is set to 0.2V

Fig. 23: PCB with reduced capacitance. FB1 of SFB submod-ule.

or 0.4V. Experimental results for the relevant time intervalwhen the switching states alternate between series and parallelinsertion of the capacitors are presented in Fig. 24 for the casewithout control and for two different voltage thresholds. Forthe uncontrolled case shown in Fig. 24a, it can be observedthat the current spikes coincide with a change to the parallelstate. They are also more pronounced the higher the voltagedifference and arm current magnitude are at the time of thatchange. Due to the fast transition between parallel and seriesstates, the capacitor voltages do not converge after a singleparallel state, but after several parallel states in a cumulativemanner. This is why small dips are visible in the plot of thecapacitor voltage difference. For the two cases applying theself-balancing control method, shown in Fig. 24b and Fig. 24c,a reduced capacitor voltage difference and lower redistributioncurrent spikes can be observed. The spikes cannot be preventedentirely since the capacitor voltages do not balance completely.A reason for this is that the switching pattern forces the parallelstate regularly (even if only for a small amount of time) so thatcondition 1) is not fulfilled anymore.

Fig. 25 shows the result of the redistribution currentmeasured over a time period of 0.5s. It can be seen thatthe controller significantly reduces the peak current, whichverifies its functionality. The tops and bottoms of each boxare the 25th and 75th percentiles of the measurement data,respectively. The line in the middle of each box is the median.

DISCUSSION

This section discusses how a voltage imbalance betweenthe two submodule capacitors should be handled in casethe submodule receives the control command to deliver onepositive voltage level, i.e. the capacitors should be inserted inparallel. In the first, and probably simplest case, the voltageimbalance can be disregarded because the total current, i.e.half of the arm current plus the redistribution current, is lessthan the maximum allowable current. However, in case thepredicted current is too high there are several possible options.The first option would be to include this case in the sortingalgorithm. That is, if the voltage difference in one moduleexceeds a certain threshold this module is prioritized the nexttime one module should be bypassed. A second option couldbe to insert only one of the capacitors until the two capacitorvoltages are equal and then connect the other one in parallel.As a third option, the proposed control mechanism can beapplied to balance the capacitor voltages. It should be notedthat with the second and third approach it has to be ensuredthat the maximum current is lower than the rated current ofthe devices S3 and S5. Another option could be to refrain frominserting the submodule until the expected current is withinthe SOA. This could, however, put serious restrictions on theconverter modulation, and must therefore be considered as alast option.

The analytical parameter study revealed that the voltagedifference only becomes critical when a high value of ca-pacitance tolerance (k = ±10%) is assumed. It is, therefore,recommended to minimize a potential mismatch between the

0 2 4 6 8 10-15

-10

-5

0

5C

urr

ent

[A]

0 2 4 6 8 10

0

0.5

1

0 2 4 6 8 10

Control OFF

Control ON

0 2 4 6 8 10

Time [ms]

parallel

series

a) b) c)

0 2 4 6 8 10-15

-10

-5

0

5

0 2 4 6 8 10

0

0.5

1

0 2 4 6 8 10

0 2 4 6 8 10

Time [ms]

0 2 4 6 8 10-15

-10

-5

0

5

0 2 4 6 8 10

0

0.5

1

0 2 4 6 8 10

0 2 4 6 8 10

Time [ms]

Fig. 24: Measurements of internal submodule current and capacitor voltage difference, control signal, and switching state.

0.5

1

1.5

2

2.5

Fig. 25: Normalized peak redistribution current measured overa period of 0.5s.

two capacitances of one submodule. Since the capacitance isusually measured and documented by the manufacturer, thecapacitors could be grouped in pairs in order to minimizethe difference from the very beginning. Moreover, an onlinemonitoring system for the capacitances could be implemented.A potential difference between the two capacitors of onesubmodule, which might occur after several years of operation,would then be noticed by such a system. Consequently, thecapacitor with higher capacitance can be given priority to be

inserted as the only capacitor. The resulting higher temperatureaccelerates ageing processes and thus reduces the capacitance[39]. As soon as the capacitances are back within a specifictolerance range, the capacitors are inserted in parallel again.

By ensuring that the two capacitors of a submodule havealmost the same capacitance initially and by monitoring thecapacitance over time along with the proposed balancingcontroller, the remaining additional current stress on the powersemiconductor devices will be negligible. Consequently, theimpact on the reliability of the power semiconductors can bedisregarded. Therefore, a separate reliability analysis of thisissue can be avoided.

CONCLUSION

The SFB is a promising submodule topology for futureMMCs operating in meshed HVDC grids, yet it requires theparallel connection of capacitors during normal operation. Thisparalleling can cause high redistribution currents in case thecapacitor voltages are not equal. The analytical parameterstudy of the maximum differences in the capacitor voltagesshows that the switching frequency and capacitance toleranceare the most important parameters. The study indicates that themaximum voltage difference can be expected to be 20-30Vfor switching frequencies in the range of 100-150Hz. Thequantification of the redistribution current as well as theidentification of the circuit parameters of a realistic SFB imple-mentation have been accomplished on a full-scale prototype.It could be demonstrated that the redistribution current peaksat critical levels if the voltage difference is greater than 20V

before paralleling. The circuit parameters can be used in theanalytical expression such that peak value and frequency of theredistribution current can be determined from measurements ofthe capacitor voltage difference.

A new balancing controller is proposed to reduce the redis-tribution current. This control mechanism is verified by sim-ulations of an MMC implemented with SFB submodules andexperimentally on a down-scaled MMC prototype. The resultsdemonstrate that the proposed controller is able to handle thevoltage imbalance and limit the redistribution current withoutimpairing the overall operation of the converter.

In summary, the impact of the capacitor voltage imbalanceon the operation of the SFB submodule is identified and severaloptions for an improved operation are presented. Based on thisknowledge the submodule controller or the high-level controlcan decide on how to handle the voltage imbalance. It canbe concluded that excessively high redistribution currents canbe prevented by implementing proper control strategies andthat those are therefore not an obstacle for using the SFBsubmodule in future HVDC converters.

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Stefanie Heinig (S’15) received the M.Sc. degreein sustainable electrical energy supply from the Uni-versity of Stuttgart, Stuttgart, Germany, in 2014. Shehas been with the ABB Corporate Research Centerin Västerås, Sweden, between 2014-2015, where shehas been working on the topic of silicon carbidedevices for voltage source converters.

Currently, she is pursuing the Ph.D. degree inelectrical engineering in the division of electricpower and energy systems at KTH Royal Institute ofTechnology, Stockholm, Sweden. Her main research

interests include power electronic converters for ultra high voltage directcurrent grids and advanced submodule topologies for modular multilevelconverters.

Keijo Jacobs (S’16) received the B.Sc. degree inelectrical engineering, information technology andcomputer engineering, and the M.Sc. degree with afocus on electrical power engineering from RWTHAachen University, Aachen, Germany, in 2011 and2015, respectively. Since 2015 he is a part of thedivision of electrical power and energy systems atKTH Royal Institute of Technology, Stockholm. Heis currently working towards the Ph.D. degree in thefield of silicon carbide semiconductor devices andHVDC converters.

Kalle Ilves (S’10–M’15) received the M.Sc., Licenti-ate, and Ph.D. degrees in electrical engineering fromKTH Royal Institute of Technology, Stockholm,Sweden, in 2009, 2012, and 2014, respectively.

Since 2014, he has with ABB Corporate Research,Västerås, Sweden. His main research interests in-clude high power converters for grid applications.

Luca Bessegato (S’14) received the M.S. degreein electronic engineering from the University ofPadova, Padova, Italy, in 2014. He is currently pursu-ing the Ph.D. degree in electrical engineering at KTHRoyal Institute of Technology, Stockholm, Sweden.His current research interests include modelling andcontrol of modular multilevel converters.

Panagiotis Bakas (S’16) was born in Athens, Greecein 1984. He received the Diploma in electrical andcomputer engineering from the Democritus Univer-sity of Thrace (DUTH), Xanthi, Greece, in 2008. Hehas been at ABB Corporate Research, Västerås, Swe-den between 2008-2009, working on photovoltaicmodule modeling and characterization. He rejoinedABB Corporate Research, Västerås, Sweden in 2010where he has been working on photovoltaic systemmodeling and design.

Since 2014 he has been working towards thePh.D. degree in the division of electric power and energy systems at KTHRoyal Institute of Technology. His research interests include power electronicconverters for high power applications.

Staffan Norrga (S’00–M’00) was born in Lidingö,Sweden, in 1968. He received the M.Sc. degree inapplied physics from Linköping Institute of Tech-nology, Linköping, Sweden, in 1993, and the Ph.D.degree in electrical engineering from KTH Royal In-stitute of Technology, Stockholm, Sweden, in 2005.

From 1994 to 2011, he worked as a Develop-ment Engineer at ABB, Västerås, Sweden, in var-ious power-electronics-related areas, such as railwaytraction systems and converters for HVDC powertransmission systems. He currently holds a position

of an Associate Professor at KTH. He is the inventor or co-inventor of 12granted patents and 13 patents pending, and has authored or co-authored morethan 75 scientific papers published at international conferences or in journals.His research interests include new converter topologies for power transmissionapplications and grid integration of renewable energy sources.

Hans-Peter Nee (S’91–M’96–SM’04–F’18) wasborn in Västerås, Sweden, in 1963. He receivedthe M.Sc., Licenciate, and Ph.D. degrees from KTHRoyal Institute of Technology, Stockholm, Sweden,in 1987, 1992, and 1996, respectively, all in electricalengineering.

Since 1999, he has been a Professor of power elec-tronics in the Department of Electrical Engineering,KTH. His research interests include power electronicconverters, semiconductor components, and controlaspects of utility applications, such as FACTS and

high-voltage direct-current transmission, and variable-speed drives.Dr. Nee was a Member of the Board of the IEEE Sweden Section for

many years and was the Chair of the Board from 2002 to 2003. He is alsoa Member of the European Power Electronics and Drives Association and isinvolved with its Executive Council and International Steering Committee.