dissertation - uni ulm

Concept and Design of a High Speed Current

Mode Based SAR ADC

DISSERTATION

to obtain the academic degree

DOKTOR-INGENIEURS(Dr.-Ing.)

Faculty of Engineering, Computer Science

and Psychology

University of Ulm

of

Abdelrahman Elkafrawy

from Cairo (Egypt)

Supervisor: Prof. Dr.-Ing. Maurits Ortmanns

External Examiner: Prof. Dr.-Ing. Bernhard Wicht

Faculty Dean: Prof. Dr. Tina Seufert

Ulm, 10.06.2016

Declaration of Authorship

I, Abdelrahman Elkafrawy, declare that this thesis, titled ’Concept and Design ofa High Speed Current Mode Based SAR ADC’ and the work presented in it aremy own. I confirm that:

• This work was done wholly or mainly while in candidature for a research degreeat this University.

• Where any part of this thesis has previously been submitted for a degree orany other qualification at this University or any other institution, this has beenclearly stated.

• Where I have consulted the published work of others, this is always clearlyattributed.

• Where I have quoted from the work of others, the source is always given. Withthe exception of such quotations, this thesis is entirely my own work.

• I have acknowledged all main sources of help.

• Where the thesis is based on work done by myself jointly with others, I havemade clear exactly what was done by others and what I have contributed myself.

(Place, Date) (Signature)

Acknowledgement

First and foremost, I would like to express my utmost gratefulness to God Almighty,Allah, for giving me the strength and perseverance to successfully complete mydissertation. Glory is to Allah and all praises are due to Allah. Second, I amgrateful to all the people who contributed and extended their valuable assistanceduring the research work and writing of my dissertation. This dissertation wouldnot have been possible without their guidance and support.

I owe my deepest gratitude to my supervisor, Prof. Dr.-Ing Maurits Ortmanns,for allowing me to undertake this research work under his supervision and for hisinsightful guidance, invaluable advices on technical discussions and scientific prob-lems. I am also indebted to his financial support during my last year of studies. Ialso express my gratitude to Jun.-Prof. Dr. Jens Anders, for his invaluable advice,comments on technical discussions and review of papers. Additionally, I would liketo thank Prof Dr.-Ing. Bernhard Wicht for acting as my external examiner.

My sincere thanks go to my colleagues who have supported me during my study,especially my officemate Ahmad AlMarashli and my colleagues from the Mixed-Signal group: Rudolf Ritter, John Kauffman and Dr.-Ing Joachim Becker. Also,not forgetting my other colleagues who have supported me directly or indirectly,namely Mathias Lorenz, Jonas Handwerker, Benedikt Schlecker, Emilia Noorsal,Chao Chu, Hongcheng Xu, Ahmed Elsokary, Naser Pour-Aryan and others. Spe-cial thanks to my friends Ramy Saad from Qualcomm, USA and Khalid Elgalandfrom Cadence, USA for their helpful technical discussions and support. I wouldalso like to show my gratitude to all technical and administration staff membersof the Microelectronics Institute for their excellent support and help during mystay at the Institute.

I would also like to convey many thanks to the DAAD for providing the financialsupport during my four years of studies and to Dr. Luecker, from the Internationaloffice of University of Ulm, during the nine months of my extension period.

Finally, I would like to express my gratitude to my wife, my parents and my wholefamily for their continuous support, encouragement, understanding and endlesslove throughout the duration of my studies.

v

Abstract

There is continuous research to exploit the improved speed of scaled CMOS tech-nologies in realizing high-speed analog-to-digital converters and SAR ADCs areone of the candidates which can significantly benefit from this technology scaling.Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range ofGS/s with excellent power efficiency but the challenge of driving a large samplingcapacitor with high accuracy in a short sampling window is often not addressed.Moreover, time-interleaving a large number of sub-ADCs introduces also inter-leaving artifacts (offset, skew) which are hard to tame at high resolutions. On theother hand, single-channel, non time-interleaved SAR ADCs suffer from settlinglimitations when higher resolutions together with higher conversion rates are re-quired.

In this work, a high-speed current-mode DAC is replacing the commonly usedcharge-mode switched capacitor DAC which alleviates the problem of driving alarge input sampling capacitor in a short time. The proposed current-mode SARADC also uses a Gm stage which converts the input voltage to a current whichis then processed in a current-based binary search algorithm SAR loop. The Gmstage is designed to achieve a 10-bit linearity over a wide differential input voltagerange, which allows to choose the sampling capacitor based only on kT/C noise andnot on the matching requirements of a switched capacitor DAC. In comparison tothe conventional switched capacitor SAR ADC structures, the sampling capacitorsize is smaller than the total capacitance of the comparable switched capacitorSAR ADCs. Moreover, low-impedance DAC-reference voltages which are essentialfor switched capacitor DAC are removed by using this approach. In validating theproposed approach, a prototype 10-bit ADC is fabricated in a 90 nm TSMC CMOSprocess. Measured results of the ADC show an SFDR of 58.4 dB at 50 MS/s, whileconsuming 6 mW from a 1.2 /1.8 V supply.

vii

Contents

Declaration of Authorship iii

Acknowledgement v

Abstract vii

List of Figures xi

List of Tables xv

Abbreviations xvii

1 Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Thesis Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Nyquist Rate SAR ADCs: A Survey and State of the Art 52.1 Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 Static Parameters . . . . . . . . . . . . . . . . . . . . . . . . 52.1.2 Dynamic Parameters . . . . . . . . . . . . . . . . . . . . . . 82.1.3 Figure of Merit in SAR ADCs . . . . . . . . . . . . . . . . . 11

2.2 Successive Approximation Register ADC . . . . . . . . . . . . . . . 112.3 Voltage-Mode and Current-Mode Signaling . . . . . . . . . . . . . . 152.4 Current-Mode SAR Architecture . . . . . . . . . . . . . . . . . . . 162.5 Proposed CM-SAR Architecture . . . . . . . . . . . . . . . . . . . . 17

2.5.1 Sampling Process Before the V-I Conversion . . . . . . . . . 172.5.2 Sampling Process After the V-I Conversion . . . . . . . . . . 18

2.6 Fully Differential System Implementation . . . . . . . . . . . . . . . 192.7 Current-Mode SAR ADCs: State of the Art . . . . . . . . . . . . . 192.8 Design Goals of This Work . . . . . . . . . . . . . . . . . . . . . . . 22

3 Current-Mode SAR ADC Design 233.1 Proposed CM-SAR ADC Architecture . . . . . . . . . . . . . . . . 23

3.1.1 CM-SAR ADC Using Unipolar NMOS DAC . . . . . . . . . 233.1.2 CM-SAR ADC Using Unipolar PMOS DAC . . . . . . . . . 243.1.3 Input Gm Stage Design Considerations . . . . . . . . . . . . 253.1.4 CM-Comparator Design Considerations . . . . . . . . . . . . 25

3.2 High-Linearity Input Stage . . . . . . . . . . . . . . . . . . . . . . . 26

ix

x Contents

3.2.1 High-Linearity Gm Stage Implementation . . . . . . . . . . 263.2.2 S/H Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3 Current Steering DAC In SAR ADC . . . . . . . . . . . . . . . . . 333.3.1 Static Properties . . . . . . . . . . . . . . . . . . . . . . . . 343.3.2 Dynamic Properties . . . . . . . . . . . . . . . . . . . . . . . 433.3.3 Unit Current Cell Final Design . . . . . . . . . . . . . . . . 483.3.4 Effect of the Statistical Variations on the CM-DAC . . . . . 48

3.4 High-Resolution Current Comparator . . . . . . . . . . . . . . . . . 523.4.1 High-Resolution TIA . . . . . . . . . . . . . . . . . . . . . . 523.4.2 Modified TIA Design . . . . . . . . . . . . . . . . . . . . . . 593.4.3 Voltage Preamplifier and Core Latch . . . . . . . . . . . . . 61

3.5 Reference Current Generator . . . . . . . . . . . . . . . . . . . . . . 633.6 CLK Generator and CLK Buffers . . . . . . . . . . . . . . . . . . . 643.7 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.7.1 SAR Logic Custom Flip-Flop . . . . . . . . . . . . . . . . . 663.7.2 SAR Logic Block Diagram . . . . . . . . . . . . . . . . . . . 66

4 System Implementation and Measurement Results 714.1 Layout of the Matching-Sensitive Blocks . . . . . . . . . . . . . . . 71

4.1.1 Layout of the Gm Stage . . . . . . . . . . . . . . . . . . . . 714.1.2 Layout of the CM-DAC . . . . . . . . . . . . . . . . . . . . 73

4.2 Top Level Implementation . . . . . . . . . . . . . . . . . . . . . . . 764.2.1 Test Measurement Setup . . . . . . . . . . . . . . . . . . . . 774.2.2 Focused Ion Beam Operation . . . . . . . . . . . . . . . . . 77

4.3 Simulation Results of the Main Blocks in CM-SAR ADC . . . . . . 794.3.1 Input Stage in SAR ADC . . . . . . . . . . . . . . . . . . . 794.3.2 CM-DAC in SAR ADC . . . . . . . . . . . . . . . . . . . . . 824.3.3 Current Comparator in SAR ADC . . . . . . . . . . . . . . 854.3.4 Gm-DAC-TIA in Current-Based SAR . . . . . . . . . . . . . 854.3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.4 Top Level Simulation and Measurement Results . . . . . . . . . . . 904.4.1 Schematic and Post-layout Simulation Results . . . . . . . . 904.4.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 90

4.5 Power Consumption of the Chip . . . . . . . . . . . . . . . . . . . . 964.6 Comparison to Other Works . . . . . . . . . . . . . . . . . . . . . . 97

5 Conclusion and Outlook 99

Bibliography 101

List of Author Publications 109

Resume 111

List of Figures

2.1 Ideal input-output transfer function of a 3-bit ADC showing aquantization error centered around zero [25]. . . . . . . . . . . . . . 6

2.2 Transfer curve illustrating the offset and gain error [25]. . . . . . . 72.3 Transfer curve for a non-ideal 3-bit ADC with a missing code [25]. . 72.4 Transfer curve for a non-ideal 3-bit ADC and its quantization error

illustrating the INL [25]. . . . . . . . . . . . . . . . . . . . . . . . . 82.5 ADC power spectrum showing the intermodulation distortion (IMD). 102.6 Basic SAR ADC model. . . . . . . . . . . . . . . . . . . . . . . . . 122.7 Five bit binary search example [27]. . . . . . . . . . . . . . . . . . . 122.8 Basic structure of a conventional N-bit SC-SAR ADC [28]. . . . . . 132.9 Time-interleaved architecture [24]. . . . . . . . . . . . . . . . . . . 152.10 Basic structure of a conventional N-bit CM-SAR ADC. . . . . . . . 162.11 Input S/H structure of a conventional N-bit CM-SAR ADC [38]. . . 172.12 Proposed CM-SAR ADC model. . . . . . . . . . . . . . . . . . . . . 172.13 Sampling process after the Gm stage model. . . . . . . . . . . . . . 18

3.1 The CM-SAR ADC architecture 1. . . . . . . . . . . . . . . . . . . 233.2 The CM-SAR ADC reported in [7], [9]. . . . . . . . . . . . . . . . 243.3 Different transconductor circuits (a) The source-coupled differential

pair. (b) The resistive source degeneration technique. (c) The activesource degeneration technique. (d) The cross coupled differentialpairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4 Adaptive biasing Gm stage presented in [44]. . . . . . . . . . . . . 273.5 (a) The linearized Gm stage for a± 200 mV differential input voltage

range. (b) The Gm stage o/p current error. . . . . . . . . . . . . . . 283.6 Settling of the Gm stage current at the proposed decision time. . . 293.7 The Gm stage current settling error versus the full-scale input range. 303.8 The RMS of the Gm stage noise current versus frequency. . . . . . . 303.9 SDR of the Gm stage with 200 Monte Carlo runs. . . . . . . . . . . 313.10 Bootstrapped switch. . . . . . . . . . . . . . . . . . . . . . . . . . . 323.11 The unit current cell of the DAC with core current source transistor

using 1.2 V supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.12 Current source mismatch model. . . . . . . . . . . . . . . . . . . . . 353.13 INL yield versus relative mismatch error standard deviation given

by equation 3.7 showing the relative mismatch standard deviationof the unit cell for a 9-bit DAC. . . . . . . . . . . . . . . . . . . . . 35

3.14 SNDR versus relative mismatch standard deviation of a 9-bit MAT-LAB model DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

xi

xii List of Figures

3.15 SFDR versus relative mismatch standard deviation of a 9-bit MAT-LAB model DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.16 Parasitic and output resistance models for (a) the unit cell and(b) the DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.17 INL versus resistance ratio for different common-mode voltages ofa 9-bit DAC model in Fig. 3.16b. . . . . . . . . . . . . . . . . . . . 38

3.18 SNDR versus resistance ratio of a 9-bit MATLAB model DAC. . . . 383.19 SFDR versus resistance ratio of a 9-bit MATLAB model DAC. . . . 393.20 Mismatch error relative standard deviation versus current source

overdrive voltage for the unit cell in Fig. 3.11. . . . . . . . . . . . . 403.21 The unit current cell with (a) resistively degenerated current source

transistor and (b) with I/O current source transistor using 1.8 Vsupply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.22 Mismatch error relative standard deviation versus current sourceoverdrive voltage for the unit cell in Fig. 3.21b. . . . . . . . . . . . . 41

3.23 RMS DAC noise current versus current source overdrive voltage. . . 423.24 Settling of MSB DAC current at the proposed decision time. . . . . 433.25 DAC output resistance and capacitance model. . . . . . . . . . . . . 443.26 MSB settling error versus resistance ratio of a 9-bit DAC model in

Fig. 3.25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.27 (a) The MSB cell with core transistor current sources from Fig. 3.11.

(b) MSB settling error versus the change of node Vcm at 50 Ω loadfor a 9-bit DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.28 (a) The effect of Vcm variation on the current source mismatchstandard deviation. (b) Mismatch error relative standard deviationversus the current source VDS change at 50 Ω load. . . . . . . . . . . 46

3.29 (a) The MSB cell with core transistor current sources from Fig. 3.11.(b) MSB settling error versus the change of Vid at Vcm=600 mV fordifferent load resistance values for a 9-bit DAC. . . . . . . . . . . . 46

3.30 (a) The MSB cell with I/O transistor current sources from Fig. 3.21b.(b) MSB settling error versus the change of Vid at Vcm=600 mV fordifferent load resistance values for a 9-bit DAC. . . . . . . . . . . . 47

3.31 (a) The MSB cell with I/O transistor current sources from Fig. 3.21b.(b) MSB settling error versus the change of Vid at Vcm=700 mV fordifferent load resistance values for a 9-bit DAC. . . . . . . . . . . . 47

3.32 The modified unit current cell for the final DAC implementation. . 483.33 Histogram of max. DNL and INL for 20 Monte Carlo runs using a

digital ramp input signal. . . . . . . . . . . . . . . . . . . . . . . . . 493.34 DNL and INL of the first Monte Carlo run. . . . . . . . . . . . . . . 503.35 DNL and INL of the second Monte Carlo run. . . . . . . . . . . . . 503.36 Worst Case DNL for a 1000 Monte Carlo runs for the CM-DAC

based on the unit cell in Fig. 3.32. . . . . . . . . . . . . . . . . . . . 513.37 Worst Case DNL for 1000 Monte Carlo runs for the RC extracted

view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.38 Comparison between the FF CG/RGC TIAs.(a) The FF-CG TIA.

(b) The FF-RGC TIA. . . . . . . . . . . . . . . . . . . . . . . . . . 533.39 Comparison between the FB voltage/current mode TIAs. . . . . . . 543.40 Resistively degenerated current source FF-CG TIA presented in [20]. 55

List of Figures xiii

3.41 Input-referred RMS noise current of the TIA versus frequency. . . . 57

3.42 TIA input resistance over the differential input voltage range. . . . 57

3.43 Voltage change of node (X) in Fig. 3.40 over the differential inputvoltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.44 TIA input impedance versus frequency. . . . . . . . . . . . . . . . . 58

3.45 The modified FF-CG TIA presented in [9]. . . . . . . . . . . . . . . 59

3.46 Comparison between the resistively degenerated current source TIA[20] and the modified FF-CG TIA [9]. . . . . . . . . . . . . . . . . 60

3.47 (a) TIA input resistance over the Vid range. and (b) Voltage changeof node (X) in Fig. 3.45 over the Vid range. . . . . . . . . . . . . . . 60

3.48 Voltage preamplifier and core of the current comparator. . . . . . . 62

3.49 Comparator comparison time vs the differential overdrive inputvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.50 SR-Latch with buffer stage. . . . . . . . . . . . . . . . . . . . . . . 63

3.51 Reference current generator given in [25]. . . . . . . . . . . . . . . . 64

3.52 CLK generator block diagram given in [71]. . . . . . . . . . . . . . 64

3.53 Delays in the SAR loop. . . . . . . . . . . . . . . . . . . . . . . . . 65

3.54 Optimization of logic and DAC-Control delays. . . . . . . . . . . . . 66

3.55 Custom FF consists of (a) Logic for enable and clear signals and(b) Edge-triggered NAND-based FF with asynchronous Set/Resetoptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.56 Shift register and extra FF for generating the enable signals andthe sampling signals (FS and FSb). . . . . . . . . . . . . . . . . . . . 68

3.57 Control register for generating the DAC-Control signals. . . . . . . 69

3.58 Output register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.1 Layout of the Gm stage with the tail current source. . . . . . . . . . 72

4.2 Current source array symmetric-pair layout pattern. . . . . . . . . . 74

4.3 CM-DAC layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.4 Chip photo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.5 Chip layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.6 Measurement setup model. . . . . . . . . . . . . . . . . . . . . . . . 77

4.7 Designed PCB to measure the CM-SAR ADC. . . . . . . . . . . . . 78

4.8 (a) The FIB machine. (b) Wire cut. (c) Platinum deposition beam.(d) Platinum deposition wire soldering. . . . . . . . . . . . . . . . . 78

4.9 Schematic and post-layout simulations of the dynamic performanceof the Gm stage in the current-based SAR ADC over a 100 MHzNyquist band. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.10 Schematic level simulations of the dynamic performance of the S/Hand Gm stage in the current-based SAR ADC up to 200 MHz samplingfrequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.11 Post-layout simulations of the dynamic performance of the S/H andGm stage in the current-based SAR ADC up to 200 MHz samplingfrequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.12 Schematic level simulations of the dynamic performance for dif-ferent DAC architectures in the current-based SAR ADC over a100 MHz Nyquist band. . . . . . . . . . . . . . . . . . . . . . . . . . 83

xiv List of Figures

4.13 Simulated dynamic performance of the DAC in the current-basedSAR ADC over a 100 MHz Nyquist band for the DAC based on theunit cell in Fig. 3.32. . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.14 Simulated dynamic performance of the TIA and current comparatorin the current-based SAR ADC over a 100 MHz Nyquist band. . . . 86

4.15 Simulated dynamic performance of the DAC, Gm stage and TIA inthe current-based SAR ADC at a conversion rate of 200 MS/s. . . . 87

4.16 Simulated dynamic performance of the Gm stage, DAC and TIA inthe current-based SAR ADC from 0 to 200 MS/s conversion rate. . 88

4.17 Summary of the post-layout simulated dynamic performance of themain blocks in the current-based SAR ADC from 0 to 200 MS/sconversion rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.18 Simulated and measured dynamic performance of the CM-SARADC vs the sampling frequency. . . . . . . . . . . . . . . . . . . . . 92

4.19 Simulated and measured dynamic performance of the CM-SARADC over a 25 MHz Nyquist band. . . . . . . . . . . . . . . . . . . 93

4.20 Measured dynamic performance of the CM-SAR ADC vs the samplingfrequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.21 Measured ADC power spectrum plot with a 2.5 MHz input signalat 50 MS/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.22 Measured ADC power spectrum plot with a two tone test withfrequencies at 1.12 and 1.6 MHz at 50 MS/s. . . . . . . . . . . . . . 95

4.23 Measured dynamic performance of the CM-SAR ADC over the tem-perature at 50 MS/s. . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.24 (a) The power dissipated from the 1.2 V supply (for analog & digitalblocks) and 1.8 V supply (for the DAC). (b) The power consumptionof the analog blocks and the DAC. (c) The power consumption ofthe digital blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

List of Tables

2.1 Literature survey of high-speed CM-SAR ADCs. (* estimated) . . . 202.2 Literature survey of CM-SAR ADCs for conversion rates below

10 MS/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.3 Design goals of this work and the achieved performance. . . . . . . 22

4.1 Comparison to the state-of-the art works . . . . . . . . . . . . . . . 98

xv

Abbreviations

ADC Analog-to-digital converterA/D Analog-to-digitalSAR Successive approximation registerCs Sampling capacitorDAC Digital-to-analog converterCM -DAC Current mode DACGm TransconductanceSC-DAC Switched capacitor DACSC-SAR Switched capacitor SARDSP Digital signal processorV GA Variable gain amplifierV -I Voltage-to-current converterI-V Current-to-voltage converterCS-DAC Current steering DACTIA Transimpedance amplifierCM -SAR Current mode SARSNR Signal-to-noise ratioSQNR Signal-to-quantization noise ratioSNDR/SINAD Signal-to-noise and distortion ratioDR Dynamic rangedBFS Decibels relative to the full scale signal rangeENOB Effective number of bitsTHD Total harmonic distortionSFDR Spurious free dynamic rangeIMD Intermodulation distortionDNL Differential nonlinearity errorINL Integral nonlinearity errorFIB Focused ion beamVref Reference voltage∆ Quantizer step sizeQe Quantization errorLSB Least significant bitMSB Most significant bitFS Full scale signal rangeRMS Root-mean-squaredBc Decibels relative to the carrierIMD3 3rd Intermodulation distortionOSR Over sampling ratioΣ∆ Sigma-delta modulator

xvii

xviii Abbreviations

S/H Sample and holdVin Input voltageVout Output voltageVDAC DAC output voltageCu DAC unit capacitancefs Sampling frequencyUWB Ultra-wide bandTI Time-interleavedN Number of bitsTs Sampling periodGBW Gain-bandwidth-productop− amp operational amplifierCML Current-mode-logicFOM Figure of MeritsFOMW Walden figure of meritsFOMS Schreier figure of meritsk Boltzmann’s constantT Temperature in Kelvingm Small signal transconductancerout Small signal output resistance of a transistorVth Threshold voltage of a transistorPSRR Power supply rejection ratioVDD Positive voltage supplyVi,p Positive input voltageVi,m Negative input voltageIgm,p Positive Gm stage output currentIgm,m Negative Gm stage output currentIdac,p Positive DAC output currentIdac,m Negative DAC output currentIcomp,p Positive current-comparator input currentIcomp,m Negative current-comparator input currentControl p Positive control signalControl m Negative control signalfclk Clock frequencyTclk Clock periodIref Reference currentH/W HardwareVid Differential input voltageVpp Peak-to-peak voltageτ Time constantSDR Signal to distortion ratioFF Feed-forwardCG Common-gateRGC Regulated cascode common-gateFB Feed-backTcomp Comparison/decision time of the comparatorδunit Relative error currentσunit Standard deviation of the relative error current

Abbreviations xix

Iunit DAC unit element current (LSB)Vcm Common-mode voltageI/O Input/outputRload Load resistanceRpar,u Parasitic resistance of the DAC unit cell switchCpar Parasitic capacitanceRbeta Resistance of the Beta-multiplier reference circuitTDAC DAC settling timeTLogic SAR logic delayTDAC,Control Delay of the DAC-Control signalTFF Delay of the Flip-Flop of the SAR logicSTD StandardCLK ClockPCB Printed circuit boardEOC End of conversion signalV erilog-A Analog extension to Verilog

Chapter 1

Introduction

1.1 Motivation

In many mixed-signal systems, analog-to-digital converters (ADCs) are requiredfor interfacing analog signals to digital circuits. The requirement is usually tointegrate these ADCs with digital signal processors (DSPs) in a low-cost CMOStechnology. The main performance measures of an ADC are its resolution (rep-resented as number of bits or decibels), its conversion rate (in Hz) and its powerconsumption(in mW). Every electronic system, which collects, processes and out-puts information, interacts with the environment. Theses systems, e.g. meas-urement equipment, include additional sensors, which convert physical propertiessuch as light, temperature or pressure into electrical signals. These analog signalsare converted into digital data by ADCs. The data is processed further by digitalsignal processing hardware, i.e. microprocessors. Although the application fieldof ADCs expanded very much since their introduction, continuous development isnecessary to cope with the steady improvements of speed, resolution, number ofchannels, power consumption etc. in the digital domain [1].

Speaking of successive approximation register (SAR) ADCs performance met-rics, remarkable improvements have been realized on time-interleaved (TI) chargedomain SAR (SC-SAR) ADCs to reach the speed in the range of GS/s withmedium-resolution and low-power consumption [2] , [3]. However, this has shif-ted the power bottleneck to the preceding block in a wireless receiver, conven-tionally the variable-gain amplifier (VGA) that has to charge a few pF of ADCsampling capacitor (Cs) with rail-to-rail voltage within a few 100 ps with 10-bit linearity [4]. Moreover, time-interleaving a large number of sub-ADCs re-quires significant design effort and complexity, such as multi-phase clock genera-tion/distribution and/or schemes for compensating the offset, gain mismatch andphase skew between the sub-channels. On the other hand, single-channel, non-TISAR ADCs suffer from settling limitations when higher resolutions together withhigher conversion rates are required. This is because the unit capacitor (Cu) sizeof the switched capacitor digital-to-analog converter (SC-DAC) is determined bythe matching requirements which usually results in bigger capacitor sizes, whichconsequently means high-speed power hungry input buffers are required.

1

2 Chapter 1. Introduction

Therefore, a potential improvement towards high-speed non-TI SAR ADCs withsmaller Cs sizes is still highly desired especially if highly scaled CMOS technologyis not available. One approach, which is reported in [5]- [9], is based on replacingthe commonly used voltage (or charge) mode SC-DAC by a high-speed current-mode DAC (CM-DAC) implementation alleviating the problem of the large inputCs [5]. Until recent years, most existing current-mode SAR (CM-SAR) ADCs areused for low power applications with very low conversion speeds [10], [11] and inapplications where the input signal is already in the form of a current, avoiding thevoltage-to-current (V-I) conversion. In most of these applications, sensor signalshave to be processed. Many signals provide a current as the information carryingsignal, e.g. a sensor with a variable shunt resistance, which is connected to avoltage source, or a photodiode as a sensor element. Therefore, in this case theADC should be designed to accept current as the input signal [12] - [16]. In [5], [6]and [8], high-speed SAR ADCs based on a current steering DAC (CS-DAC) arepresented, where the DAC current is converted to voltage and compared with theinput in the voltage domain. In this thesis, the implementation and measurementsof a CM-SAR ADC which also uses a CS-DAC (or CM-DAC) is presented. ThisCM-SAR ADC converts the input voltage signal into a current signal using a Gmstage, thus the whole SAR operation is performed in the current domain.

1.2 Contribution

The contributions made in this thesis are related to the feasibility study andimplementation of a CM-SAR ADC and are listed as follows:

• The implementations of a high-linearity high-speed sample and hold (S/H) andGm stage are given. The Gm stage converts the input voltage to a currentwhich is then processed with a binary search algorithm in a current-based SARloop, where results are published in [17].

• The feasibility and design guidelines for implementing the CM-DAC in the SARADC have been studied, where results are published in [7], [18] and [19].

• The implementation of a high-resolution transimpedance amplifier (TIA) isgiven. The main function of the TIA is to detect the current difference andto amplify it as much as possible to allow for a correct quantization by thesubsequent latch. Results are presented and published in [20] and [21].

• As a proof of concept, the complete schematic implementation of the CM-SARADC is presented. A 10-bit 150 MS/s current-based SAR ADC has been pub-lished in [9].

• The proposed CM-SAR is designed for an overall resolution of 10-bit over aNyquist band from DC to 25 MHz. Measured results of the ADC fabricated ina 90 nm CMOS technology, show a signal-to-noise and distortion ratio (SNDR)of 45 dB and spurious free dynamic range (SFDR) of 58.4 dB, while consuming6 mW from a 1.2 /1.8 V supply. The total input capacitance of the ADC isapproximately 60 % smaller in size compared to the other SC-SAR ADCs in thesame technology node and with the same resolution. This in turn will lead to

1.3. Thesis Outlines 3

a power saving benefit as the input buffers can be excluded. These results arepresented in [22] and [23]. Discrepancies between simulations and experimentsare discussed and possibilities for performance improvement are suggested.

1.3 Thesis Outlines

Chapter 2 introduces the conventional SAR ADCs, compares the voltage-modeand current-mode signal processing, discusses the different CM-SAR ADC archi-tectures and lists a summary of the performance achieved in the published CM-SAR ADCs.

Chapter 3 is about the principle design of the V-I and current-to-voltage (I-V) converters as well as the CS-DAC which are the basic building blocks of theproposed CM-SAR ADC architecture. The first part deals with the V-I block thatis a high-linearity Gm stage which converts the sampled input into a current withthe required accuracy for further processing in the SAR loop. The second partpresents the design guidelines, analysis and simulations of the CM-DAC adaptedin the SAR loop. The section starts with MATLAB simulations to calculatethe static and dynamic requirements of the DAC. Thereafter, different designsare discussed and finally a DAC based on a unary structure, i.e. unit cascoded-current elements, with binary weighted decoding is chosen. The robustness ofthe design is verified using Monte Carlo simulations to determine the differentialnonlinearity (DNL) and integral nonlinearity (INL) of the designed DAC. In thethird part, the I-V block is converting back the difference between the input andthe feedback DAC currents into a voltage to be quantized by the subsequent latch.This chapter finally ends by presenting the speed limitations in the SAR loop andthe implementation of the SAR control logic.

Chapter 4 presents the implementation of a first prototype in 90 nm CMOS,which shows the feasibility of the high-speed and small Cs size in an applicationwith reduced power consumption requirements. This chapter is dealing with threemain parts, the first part presents the layout of the main blocks of the system.In the second part of chapter 4, the layout of the whole CM-SAR ADC, testmeasurement setup and focused ion beam (FIB) operation are presented. In thelast sections, simulation and measurement results of the CM-SAR ADC, powerconsumption of the fabricated chip and comparison to other works are discussed.

Chapter 5 concludes the dissertation and suggests some future work.

Chapter 2

Nyquist Rate SAR ADCs: ASurvey and State of the Art

2.1 Converter Parameters

A large set of parameters describe the performance of data converters. However,the parameters are mainly divided into two classes: static and dynamic.

2.1.1 Static Parameters

In Nyquist rate ADCs, there is a direct relation from input to output for eachsample with ideally no correlation to the previous or following sample. Thus, inan ideal converter and by applying any input, there is a unique quantized outputfor the applied input. The input-output transfer characteristic depicts the staticbehavior of a data converter. For an ideal case the input-output characteristic isa staircase with uniform steps over the entire dynamic range. In Fig. 2.1 the inputvoltage is swept from zero to full scale and the output of a 3-bit ADC is given. TheADC quantizes the input signal into seven discrete levels relative to a referencevoltage Vref . The difference between the actual input voltage to the quantizedoutput is called the quantization error (Qe) of the ADC [24]. The quantizationerror ranges between ±∆/2 and is equal to zero at the mid step. Assuming awhite noise approximation [24], the average noise power of the Qe is given by

PQe =1

∆

∫ ∆/2

−∆/2

Q2e dQe =

∆2

12(2.1)

where ∆ is the least significant bit (LSB) of the N-bit ADC quantized over Vref

and defined by:

∆ =Vref

2N(2.2)

Thus, by reducing the overall quantization noise, converter resolution can then beincreased.

Resolution: the resolution of an ADC defines the accuracy of the A/D conver-sion. It is measured in bits and defines the number of digits of the digital word.The lowest bit of the digital word is the LSB, which defines the step-size, the

5

6 Chapter 2. Nyquist Rate SAR ADCs: A Survey and State of the Art

100

010

Vin/Vref000

011

001

1/8

Digital Output

111

101

110

2/8 3/8 4/8 5/8 6/8 7/8 8/80

1

Vin/Vref

-1

0.5

-0.5

0

Quantization

Error (LSB)

Midstep

Step width

(1 LSB=Δ)

Figure 2.1: Ideal input-output transfer function of a 3-bit ADC showing a quant-ization error centered around zero [25].

highest is the most significant bit (MSB). The higher the resolution of a systemis, the lower is the Qe between the analog input and the quantized digital outputvalue. An ADC with N-bit resolution encodes the full scale (FS) of the analoginput into 2N levels.

Offset: an offset error occurs when there is a constant difference between thevalue of all code transitions and the ideal value of 0.5 LSB. As seen in Fig. 2.2 a, theoffset error is a constant value and it changes the transfer characteristics so that allthe quantization steps are shifted by the ADC offset. Note that the quantizationerror becomes ideal after the initial offset voltage is overcome.

Gain error: is the difference in the slope of a straight line drawn through thetransfer characteristic and the slope of 1 of an ideal ADC, as seen in Fig. 2.2 b.

DNL: is the deviation of the step size of a real data converter from the idealwidth of the bins ∆. Assuming that X(k) is the transition point between successivecodes k and k+1, then the width of the bin k is (X(k + 1) - X(k)); the differentialnon-linearity is:

DNL(k) =(X(k + 1)− X(k))−∆

∆, k = 0.....(2N − 2) (2.3)

2.1. Converter Parameters 7

100

010

Vin/Vref000

011

001

1/8

Digital Output

111

101

110

2/8 3/8 4/8 5/8 6/8 7/8 8/80

1.5

Vin/Vref

1

0

0.5

Quantization

Error (LSB)

Ideal

Offset error

Real

2.5

2

100

010

Vin/Vref000

011

001

1/8

Digital Output

111

101

110

2/8 3/8 4/8 5/8 6/8 7/8 8/80

1.5

Vin/Vref

1

0

0.5

Quantization

Error (LSB)

Ideal

Gain error

Real

2.5

2

Figure 2.2: Transfer curve illustrating the offset and gain error [25].

100

010

Vin/Vref000

011

001

1/8

Digital Output

111

101

110

2/8 3/8 4/8 5/8 6/8 7/8 8/80

Ideal

2 LSBs

(DNL=1)

Real

Missing code

(DNL=-1)

Figure 2.3: Transfer curve for a non-ideal 3-bit ADC with a missing code [25].

A DNL that is equal to -1 LSB represents a missing code. Fig. 2.3 illustrates thiscase. The total width of the step corresponding to 101 is completely missing; thus,the value of DNL5 is -1 LSB. Any ADC possessing a DNL that is equal to -1 LSBis guaranteed to have a missing code [25].

INL: is a measure of the deviation of the transfer function from a reference line(Fig. 2.4) that can be the best-fit line, the end-point line or the ideal DAC line.


100

010

Vin/Vref000

011

001

1/8

Digital Output

111

101

110

2/8 3/8 4/8 5/8 6/8 7/8 8/80

Ideal

Straight line

through end

transitions

1

Vin/Vref

-1

0.5

-0.5

0

Quantization

Error (LSB)

INL

INL

DNL≤0.5

INL≤1

Figure 2.4: Transfer curve for a non-ideal 3-bit ADC and its quantization errorillustrating the INL [25].

The integral non-linearity is given by:

INL(k) =X(k)− Xref(k)

∆, k = 0.....(2N − 1) (2.4)

Where Xref(k) is the ideal transition point of the ideal input-output transfer func-tion. The most suitable reference line is the best-fit line which accounts for gainerror and offset. But when the best-fit line calculation is not required, the end-point line can be used to estimate the INL. In this case the curve corresponds tothe running sum of the DNL:

INL(k) =k∑

i=1

DNL(i) (2.5)

2.1.2 Dynamic Parameters

The frequency response and speed of the analog components of a data converterdetermine its dynamic performance. Obviously, the performance becomes criticalwhen the input bandwidth and the conversion rate are high.

2.1. Converter Parameters 9

Settling-time: is the time at which the step response of a feedback (FB) DACin an ADC remains within a specified error band around its final value. The inputis a step signal applied at time t = 0. The final value is defined to occur a longtime after the beginning of the step.

Aperture uncertainty (clock jitter): is the standard deviation of the samplingtime. It is also called aperture jitter or timing phase noise. It is often assumedthat clock jitter is like a noise with a white spectrum.

Glitch power: can be due to a delay between bit controls or to timing mismatchin the analog sections. Normally its maximum occurs at half scale of Vref , i.e. MSBtransition.

Signal-to-quantization-noise ratio (SQNR): is the ratio between the powerof the signal and the quantization noise of the ADC. The SQNR accounts for thenoise in the entire Nyquist interval. Thereby, SQNR is typically expressed in dBby:

SQNR = 10 ∗ logPsig

PQe

(dB) (2.6)

Since the input signal is typically considered to be a peak-to-peak sine wave equalto the full scale reference of the ADC, then the signal power is defined as:

SQNR = 10 ∗ log(2N∆

2√

2)2

PQe

; SQNR = 6.02 N + 1.76 (dB) (2.7)

Signal-to-noise ratio (SNR): is the ratio between the power of the signal andthe total noise produced by quantization and the noise of the circuit. The SNRalso accounts for the noise in the entire Nyquist interval.

SINAD or SNDR: is similar in definition to the SNR except that non-lineardistortion terms, generated by the input sine wave, are also accounted for.

SNDR = 10 ∗ logPsig

PQe + Pcircuit noise + Pdistortion

(dB) (2.8)

Dynamic range (DR): is the value of the input signal at which the SNR (orthe SNDR) is 0 dB. The parameter is useful for some types of data converters thatdo not obtain their maximum SNR (or SNDR) at 0 dB full scale (dBFS) input.This typically happens in sigma-delta (Σ∆) converters.

Effective-number-of-bits (ENOB): measures the SNDR using number ofbits. SNDR (in dB) and ENOB are linked by:

ENOB =SNDRdB − 1.76

6.02(bit) (2.9)


Total harmonic distortion (THD): is the ratio between the sum of the powersof all harmonic components to the power of the fundamental frequency. It is givenby the following formula:

THD = 10 ∗ log

∑PHD

Psignal

(dB) (2.10)

SFDR: is the ratio of the power of the signal and the power of the highest spuri-ous spectral component in the first Nyquist zone. The SFDR provides informationsimilar to the total harmonic distortion but focuses on the worst tone. The SFDRdepends on the input amplitude.

Intermodulation distortion (IMD): accounts for spur tones caused by non-linearity when the input is made of multiple sine waves as the interaction betweenthem produces intermodulation terms. This non-linearity of a data convertercauses the mixing of the spectral components thus generating spurs at sum anddifference frequencies for all possible integer multiples of the input frequency tones.As shown in Fig. 2.5, the ratio of the root-mean-square (RMS) value of eitherinput tone to the RMS value of the worst third order intermodulation product,reported in decibels relative to the carrier (dBc), is called the IMD3 or the thirdintermodulation distortion term. The input is made by two closely spaced tonesf1 and f2. Often the specification accounts for the third order spurs only, whichoccur at (2f1 - f2), (2f2 - f1). The reason for considering third order terms onlyis that they are close to the input frequencies f1 and f2. Other intermodulationterms are far away from the input and can be filtered out in the digital domain.

Frequency

f2-f1

Power

f1 f2

Intermodulation

distortion (IMD3)

2f1-f2 2f1-f2

Third-order

distortion

product

2f1 2f2

f1+f2

Second-order

distortion

product

3f1 3f2

f1+2f2

Third-order

distortion

product

2f1+f2

Figure 2.5: ADC power spectrum showing the intermodulation distortion (IMD).

Nyquist rate sampling: in order to avoid aliasing during the sampling pro-cess, which would further decrease the SQNR of the ADC, the Nyquist criterionneeds to be met [25]. Nyquist states that the required signal bandwidth must beless than half the sampling frequency of the ADC. Therefore, when the sampling

2.2. Successive Approximation Register ADC 11

frequency is twice the signal bandwidth, the ADC is called a Nyquist rate ADC.This group of ADCs, therefore, can convert higher signal bandwidths comparedto the oversampling ADCs where an over sampling ratio (OSR), defined as theratio between the actual and Nyquist sampling rates, greater than one is used.Flash, folding interpolating, pipeline and SAR ADCs are examples of Nyquistrate converters.

2.1.3 Figure of Merit in SAR ADCs

Figure of merit (FOM) is a parameter used to measure the power efficiency of anADC. The popular Walden figure of merit (FOMW) is usually used to comparedifferent ADCs up to 70 dB linearity:

FOMW =Power

(2ENOB)(fs)(fJ/conv.step) (2.11)

where fs is the sampling rate in Nyquist-rate ADCs and ENOB is the effective-number-of-bits. This figure of merit is commonly used to compare publishedresults as it compares the energy required per conversion step, thus lower FOMmeans a better ADC power efficiency. However, for the converters with more than70 dB linearity, the Schreier figure-of-merit (FOMS) is preferred for the powerefficiency calculations. It represents the 4x per bit trade off slope of the ADCenergy versus the conversion rate [26], thus higher FOMS means a better ADCpower efficiency. The Schreier FOM has two formula, one is related to the DRwhile the other deals with the SNDR:

FOMS,DR = DR + 10log(BW

Power) (dB) (2.12)

FOMS,SNDR = SNDR + 10log(fs/2

Power) (dB) (2.13)

2.2 Successive Approximation Register ADC

The basic SAR ADC block diagram is shown in Fig. 2.6. The analog input voltageVin is held on a S/H circuit. Then, the held value is processed with a binary searchalgorithm within N+1 clock cycles until the final output is stored in a register. Toimplement the binary search algorithm, the N-bit register is first set to midscalethat is, 10000, where the MSB is set to 1 in the 5-bit binary search exampledescribed in Fig. 2.7. This forces the DAC output VDAC to be Vref/2, where Vref

is the reference voltage provided to the DAC. A comparison is then performed todetermine if Vin is less than, or greater than, VDAC. If Vin is greater than VDAC,the comparator output is a logic high, or 1, and the MSB of the N-bit registerremains at 1. In contrast, if Vin is less than VDAC, the comparator output is alogic low and the MSB of the register is cleared to logic 0. The SAR control logicthen moves to the next bit down, forces that bit high, and does another compar-ison. The sequence continues all the way down to the LSB. Once this is done, theconversion is complete and the N-bit digital word is available in the register [27].


S/H

Comparator

SAR LogicN-bit

N-bit

DAC

rst clk

VS/H

VDAC

Vref

N

Output

Vin

Figure 2.6: Basic SAR ADC model.

Vref

Vref/2

Time0

3Vref/4

Vref/4

Bit 4

(MSB)

1 0 1 0 1

VDAC

VS/H

Bit 0

(LSB)

Bit 3 Bit 2 Bit 1

Figure 2.7: Five bit binary search example [27].

The common mode of operation in SAR ADCs is the voltage, or charge, mode. Inthis mode the feedback DAC is built using SC networks. This SC-SAR converterwas first published in [28] and uses a capacitive DAC in the feedback loop whichelegantly combines the DAC with a S/H circuit at the expense of increasing theload capacitor of the previous stage in a wireless receiver chain [4]. Fig. 2.8 showsthe basic structure of a conventional N-bit SC-SAR ADC. First, Vin is sampled onall the 2N capacitors. Then in the hold mode, the bottom plates of all capacitorsare connected to −Vref . Next, the bottom plate of the first capacitor (2N−1Cu)

2.2. Successive Approximation Register ADC 13

Nb1 … bN

+

- C C 2C 4C 2(N-1)C

-Vref

+Vref

Vin

SAR LogicOutput

Figure 2.8: Basic structure of a conventional N-bit SC-SAR ADC [28].

is connected to +Vref while the rest to −Vref , and the top plate switch turns off.The comparator determines the sign of the voltage on the top plate, if positive,then the MSB of Vin is determined to be zero, and in the next clock cycle, the firstcapacitor is connected to −Vref and the second one to +Vref . The same processcontinues until all the N-bits are determined. In the end, the digital output willswitch each capacitor in such a way that the voltage on the capacitor top platewill be very close to zero. The conversion process can be seen as “digital feedback”as opposed to analog feedback to achieve the desired accuracy. All the problemsassociated with analog feedback, such as phase margin, gain margin and linearitydo not exist in “digital feedback”, since there is complete control over the processto avoid any oscillation [29].

The SAR is a very hardware efficient architecture as it uses only a few analog com-ponents (notably only a single comparator and a SC-DAC) to implement N-bitdata conversion, resulting in a compact area and simple design. Moreover, SARADCs consist of circuits which scale well in advanced technologies [30]. Anothermajor benefit of a Nyquist rate SAR converter, in contrast to Σ∆ converter, is itsability to be connected to multiplexed inputs at a high data acquisition rate. Theconversion time is the same for all conversions. This makes the SAR converterideal for many real-time applications, including motor control, touch-screen sens-ing, medical and other data acquisition systems. Furthermore since the topologyproduces a new digital output every 1/fs, the latency of the ADC with respect tothe sampling rate is only one clock cycle of the Nyquist-rate clock fs. As a resultthe SAR topology can be useful in systems which require ADCs in feedback [31].

Since SAR ADCs are commonly known by achieving a moderate-resolution, high-speed and low-power, they are meanwhile employed in communication systemssuch as ultra-wide band (UWB), mm-wave and serial link transceivers. In a wire-less context, the ADC has to be power efficient, and SAR ADCs have been recog-nized in recent years to be the most power-efficient architecture of choice due tothe new invented switching schemes to lower the capacitive dynamic power [2]- [4]and [32]. Moreover, because of the improvement of the CMOS process, SAR ADCs


are a type of ADCs which can significantly benefit from technology scaling becauseCu can be realized in the sub-fF range. Thus for low resolution, smaller samplingcaps can be realized. Therefore, there is continuous research to exploit the im-proved speed of scaled CMOS technologies to increase the achievable samplingrate of SAR ADCs. Additionally, SAR ADCs take advantage of time interleaving,since they are Nyquist rate converters [2].

The two major limitations on the speed of SAR ADCs are the settling time ofthe DAC and the speed of the comparator. Another disadvantage of the SC-SARADC with its built in sampling capacitor in the SC-DAC is that the precedingblock for the ADC in a wireless receiver, which is typically the VGA, has to chargea few pF of ADC sampling capacitor with rail-to-rail voltage within a very shorttime period with high linearity [4]. This will increase the power consumption ofthe VGA and degrades the receiver power efficiency. This is because the Cu sizeof the SC-DAC is determined by the matching requirements for a chosen resol-ution which usually results in bigger capacitor sizes. On the other hand, if thesampling capacitor size of a SAR ADC can be determined only by the kT/C noisesuch as it becomes smaller than 2NCu of the SC-DAC, then the VGA would drivesmaller capacitor size and this will result in a more power efficient system as thehigh-speed power hungry input buffers are excluded.

Obviously, conventional SAR ADCs have a logarithmic dependence on resolution,but they consume multiple clock cycles to implement the conversion algorithm.Thus, one solution to speed up the SAR algorithm is by using an asynchron-ous ADC architecture [33]. The profit from the asynchronous architecture besidethe speed, the power efficiency and the area of the high-speed ADC can be op-timized [34]. However, the problem of the SC-DAC settling time still exists. ATI-ADC architecture, shown in Fig. 2.9, is another solution which can increase theeffective conversion rate of an ADC by multiplexing several ADCs in parallel. Theeffective conversion rate of a TI-ADC can be expressed as fs=fc*N, where fc and Nare the conversion rate of each channel and the number of the interleaved channels,respectively. Generally, power consumption of an ADC grows much faster thanproportional to the conversion rate of the ADC. However, in the TI-structure, theeffective conversion rate can be theoretically increased by N at the cost of onlyN-times power consumption plus the power increase in the clock distribution [35].

The architecture shown in Fig. 2.9 uses an input S/H running at its full speed fs= 1/Ts to acquire the samples to be converted. Then, an analog selector deliversthe input samples to the N parallel ADCs whose conversion frequency is fs/N.Finally, the digital multiplexer sequentially selects the output of each channel toobtain the full speed ADC code. An alternative solution that avoids the demand-ing specification associated with the full speed S/H employs one S/H in each path.However, this requires careful generation and distribution of the control phases asmisalignment degrades the dynamic performances. Other important limitationsare the offset and the gain mismatch between channels. These error sources, whichdo not occur in high-speed single converter applications become significant for in-terleaved architectures as they are transformed into dynamic errors by the systemoperation [24].

2.3. Voltage-Mode and Current-Mode Signaling 15

S/H

VS/H

Digital

MUX

K-bit

ADC

K-bit

fS

2

fS/N

fS

OutputVin

CS

ANALOG

DE-MUX K-bit

ADC

K-bit 1

fS/N

K-bit

ADC

K-bit N

fS/N

K-bit

ADC

K-bit 3

fS/N

Figure 2.9: Time-interleaved architecture [24].

In view to the aforementioned discussion, a potential improvement towards high-speed non-TI SAR ADCs with smaller sampling capacitor sizes is still highlydesired. In this thesis and as previously mentioned, an approach which is basedon replacing the commonly used voltage-mode SC-DAC by a high-speed CM-DACimplementation is presented to alleviate the problem of the large input samplingcapacitor. A comparison between the voltage and current-mode signaling is givenin the next section.

2.3 Voltage-Mode and Current-Mode Signaling

The aggressive reduction in the supply voltage and moderate reduction in thedevice threshold voltage of CMOS voltage-mode circuits, yields a reduced dynamicrange, an increased propagation delay and reduced noise margins [36]. Such scal-ing motivated the designers to introduce the current-mode circuit as a promisingsubstitute for its voltage-mode counterpart. The impact of supply voltage reduc-tion on the performance of current-mode circuits is less severe as compared withthat of voltage-mode circuits. This is because the design emphasis of current-modecircuits is on branch currents rather than nodal voltages [36].

Current-mode techniques (in which the signal is essentially processed in the cur-rent domain) offer a number of advantages. Generally current-mode circuits donot require amplifiers with high-voltage gains thereby reducing the need for highperformance amplifiers. Moreover, current signals are easy to sum, scale and invertwithout the need for operational amplifiers (op-amps). Consequently, its speed isnot limited by the gain-bandwidth-product (GBW) as it is the case for op-amps.At the same time current-mode circuits generally do not require either high pre-


cision resistors or capacitors and when capacitors are used to store the signal, thecapacitors do not need to maintain either good ratio matching or good linear-ity [37]. Consequently, current-mode circuits can be designed almost exclusivelywith transistors making them fully compatible with most digital processes [37].

Signal representation in current-mode circuits depends on the value of the currentflowing through certain branch. Consequently, its upper limit is not constrainedby the supply voltage as in the voltage-mode case in which the voltage signalmust be less than the supply voltage except in some rare applications. In ad-dition, high-frequency operation favors current-mode circuit topologies that arecharacterized by having low-impedance nodes compared to its voltage-mode coun-terpart. Thus, high-frequency applications usually employ current-mode analogcircuits and current-mode-logic (CML) to extend the operating bandwidth. How-ever, current-mode circuits show also good power efficiencies when they are appliedin low-frequency applications [14], [15].

2.4 Current-Mode SAR Architecture

A general CM-SAR block diagram is shown in Fig. 2.10. A current S/H block isused to capture the input current signal at the sampling instants and then holdsthe captured value while the conversion in the SAR ADC takes place. Thereafter,the held value is processed with a binary search algorithm in a current-based SARloop containing a current comparator, a CM-DAC and a SAR control logic. Thefinal digital value is then registered to the output after N+1 clock cycles.

Current Comparator

SAR LogicN-bit

CM-DAC

rst clk

IS/H

IDAC

Iref

N

Output

IinS/H

Figure 2.10: Basic structure of a conventional N-bit CM-SAR ADC.

The S/H block, which is reported in [38], is shown in Fig. 2.11. The input currentis converted to voltage over the diode connected transistor M1, which is thensampled on CS and finally is converted to a current which is then mirrored bythe current mirror formed by transistors M3 and M4. Since the input signal is acurrent signal, internal voltage swings, which also develop along with the currentsignals, do not need to be linear for correct algorithmic operation and this givesswitched-current the potential for low-voltage operation [39].

2.5. Proposed CM-SAR Architecture 17

M2M1

Vdd

Iin

IS/H

Vdd

M3 M4

S/H

IS/H

CS

Figure 2.11: Input S/H structure of a conventional N-bit CM-SAR ADC [38].

However, the aliasing introduced by sampling operation after the I-V conversionby the diode connected transistor M1, which has a non-linear characteristics, limitsthe operating frequency of the input signal, i.e. the input signal must be over-sampled in order to eliminate the aliasing effect. As a result, the BW of the inputsignal is reduced by the oversampling ratio. This is also the reason why mostreferences which using this sampling method are using their ADCs for low speedapplications only, as will be shown in section 2.7.

2.5 Proposed CM-SAR Architecture

2.5.1 Sampling Process Before the V-I Conversion

In contrast to the general CM-SAR ADC architecture, the proposed architecture,as shown in Fig. 2.12, samples the input voltage signal and then the held value isconverted through a Gm stage to a current which is then processed as usual withbinary search algorithm in a current-based SAR loop. The advantage here is thatthis architecture can be used with an input voltage signal, making it usable forgeneral applications.

S/H

VS/H

Gm

Current Comparator

SAR LogicN-bit

CM-DAC

rst clk

IS/H

IDAC

Iref

N

Output

Vin

CS

Figure 2.12: Proposed CM-SAR ADC model.


2.5.2 Sampling Process After the V-I Conversion

An alternatively proposed architecture which was shortly investigated, is basedon the same architecture but the S/H block is moved into the Gm stage, namelybetween the two current mirror transistors M1 and M2. Fig. 2.13 demonstratesthis approach. If the Gm stage, with its current mirror load, has a voltage gaingreater than one, then the signal swing after the Gm stage would be increasedand this in turn allows more kT/C noise and consequently results in a smaller CS.However, the voltage gain of the Gm stage with diode connected load transistorM1 is given by:

Av =VA

Vin

= − gm,Gm stage . rout ≈ −gm,Gm stage

gm,Diode,M1

(2.14)

where gm,Gm stage and gm,Diode,M1 are the transconductances of the Gm stage andthe diode connected load transistor M1, respectively. Unfortunately, increasingthe voltage gain of the Gm stage requires large output resistance, i.e. smallergm,Diode,M1 , which will result in large voltage drop, i.e. large VDS on the diodeload and then will set the input transistors of the Gm stage into the linear mode.Consequently, linearity and voltage gain of the Gm stage are degraded. Therefore,the previously mentioned advantage of implementing the S/H block into the Gmstage is diminished. Due to these reasons, this approach was excluded from thefurther designs and implementations.

Gm

I-Comparator

SAR Logic

CM

-DA

Crst clk

IDAC

Iref

NOutput

Vin

M2M1

IS/H

S/H

CS

M4 M3

IDAC,mirroredIgm

N

VA

Figure 2.13: Sampling process after the Gm stage model.

2.6. Fully Differential System Implementation 19

2.6 Fully Differential System Implementation

The structure shown in Fig. 2.12 is based on a single-ended concept. However,in practical implementations and in order to obtain a high immunity againstcommon-mode interferers, systems are usually implemented as a fully differen-tial structure [40], where inputs and outputs are differential signals. In this case,the output swing is increased by a factor of two over the single-ended output withthe same available voltage swing, which leads to a 3 dB better SNR performance,which is very effective especially for low-voltage applications. Another advantageis that the power supply rejection ratio (PSRR) will be improved. This is becausethe supply noise appears at the outputs as common-mode noise which is canceledout. Moreover, the even order harmonic at the outputs of each block will be can-celed in the ideal case as they have similar amplitude and phase. However, inpractical implementation, exact cancellation is not possible due to process para-meter tolerances and temperature gradients, which result in mismatches betweentransistors.

2.7 Current-Mode SAR ADCs: State of the Art

The ADCs in [5] and [6] show high-speed conversion rates in the range of GS/s.They are based on a TI architecture which is based on a CS-DAC but the DACcurrent is converted to voltage and compared with the input in the voltage do-main. The paper in [5] presents a 10-bit 2.6 GS/s ADC, which interleaves 64reduced-radix SAR ADCs employing CS-DACs. The ADC combines interleavinghierarchy with an open-loop buffer array operated in feedforward-sampling andfeedback-SAR mode. The sampling front-end consists of four interleaved track &hold (T/Hs) at 650 MS/s that are optimized for timing accuracy and samplinglinearity, while the back-end consists of four ADC arrays, each consisting of 1610-bit current-mode non-binary SAR ADCs. Timing and bandwidth matchingis achieved intrinsically, while gain and offset mismatches and DAC linearity arecalibrated on-chip.

Similar to the design in this thesis, the SAR ADC architecture that is used in [5]splits the sampling and DAC functions, allowing the sampling node to be dimen-sioned for thermal noise, and not for matching. The CM-DAC approach used in [5]simplified the reference generation and distribution in the ADC array. It also en-abled large input signal swing and low capacitor values, resulting to low-powerand high-speed operation. The ADC in [8] represents a non-TI, high-speed andhigh-resolution CS-DAC in SAR based on the same concept in [5]. A comparisonbetween the recently implemented high-speed CM-SAR ADCs is given in Table 2.1.

On the other hand, Table 2.2 summarizes the published lower speed CM-SARADCs from the year 2007 until now. All the published works are used in applica-tions where the input signal is already in the form of a current such as IntegratedBiosensor Arrays [41] except the paper in [13] which uses a Gm stage to convertthe input voltage to a current for processing in a current-based SAR loop. Itcan be seen also from the table that in all published works, low-power and lowconversion speeds were the main targets of the designed ADCs. Moreover, all the


presented results are only simulation results and due to the input signal currentnature, the estimation of the CS size is not applicable when it is not mentioned inthe papers.

The paper in [13] presents a low-power interface circuit with CM-SAR ADC forbiomedical implantable devices application. The circuit incorporates a current-mode S/H into the Gm stage as an ADC front-end, i.e. the sampling process isperformed after the Gm stage as in Fig. 2.13. Even though, the simulation resultsshow that the maximum linearity range of the Gm stage is obtained from -0.2 V to+0.2 V, the input signal range is only set from 0 to 50 mV, which results in an es-timated CS of about 330 fF. However, the acceptable input signal frequency rangeis from 0.1 Hz to 500 Hz at a sampling rate of 40 KS/s. The ADC performance athigher signal frequencies is not addressed in this paper, indicating that the signalbandwidth is only limited to 500 Hz due to the problem mentioned in section 2.4.

The paper in [15] presents a switched-current SAR ADC tailored for column-parallel operation in a high-resolution current-mode imagers. The ADC is builtaround a single current comparator and an 11-bit sub-binary CM-DAC. The ADCconverts an input current signal and does not need an input sampling circuit. Suchfunction is already implemented in the imaging array when the pixels are selectedfor output one at a time. Output from a pixel can be regarded constant dur-ing conversion, since the conversion period is much shorter than the frame time.The output is digitally calibrated in order to compensate for component mismatch.

In comparison to reference [13], the work in this thesis also uses a Gm stage toconvert the input voltage to a current which is then processed with a binary searchalgorithm in a current-based SAR loop. However, the sampling capacitor in thiscase is moved before the Gm stage to overcome the problem of the low-voltagegain of the Gm stage with diode-connected-transistor load and the resulting biggerCS as discussed in the previous section. Additionally, the performance of thefabricated prototype is validated for the whole Nyquist band of 25 MHz. Moreover,the ADC architecture in this thesis can be used with an input voltage signal,making it usable for general applications compared to the paper in [15] which isadopted for input current signals only.

Ref.Tech. Res. Speed SNDR CS (pF) Power FOM

(nm) (bits) (GS/s) (dB) Vswing (Vpp−diff) (mW) (fJ/conv.-step)

[5] 65 10 2.6 48.50.11*

480 849.21.4

[6] 65 11 3.6 500.58*

795 854.71.2

[8] 40 14 0.035 74.47

54.5 363.11.8

Table 2.1: Literature survey of high-speed CM-SAR ADCs. (* estimated)

2.7. Current-Mode SAR ADCs: State of the Art 21

Ref

.Y

ear

Tec

hnol

ogy

Res

oluti

onC

onve

rsio

nSN

DR

EN

OB

SF

DR

TH

DP

ower

FO

MIn

put

Sig

nal

(nm

)(b

its)

Rat

e(K

S/s

)(d

B)

(bit

s)(d

Bc)

(dB

)(µ

W)

(fJ/c

onv.-

step

)T

yp

e

[12]

2014

180

825

20.6

3.12

38.0

5-

2.6

1188

3C

urr

ent

[10]

2012

180

816

508

--

0.45

132

Curr

ent

[13]

2012

180

840

508

--

2.2

215

Vol

tage

[11]

2011

180

81.

2346

.23

7.38

--

73.1

935

7C

urr

ent

[14]

2010

130

81

47.5

17.

6-

-47.

510.

255

657

Curr

ent

[15]

2008

250

1083

0062

.410

85.7

-93

010

9.4

Curr

ent

[16]

2007

180

860

050

8-

-0.

563.

6C

urr

ent

Tab

le2.

2:L

iter

ature

surv

eyof

CM

-SA

RA

DC

sfo

rco

nve

rsio

nra

tes

bel

ow10

MS/s

.


2.8 Design Goals of This Work

Since the original design specifications were targeting a high conversion rate non-TI SAR ADCs, the design in this work started by considering a conversion rate of200 MS/s and a 10-bit ADC resolution as shown in Table 2.3. The conversion wasdone within 10 clock cycles, as the sampling process was initially included in thefirst cycle together with the settling of the Gm stage and this is translated to asystem clock frequency of 2 GHz as will be discussed in section 3.2.1. In this case,a special clock generator circuit has to be designed to reduce the sampling clockjitter for the desired 10-bit linearity at 200 MS/s conversion rate. This clock jittermust be smaller than 630 fsec [42], to ensure that the linearity of the system is notlimited by the clock jitter. After implementing the S/H circuit and the SAR logicon transistor level, the conversion speed was reduced to about 150 MS/s due tothe delay of the SAR logic in the chosen technology and the required extra cyclefor the sampling process. As a result, the system clock frequency was reduced toabout 1.65 GHz as will be discussed in section 3.4.3. After the layout of the DACand due to the increased parasitic capacitance at the DAC output together withthe large input impedance of the TIA, the speed of the SAR ADC was reducedagain to about 70 MS/s as will be discussed in section 4.4.1. Finally, the measuredspeed of the fabricated chip is dropped from the post-layout simulations to about50 MS/s. Discrepancies between simulations and experiments are discussed insection 4.4.2. Since the measured speed is dropped by about four times comparedto the originally designed specifications, the effect of the sampling clock jitter inthis case can practically be ignored.

ParameterResolution Speed SNDR

(bits) (MS/s) (dB)

Design Goals (section 3.2.1) 10 200 62

Schematic simulations (section 3.4.3) 8.5 150 53

Post-layout simulations (section 4.4.1) 8 70 50

Measurements (section 4.4.2) 7.2 50 45

Table 2.3: Design goals of this work and the achieved performance.

Chapter 3

Current-Mode SAR ADC Design

3.1 Proposed CM-SAR ADC Architecture

3.1.1 CM-SAR ADC Using Unipolar NMOS DAC

Fig. 3.1 shows the first architecture, where the DAC is based on NMOS unit currentsources. Since the operation of the SAR logic is to equalize the input currents ofthe comparator, the positive output terminal of the Gm stage must be connectedto the negative one of the DAC, and vice versa. For this case, the TIA, as aninput stage of the current-mode comparator has to provide, in addition to its owncurrent, the current for the Gm stage and the DAC (Igm,p + Idac,m), a relativelynon-power-efficient solution.

TIA+

Register

SAR

Control

Logic

Output

[0:9]

fclk

Iref

Icomp,p

Icomp,m

Control_p [0:8]

Igm,p Igm,m

S/HfsampleVi,m

Vi,p

++

Gm

X

Y

Control_m [0:8]

Tclk

Tsample=11*Tclk

fclk

Current Comparator

Av

DAC

+

Idac,pIdac,m

Figure 3.1: The CM-SAR ADC architecture 1.

23

24 Chapter 3. Current-Mode SAR ADC Design

TIA+

Register

SAR

Control

Logic

Output

[0:9]

DAC

fclk

+

Iref

Icomp,p

Icomp,m

Idac,p Idac,m

Control_p [0:8]

Igm,p Igm,m

S/HfsampleVi,m

Vi,p

++

Gm

X

Y

Control_m [0:8]

Tclk

Tsample=11*Tclk

fclk

Current Comparator

Av

Figure 3.2: The CM-SAR ADC reported in [7], [9].

3.1.2 CM-SAR ADC Using Unipolar PMOS DAC

The architecture in Fig 3.2 yields a more power efficient solution. The DAC islocated above the Gm stage and realized with PMOS transistors. In this case, thepositive output terminals of the Gm stage and the DAC are connected together,also the negative ones too, to ensure proper operation. The provided current forthe Gm stage from the TIA in this case is reduced to (Icomp,p = Igm,p - Idac,p).A disadvantage of this structure compared to the one in Fig. 3.1 comes from thelimited voltage swing for both Gm stage and DAC especially in low voltage ap-plications.

The detailed description of the ADC architecture in Fig. 3.2 is as follows: A boot-strap switch is used to linearize and minimize the ON-resistance of the samplingswitch. The sample switch captures the input voltage signal at the sampling in-stants and then holds the captured value while the conversion in the SAR ADCtakes place. Thereafter, the held value is converted to a current by a Gm stage.In high resolution SC-SAR ADCs, the sampling capacitor size is limited by thematching requirements of the SC-DAC. This results in lower settling speeds be-cause bigger sampling capacitors are usually required. In the system of Fig. 3.2,the sampling capacitor size is only limited by the kT/C noise of the S/H circuit.For the target 10-bit ADC resolution, the input signal range should be maximizedin order to allow a maximum kT/C noise. This will result in a minimum samplingcapacitor size, which is smaller than the sampling capacitor size of a corresponding

3.1. Proposed CM-SAR ADC Architecture 25

SC-SAR ADC with the same resolution. The maximized input voltage swing alsorequires, a V-I converter having a wide linear input voltage range with a 10-bitoutput current accuracy [17].

3.1.3 Input Gm Stage Design Considerations

The linear input voltage range depends on the transconductor’s architecture, thelinearization technique and the selected technology. Moreover, for high-speed op-erations, large transconductance values are needed. In the proposed prototypedesign, with the proposed settling speed of 4.6 GHz as well be described in sec-tion 3.2.1, the required transconductance value is found to be 8 mS for a lineardifferential input voltage (Vid) range of about 400 mVpp with a 10-bit output cur-rent accuracy. With these values, CS is found to be 700 fF and the single-endedcurrent range at the output of the Gm stage is found to be 1.6 mA, which is thenused as the DAC-reference current in the following current-based SAR loop as willbe explained in sections 3.2.2 and 3.3, respectively.

In order to obtain a high immunity against common-mode interferers, the pro-posed system is implemented as a fully differential structure [40]. In addition,due to the differential nature of the converted current, the current comparatorcan perform the first comparison without any DAC current cells switching: In thefirst conversion step, the currents of the DAC outputs are used to bias the Gmstage and the 1st decision is made based only on the differential input currentlevel. During the next conversion steps and based on the comparator decisions,the binary search algorithm is adopted, where the two DAC outputs are switch-ing their currents during the bit cycle in a fully differential fashion. The DAC isrealized with PMOS transistors, since the output resistance is higher for PMOStransistors compared to their NMOS counterpart. A high output resistance is oneof the most important parameters influencing the DAC dynamic properties. Fora fully differential 10-bit SAR ADC, only a 9-bit DAC is required because the1st bit is determined based on the sign of the input signal. The DAC is builtusing a single-sided PMOS current cell array with 511 unit current cells, only halfthat of the charge-based SAR ADC where a double-sided unit capacitor array isrequired [43]. Although the use of a single-sided array is less power efficient, itreduces the hardware (H/W) effort, which is desired for this prototype design. Byusing currents instead of voltages, the sensitivity to supply and substrate noiseand parasitic coupling is significantly reduced [5]. Moreover, the CS-DAC, whenused with a small load resistance, can drive large capacitive loads without sufferingfrom the SAR converter-gain being highly dependent on the amount of parasiticcapacitance at the DAC output [5].

3.1.4 CM-Comparator Design Considerations

The current comparator consists of a TIA, which serves as preamplifier of thecomparator, and a latch as the comparator core. The main function of the TIAis to detect the current difference and to amplify it as much as possible to allowfor a correct quantization by the subsequent latch. Trade-offs between input res-istance, noise and voltage headroom pose challenges in the design of high-speedhigh-resolution TIAs. A low TIA input resistance is needed due to the precision


requirement imposed by the DAC and the Gm stage which in turn requires eithera large biasing current or adding additional noisy components which in both casesresults in an increased input referred noise current. The algorithm of the SAR-logic tries to equalize the two currents (Icomp,p and Icomp,m) of Fig. 3.2 flowing intothe current comparator. This is achieved by the negative feedback of the SARloop which iteratively forces the two currents to become equal. Moreover, thelow-impedance nature that is assumed for the TIA causes the DAC current to beeffectively subtracted from the input current. If the two input terminals of theTIA have a sufficiently low input impedance, their input voltages will barely varyand the voltages at node X and Y in Fig. 3.2 can be assumed to be constant or atleast low swing. This is beneficial for precise operation of the DAC and the Gmstage because it minimizes the effect of channel length modulation. The detailedsub-circuit design of the CM-SAR ADC is described in the following sections.

3.2 High-Linearity Input Stage

Design considerations for high-linearity Gm stage and S/H circuits are discussedin this section. Achieving high-linearity input voltage range with 10-bit outputcurrent precision is the design goal of this section.

3.2.1 High-Linearity Gm Stage Implementation

In this section, the aim is to design a low-noise, high-speed and high-linearityGm stage to be adopted in the current-based SAR ADC. In principle, the well-known source-coupled differential pair shown in Fig. 3.3a has only a very narrowV-I linearity range, resulting in limited input signal range. This limited signalrange needs small kT/C noise for the required 10-bit linearity, which results inlarger sampling capacitor size. Transconductor circuits employing different lin-earization techniques are presented in [40]. One linearization technique that iscommonly used employs passive and active source degeneration. However, in or-der to achieve high V-I linearity range with resistive source degeneration technique(Fig. 3.3b), big resistance values are needed. This will result in small values of Gmand, therefore, lower settling speeds.

On the other hand, the active source degeneration technique shown in Fig. 3.3cachieves higher V-I linearity ranges but only with very precise adjustment of theactive linearization circuit. The linearity of this architecture is then degraded byconsidering the process variation and the transistors mismatch. More elegant lin-earization techniques are based on an optimal algebraic sum of non-linear terms,yielding ideally only a linear term. This can be done in practice by using crosscoupled differential pairs as shown in Fig. 3.3d. The drawback of this technique isthe increased sensitivity to transistors mismatch, resulting in a linearity degrad-ation. Also, since it depends on current subtraction, the Gm values are smallresulting in lower settling speeds.

In this work, the chosen linearization technique is based on an adaptive biasingtechnique [44]. The Gm circuit is shown in Fig. 3.4. The circuit has a simpleconfiguration and good high-frequency performance due to the absence of internalhigh-impedance nodes. Qualitatively, the circuit operates in the following way:

3.2. High-Linearity Input Stage 27

M1 M2

Vi,mVi,p

Igm,mIgm,p

MCS

IBVB

(a)

M1 M2

Vi,mVi,p

Igm,mIgm,p

MCSVB

RSRS

IB

(b)

M1 M2 Vi,mVi,p

Igm,mIgm,p

MCS

IB

M3

M4

MCSVB

IB

(c)

M1 M2 Vi,mVi,p

Igm,mIgm,p

Mcs1

VB1

IB1

M3 M4

Mcs2

IB2

VB2

(d)

Figure 3.3: Different transconductor circuits (a) The source-coupled differentialpair. (b) The resistive source degeneration technique. (c) The active source de-generation technique. (d) The cross coupled differential pairs.

M1 M2

M3 M4

M5 M6

VCS

Vi,mVi,p Igm,mIgm,p

VddVdd

MCS

IB= 4.5 mA

VB

Figure 3.4: Adaptive biasing Gm stage presented in [44].


When Vid is small, both M5, and M6, operate in the linear region. However, whenVid is positive and large, M5 enters the cutoff region while M6 remains in the linearregion. If Vid is negative and large, M5 stays in linear region while M6 enters thecutoff region. The sum of the currents through the transistors M3-M6 decreases asthe magnitude of Vid increases, thereby increasing the sum of the currents throughthe source-coupled pair M1 and M2 to keep a constant bias current IB. This tendsto keep the common source voltage VCS at a constant value within a certain rangeof the differential input signals. The output current for this Gm stage is given by

Iout = 2 β1,2 (VCS + Vth) Vid, (3.1)

where Vth is the threshold voltage and VCS is the source potential of transistorsM1 and M2. β1,2 is equal to µnCox

WL

of transistors M1 and M2. Therefore, thetransconductor has a constant transconductance given by

Gm = 2 β1,2 (VCS + Vth). (3.2)

The advantage of this Gm circuit configuration compared to the other Gm stagesin Fig. 3.3 is that the transconductance value can be adjusted independently fromthe linear range and the effect of transistors mismatch on the Gm stage linearityis reduced. In the following sections, the performance of the Gm stage designin terms of linear input range, settling, noise and matching will be discussed.As a major advantage, the current-based SAR requires precision only during thecomparator decisions, i.e. in the settled state. Therefore, the settling performanceof the Gm stage can be met more easily.

Linear Input Voltage Range

The Gm stage from Fig. 3.4 is implemented in a 1.2 V 90 nm CMOS technology,and designed to achieve a maximum linear Vid range of about 400 mVpp. Increasingthe input voltage would bring the differential pair transistors M1 and M2 into thelinear mode, hence decreasing the output current precision. The transconductancestage is designed for 8 mS, which, according to Fig. 3.5, is kept sufficiently constantfor above 10-bit linearity over the 400 mVpp differential input range.

-200 -100 0 100 200

7.85

7.9

7.95

8

8.05

Vid (mV)

Gm

(m

S)

(a)

-200 -100 0 100 200

-0.5

0

0.5

Vid (mV)

Ou

tpu

t C

urr

en

t E

rro

r (L

SB

)

(b)

Figure 3.5: (a) The linearized Gm stage for a ± 200 mV differential input voltagerange. (b) The Gm stage o/p current error.


Settling Performance

This design requirement is related to the dynamic properties of the transconductorcircuit. In this work, where the Gm stage is adopted in the current-based SARADC, dynamic errors are not seen at the output because only the settled accuracybefore the decision process by the latch is of importance. For the proposed system,a decision time of 250 ps, that is half of the period of the 2 GHz clock frequency asshown in Fig. 3.6, is assumed. This decision time is the maximum available timefor the settling of the Gm stage current step before the decision process.

The error ∆I associated with each current transition can be expressed as [45]:

|∆I(kT)| = |Iload(k)− Iload(k− 1)| . e(−T/τ) < 0.5 LSB, (3.3)

where |Iload(k)− Iload(k− 1)| is the steady state absolute difference between twocurrent steps. T is the settling time and τ is the time constant of the settlingprocess. The Gm stage current must settle to a 10-bit accuracy within time T,meaning that a time constant of about 35 ps is required. Assuming a TIA inputimpedance of 50 Ω and the output resistances of the DAC and the Gm stage arelarge, the maximum acceptable parasitic capacitance at the TIA input node is ap-proximately 0.7 pF. Together with the 50 Ω TIA impedance, this capacitance leadsto a 3-dB bandwidth of about 4.6 GHz, which also determines the noise bandwidthof the Gm stage. The lengths for transistors M1 and M2 in Fig. 3.4 are chosen,such as to minimize the parasitic capacitances at the TIA input nodes. Duringthe Gm stage current settling, the DAC is in the reset phase, meaning that theoutput capacitance and resistance of the DAC have less influence on the settlingprocess of the Gm stage. The settling speed requirement leads to a design withIB = 4.5 mA bias current in the Gm stage, which is translated into an 8 mS lineartransconductance over a 400 mVpp differential input range.

The Gm stage current settling error is simulated for the entire Vid range andthe result of the simulation is shown in Fig. 3.7. The simulation shows that theabsolute value of the Gm stage current settling error is much less than 0.5 LSB forthe entire range. It also shows that the settling of the Gm stage is sufficiently fastas to leave enough time for the settling of the input S/H within the same clockcycle. These results indicate that the dynamic requirement for the designed Gmstage in the presented current-based SAR ADC can practically be achieved.

ΔI

Igm_ideal

500 psec

ReadIgm(t)

T=250 psec

Iload(k)

Iload(k-1)

Figure 3.6: Settling of the Gm stage current at the proposed decision time.


-200 -150 -100 -50 0 50 100 150 200

0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

Vid (mV)

|Gm

Cu

rre

nt S

ettlin

g E

rro

r| (

LS

B)

Figure 3.7: The Gm stage current settling error versus the full-scale input range.

10-2

10-1

100

101

0.2

0.4

0.6

0.8

1

1.2

1.4

Frequency (GHz)

RM

S N

ois

e C

urr

en

t (µ

A)

4.6 GHz

Quantization Noise Current Limit

Gm Stage RMS Noise Current

Figure 3.8: The RMS of the Gm stage noise current versus frequency.


Noise Performance

The 3-dB bandwidth required for sufficiently fast settling together with the chosenbias current and the Gm stage’s input transistors operating point determine theGm stage RMS noise current. Choosing the RMS value of the Gm stage noisecurrent equal to the quantization noise current results in a 3 dB or 0.5-bit per-formance drop compared to the ideal SQNR. Fig. 3.8 shows the RMS of the Gmstage output noise current versus frequency. The red line indicates the quantiza-tion noise current limit. The figure also shows that the frequency, where the RMSvalue of the Gm stage noise current is equal to the quantization noise currentindeed occurs around 4.6 GHz, according to the settling speed requirements.

Matching Analysis

In order to demonstrate the robustness of the designed Gm stage, namely theeffect of transistor mismatch and process variations on the linearity of the Gmstage, results of a 200 run Monte Carlo simulation of the Gm stage are presentedin Fig. 3.9. The simulation shows that the signal to distortion ratio (SDR) isbetter than 62 dB for all runs, meaning that the required 10-bit linearity of theGm stage is achieved even under the effect of transistor mismatch and processvariations. Here, the main source of mismatch is the source-coupled pair M1 andM2 in Fig. 3.4, because it has a direct influence on the output currents Igm,p andIgm,m.

62 64 66 68 70 72 74 76 78 800

10

20

30

40

50

Signal to Distortion Ratio (dB)

Nu

mb

er

of R

un

s

µ = 72.34

σ = 3.03

N = 200

Figure 3.9: SDR of the Gm stage with 200 Monte Carlo runs.


CB

FS

Vdd

FSb

FSbBootstrapped

switchVin

Vout

CS

Mp

Mn M1

G1CG+Cp

Figure 3.10: Bootstrapped switch.

3.2.2 S/H Circuit

The bootstrapped switch [43] shown in Fig. 3.10 performs the S/H function. Withthe bootstrapped switch, the gate-source voltage of the sampling transistor is fixedat the supply voltage VDD. This improves the switch linearity and decreases theswitch resistance for high-speed operations.

In the tracking phase the pre-charged capacitor CB bootstraps the switch M1 toVDD. In the hold phase, the switch gate is grounded. In this topology, the risetime of VG1 is determined by the time constant of the bootstrap loop, given by theseries connection of CB and CG1 + CP and the values of the ON-resistors RMn,ON

and RMp,ON of transistors Mp and Mn, respectively, in the bootstrapping loop.Capacitor CB is the bootstrap capacitor, CG1 is the switch gate load and CP is thetotal parasitic capacitance of the devices and interconnects. The time constantcan be expressed as:

τ = (RMn,ON + RMp,ON)CB(CG1 + CP)

CB + CG1 + CP

≈ (RMn,ON + RMp,ON) (CG1 + CP),

if CB >> (CG1 + CP).

(3.4)

At the initial phase of the track transient, before VG1 assumes a sufficiently largevalue to fully turn on Mn, Mp is saturated and dictates the current flowing fromCB to charge node G1. The slowly rising VG1 defines RON of Mn, which influenceshow quickly VG1 rises to track the signal. Increasing Mp does not make the tran-sient fast enough and introduces more parasitics.

3.3. Current Steering DAC In SAR ADC 33

The ON-resistance of the bootstrapped switch is given by:

RON,NMOS =1

µnCox(WL

)M1(VDD − Vth,NMOS). (3.5)

Therefore, the ON-resistance in ideal case is independent on the input voltagewhich improves the switch linearity. As mentioned in section 3.1, the samplingcapacitor size is set by the kT/C noise of the S/H circuit. For the target 10-bitADC resolution, the input signal range should be maximized in order to allow amaximum kT/C noise. This will ensure a minimum sampling capacitor size. Forsufficient SNR, the thermal kT/C noise of the S/H circuit has to be smaller thanthe quantization noise given in equation 2.1. Therefore, the sampling capacitorsize is determined based on the following inequality:

2kT

CS

≤ PQe ⇒ CS ≥ 24kT(2N

VFS

)2 (3.6)

where VFS is approximately equal to Vref in equation 2.2 for high resolution ADCs.Obviously, the input swing is the factor for determining the sampling capacitorsize. In this prototype design, and for a linear Vid range of about 400 mVpp with a10-bit output current accuracy, the single-ended sampling capacitor size is chosento be 700 fF, which ensures that the total thermal kT/C noise is smaller than thequantization noise.

3.3 Current Steering DAC In SAR ADC

Various CS-DAC designs are presented, e.g. in [46] - [60]. Some of them are basedon binary weighted current sources [46] - [53]. Others are based on segmented orthermometer architectures [54] - [60]. However, adapting the CS-DAC into theproposed SAR ADC requires to switch one binary weighted current cell in eachcycle, avoiding the use of a complex thermometer decoder. Therefore, the designedDAC in this work is based on a unary structure, i.e. unit current elements, withbinary weighted decoding.

The first investigated version of the unit current cell for this design is shown inFig. 3.11. It consists of a cascoded current source with differential switches con-trolled by a D-flip-flop. Initially, the D-flip-flop is considered as an ideal block witha reset capability in order to dump the DAC current during the reset phase. Therequirements on a CS-DAC are divided into static and dynamic ones. The staticbehavior is determined by the settled output values while the dynamic propertiesare determined by the transition between two states. The later includes slewing,glitches, time skew, etc. [45]. As a huge benefit, the current-based SAR requiresprecision only during the comparator decisions, i.e. in the settled state. Therefore,in this system, it is not required to have dynamic errors being as precise as theoverall DAC resolution, as it is usually the case for CM-DACs where the entiresettling process must be taken into account. Thus, dynamic error specifications ofthe CM-DAC can more easily be met for the proposed high-speed current-basedSAR. In the following subsections, the static and dynamic requirements of theCM-DAC are discussed in detail.


Mcasp

Mcsp

Ms Ms

Vdd

Vcasp

Vcsp

D Q

Qb

Control

CLK

Iom Iop

Dump

Ms

Idumpreset

N-Well

1.2V

Figure 3.11: The unit current cell of the DAC with core current source transistorusing 1.2 V supply.

3.3.1 Static Properties

Current Source Mismatch

The most important static property is the current source mismatch. Mismatchof transistors due to process variations are of stochastic nature. The β, W/L orVth mismatch for a CMOS current source can be characterized by its distribution,transistor sizes, and physical distance. The mismatch may also depend on otheraspects such as, for example, the gradient of the oxide thickness over the arrayof current sources, or voltage drops over bias or supply wires. A current sourcemismatch error can be modeled as an additional current source ∆I0 in parallelwith the nominal one of Fig. 3.12. For a unit current source, the relative errorcurrent δunit is normally distributed with zero mean and standard deviation σunit.First, it is assumed that the current sources are uncorrelated. This is a very coarseassumption, and in reality, transistors close to each other will have highly correl-ated errors [45]. For the ith bit current source, the relative error current is δi withzero mean and standard deviation σi = σunit/

√2i, since 2i unit current sources are

connected in parallel [45].

An N-bit binary-weighted DAC has current sources with sizes ranging from onetimes the LSB current to 2N−1 times the LSB current. This can lead to largelinearity errors at the major code transitions. It is important to limit the linearityerrors at these major code transitions, otherwise they can reduce the obtainedSFDR. In this design, the aim is to achieve a 3σ yield, meaning that 99.7 % ofthe converters must have an INL smaller than 0.5 LSB. An INL smaller than 0.5LSB guarantees that the maximum linearity error is smaller than the maximumquantization error. Additionally, if the INL is less than 0.5 LSB then the DNL willbe less than 1 LSB [53]. A DNL smaller than 1 LSB ensures that the converter


Iunit

Vdd

Φ0

ΔI02N-1

Iunit

ΦN-1

ΔIN-1

Iload

RL -5 -4 -3 -2 -1 0 1 2 3 4 50

0.1

0.2

0.3

0.4

Normal Distribution Function

x

f(x)

Figure 3.12: Current source mismatch model.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.997.5

98

98.5

99

99.5

100

100.5

Relative Mismatch Error Standard Deviation [%]

INL

Yie

ld [%

]

σunit/Iunit= 0.74%

INL

Yie

ld=

99.7

%

Figure 3.13: INL yield versus relative mismatch error standard deviation given byequation 3.7 showing the relative mismatch standard deviation of the unit cell fora 9-bit DAC.

is monotonic: every increase of the digital input code leads to an increase ofthe analog output value. The relative standard deviation of the unit cell can becalculated using the equation in [60] which is displayed in Fig. 3.13:

σ(I)

I≤ 1

2C√

2Nwith C = inv−norm(0.5 +

yield

2). (3.7)

Where σ(I)I

denotes the relative standard deviation of a unit current source. N isthe resolution of the DAC, inv−norm is the inverse cumulative normal distribution


and yield is the relative number of DACs with an INL < 0.5 LSB. Therefore, therelative standard deviation of the unit cell for a 9-bit DAC is ≤ 0.74 %. To obtaininsight into the SFDR (which is important for high-speed DACs) and the SNDRagainst the relative current source mismatch, the average SNDR and SFDR of 100MATLAB simulations against the relative mismatch are drawn. As can be seenin Figs. 3.14 and 3.15, the SNDR and SFDR have almost the ideal values for 9-bitDAC as long as the relative mismatch is below the 0.74 %.

10-4

10-3

10-2

10-1

100

38

40

42

44

46

48

50

52

54

56

58

Relative Mismatch Error Standard Deviation

SN

DR

[d

B]

MATLAB Model

SN

DR

~5

5.5

dB

Figure 3.14: SNDR versus relative mismatch standard deviation of a 9-bit MAT-LAB model DAC.

10-4

10-3

10-2

10-1

100

45

50

55

60

65

70

75

80

Relative Mismatch Error Standard Deviation

SF

DR

[d

Bc]

SF

DR

~7

2 d

Bc

MATLAB Model

Figure 3.15: SFDR versus relative mismatch standard deviation of a 9-bit MAT-LAB model DAC.


Iunit Runit

Rload+Rpar,u

Vdd

Iload

Vcm

(a)

Iout(X) Rout(X)

Rload+Rpar(X)

Vdd

Iload(X)

Vcm

(b)

Figure 3.16: Parasitic and output resistance models for (a) the unit cell and (b) theDAC.

Unit Cell Output Resistance

The output impedance and the parasitic impedance of interconnections and switchesin the converter will strongly determine the performance [45]. Every currentsource has a finite output resistance and can be modeled as in Fig. 3.16. As theoutput resistance of the current cell is finite, the total output resistance of theDAC in Fig. 3.16b is dependent on the number of current cells connected to theoutput. Therefore, it is dependent on the input code (X). The code-dependentoutput current of the DAC (Iout(X)) is hence converted to a voltage over the par-allel combination of the linear load resistor and the code-dependent DAC outputresistance (Rout(X)), resulting in distortion. The influence of cell impedance onthe INL of the converter can be described using the following relation [59], [61]:

INL ∝ (No. of DAC unit cells)2

Rratio

. (3.8)

Where the ratio of the Runit to the linear resistance Rload is defined as Rratio. Rpar,u

and Rpar(X) represent the parasitic resistance of the switch transistor of the unitcell and the DAC, respectively. Rload is the impedance of node X and Y in Fig. 3.2.This parasitic resistance is added to the load resistance and hence degrades theRratio. In Fig. 3.17 the INL versus Rratio is simulated for different common-modevoltages of the current source output of the DAC cell in Fig. 3.11. The simulationdemonstrates that for a common-mode voltage range from 500 to 700 mV, the Rratio

must be higher than about 158 K in order to keep the INL smaller than 0.5 LSB.The effect of the finite resistance of the unit current cell on the SNDR and SFDRis shown in Figs. 3.18 and 3.19. The SNDR and SFDR are close to the ideal valuesfor 9-bit DAC as long as the Rratio is above the 158 K.


105

106

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Unit Cell/ Load Resistance Ratio

INL

[L

SB

]

Vcm=500mV

Vcm=600mV

Vcm=700mV

Rratio= 158 K

Figure 3.17: INL versus resistance ratio for different common-mode voltages of a9-bit DAC model in Fig. 3.16b.

100

101

102

103

104

105

106

0

10

20

30

40

50

60


SN

DR

[d

B]

MATLAB Model

SN

DR

=5

5.3

dB

Figure 3.18: SNDR versus resistance ratio of a 9-bit MATLAB model DAC.


100

101

102

103

104

105

106

0

10

20

30

40

50

60

70

80


SF

DR

[d

Bc]

MATLAB Model

SF

DR

=7

3.5

dB

Figure 3.19: SFDR versus resistance ratio of a 9-bit MATLAB model DAC.

Design for Matching

Using the calculated relative standard deviation of the unit cell for a 9-bit DAC(equation 3.7), the area of the matched transistors can, to the first order, be de-scribed using the Pelgrom model [62]

(WL)min =1

(σ(I)I

)2(A2

β +4A2

VT

(VGS − Vth)2). (3.9)

In (3.9) AVT and Aβ are technology dependent matching constants. WL representsthe area of the matched transistors, and VGS − Vth is their gate overdrive voltage.The transistor area is chosen to satisfy the requirement on the relative standarddeviation for the maximum available overdrive voltage. The maximum overdrivevoltage is necessary to lower the thermal noise contributed from the current sourcetransistor as described in the next section. Therefore, with the predefined DAC-reference current of section 3.1, the current source overdrive voltage for the unitcell in Fig. 3.11 is set to 360 mV using a transistor length of 7µm and an absolutearea of 30µm2 as shown in Fig. 3.20.

Obviously the current source transistor in Fig. 3.11 occupies a large area due tothe limited headroom voltage when using a 1.2 V supply. On the other hand,by using the resistively degenerated PMOS current source technique as shownin Fig. 3.21a, better matching and lower noise than a MOS only current sourcecan be achieved [63]. By using a higher supply voltage of 1.8 V for the DAC, thedegeneration resistance RCS can be made large to significantly reduce the noisecontribution of the unit current source. Moreover, since the voltage drop on RCS


250 300 350 400 450

0.6

0.65

0.7

0.75

0.8

Current Source Overdrive Voltage (mV)

Mis

ma

tch

Err

or

Sta

nd

ard

De

via

tio

n (

%)

Std. Dev. Limit

WL = 30µm2

Vod=360mV

0.6

8

0.85

Figure 3.20: Mismatch error relative standard deviation versus current sourceoverdrive voltage for the unit cell in Fig. 3.11.

Mcasp

Mcsp

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iom Iop

Ms

Idump

N-Well

1.2V

Vdd 1.2V

IunitRCS=210KΩ

(a)

Mcasp

Mcsp

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iom Iop

Ms

Idump

N-Well

1.8V

N-Well

1.2VVdd 1.2V

I/O transistor

(b)

Figure 3.21: The unit current cell with (a) resistively degenerated current sourcetransistor and (b) with I/O current source transistor using 1.8 V supply.


400 450 500 550 600 650 700

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8


Mis

ma

tch

Err

or

Sta

nd

ard

De

via

tio

n (

%)

Std. Dev. LimitWL = 2 µm

2

Vod=500mV

0.6

3

Figure 3.22: Mismatch error relative standard deviation versus current sourceoverdrive voltage for the unit cell in Fig. 3.21b.

is about 650 mV, MCSP can still be implemented using thin-oxide transistors. Thedrawback of this method is that a large RCS of about 210 K Ω should be usedfor the predetermined unit current of about 3.2µA. This large resistor will stilloccupy larger area compared to the current source transistor in Fig. 3.11. Due tothis reason, this solution will not be considered in the further design. However, analternative solution to increase the transistor overdrive voltage and hence decreasethe transistor current source area can be achieved by using a thick oxide I/Ocurrent source transistor. This also requires a higher supply voltage of 1.8 V asshown in Fig. 3.21b. In this case, the current source overdrive voltage is set to500 mV while a transistor length of 1.8µm and an absolute area of 2µm2 are usedas shown in Fig. 3.22.

Noise Performance

Based on the current source matching requirements, the chosen transistor sizetogether with the DAC-reference current determine the transconductance of thecurrent source (gmCS). The current noise power is directly proportional to gmCS,since the noise power is thermal noise limited. Choosing the RMS value of the noisecurrent of the 511 unit current sources less than or equal to the quantization noisecurrent results in an SNR which is within 3 dB of the ideal SQNR, i.e. a resolutionloss due to thermal noise less than 0.5-bit. Fig. 3.23a shows the RMS DAC noiseas a function of overdrive voltage of the core current source transistor, the redline indicates the quantization noise current. The RMS value of the DAC currentnoise at 360 mV overdrive voltage is almost 15 % lower than the quantization noisecurrent which corresponds to a 2.4 dB loss compared to the ideal SQNR. On the


250 300 350 400 450

700

750

800

850

900

950

1000


RM

S N

ois

e C

urr

en

t (n

A)

Quantization Noise Current

DAC RMS Noise Current

SNR=SQNR - 2.4dB

(a) Core transistor current source in Fig. 3.11.

400 450 500 550 600 650 700

500

600

700

800

900

1000


RM

S N

ois

e C

urr

en

t (n

A)

Quantization Noise Current

DAC RMS Noise Current

SNR = SQNR – 1.9 dB

(b) I/O transistor current source in Fig. 3.21b.

Figure 3.23: RMS DAC noise current versus current source overdrive voltage.


other hand, Fig. 3.23b shows the RMS DAC noise as a function of the overdrivevoltage of the I/O current source transistor of Fig. 3.21b. The RMS value of theDAC current noise at 500 mV overdrive voltage is almost 26.5 % lower than thequantization noise current which corresponds to a 1.9 dB loss compared to theideal SQNR. As can be seen from the figure, the noise performance of the seconddesign overpass the first one by 11.5 % due to the increased overdrive voltage ofthe current source transistor.

3.3.2 Dynamic Properties

Settling Performance

Typically, dynamic non-idealities become dominant for high-speed CM-DACs, be-cause the transient output current is directly seen in the analog output. Thus,any dynamic error directly results in an output error. In this work, where theCM-DAC is adopted in the current-based SAR ADC, dynamic errors are not seenat the output because the care is only about the settled accuracy before the de-cision process by the latch. As described in section 3.2.1 and shown in Fig. 3.24,for this system, a decision time of 250 ps is assumed. The decision time is themaximum available time for the settling of the largest current step of the DACbefore the decision process. The largest current transition, which in this systemoccurs when switching the MSB, suffers the largest error ∆I. This error, similarly,can be expressed as in equation 3.3.

In this case and similar to the Gm stage current in section 3.2.1, the MSB currentmust settle to a 10-bit accuracy within time T. This requires a time constantof about 35 ps. With a load of 50 Ω and assuming the output resistance of theDAC (Rout(X)) in Fig. 3.25 is very large, the maximum acceptable output andparasitic capacitances (Cout(X) + Cpar(X)) in Fig. 3.25 at the TIA input node is0.7 pF. In order to minimize the value of the capacitance at this node, the switchand cascode transistor lengths are set to the minimum length provided by theselected technology. The MSB settling error versus Rratio for different common-mode voltages is simulated in Fig. 3.26. The simulation shows that the Rratio

should be higher than about 123 K to keep the INL below the 0.5 LSB, a lessstringent requirement compared to the INL requirement in section 3.3.1.

ΔI

IMSB_ideal=256*Iunit

500 psec

Decision

iload(t)

T=250 psec

Iload(k)

Iload(k-1)

Figure 3.24: Settling of MSB DAC current at the proposed decision time.


iload(t,X)

Rload+Rpar(X)Cout(X)+Cpar(X)

Iout(X) Rout(X)

Vdd

Vcm

Figure 3.25: DAC output resistance and capacitance model.

105

106

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8


|MS

B S

ettlin

g E

rro

r| [L

SB

]

Vcm=500mV

Vcm=600mV

Vcm=700mV

Rratio=123 K

Figure 3.26: MSB settling error versus resistance ratio of a 9-bit DAC model inFig. 3.25.


Effect of Transistor Non-idealities on the DAC Accuracy

The effect of the transistor non-idealities on the DAC accuracy and current sourcematching is investigated for the two designs in Figs. 3.11 and 3.21b. In the firstdesign of Fig. 3.11 with the MSB cell in Fig. 3.27a, the voltage at node Vcm isswept from 550 mV to 700 mV. The results of these simulations for the MSB set-tling error are shown in Fig. 3.27b. The simulation shows that the allowable range,for which |∆I| is less than 0.5 LSB, is about 100 mV for the cascoded current cellswhile it decreases to 30 mV in case of non-cascoded current cells. Assuming a 50 ΩTIA input resistance and a maximum single-ended current change of ±0.8 mA, theresulting voltage swing is below 100 mV and the cascoded current cell solution sat-isfies the settling requirements for a 10-bit ADC. The effect of this voltage changeon the current source matching is also simulated and shown in Fig. 3.28. Here, a200 mV voltage variation of node Vcm causes only a change of 0.2 % in the stand-ard deviation of the relative mismatch error. Indicating that the effect of finiteoutput swing on the current source matching can practically be ignored.

An alternative method to the simulation in Fig. 3.27b for the effect of transistornon-idealities on the DAC accuracy is done by sweeping the Vid for ± 200 mVrange. The results of these simulations for the MSB settling error for differentvalues of Rload are shown in Fig. 3.29b. The simulations show that the load resist-ance, for which |∆I| is less than 0.5 LSB, must be less than 50 Ω for Vcm=600 mV.For the second design with I/O transistor current source in Fig. 3.21b and thecorresponding MSB cell in Fig. 3.30a, the effect of transistor non-idealities on theDAC accuracy is investigated similar to the method in Fig. 3.29b. The results ofthese simulations for the MSB settling error for different values of Rload are shownin Figs. 3.30b and 3.31b. The simulations show that the load resistance, for which|∆I| is less than 0.5 LSB, must be less than 200 Ω and 100 Ω for Vcm=600 mV andVcm=700 mV, respectively. Obviously, the second design can tolerate much largerload resistance values than the first one due to the increased headroom voltage forthe unit cells which increases the unit cell resistance as described in section 3.3.1.

M2M2

M1M1

MsMs MsMs

V ddVdd

VcaspVcasp

VcspVcsp

I opIop I omIom

MsMs

I dumpIdump

M2

M1

Ms Ms

Vdd

Vcasp

Vcsp

Iop Iom

Ms

Idump

M2

M1

Ms Ms

Vdd

Vcasp

Vcsp

Iop Iom

Mcasp

Mcsp

Vdd

Vcasp

Vcsp

iload(t,X)


Vcm

256 cells

500 psec

Qb

Msw Msw

Iop Iom

Msw

Idump

Vdd

Q

500 psecIdump

Vdd

Vdd

Vdd

N-Well

1.2V

N-Well

1.2V

(a)

580 600 620 640 660 680 7000

0.1

0.2

0.3

0.4

0.5

Voltage of Node Vcm (mV)

|MS

B S

ettlin

g E

rro

r| (

LS

B)

Cascoded Unit Cell

Non-Cascoded Unit Cell30 mV

108 mV

(b)

Figure 3.27: (a) The MSB cell with core transistor current sources from Fig. 3.11.(b) MSB settling error versus the change of node Vcm at 50 Ω load for a 9-bit DAC.


Gm

DAC

Iref

Idac,p

rin,TIA~ 50Ω

TIA+

Q

ΔV

ΔVds

Vcm Vcm

Igm,p

ITIA,p

(a)

500 520 540 560 580 600 620 640 660 680 700

0.677

0.6775

0.678

0.6785

0.679

Current Source ΔVds (mV)

Mis

ma

tch

Err

or

Sta

nd

ard

De

via

tio

n (

%)

0.2%

(b)

Figure 3.28: (a) The effect of Vcm variation on the current source mismatch stand-ard deviation. (b) Mismatch error relative standard deviation versus the currentsource VDS change at 50 Ω load.

M2M2

M1M1

MsMs MsMs

V ddVdd

VcaspVcasp

VcspVcsp

I opIop I omIom

MsMs

I dumpIdump

M2

M1

Ms Ms

Vdd

Vcasp

Vcsp

Iop Iom

Ms

Idump

M2

M1

Ms Ms

Vdd

Vcasp

Vcsp

Iop Iom

Mcasp

Mcsp

Vdd

Vcasp

Vcsp

iload(t,X)


Vcm

256 cells

500 psec

Qb

Msw Msw

Iop Iom

Msw

Idump

Vdd

Q

500 psecIdump

Vdd

Vdd

Vdd

N-Well

1.2V

N-Well

1.2V

(a)

Vid (mV)-200 -150 -100 -50 0 50 100 150 200

|MS

B S

ettli

ng E

rror

(LS

B)|

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9 RL=25 OhmRL=50 OhmRL=60 OhmRL=75 OhmRL=100 Ohm

Vcm= 600mV

(b)

Figure 3.29: (a) The MSB cell with core transistor current sources from Fig. 3.11.(b) MSB settling error versus the change of Vid at Vcm=600 mV for different loadresistance values for a 9-bit DAC.


M2M2

M1M1

MsMs MsMs

V dd 1.8VVdd 1.8V

VcaspVcasp

VcspVcsp

I opIop I omIom

MsMs

I dumpIdump

iload(t,X)

RloadCout(X)

Vcm

256 cells

500 psec

Qb

Q

500 psec

M2

M1

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iop Iom Idump

Mcasp

Mcsp

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iom Iop

Ms

Idump

N-Well

1.8V

N-Well

1.2VVdd 1.2V

Mcasp

Mcsp

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iom Iop

Ms

Idump

N-Well

1.8V

N-Well

1.2VVdd 1.2V

N-Well

1.8V

-Well

1.2VN-Well

1.2V

-Well

1.8V

(a)

-200 -150 -100 -50 0 50 100 150 200

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Vid (mV)

|MS

B S

ettlin

g E

rro

r| (

LS

B)

RL=50 Ohm

RL=100 Ohm

RL=150 Ohm

RL=200 Ohm

RL=225 Ohm

Vcm= 600mV

(b)

Figure 3.30: (a) The MSB cell with I/O transistor current sources from Fig. 3.21b.(b) MSB settling error versus the change of Vid at Vcm=600 mV for different loadresistance values for a 9-bit DAC.

M2M2

M1M1

MsMs MsMs

V dd 1.8VVdd 1.8V

VcaspVcasp

VcspVcsp

I opIop I omIom

MsMs

I dumpIdump

iload(t,X)

RloadCout(X)

Vcm

256 cells

500 psec

Qb

Q

500 psec

M2

M1

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iop Iom Idump

Mcasp

Mcsp

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iom Iop

Ms

Idump

N-Well

1.8V

N-Well

1.2VVdd 1.2V

Mcasp

Mcsp

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iom Iop

Ms

Idump

N-Well

1.8V

N-Well

1.2VVdd 1.2V

N-Well

1.8V

-Well

1.2VN-Well

1.2V

-Well

1.8V

(a)

-200 -150 -100 -50 0 50 100 150 200

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Vid (mV)

|MS

B S

ettlin

g E

rro

r| (

LS

B)

RL=50 Ohm

RL=75 Ohm

RL=100 Ohm

RL=125 Ohm

Vcm= 700mV

(b)

Figure 3.31: (a) The MSB cell with I/O transistor current sources from Fig. 3.21b.(b) MSB settling error versus the change of Vid at Vcm=700 mV for different loadresistance values for a 9-bit DAC.


Mcasp

Mcsp

Ms Ms

Vdd 1.8V

Vcasp

Vcsp

Iom Iop

N-Well

1.8V

N-Well

1.2VVdd 1.2V

I/O transistor

Q

Qb

Figure 3.32: The modified unit current cell for the final DAC implementation.

3.3.3 Unit Current Cell Final Design

For the previous unit current cell designs, the DAC current is dumped during theDAC reset phase. This complicates the design of the proceeding blocks, i.e. thecurrent comparator as a comparator with wide input common-mode range will berequired because the common-mode level changes for every bit cycle. Therefore,the unit cell in Fig. 3.21b is modified in the final design as shown in Fig. 3.32by dumping the current of the unit cells to the Gm stage, instead of a commonnode, during the reset phase. This dumped current is used as a bias current forthe Gm stage and hence decreases the biasing current provided by the TIA andavoiding the need for wide input common-mode range comparator. Moreover, thebodies of the switch transistors are connected to their sources in order to lower thethreshold voltage of the switch transistors and decrease their ON-resistances forhigh-speed operation. Even though the sensitivity to the substrate noise causedby the source-bulk connection of the switch transistors is increased, this can bealleviated by adding guard rings around the switch transistors to isolate themfrom the noisy substrate.

3.3.4 Effect of the Statistical Variations on the CM-DAC

Histograms of the maximum DNL and INL for a 20 Monte Carlo runs includingprocess variations and device mismatches for the CM-DAC based on the unitcell in Fig. 3.32 are shown in Fig. 3.33. The mean value of the maximum DNL is0.152 LSB and the three sigma variation is below 0.18 LSB, indicating that missingcodes do not occur. The three sigma variation of the maximum INL is below0.105 LSB. In this simulation, a digital ramp input is inserted to the DAC and the


DNLmax

(LSB)0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26N

o. o

f Mon

te C

arlo

Run

s

0

1

2

3

4Mean=0.152 LSB , Sigma=0.059 LSB , No. of runs=20.0

INLmax

(LSB)0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28N

o. o

f Mon

te C

arlo

Run

s

0

1

2

3

4Mean=0.216 LSB , Sigma=0.035 LSB , No. of runs=20.0

Figure 3.33: Histogram of max. DNL and INL for 20 Monte Carlo runs using adigital ramp input signal.

output current is summed up over a 50 Ω load resistance, then the DNL and INLare calculated according to the definition in equations 2.3 and 2.5, respectively.The DNL and INL curves for selected runs are shown in 3.34 and 3.35. Obviouslythe maximum DNL occurs at the MSB code transition. The worst case DNLassociated with switching the MSB current cell, is simulated with one thousandMonte Carlo runs for both schematic and RC extracted views after layout. Inthis case, a DC simulation is performed where the DAC is also loaded with a 50 Ωresistance. The results and histogram are shown in Figs. 3.36 and 3.37. As canbe seen from both figures, the three sigma variations of the schematic and RCextracted views are below 0.6 LSB and 0.4 LSB, respectively. The results verifythat for the three sigma design, missing codes do not exist.


Code0 100 200 300 400 500 600

DN

L(LS

B)

-0.1

0

0.1

0.2

0.3

Code0 100 200 300 400 500 600

INL(

LSB

)

-0.3

-0.2

-0.1

0

0.1

Figure 3.34: DNL and INL of the first Monte Carlo run.

Code0 100 200 300 400 500 600

DN

L(LS

B)

-0.3

-0.2

-0.1

0

0.1

Code0 100 200 300 400 500 600

INL(

LSB

)

-0.3

-0.2

-0.1

0

0.1

Figure 3.35: DNL and INL of the second Monte Carlo run.


Monte Carlo Runs0 100 200 300 400 500 600 700 800 900 1000

Wor

st C

ase

DN

L (L

SB

)

-1

-0.5

0

0.5

1

[-0.62/0.76] LSB

Worst Case DNL (LSB)-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

No.

of S

ampl

es

0

20

40

60

80

Mean= 0.01 Sigma= 0.19 N= 1000

Figure 3.36: Worst Case DNL for a 1000 Monte Carlo runs for the CM-DAC basedon the unit cell in Fig. 3.32.

Monte Carlo Runs0 100 200 300 400 500 600 700 800 900 1000

Wor

st C

ase

DN

L (L

SB

)

-0.4

-0.2

0

0.2

0.4

0.6

[-0.28/0.5] LSB

Worst Case DNL (LSB)-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6

No.

of S

ampl

es

0

20

40

60

80

Mean= 0.01 Sigma= 0.12 N= 1000

Figure 3.37: Worst Case DNL for 1000 Monte Carlo runs for the RC extractedview.


3.4 High-Resolution Current Comparator

The main goal of this section is to design a high resolution current comparatorincluding a low-noise transimpedance amplifier (TIA) as the first stage in thecomparator. The DAC precision is also determined by the input impedance ofthe TIA. For high-speed operation, trade-offs between input resistance, noise andvoltage headroom pose challenges in the design of the high-speed TIAs. Twocircuit implementations are addressed in this section.

3.4.1 High-Resolution TIA

A variety of different topologies exists for the realization of a TIA, including feed-forward (FF) common-gate (CG) and regulated cascode common-gate (RGC) in-put configurations as well as voltage/current mode feedback (FB) topologies [64] -[67]. Figs. 3.38 and 3.39 give a comparison between the different FF and FBconfigurations. As shown in Fig. 3.38, the FF-RGC configuration has smaller in-put resistance and therefore larger bandwidth than the FF-CG. This advantage ofthe FF-RGC configuration comes at the expense of increased input referred noiseof the TIA due to the added auxiliary amplifier if the same biasing constraints,i.e. same Ibias and RL, have to be maintained [65].

The resistive-type FB configuration shown in Fig. 3.39 is built by taking a samplevoltage from the output node, i.e. shunt sampling, and then feeding back a currentto the input node, i.e. shunt mixing. Hence, the name is shunt-shunt FB-TIA. Asshown in Fig. 3.39, the input node of the amplifier in the FB voltage-mode TIA isa high-impedance node, i.e. no current is flowing into the amplifier. On the otherhand, for the FB current-mode TIA configuration, the input node of the amplifieris a low-impedance node. The advantages of both configurations can be seen inthe figure, where the input resistance is decreased approximately by the amplifiergain (A) and the bandwidth is increased by the same value. However, the noiseof both FB topologies are comparable depending on the design constraints but inboth cases the noise is degraded by the added FB resistor.

In this design, the main concern is to design a high-speed 10-bit TIA, i.e. theinput referred noise of the TIA should be decreased in order to be able to resolvethe LSB of a 10-bit accuracy at the required speed. Therefore, when comparingthe FF and FB topologies, the FF-CG input configuration allows for a largerbandwidth than the conventional voltage-mode feedback TIAs [68].

3.4. High-Resolution Current Comparator 53

Architecture FF-CG Input Stage

Circuit

ZT(0)

BW

Rin

+

IbiasMTIA

Vb

ias

RL

Icomp,p Vout,p

Ibias

MTIA

RLIcomp,m Vout,m+

I/P Ref. Noise

(a)

Architecture FF-RGC Input Stage

Circuit

ZT(0)

BW

I/P Ref. Noise

Rin

+

IbiasMTIA

Vcm

RL

Icomp,p Vout,p

Vcm

Ibias

MTIA

RLIcomp,m Vout,m

Vcm

+

- +

- +

(b)

Figure 3.38: Comparison between the FF CG/RGC TIAs.(a) The FF-CG TIA.(b) The FF-RGC TIA.


Architecture FB Voltage Mode TIA FB Current Mode TIA

Circuit

ZT(0)

BW

I/P Ref.

Noise

Rin, FB

-Av

IinVout

RFB

Rin,FB

CT

Av

++

Icomp,p

Vout,p

RFB

Vout,m

RFB

Rin,FB

CT Rin

Where

Figure 3.39: Comparison between the FB voltage/current mode TIAs.

For the FF-CG TIA shown in Fig. 3.40, at low frequencies, the input resistance,transimpedance gain (ZT) and input-referred current noise power (I2

n,in) are givenby

Rin ≈1

gm1

if RL1 << rds1 (3.10)

ZT = RL1 (3.11)

I2n,in =

4kT

RL1

+ I2n,IB (3.12)

where I2n,IB denotes the noise from the tail current source (IB) and gm1, rds1 are the

transconductance and drain-source resistance of the transistor M1, respectively. Inthe first considered design, a total DC current of about 5 mA was required fromthe TIA to bias the preceding Gm stage. This bias current constraint degradedthe input referred noise current, since the noise current produced by IB is directlyseen at the input of the TIA.

Applying a feedback resistor between the TIA output and the source of M1 wouldprovide a lower input resistance and thereby improve the DAC and Gm stage pre-cision, but the added component would degrade the input-referred noise currentsince the core design cannot be changed. Similarly, the RGC input configura-tion greatly decreases the input resistance at the expense of increasing the input-referred noise current due to the noise of the auxiliary amplifier which is also seenat the TIA’s input. Moreover, to benefit from the advantages of feedback, the loop


IB = 2.5 mA

M1

Vb

2

Icomp,p Vout,p

M1

RL1Icomp,m Vout,mIB

Vb1

RS

Vdd=1.8VRL1

MCS

Y

X

Figure 3.40: Resistively degenerated current source FF-CG TIA presented in [20].

gain must be maintained up to high frequencies [65]. Therefore, in this design, theuse of a feedback resistor and an RGC input configuration are avoided in order tokeep the TIA’s input-refereed noise current small.

In the presented design which is reported in [20], a FF-CG TIA with resistivelydegenerated PMOS current source according to Fig. 3.40 is used, which mitigatesthe noise problem associated with the large bias current to some extent. In usingthe resistively degenerated PMOS current source technique, better matching andlower noise than a MOS only current source can be achieved [63]. By using ahigher supply voltage of 1.8 V for the TIA, the degeneration resistance RS can bemade relatively large to significantly reduce the noise contribution of IB. Moreover,since the voltage drop on RS is about 700 mV, MCS can still be implemented usingthin-oxide transistors. However, by controlling the power-up sequence of the 1.2and 1.8 V supply, the over voltage on transistor MCS which can happen during thestart-up operation is alleviated.


Noise Analysis

The TIA of Fig. 3.40 is implemented in a 1.2/1.8 V 90 nm CMOS technology. The3-dB bandwidth which is required for sufficiently fast settling for the Gm stage andDAC [7] together with the TIA’s bias current and load resistance value determinethe TIA’s RMS noise current. Choosing the RMS value of the TIA input-referrednoise current equal to the quantization noise current results in a 3 dB or 0.5-bitperformance drop compared to the ideal SQNR. These noise requirements lead toa design with RL1=500 Ω which in turn gives a low-frequency transimpedance gainof 54 dBΩ. The value of RS is 250 Ω which for the given single-ended common-mode current of 2.5 mA results in a voltage drop of about 700 mV. Fig. 3.41 showsthe TIA input-referred RMS noise current versus frequency, where the red lineindicates the quantization noise current limit. The figure illustrates that the fre-quency, where the RMS value of the TIA input-referred noise current is equalto the quantization noise current, is designed to be around 4.6 GHz, which is inaccordance to the required settling speed derived in section 3.2.1.

TIA Input Impedance and Input Voltage Swing

The chosen input-referred RMS noise current leads to a TIA input resistance of lessthan 170 Ω which in turn results in an input voltage swing of about 400 mV overall process corners, cf. Figs. 3.42 and 3.43, respectively. The frequency behavior ofthe input impedance is shown in Fig. 3.44, where the input impedance is constantup to around 4.6 GHz. This input impedance value affects the precision of theDAC and Gm stage. To obtain a lower TIA input resistance, and thereby a higherDAC and Gm stage precision, a larger bias current for M1 would be requiredbecause the large required bandwidth imposes a small size for M1. Accordingto equation 3.12, this increase in IB not only raises the input-referred noise fromthe tail current source (IB) in Fig. 3.40 but also results in a small RL1 due to thevoltage headroom limitation, which in turn worsens the overall noise performanceof the TIA’s input stage and the following amplifier stages [65].

Current to Voltage Propagation Delay Time

The propagation delay time of a converted voltage signal is found to be less than25 ps for the entire input current range, indicating that the current to voltageconversion process is sufficiently fast to leave sufficient time for the settling of theDAC and Gm stage currents in the overall SAR operation.


10−1 100 1010

0.5

1

1.5

2

2.5

4.6 GHz

Frequency (GHz)

RM

SN

oise

Cu

rren

t(µ

A)

TIA Input-Referred Noise Current

Quantization Noise Current Limit

Figure 3.41: Input-referred RMS noise current of the TIA versus frequency.

−200 −150 −100 −50 0 50 100 150 20040

60

80

100

120

140

160

180

200

Vid (mV)

Rin

-TIA

(Ω)

TT Corner

Fast Best Corner

Slow Worst Corner

Figure 3.42: TIA input resistance over the differential input voltage range.


−200 −150 −100 −50 0 50 100 150 200500

600

700

800

900

1,000

Vid (mV)

VX

(mV

)

TT Corner

Fast Best Corner

Slow Worst Corner

Figure 3.43: Voltage change of node (X) in Fig. 3.40 over the differential inputvoltage range.

106 107 108 109 10100

50

100

150

200

4.6 GHz

Frequency (Hz)

Zin

-TIA

(Ω)

TT Corner

Fast Best Corner

Slow Worst Corner

Figure 3.44: TIA input impedance versus frequency.


IB = 1.25 mA

M1

Vb

2

Icomp,p Vout,p

M1

RL1Icomp,m Vout,mIB

Vb1

Vdd

RL1

MCS

X

Y

Figure 3.45: The modified FF-CG TIA presented in [9].

3.4.2 Modified TIA Design

The design of the TIA, which is presented in section 3.4.1 and in [20], is modifiedthereafter by replacing the resistively degenerated current source by a simple cur-rent source avoiding the use of the 1.8 V supply in the TIA and decreasing the biascurrent of the Gm stage provided by the TIA, since the dump current of the DACin the reset phase is used as a part of the Gm stage bias current as discussed insection 3.3.3. In the modified design, a single-ended DC current of about 1.25 mAis only required from the TIA to bias the preceding Gm stage. The modified TIAis shown in Fig. 3.45 and is implemented in a 1.2 V 90 nm CMOS technology.

Comparison to the Old Design

The comparison between the resistively degenerated current source TIA [20] andthe modified FF-CG TIA [9] is shown in Fig. 3.46. The current noise power isinversely proportional to resistance RS of the resistively degenerated current source(Fig. 3.46a) and is directly proportional to the gmCS of a simple current source(Fig. 3.46b). Since the current and the transistor overdrive voltage in Fig. 3.46bare approximately halved compared to the TIA in Fig. 3.46a, the gmCS and theequivalent transconductance of the resistively degenerated current source, i.e. ( 1

RS),

are almost equal for both circuits. As a result, the input-referred noise currentsof both TIAs are equal. However, the input resistance of the TIA in Fig. 3.46b,which is shown in Fig. 3.47, is approximately 41 % smaller than its counterpartof the TIA in Fig. 3.46a for the typical corner and shows worse characteristics forthe slow worst corner. The input voltage swing of the TIA in Fig. 3.46b is about350 mV over all process corners.


Icomp,m IB

Vb1

RS

Vdd=1.8V

MCS

XITIA,p

IB

Vb1MCS

Icomp,m

XITIA,p

Vdd=1.2V

Vb2M1

RL1

Vcomp,m

Vb2M1

RL1

Vcomp,m

IB=2.5mA

RL1=500Ω

RS=250Ω

VX≈700mV

IB=1.25mA

RL1=500Ω

VX≈700mV

Rin Rin

(a) (b)

Figure 3.46: Comparison between the resistively degenerated current source TIA[20] and the modified FF-CG TIA [9].

−200 −100 0 100 200

50

100

150

200

250

300

Vid (mV)

Rin

-TIA

(Ω)

TT Corner

Fast Best Corner

Slow Worst Corner

−200 −100 0 100 200

500

600

700

800

900

1,000

Vid (mV)

VX

(mV

)

TT Corner

Fast Best Corner

Slow Worst Corner

Figure 3.47: (a) TIA input resistance over the Vid range. and (b) Voltage changeof node (X) in Fig. 3.45 over the Vid range.


3.4.3 Voltage Preamplifier and Core Latch

For the required 10-bit current comparator accuracy, the transimpedance gainas well as the relatively low output common-mode voltage provided by the TIAare not suitable for directly driving the subsequent latch. Therefore, a voltagepreamplifier stage is added to adjust the common-mode levels and to amplify thevoltage signal to allow for a correct quantization by the latch and reduce thekickback noise. Fig. 3.48 shows a schematic of the preamplifier and the core. Forthe preamplifier operating with an input common-mode voltage around 250 mV,the comparator uses a p-type input pair. The comparator core is based on adynamic latch. When CLK is low, the comparator outputs are reset to high. WhenCLK goes high, the differential pair and the cross-coupled inverters compare thetwo input voltages. Then, the latch regeneration forces one output to high andthe other to low according to the comparison result. Typical regenerative latchcomparison time is given by [69],

Tcomp = τ ∗ ln(VFS

Av ∗∆Vin

) =CL

gm

∗ ln(VFS

Av ∗∆Vin

) (3.13)

where CL is the total output load, gm is the latching stage transconductance, Av

is the inter-stage gain, VFS is the desired output level and ∆Vin is the input differ-ence. Obviously, a trade-off between the comparison time and the input difference∆Vin is seen. The comparison time (Tcomp) vs the differential overdrive inputvoltage is simulated over corners and the results are shown in Fig. 3.49.

The delays from the two main blocks in the SAR loop, namely the DAC (sec-tion 3.3.2) and the SAR logic as will be discussed in section 3.7, set the maximumallowable latch comparison time to about 170 ps in the typical corner as seen inFig. 3.49. As a result, the system clock frequency is reduced from 2 GHz to about1.65 GHz and the conversion rate of the ADC is finally set to 150 MS/s after con-sidering a dedicated clock cycle for the sampling operation. However, the latchcomparison time will be significantly increased in the slow worst corner, indicatingthat the intended speed will not be achieved in this case. In order to satisfy thetypical corner requirement, the minimum differential overdrive input voltage hasto be around 6 mV. The preamplifier is designed to have a gain of 4 and an outputcommon-mode level of 600 mV. Therefore, the 10-bit differential LSB DAC-currentwhich is designed to be 3.2µA is multiplied by the ZT of the TIA and the voltagepreamplifier gain to achieve the required 6 mV differential input voltage.

During the conversion phase, the outputs of the comparator are captured by theSR data capture cell, which needs to perform the following two tasks: (1) Store thecomparator decision (digital output) until the latch is reset for the next conversioncycle. (2) Feed back the comparator decision as quickly as possible to the CM-DAC. This delay is part of the SAR loop delay and minimizing it is critical toachieve high conversion speed [70]. A NOR-based SR-Latch in Fig. 3.50 is usedto preserve the comparator decision for one complete clock cycle. The solutionwith NOR SR-latch is preferred because it requires less inverters compared to thesolution with the NAND latch. A buffer is used after the SR-Latch to drive thecircuit of the SAR logic.


RL2

IB2

Vb3

Vdd

RL2

MCS

CLK

CLKCLK

Vdd

Vcomp,p

Vcomp,m

Vi,p

Vi,m

Figure 3.48: Voltage preamplifier and core of the current comparator.

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 300

50

100

150

200

250

300

350

170 ps

Differential Overdrive Input Voltage (mV)

Com

para

tor

Com

par

ison

Tim

e(p

s)

TT Corner

Fast Best Corner

Slow Worst Corner

Figure 3.49: Comparator comparison time vs the differential overdrive inputvoltage.

3.5. Reference Current Generator 63

Q

Qb

Vcomp,p

Vcomp,m

Buffer StageSR-Latch

Figure 3.50: SR-Latch with buffer stage.

3.5 Reference Current Generator

The reference current generator given in [25] is shown in Fig. 3.51. The referencecurrent Iref is given by,

Iref =2

R2betaβ1

(1− 1√K

)2 (3.14)

where β1 is equal to µnCoxWL

of transistor M1, Rbeta is the source degenerationresistance connected to transistor M2 and K is the multiplication factor of β1

which is reflected into transistor M2, i.e. β2 = Kβ1. Generally, this is done bysimply using a larger width in M2. The resulting circuit is called a beta-multiplierreference circuit [25]. This circuit, when K=4, is sometimes called a constant-gm

bias circuit because,

gm =1

Rbeta

=√

2β1Iref (3.15)

which indicates that gm is a constant and independent of transistor process vari-ations. The reference current circuit in Fig. 3.51 is basically built from the tran-sistors M1 to M4. A start-up circuit is included for proper operation at the startup condition. Since in any self-biased circuit, there is one possible undesired op-erating point where zero current flows in the circuit. This unwanted state occurswhen the gates of M1/M2 are at ground while the gates of M3/M4 are at VDD.When in this state, the gate of MSU1 is at ground and so it is off. The gate ofMSU2 is somewhere between VDD and (VDD - VTHP). MSU3, which behaves likean NMOS switch, turns on and leaks current into the gates of M1/M2 from thegates of M3/M4. This causes the current to snap to the desired state and MSU3 toturn off. During the normal operation, the start-up circuit should not affect thebeta-multiplier’s operation. The current through MSU3 should be zero (or verysmall) [25].

However, the low output resistance of the short-channel devices causes the draincurrent to change significantly with changes in drain-to-source voltage. In order toreduce the sensitivity, the variations in the drain-to-source voltages of the NMOSdevices with changes in VDD need to be reduced. Therefore, a differential amplifierstage is added to the basic beta-multiplier seen in Fig. 3.51. The idea is to use


the amplifier to compare the drain voltage of M1 (Vbiasn) with the drain voltageof M2 (Vbiasp) and regulate them to be equal. The result is an effective increase inM2’s output resistance [25]. Moreover, in order to make the reference stable, bigcapacitors are added to the output of the circuit. Current copier transistors canbe added at the circuit outputs to distribute reference current signals which areless prone to resistive losses and capacitive coupling as compared to the voltagesignals.

Vdd

RbetaStart-up Circuit

Differential Amp

Iref

Iref

C

C

Vbiasp

Vbiasn

M2M1

M3

M4

MSU2

MSU1

MSU3

Figure 3.51: Reference current generator given in [25].

3.6 CLK Generator and CLK Buffers

The block diagram of the CLK generator given in [71] is shown in Fig. 3.52. Anopen-loop amplifier with resistor load drives a symmetrical output inverter toconvert the input sine wave to a square wave. Two inverters following the CLKgenerator to produce the CLK1 and CLK1 which are used to clock the comparatorand SAR control logic as will be described in the next section.

CLK Generator

Vsin,p

Vsin,m

CLK1CL

K1

Figure 3.52: CLK generator block diagram given in [71].

3.7. SAR Control Logic 65

3.7 SAR Control Logic

The speed of a SAR ADC is limited by the delays through its main blocks(Fig. 3.53): DAC settling (TDAC), comparator decision time (TComp) and SAR logicdelay (TLogic). Maximizing the speed therefore requires a joint minimization of allthree components [70]. The worst case delay is associated with the current switch-ing of the MSB. To illustrate the trade-offs explored in this design, consider thecircuit slice shown in Fig. 3.53, the SAR logic uses multi-stage inverters to drivethe MSB DAC-cell. The sizes of the NMOS and PMOS devices of the multi-stageinverters are defined by the required on-resistance for fast switching. Widening thedevices improves the delay of the DAC-Control signal (TDAC,Control) but increasesthe delay of the Flip-Flop (FF) of the SAR logic (TFF). Consequently, there ex-ists an optimum sizing that minimizes (TFF+TDAC,Control) as shown in Fig. 3.54.The optimum is shallow, but the reward for proper optimization is high, since thetime savings multiply with the number of conversion cycles [70]. The resultingSAR logic delay (TLogic) of the custom FFs and inverters is around 180 ps in thechosen 90 nm technology for the typical corner case, fitting the original designspecifications with conversion rate of 150 MS/s [9].

Output Register

SAR Control

Output [0:9]

9-bit

CMDAC

+

Control_p [0:8]

fclk

Control_m [0:8]

TDAC

fclk

TComp

TLogic

CLK

D Q

Enb Clear

TLogic

CMSB

Vcomp_p

Worst case logic delay path (CL=CMSB)

Custom

Flip-Flops

TFF TDAC,Control

Figure 3.53: Delays in the SAR loop.


1 1.5 2 2.5 3 3.5 4 4.50

50

100

150

200

250

300

350

180 ps

NMOS Transistor Width (µm)

Del

ays

inS

AR

Loop

(ps)

TFF

TDAC,Control

TLogic=(TFF+TDAC,Control)

Figure 3.54: Optimization of logic and DAC-Control delays.

3.7.1 SAR Logic Custom Flip-Flop

The circuit of the custom FF [72] is shown in Fig. 3.55. It basically consists ofa logic for either bypassing the input signal (D) by the enable signal (E) or by-passing the output (Q) of the FF as shown in block (a). The circuit in (b) consistsof two stages implemented by SR NAND latches. The first stage (the two latcheson the left) processes the clock and data signals to ensure correct input signalsfor the second stage (the single latch on the right). If the clock is low, both theoutput signals of the first stage are high regardless of the data input; the secondlatch is unaffected and it stores the previous state. When the clock signal changesfrom low to high, only one of the output voltages of the first stage (depending onthe input signal) goes low and sets/resets the second stage: if D = 0, the loweroutput becomes low; if D = 1, the upper output becomes low. If the clock signalcontinues staying high, the outputs keep their states regardless of the input andforce the second stage to stay in the corresponding state. The second stage roleis to store the data only when the clock is low.

3.7.2 SAR Logic Block Diagram

The SAR control logic is based on a synchronous state machine which uses apositive edge-triggered enable-shift-register as shown in Fig. 3.56. The register isinitialized with 11-bit word ”10000000000”, thereafter the MSB digit is shiftedto the right in each clock cycle, generating the enable signals E (9:0) as shown inthe timing diagram of Fig. 3.56. These enable signals E (9:0) activate the corres-ponding FF in the control and output registers as shown in Figs. 3.57 and 3.58,respectively.


Q

Qb

CLK

Reset

Set

X

X

D

Enb

Q

Clear

(a) (b)

1 2

Figure 3.55: Custom FF consists of (a) Logic for enable and clear signals and (b)Edge-triggered NAND-based FF with asynchronous Set/Reset options.

However, additional D-FF is used to generate the sampling signals (FS and FSb)which are used to drive the S/H bootstrap loop in the S/H circuit of Fig. 3.10.This FF uses the E (0) signal as an input and is clocked by CLK1 to generatethe sampling signals (FS and FSb) as shown in Fig. 3.56. In the control register ofFig. 3.57, the signal E (0) is used to clear all DAC-control lines to zero in the DACreset phase. The signal FSb is also used to clock the output register as seen inFig. 3.58 when the end of conversion (EOC) and the digital output D (9:0) signalsare ready, indicating that the output code word is readable.


DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

Se

t

Re

se

t

DF

F

DQ

E(8

)E

(7)

E(6

)E

(5)

E(4

)E

(3)

E(2

)E

(1)

E(0

)

Fs

Se

t

Re

se

t

Se

t

Re

se

t

Se

t

Re

se

t

Se

t

Re

se

t

Se

t

Re

se

t

Se

t

Re

se

t

Se

t

Re

se

t

Se

t

Re

se

t

DF

F

DQ

DF

F

DQ

CL

K1

Lo

ad

E(9

)

Se

t

Re

se

t

Se

t

Re

se

t

Vd

d

E(0

)

E(0

)

Qb

Fsb

Vd

d

Tclk

Tsa

mp

le

CL

K1

CL

K1

Lo

ad

CL

K1

E(1

0)

E(9

)

E(8

)

E(7

)

E(6

)

E(5

)

E(4

)

E(3

)

E(2

)

E(1

)

E(0

)

Fs

Fsb

E(1

0)

Fig

ure

3.56

:Shif

tre

gist

eran

dex

tra

FF

for

gener

atin

gth

een

able

sign

als

and

the

sam

pling

sign

als

(FS

and

FS

b).


DF

F

DQ

En

bC

lea

r

Vco

mp

_p

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

Vco

mp

_m

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

DF

F

DQ

En

bC

lea

r

CT

Rp

(8)

CT

Rp

(7)

CT

Rp

(6)

CT

Rp

(5)

CT

Rp

(4)

CT

Rp

(3)

CT

Rp

(2)

CT

Rp

(1)

CT

Rm

(8)

CT

Rm

(7)

CT

Rm

(6)

CT

Rm

(5)

CT

Rm

(4)

CT

Rm

(3)

CT

Rm

(2)

CT

Rm

(1)

E(8

)

E(8

)

E(7

)

E(7

)E

(0)

E(6

)

E(6

)

E(5

)

E(5

)

E(4

)

E(4

)

E(3

)

E(3

)

E(2

)

E(2

)

E(1

)

E(1

)

En

ab

le

9

CT

Rp

(9)

CT

Rm

(9)

E(9

)

E(9

)

CL

K1

Fig

ure

3.57

:C

ontr

olre

gist

erfo

rge

ner

atin

gth

eD

AC

-Con

trol

sign

als.


DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

DF

F

DQ

Enb

Cle

ar

Vco

mp_

p

DF

F

DQ

Enb

Cle

ar

DF

F

DQ

Enb

Cle

ar

DF

F

DQ

Enb

Cle

ar

DF

F

DQ

Enb

Cle

ar

DF

F

DQ

Enb

Cle

ar

DF

F

DQ

Enb

Cle

ar

DF

F

DQ

Enb

Cle

ar

DF

F

DQ

Enb

Cle

ar

D(8

)D

(7)

D(6

)D

(5)

D(4

)D

(3)

D(2

)

E(8

)E

(7)

E(6

)E

(5)

E(4

)E

(3)

E(2

)E

(1)

Ena

ble

10

E(9

)

DF

F

DQ

Enb

Cle

ar

D(1

)

E(0

)

Vdd

D(9

)

DF

F

DQ D(0

)

DF

F

DQ Q

b EO

C

T(8

)T

(7)

T(6

)T

(5)

T(4

)T

(3)

T(2

)T

(1)

T(9

)T

(0)

Fsb

CLK

1

Fig

ure

3.58

:O

utp

ut

regi

ster

.

Chapter 4

System Implementation andMeasurement Results

This chapter addresses the system implementation and the simulation and meas-urement results. In the first section, the layout techniques for the Gm stage andthe CS-DAC are discussed. A focus on the current source matching and layoutcomplexity versus the impact on the DAC performance is the main target of thissection. The second section of the chapter describes the top level implementation,the FIB operation and the test measurement setup. In the third and forth sections,simulation results of each individual block in the CM-SAR as well as the top levelsimulation and measurement results are discussed. Finally, power consumption ofthe chip and a comparison to other works are given in the last two sections.

4.1 Layout of the Matching-Sensitive Blocks

4.1.1 Layout of the Gm Stage

The design of the Gm stage, as described in section 3.2.1, requires high devicematching. In order to reduce the effect of transistors mismatch, a common-centroidlayout technique is used. This technique is usually used for the cancellation ofgradient errors of process parameter variations [73].

The differential pair and the adaptive biasing circuit of the Gm stage shown inFig. 3.4 are divided into unit cells and distributed symmetrically around the cen-ter having the same centroid. Dummy structures are surrounding the common-centroid structure as well. The layout of the Gm stage is shown in Fig. 4.1. TheGm stage size is 30µm x 60µm. The total extracted parasitic capacitances at theGm stage input and output are about 44 fF and 13 fF, respectively. The length ofthe source-coupled pair transistors M1 and M2 in Fig. 3.4 is optimized in order tominimize the value of the capacitance at the output node while maintaining therequired matching.

71

72 Chapter 4. System Implementation and Measurement Results

Differential pair and

adaptive bias circuit

30µm6

0µ

m

Tail current source

Figure 4.1: Layout of the Gm stage with the tail current source.

4.1. Layout of the Matching-Sensitive Blocks 73

4.1.2 Layout of the CM-DAC

DAC arrays usually use quadruple technique to layout the array in a common-centroid structure [73]. This technique has been used successfully in [74]- [77]to cancel gradient errors and to reduce quadratic errors. Although, quadruplingsolves the problem of gradient errors, there are disadvantages in using it. Dividinga unit into four smaller subunits and placing them in four distant locations bringsup the problem of routing the interconnection between them. Besides complicat-ing the layout, these routings can degrade the performance of the DAC becausemore wiring capacitances are introduced which lead to slower settling speeds.

Another disadvantage is that even though a unit is subdivided into four separatesubunits, the total area of each subunit is more than 1/4 of the original unit.This is due to the required minimum spacing between subunits dictated by thefabrication technology rules. Furthermore, routing between the subunits shouldnot be run over the active area of the DAC in order to reduce crosstalk [73]. Allthese requirements increase the total active area of the quad DAC array comparedto the original DAC. This increase in total active area results in higher gradienterror and even more quadratic error and is, therefore, not desirable [73].

In this work, and in order to minimize the routing complexity, a “symmetric-pair common-centroid layout” technique is used for cancellation of gradient errorswithout the need for quadrupling [73]. The layout pattern of the current sourcearray is shown in Fig. 4.2. The bias transistor is in the middle of the array and theunit current cells are distributed symmetrically around the center. The layout ofthe CM-DAC is shown in Fig. 4.3. The DAC size is 245µm x 265µm and occupiesabout 17 % of the chip area. The total extracted parasitic capacitance at the DACoutput is about 860 fF in this chosen technology.

Even though the “symmetric-pair common-centroid layout” technique [73] is used,unfortunately, the capacitance at the DAC output is increased by about 23 %above the maximum allowed value determined by the DAC settling requirementsas described in section 3.3.2. To overcome this problem, the load resistance of theDAC (TIA input resistance) has to be decreased by the same amount in orderto achieve the required MSB settling accuracy within the same proposed time asdescribed in section 3.3.2. Since decreasing the TIA input resistance results in anincrease in the TIA input-referred noise (section 3.4.1), the dynamic performanceof the DAC in SAR will significantly drop at high sampling speeds as will bediscussed in section 4.3.2.


DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

DmDm

DmDm

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

DmDm

DmDm

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

DmDm

DmDm

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M7

M8

M8

M8

M8

M8

M8

M8

M8

M0

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M7

M7

M7

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M7

M7

M7

M7

M6

M6

M6

M6

M6

M7

M7

M7

M7

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M5

M5

M5

M5

M5

M5

M5

M5

M5

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M5

M5

M4

M4

M4

M4

M4

M5

M5

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M5

M4

M3

M2

M1

M2

M3

M4

M5

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M5

M4

M3

M3

Mbias

M3

M3

M4

M5

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M5

M4

M3

M2

M1

M2

M3

M4

M5

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M5

M5

M4

M4

M4

M4

M4

M5

M5

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M5

M5

M5

M5

M5

M5

M5

M5

M5

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M6

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M7

M7

M7

M7

M6

M6

M6

M6

M6

M7

M7

M7

M7

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M7

M8

M8

M8

Dm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M7

M7

M7

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M7

M8

M8

M8

M8

M8

M8

M8

M8

DmDm

DmDm

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

DmDm

DmDm

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

DmDm

DmDm

Dm

DmDm

DmDm

DmM8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

M8

DmDm

DmDm

Dm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

DmDm

Dm

Dm ≡

Dum

my

trans

istor

, Mbi

as ≡

Bia

s to

the

curre

nt s

ourc

e ar

ray,

M8

≡ M

SB b

it, M

0 ≡

LSB

bit

Fig

ure

4.2:

Curr

ent

sourc

ear

ray

sym

met

ric-

pai

rla

yout

pat

tern

.

4.1. Layout of the Matching-Sensitive Blocks 75

Current Source Array

Cascode-Switch Cells

245µm

26

5µ

m

Figure 4.3: CM-DAC layout.


4.2 Top Level Implementation

The photo and layout of the chip, fabricated in 90 nm TSMC CMOS process,are shown in Figs. 4.4 and 4.5, respectively. The ADC occupies a total area of500 µm x 800 µm. The custom digital blocks occupy almost 40 % of the ADC area.However, the use of custom digital cells are necessary when using this technologyto achieve the target speed as discussed in section 3.7. Nonetheless, this largeoccupied area by the digital cells could be avoided when using standard cell logicin a smaller CMOS technology node.

500µm

CS-DAC

An

alo

g B

loc

ks

Custom

SAR Logic &

Output Register

80

0µ

m

CLK

Generator

Figure 4.4: Chip photo.

390µm

41

0µ

m

Output Register

Enable Register

Control Register

Figure 4.5: Chip layout.

4.2. Top Level Implementation 77

Virtex-5

FPGA

Test Board

MATLAB for FFT

spectrum

Reset

EOC

Ba

lun

Test

Chip

Do

ut [

0:9

]

1

1

RS232CLK

Vip

Vim

Signal

Gen.2

Signal

Gen.1

Re

f.C

LK

Re

ad

CL

K

NI PXIe-5451

16-Bit, Arbitrary

Waveform Generator

Figure 4.6: Measurement setup model.

4.2.1 Test Measurement Setup

The manufactured chip has been glued into a 64 pin QFN packages (9x9 mm2) andwire bonding is performed. The measurement setup is done as shown in Fig. 4.6,a test PCB shown in Fig. 4.7 has been designed to measure the characteristicsof the CM-SAR ADC. The test board is plugged into the FPGA board whichcommunicates via a serial to USB converter with MATLAB and thus the chipcan be controlled and the output signal can be evaluated with a PC. First, areset signal is sent from MATLAB to initialize the SAR control logic on chip andthen an external low-speed read-CLK from signal generator 1 is used, insteadof using the end of conversion (EOC) signal from the ADC, to read the digitalwords from the ADC at the Nyquist sampling rate and send them to MATLAB.The differential input signals are coming from an arbitrary waveform generatorfrom National Instruments (NI PXIe-5451 16-Bit) which is used to realize a low-distortion highly linear (up to 99 dB SFDR) sinusoidal differential input signal.The high-speed clock (ADC-CLK) as well as the read clock are generated fromROHDE & SCHWARZ SMA 100 A signal generator 1 (Fig. 4.6). By using anexternal read-CLK signal instead of the EOC signal, the phase difference betweenthe read-CLK and the ADC-CLK can be adjusted to ensure the correct readingof the digital output. A reference clock of 10 MHz output is applied from signalgenerator 1 to signal generator 2 for the sake of clock synchronization. On thetest board, a balun is used to convert the single-ended clock signal to a differentialsignal.

4.2.2 Focused Ion Beam Operation

Unfortunately, the digital outputs were not readable from the fabricated chip.Thereafter, the failure case was isolated and it appeared, that the digital I/Ocells are not correctly tied to work as input or output modes. This was partiallyrepaired using a FIB operation (Fig. 4.8). First, a cut of the desired wire (resetline) is done very close to the non-working digital I/O cell in order to isolate it(Fig. 4.8b). Second, the oxide and the metal fillers above the desired wire in aproper place are removed and a platinum connection between the digital supplyline and the reset line is deposited as shown in Fig. 4.8d. A packaging of anotherthree sample chips was thereafter done.


US

B t

o

MA

TL

AB

Signal

Generator

(2)

Signal

Generator

(1)

FPGA

Core

Test Board

Fro

m S

ig.

Ge

n. (1

)

Figure 4.7: Designed PCB to measure the CM-SAR ADC.

(a) (b)

(c) (d)

Figure 4.8: (a) The FIB machine. (b) Wire cut. (c) Platinum deposition beam.(d) Platinum deposition wire soldering.

4.3. Simulation Results of the Main Blocks in CM-SAR ADC 79

4.3 Simulation Results of the Main Blocks in

CM-SAR ADC

The effect of each block nonidealities on the overall SAR ADC performance isevaluated using transient noise simulations in Spectre. In these simulations, thesystem clock frequency is set to 2 GHz within 10 conversion cycles when the S/Hblock is ideal, resulting in a conversion rate of 200 MS/s. However, the system clockfrequency is only increased to 2.2 GHz when the S/H is simulated on transistorlevel with the Gm stage and an extra clock cycle is dedicated to the samplingprocess, maintaining the conversion rate up to 200 MS/s too. The results of thesesimulations including the effect of layout related parasitics are discussed in thefollowing sections.

4.3.1 Input Stage in SAR ADC

The effect of Gm stage and S/H nonidealities on the overall SAR ADC performanceis simulated and the results of these simulations are shown in Fig. 4.9 and furtherdiscussed in the following sections.

Gm Stage in Current-Based SAR ADC

For this set of simulations, the Gm stage is built on transistor level while allremaining components are modeled using Verilog-A except for the TIA, which ismodeled with a 50 Ω input resistance. The common-mode of nodes X and Y inFig. 3.2 is set to 700 mV. The simulation results in Fig. 4.9 show that the SNDRremains above 58 dB and the SFDR above 77 dBc over the entire Nyquist band forthe schematic level case. The performance drop in this case is due to the relativelysmall voltage headroom for transistors M1,2 and MCS in the Gm stage of Fig. 3.4imposed by the DAC requirements. In case of the post-layout simulations, theSNDR remains approximately above 56 dB and the SFDR above 71 dBc over theentire Nyquist band.

S/H and Gm Stage in Current-Based SAR ADC

For the next set of simulations, the input S/H and Gm stage are modeled ontransistor level and all remaining blocks of the SAR ADC in Verilog-A exceptalso for the TIA, which is modeled with a 50 Ω input resistance. The schematicsimulation results in Fig. 4.10 show that the SNDR, for an input frequency closeto Nyquist, remains approximately above 55 dB and the SFDR above 66 dBc up to200 MHz sampling frequency. Here, the degraded performance is due to the non-ideal sampling process imposed by the signal-dependent input capacitance of theGm stage. The post-layout simulation results in Fig. 4.11 show that the SNDR,for an input frequency close to Nyquist, remains approximately above 37 dB andthe SFDR above 37 dBc up to 200 MHz sampling frequency. Obviously, a drop inSNDR and SFDR of about 16 dB is seen for the range of sampling frequencies from100-200 MS/s in the post-layout simulations. This is because the added parasiticresistance and capacitance after the RC-extraction, which results in an increasedsettling time for the bootstrap loop of the S/H circuit in Fig. 3.10. This increasein the settling time of the loop increases the non-linear distortion caused by theON-resistance of the S/H switch.


0 10 20 30 40 50 60 70 80 90 100

54

56

58

60

62

64

Input Frequency (MHz)

SN

DR

(dB

)

Schematic Level Simulation

Post-layout Simulation

0 10 20 30 40 50 60 70 80 90 100

65

70

75

80

85

90

95


SF

DR

(dB

c)

Schematic Level Simulation

Post-layout Simulation

Figure 4.9: Schematic and post-layout simulations of the dynamic performance ofthe Gm stage in the current-based SAR ADC over a 100 MHz Nyquist band.


50 100 150 200

54

56

58

60

62

64

Sampling Frequency (MS/s)

SN

DR

(dB

)

fin=fs/10

fin=fs/2.5

50 100 150 200

55

60

65

70

75

80


SF

DR

(dB

c)

fin=fs/10

fin=fs/2.5

Figure 4.10: Schematic level simulations of the dynamic performance of the S/Hand Gm stage in the current-based SAR ADC up to 200 MHz sampling frequency.

50 100 150 200

35

40

45

50

55

60

65


SN

DR

(dB

)

fin=fs/10

fin=fs/2.5

50 100 150 200

30

40

50

60

70


SF

DR

(dB

c)

fin=fs/10

fin=fs/2.5

Figure 4.11: Post-layout simulations of the dynamic performance of the S/H andGm stage in the current-based SAR ADC up to 200 MHz sampling frequency.


4.3.2 CM-DAC in SAR ADC

The DAC based on the unit cell shown in Fig. 3.11 is designed using a 1.2 V supplywhile the other DAC based on the unit cell shown in Fig. 3.32 is designed using a1.2 / 1.8 V supply. The designed DACs are simulated on the transistor level insidea SAR loop where all remaining components are ideal except for the TIA, which ismodeled with a 50 Ω input resistance. The results of these simulations are shownin Figs. 4.12 and 4.13 and further discussed in the following sections.

Schematic Level Simulations of Different DAC Architectures

For this set of simulations, the two DAC architectures based on the unit cells shownin Figs. 3.11 and 3.32 are modeled on the schematic transistor level. The SNDRand SFDR values of the converter as a function of input frequency are shownin Fig. 4.12. The SNDR, for the first design based on the unit cell in Fig. 3.11,remains above 54 dB, while the SFDR is approximately above 70 dBc over theentire Nyquist band. For the final design based on the unit cell in Fig. 3.32, theSNDR remains approximately above 60 dB and the SFDR above 77 dBc over theentire Nyquist band. This is an improvement in SNDR and SFDR of around 6 dBand 7 dBc, respectively, compared to the first design. The improvement in SFDRis due to the increased output resistance of the unit cell because more headroomvoltage is given to the cascode transistor of the unit cell in Fig. 3.32. The noiseperformance improvement is due to the increased current source overdrive voltagewhich lowers the thermal noise contribution from the thick oxide (I/O) currentsource transistor of the unit cell in Fig. 3.32.

Schematic/Post-layout Simulations of the Modified DAC Architecture

In this section, the DAC layout, for the final design based on the unit cell inFig. 3.32, is RC extracted and re-simulated. The SNDR and SFDR values ofthe converter as a function of input frequency are shown in Fig. 4.13. In thefirst case, the load resistance is set to 50 Ω. The SNDR remains above 47 dB,while the SFDR is above 60 dBc over the entire Nyquist band. In case the loadresistance is decreased to 40 Ω, the SNDR and SFDR remain above 50 dB and63 dBc, respectively. The drop in performance between the schematic and the twodifferent post-layout simulations is due to the large extracted wiring capacitanceat the DAC output, which is approximately 860 fF. This in turn increases the timeconstant of the settling process of the DAC current and results in an incompletesettling accuracy for the DAC, according to the time specifications described insection 3.3.2.


0 10 20 30 40 50 60 70 80 90 100

54

56

58

60

62

64


SN

DR

(dB

)

Core transistor current source based DAC

I/O transistor current source based DAC

0 10 20 30 40 50 60 70 80 90 100

70

75

80

85

90


SF

DR

(dB

c)

Core transistor current source based DAC

I/O transistor current source based DAC

Figure 4.12: Schematic level simulations of the dynamic performance for differentDAC architectures in the current-based SAR ADC over a 100 MHz Nyquist band.


0 10 20 30 40 50 60 70 80 90 100

40

45

50

55

60

65

70

75


SN

DR

(dB

)

Schematic Level Simulation - RL=50 Ω

Post-layout Simulation - RL=40 Ω


0 10 20 30 40 50 60 70 80 90 100

60

70

80

90

100


SF

DR

(dB

c)

Schematic Level Simulation - RL=50 Ω



Figure 4.13: Simulated dynamic performance of the DAC in the current-basedSAR ADC over a 100 MHz Nyquist band for the DAC based on the unit cell inFig. 3.32.


4.3.3 Current Comparator in SAR ADC

The current comparator blocks containing the TIA, voltage preamp and latch aredesigned with 1.2 V supply. The effect of the current comparator nonidealities onthe overall SAR ADC performance is simulated and the results of these simulationsare shown in Fig. 4.14 and further discussed in the following sections.

TIA in Current-Based SAR

For this set of simulations, the TIA is modeled on transistor level and all remainingblocks of the SAR ADC in Verilog-A. The simulation results, in Fig. 4.14 referredto as ”TIA schematic”, show that the SNDR remains above 59 dB and the SFDRabove 77 dBc over the entire Nyquist band. The simulation results, in Fig. 4.14referred to as ”TIA post-layout”, show that the SNDR remains above 55 dB andthe SFDR above 68 dBc over the entire Nyquist band.

TIA-Preamp-Latch in Current-Based SAR

For the next set of simulations, the whole current comparator is modeled on tran-sistor level and all remaining blocks of the SAR ADC in Verilog-A. The latch isloaded with a 50 fF capacitor that represents the total input capacitance of thebuffer stage following the latch in Fig. 3.50. The simulation results, in Fig. 4.14referred to as ”Current comparator schematic”, show that the SNDR remainsabove 57 dB and the SFDR approximately above 76 dBc over the entire Nyquistband. The simulation results, in Fig. 4.14 referred to as ”Current comparatorpost-layout”, show that the SNDR remains approximately above 55 dB and theSFDR above 68 dBc over the entire Nyquist band.

4.3.4 Gm-DAC-TIA in Current-Based SAR

In this set of simulations, the three main blocks including the input Gm stage,DAC and TIA are modeled on transistor level and all remaining blocks of the SARADC in Verilog-A. The simulation results, in Fig. 4.15 referred to as ”Gm-DAC-TIA schematic”, show that the SNDR remains approximately above 57 dB and theSFDR above 76 dBc over the entire Nyquist band. Degraded performance in thiscase is due to the relatively small headroom voltage for transistor M1 in the TIAof Fig. 3.45 imposed by the DAC requirements. On the other hand, the simulationresults, in Fig. 4.15 referred to as ”Gm-DAC-TIA post-layout”, show that theSNDR remains approximately above 39 dB and the SFDR above 55 dBc over theentire Nyquist band. As seen in Fig. 4.15 the SNDR and SFDR of the post-layoutsimulations are degraded by about 17 dB and 20 dBc, respectively. This degradedperformance is because of the combination of the designed, rather large inputimpedance of the TIA of 100 Ω (section 3.4.2) together with the extracted wiringcapacitance at the DAC output, which is approximately 860 fF. Both togetherincrease the time constant of the settling process and result in incomplete settlingaccuracy for the DAC. However, for lower sampling speeds up to 100 MS/s, theSNDR remains above 51 dB and the SFDR above 63 dBc as shown in Fig. 4.16.


0 10 20 30 40 50 60 70 80 90 100

54

56

58

60

62

64


SN

DR

(dB

)

TIA schematic

TIA post-layout

Current comparator schematic

Current comparator post-layout

0 10 20 30 40 50 60 70 80 90 100

65

70

75

80

85

90


SF

DR

(dB

c)

TIA schematic

TIA post-layout

Current comparator schematic

Current comparator post-layout

Figure 4.14: Simulated dynamic performance of the TIA and current comparatorin the current-based SAR ADC over a 100 MHz Nyquist band.


0 10 20 30 40 50 60 70 80 90 100

35

40

45

50

55

60

65


SN

DR

(dB

)

DAC-Gm-TIA (schematic)

DAC-Gm-TIA (post-layout)

0 10 20 30 40 50 60 70 80 90 100

50

60

70

80

90


SF

DR

(dB

c)



Figure 4.15: Simulated dynamic performance of the DAC, Gm stage and TIA inthe current-based SAR ADC at a conversion rate of 200 MS/s.


0 20 40 60 80 100 120 140 160 180 200

35

40

45

50

55

60

65


SN

DR

(dB

)



0 20 40 60 80 100 120 140 160 180 200

50

60

70

80

90


SF

DR

(dB

c)



Figure 4.16: Simulated dynamic performance of the Gm stage, DAC and TIA inthe current-based SAR ADC from 0 to 200 MS/s conversion rate.


4.3.5 Summary

In all previous results, the dynamic performance of the schematic simulations ofeach individual block in the CM-SAR ADC show flat responses over the Nyquistband of 100 MHz with the SNDR which remains approximately above 55 dB andthe SFDR above 65 dBc. The post-layout simulations are summarized in Fig. 4.17.As seen from the figure, the dynamic performance is kept approximately flat upto 100 MS/s conversion rate. However, the dynamic performance referred to as”DAC-RL=50 Ω” and ”Gm-DAC-TIA”, starts to drop after this speed due to thereasons mentioned in sections 4.3.2 and 4.3.4, respectively. The dynamic perform-ance of the RC-extracted S/H block loaded with the Gm stage, referred to as”S/H-Gm”, shows a severe drop in SFDR at higher speeds due to the reasonmentioned in section 4.3.1.

0 20 40 60 80 100 120 140 160 180 200

35

40

45

50

55

60

65


SN

DR

(dB

)

S/H-Gm

DAC-RL=50 Ω

DAC-Gm-TIA

0 20 40 60 80 100 120 140 160 180 200

40

50

60

70

80


SF

DR

(dB

c)

S/H-Gm

DAC-RL=50 Ω

DAC-Gm-TIA

Figure 4.17: Summary of the post-layout simulated dynamic performance of themain blocks in the current-based SAR ADC from 0 to 200 MS/s conversion rate.


4.4 Top Level Simulation and Measurement Res-

ults

The results of the top-level simulations as well as the measurements are shown inFigs. 4.18 - 4.23 and are further discussed in the following sections.

4.4.1 Schematic and Post-layout Simulation Results

Dynamic Performance vs Sampling Frequency

For this set of simulations, the dynamic performance is simulated against thesampling frequency for an input frequency of (fs/10) as shown in Fig. 4.18. First,the simulation results in Fig. 4.18 labeled as ”Schematic” show that the SNDRremains approximately above 53 dB and the SFDR above 60 dBc up to a samplingfrequency of 150 MS/s. Then, the layout is RC extracted with 500 mΩ and 100 mΩaccuracies and then re-simulated. It can be seen from Fig. 4.18 that the dynamicperformance of the post-layout simulations can not achieve its counterpart of theschematic simulations due to the aforementioned problems in sections 4.3.2 and4.3.4. Nonetheless, the post-layout simulation results in Fig. 4.18 labeled as ”Post-layout (Racc. = 500 mΩ)” show that the SNDR remains approximately above 50 dBand the SFDR above 57 dBc up to a sampling frequency of 70 MS/s. In contrast,the simulation results labeled as ”Post-layout (Racc. = 100 mΩ)” show a significantperformance degradation and the resulting SNDR drops to approximately 40 dBand the SFDR to around 55 dBc up to a sampling frequency of 70 MS/s. Here, thedegraded SNDR is due to the increased resistance of the power routing grid of thedigital supply which introduces a transient IR-drop in the digital supply line and,consequently, decreases the delivered voltage to the comparator and CLK buffers.

Dynamic Performance vs Input Frequency

In this set of simulations, the dynamic performance is simulated against the inputfrequency for a Nyquist band of 25 MHz as shown in Fig. 4.19. The simulationresults in Fig. 4.19 labeled as ”Schematic” show that the SNDR remains approx-imately above 55 dB and the SFDR above 61 dBc over the entire Nyquist band.The simulation results in Fig. 4.19 labeled as ”Post-layout (Racc. = 500 mΩ)” showthat the SNDR remains approximately above 51 dB and the SFDR above 58 dBcover the entire Nyquist band. In contrast, the simulation results labeled as ”Post-layout (Racc. = 100 mΩ)” show a significant performance degradation, due to theaforementioned power routing issue, and the resulting SNDR drops to approxim-ately 45 dB and the SFDR to 56 dBc over the entire Nyquist band.

4.4.2 Measurement Results

Dynamic Performance vs Sampling Frequency

Similar to the previous sections, the measured dynamic performance is sweptagainst the sampling frequency and the results are shown in Fig. 4.18 labeled as”Measurement”. As seen in the figures, the measured SNDR is dropped by about1.5 bit below the parasitic extracted simulation with 500 mΩ accuracy at the speed

4.4. Top Level Simulation and Measurement Results 91

of 70 MS/s. The reason for the degraded SNDR is due to the power routing issuementioned in the previous sections. Nonetheless, the measured SFDR shows onlyabout 3 dB drop from the lower accuracy parasitic extracted simulation at thesame speed of 70 MS/s. The measured SNDR, SFDR, THD and SNR are shownin Fig. 4.20. The SNR is above 44 dB up to 70 MS/s. The THD is above 50 dB at50 MS/s and it shows about 8 to 9 dB drop below the SFDR.

Dynamic Performance vs Input Frequency

In this case, the measured dynamic performance is swept over a Nyquist band of25 MHz and the results are shown in Fig. 4.19 labeled as ”Measurement”. TheSNDR remains approximately flat above 44 dB and the SFDR above 56 dBc overthe entire Nyquist band of 25 MHz.

ADC Power Spectrum and Intermodulation Distortion

Fig. 4.21 shows the measured ADC power spectrum plot for a 320 mVpp−diff inputsignal at fin=2.5 MHz and fs=50 MS/s. The SNDR is 45 dB and the SFDR is58.4 dBc which is dominated by the 3rd order harmonic distortion. Fig. 4.22 showsthe measured ADC power spectrum plot for a two tone test with frequencies atfin1= 1.12 MHz and fin2=1.608 MHz. The measured IMD3 is approximately 52 dB.

Dynamic Performance vs Temperature Variations

Even though this prototype has not been designed to work over a significanttemperature range, the dynamic performance over the temperature variation from-40 to about 70C is shown in Fig. 4.23. The variation in SNDR is from 5 to 6 dB forthe range of temperatures from -10 to 50C. The SFDR changes by approximately8 to 9 dB in the same range.


0 20 40 60 80 100 120 14020

30

40

50

60

70


SN

DR

(dB

)

Schematic

Post-layout (Racc. = 500 mΩ)


Measurement

0 20 40 60 80 100 120 14040

45

50

55

60

65

70


SF

DR

(dB

c)

Schematic



Measurement

Figure 4.18: Simulated and measured dynamic performance of the CM-SAR ADCvs the sampling frequency.


0 2 4 6 8 10 12 14 16 18 20 22 24

40

45

50

55

60

65

70


SN

DR

(dB

)

Schematic



Measurement

0 2 4 6 8 10 12 14 16 18 20 22 24

50

55

60

65

70


SF

DR

(dB

c)

Schematic



Measurement

Figure 4.19: Simulated and measured dynamic performance of the CM-SAR ADCover a 25 MHz Nyquist band.


0 10 20 30 40 50 60 70 80 90

30

40

50

60

70


P(d

B)

SNDR

SFDR

THD

SNR

Figure 4.20: Measured dynamic performance of the CM-SAR ADC vs the samplingfrequency.

HD2 HD3 HD5

Figure 4.21: Measured ADC power spectrum plot with a 2.5 MHz input signal at50 MS/s.


IMD3

IMD3

Figure 4.22: Measured ADC power spectrum plot with a two tone test with fre-quencies at 1.12 and 1.6 MHz at 50 MS/s.

−40 −30 −20 −10 0 10 20 30 40 50 60 70

30

40

50

60

70

Temperature (C)

P(d

B)

SNDR

SFDR

Figure 4.23: Measured dynamic performance of the CM-SAR ADC over the tem-perature at 50 MS/s.


4.5 Power Consumption of the Chip

The total power consumption of the chip is about 6 mW excluding the CLK gen-erator and CLK buffers. The power is delivered from one 1.8 V supply (DACpower supply) and two 1.2 V supplies, one delivers the power to the analog blocks(including the reference current generator, S/H circuit, Gm stage, TIA and thevoltage-preamp of the comparator) and the other to the digital blocks (includ-ing the comparator latches and the SAR control logic). The power consumptionfrom the analog blocks dominates the other power consumptions with more than56 % while the digital power consumption is the lowest with only 8.3 % as shownin Fig. 4.24a. The distribution of the power consumption among the analog anddigital blocks are also shown in Fig. 4.24. Obviously seen that the major contrib-utors of the analog power consumption, with more than 47 %, are the Gm stageand the TIA, which explicitly biases the Gm stage. The contributions of both,the S/H circuit and the reference current generator (beta-multiplier), in analogpower consumption are minor with only 1.85 %. The digital power consumptionis dominated by the SAR control logic which consumes 80 % of the total digitalpower.

8.3%

35%

56.7%

Analog

1.2V Supply

Digital

1.2V Supply

DAC

1.8V Supply

Total Power

= 6 mW

(a)

Gm & TIA

Av

38.18%

12.67%

1.85%

47.3%

Total Power

= 5.5 mW

Beta

Multiplier

& S/H

DAC

(b)

8.3%

20%

80%

SAR Logic

& Output

Registers

Comparator

Latches

Total Power

= 0.5 mW

(c)

Figure 4.24: (a) The power dissipated from the 1.2 V supply (for analog & digitalblocks) and 1.8 V supply (for the DAC). (b) The power consumption of the analogblocks and the DAC. (c) The power consumption of the digital blocks.

4.6. Comparison to Other Works 97

4.6 Comparison to Other Works

The measurement results of the most power efficient, single-channel, non-TI,higher than or equal to 10-bit state-of-the-art SC-SAR ADCs are compared withthe proposed CM-SAR ADC and the comparison is given in Table 4.1. As shownin the table, the CS of the proposed ADC is smaller than the total capacitance ofthe other technology-scaled SC-SAR ADCs, even though the linear input range ofthe Gm stage is limited to about 400 mVpp in this design. The CS is approximately60% smaller compared to the ones in references [78] and [79] which are implemen-ted for 10-bit resolution with higher signal swings in almost similar technologynodes.

Even though, the paper in [4] has been also implemented for a 10-bit resolutionin smaller technology node, but the total capacitance size can not be decreased tobe smaller than the capacitor size presented in this work. This is because the unitcapacitor size of the SC-DAC is determined by the matching requirements whichusually constrains the minimum allowable capacitor size. Moreover, it should benoted, that the power of the reference and input buffers is significantly high inSC-SAR ADCs, which is usually not included in reported FOMs. However, asevere performance loss in this prototype measurement is clearly observed dueto the aforementioned power routing issue; without the power routing associatedperformance loss, the FOM would come closer to the state of the art CM-SARADCs.


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Chapter 5

Conclusion and Outlook

In this thesis, an approach to high-speed reduced cap-size CM-SAR ADCs has beenpresented. In this approach, a Gm stage has been used to convert the input voltageto a current which is then processed in a current-based binary search algorithmSAR loop. The Gm stage is designed to achieve a 10-bit linearity over a Vid rangeof 400 mVpp, which allows to choose the sampling capacitor based only on kT/Cnoise and not on the matching requirements of a SC-DAC. This in turn leads to apower saving benefit as the input buffers can be excluded. Moreover, by using thisapproach, DAC-reference buffers are not required as a reference current generatorhas been used to generate reference currents which are then switched during theSAR operation. The measured dynamic performance of the ADC is nearly flatover the whole Nyquist band of 25 MHz and achieves an SNDR and ENOB ofaround 45 dB and 7.2 bit, respectively. However, the measured SNDR dropped byabout 1-bit below the parasitic extracted simulation with 500 mΩ accuracy, dueto the increased resistance of the power routing grid of the comparator supply linewhich decreases the SNDR of the converter. Nonetheless, the measured SFDR isclose to the parasitic extracted simulations and shows about 58.4 dBc. Comparedto the existing CM-SAR ADCs, measurement results demonstrate the potential toachieve high-speed single channel SAR ADCs. Moreover, the sampling capacitorsize is smaller than the total capacitance of the comparable SC-SAR ADC by ap-proximately 60 %, although the linear input range of the Gm stage is limited toabout 400 mVpp in this design. However, much smaller sampling capacitor sizescan be achieved by increasing the linear input range of the Gm stage using a back-ground calibration technique for the Gm stage non-linearities. On the other hand,further improvement in speed is limited due to the long comparator decision timeand large SAR logic delay in this chosen technology. However, higher conversionrates of this type of ADCs can be achieved in advanced scaled CMOS technologiesand/or by using asynchronous SAR logic. Nonetheless, The incomplete settling ofthe DAC current at high-speed operation can be tolerated by considering singleor multiple redundant cycles. The increased extracted capacitance at the DACoutput can be resolved by decreasing the matching constraints of the DAC layoutand then compensate the mismatch by considering a background calibration forthe DAC unit element mismatch. The main power dissipation in the ADC ori-ginates from the Gm stage and the comparator front-end. Investigation on morepower efficient circuit topologies might potentially yield in a more compatibleFOM compared to the other ADCs.

99

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List of Author Publications

• A. Elkafrawy, J. Anders and M. Ortmanns, ”Design and Validation of a 10-bitReference Free Current Mode SAR ADC in 90 nm CMOS,” Springer Interna-tional Journal: ”Analog Integrated Circuits and Signal Processing, Special IssueNORCAS 2015”, 2016, accepted for publication.

• A. Elkafrawy, J. Anders and M. Ortmanns, ”A 10-bit Reference Free CurrentMode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS,” IEEENORCAS, Oslo, Norway, October 2015.

• A. Elkafrawy, J. Anders and M. Ortmanns, ”Design and Validation of a Cur-rent Mode Based SAR ADC in 90 nm CMOS,” Kleinheubacher Tagung, Milten-berg, Germany, September 2015.

• A. Elkafrawy, J. Anders and M. Ortmanns, ”A 10-bit 150 MS/s Current ModeSAR ADC in 90 nm CMOS,” IEEE PRIME, Glasgow, Scotland, United King-dom, June 2015.

• A. Elkafrawy, A. AlMarashli, R. Ritter, J. Anders and M. Ortmanns, ”Designof a High Linearity Gm Stage for a High Speed Current Mode SAR ADC,”IEEE ICECS, Marseille, France, December 2014.

• A. Elkafrawy, J. Anders and M. Ortmanns, ”Design of a High ResolutionTransimpedance Amplifier for a High Speed Current Mode SAR ADC,” Klein-heubacher Tagung, Miltenberg, Germany, September 2014.

• A. Elkafrawy, J. Anders and M. Ortmanns, ”A High Resolution Transimped-ance Amplifier for Use in a 10-bit 200 MS/s Current Mode SAR ADC,” IEEEMWSCAS, College Station, Texas, USA, August 2014.

• A. Elkafrawy, J. Anders and M. Ortmanns, ”A High Speed Current SteeringDAC Based Current Mode SAR ADC,” Analog Circuits Workshop, Vienna,Austria, February 2014.

• A. Elkafrawy, J. Anders, T. Bruckner and M. Ortmanns, ”Design of a CurrentSteering DAC for a High Speed Current Mode SAR ADC,” IEEE ICECS, AbuDhabi, UAE, December 2013.

• A. Elkafrawy, J. Anders and M. Ortmanns, ”An Approach to High Speed SARADCs,” Kleinheubacher Tagung, Miltenberg, Germany, September 2013.

109

Resume

Dr.-Ing. Abdelrahman Elkafrawy

Email: [email protected]

Education

06/2016 Dr.-Ing. in Microelectronics, Institute of Microelectronics,

University of Ulm, Germany.

08/2008 M.Sc. in Microelectronics, Cairo University, Egypt.

Title: New CMOS Realizations of the Operational Transresistance

Amplifier & Operational Floating Conveyor and their Applications.

05/2005 B.Sc. in Electronics and Communication Engineering,

Cairo University, Egypt. Grade: Very Good with Honor (83.4%).

Awards

06/2015 Best Student Paper Award, SILVER Leaf, awarded for the paper:

A. Elkafrawy, J. Anders and M. Ortmanns, ”A 10-bit 150 MS/s Current

Mode SAR ADC in 90 nm CMOS,” 11th IEEE PRIME 2015, Glasgow,

United Kingdom, pp.274-277, June 2015.

10/2010 DAAD Scholarship, German Egyptian Research Long-Term

Ph.D. Scholarship (2010-2015).

Professional Experience

05/2011 Research/Teaching Assistant, Institute of Microelectronics,

-04/2016 University of Ulm, Germany.

- Design, layout and lab characterization of a 10-bit 150 MS/s Current

Mode SAR ADC in TSMC 90 nm CMOS technology.

- Supervising postgraduate students in the design of:

2nd order DT Sigma-Delta modulator for audio applications.

09/2006 Research/Teaching Assistant, Dept. of Information Engineering &

-08/2010 Technology, German University in Cairo (GUC), Egypt.

- Co-supervisor for Bachelor/Master students in their graduation projects.

- Teaching undergraduate/postgraduate students the following courses:

- Analog Circuit Design & Advanced Microelectronics Lab.

- Electric Circuits, Communication Systems Design and Networks Lab.

- Signals and Systems Theory, Mathematics and Physics 101, 102.

dissertation - uni ulm

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