DIRECT CONVERSION RECEIVERS IN WIDE-BAND SYSTEMS

THE KLUWER INTERNATIONAL SERIESIN ENGINEERING AND COMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSINGConsulting Editor: Mohammed Ismail. Ohio State

University

Related Titles:

AUTOMATIC CALIBRATION OF MODULATED FREQUENCY SYNTHESIZERSD. McMahill

ISBN: 0-7923-7589-0MODEL ENGINEERING IN MIXED-SIGNAL CIRCUIT DESIGN

S. HussISBN: 0-7923-7598-X

CONTINUOUS-TIME SIGMA-DELTA MODULATION FOR A/D CONVERSION INRADIO RECEIVERS

L. Breems, J.H. HuijsingISBN: 0-7923-7492-4

DIRECT DIGITAL SYNTHESIZERS: THEORY, DESIGN AND APPLICATIONSJ. Vankka, K. HalonenISBN: 0-7923 7366-9

SYSTEMATIC DESIGN FOR OPTIMISATION OF PIPELINED ADCsJ. Goes, J.C. Vital, J. FrancaISBN: 0-7923-7291-3

OPERATIONAL AMPLIFIERS: Theory and DesignJ. HuijsingISBN: 0-7923-7284-0

HIGH-PERFORMANCE HARMONIC OSCILLATORS AND BANDGAP REFERENCESA. van Staveren, C.J.M. Verhoeven,A.H.M. van RoermundISBN: 0-7923-7283-2

HIGH SPEED A/D CONVERTERS: Understanding Data Converters Through SPICEA. MoscoviciISBN: 0-7923-7276-X

ANALOG TEST SIGNAL GENERATION USING PERIODIC DATASTREAMS

B. Dufort, G.W. RobertsISBN: 0-7923-7211-5

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORSA. Bakker, J. HuijsingISBN: 0-7923-7217-4

DESIGN, SIMULATION AND APPLICATIONS OF INDUCTORS AND TRANSFORMERSFOR Si RF ICs

A.M. Niknejad, R.G. MeyerISBN: 0-7923-7986-1

SWITCHED-CURRENT SIGNAL PROCESSING AND A/D CONVERSION CIRCUITS:DESIGN AND IMPLEMENTATION

B.E. JonssonISBN: 0-7923-7871-7

RESEARCH PERSPECTIVES ON DYNAMIC TRANSLINEAR AND LOG-DOMAINCIRCUITS

W.A. Serdijn, J. MulderISBN: 0-7923-7811-3

CMOS DATA CONVERTERS FOR COMMUNICATIONSM. Gustavsson, J. Wikner, N. TanISBN: 0-7923-7780-X

DESIGN AND ANALYSIS OF INTEGRATOR-BASED LOG -DOMAIN FILTER CIRCUITSG.W. Roberts, V. W. LeungISBN: 0-7923-8699-X

VISION CHIPSA. MoiniISBN: 0-7923-8664-7

DIRECT CONVERSIONRECEIVERS IN WIDE-BAND

SYSTEMS

by

Aarno PärssinenNokia Research Center

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47545-6Print ISBN: 0-7923-7607-2

©2002 Kluwer Academic PublishersNew York, Boston, Dordrecht, London, Moscow

Print ©2001 Kluwer Academic Publishers

All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Kluwer Online at: http://kluweronline.comand Kluwer's eBookstore at: http://ebooks.kluweronline.com

Dordrecht

Preface

This book is based on my doctoral thesis at the Helsinki University of Technology. Severaldifferent projects during five years guided me from the basics of the RF IC design to theimplementations of highly integrated radio receiver chips. Sharing time and effort between ICand system issues is not always straightforward. I have been lucky to follow both topics andshare experiences with diligent and enthusiastic people having different specialities. As a result,this book will cover a wide range of different topics needed in the design of highly integratedradio receivers. Experiences from the first receiver prototypes for the third generation cellularsystems form the basis of this book. Most of the issues are directly related to the early proposalsof European and Japanese standardization organizations. For example, the chip rate wasoriginally set to 4.096 Mcps in a wide-band CDMA channel. I have kept that number in thebook in most of the examples although it has been later changed to 3.84 Mcps. I hope that thereaders will accept that and the possible other incompabilities to the latest specifications. Atleast in the research phase the changes even in the most essential requirements are definitely nota rare incident and IC designers should be able to react and modify their designs as soon as theycan.

Also several other new radio systems, like Bluetooth and wireless LAN, are coming to themarket in a relatively short period of time hence often demanding shared resources and fastdevelopment times from IC designers. Radio system characteristics should be quicklytransferred into integrated circuits using the most optimal architecture in each case. I hope thatthis book will be useful not only for IC designers contemplating on third generation cellularsystems but also for professionals working with wider area of applications. To promote that Ihave tried to collect the most essential issues from radio communication principles withoutgoing deep into theory. I have assumed that the reader is familiar with the basic RF and ICdesign principles, and most of the details can be found in the references. The main focus in thisbook is to transfer the system description into an optimal IC implementation in different cases.Typically new systems will be specified without deep understanding of the implementationissues and even a small detail may cause considerable difficulties for the realization and extendthe development time. Maybe this book could also give communications engineers some adviceon the recent trends, limitations and capabilities of modern IC techniques for radio reception.

I have done the research work included in this book at the Electronic Circuit Design Laboratory,Helsinki University of Technology except for one year at the University of California SantaBarbara. My supervisor Professor Kari Halonen deserves my gratitude for his confidence to mywork and for giving me excellent challenges and opportunities. With a great enthusiasm foranalog electronics Professor Veikko Porra guided my interest in this field during my studies andin the early steps of IC design. My first research project was given by Professor Stephen I. Longfrom the University of California Santa Barbara. He also offered me the possibility to work inCalifornia and instructed my research for several years. I am grateful for all his wise pieces ofadvice and for teaching me a scientific way of thinking. I would also like to thank Dr. PetteriAlinikula for the important support and encouragement he gave me as a teacher and as a mentorat the beginning of my RF IC design efforts.

I would like to thank all my colleagues at the Electronic Circuit Design Laboratory. Especially,Mr. Kari Stadius and Dr. Risto Kaunisto deserve my gratitude for teaching me the essentialpractices of IC design and later being my close friends and advisors. Dr. Saska Lindfors taughtme a lot of things about CMOS design and I will remember the cooperation in subsamplingissues as a fruitful experience. I learned the principles of the third generation cellular systems inthe team with Jarkko Jussila, Jussi Ryynänen, Lauri Sumanen and Kalle Kivekäs. Their

i

dedication to the collective challenges when integrating direct conversion receivers has beenrespectable. I would like to thank all of them individually and acknowledge their importance asmembers of the team. Their work is an essential part of this book. Rami Ahola deserves mygratitude for prompt process support. I would also like to thank Rahul Magoon for theproductive discussions and help during my stay at Santa Barbara. Timo Knuuttila has promotedthis book by offering a challenging project to get acquainted with the third generation systems.Mauri Honkanen has been a significant advisor for me in the area of radio systems.

Professor Qiuting Huang, Dr. Jan Sevenhans and Dr. Pertti Ikäläinen are acknowledged forreviewing my thesis. I would like to express my warmest thanks for their encouragingcomments.

I wish to thank my wife Salla, my parents Anna-Leena and Tapio and my sister Maria with herfamily for their constant and strong support.

This book is based on the work, which has been financed by Graduate School in Electronics,Telecommunications and Automation, Technology Development Centre of Finland, Academyof Finland, Nokia Networks and Nokia Mobile Phones. Also, grants by Nokia Foundation,Foundation for Financial Aid at the Helsinki University of Technology, Emil AaltonenFoundation and Elektroniikkainsinöörien säätiö (Foundation of Electronics Engineers inFinland) have given significant support. All of them are gratefully acknowledged.

Aarno PärssinenSeptember 2001

ii

Contents

Preface i

Contents iii

Symbols and Abbreviations vSymbols vAbbreviations xii

1 Introduction 1

2 System Requirements for Radio Receivers in Wireless Communications 32.1 Mobile Communications 3

2.1.1 Wireless Systems 62.2 Multiple Access Methods and Duplexing 8

2.2.1 Frequency Division Multiple Access 92.2.2 Time Division Multiple Access 92.2.3 Code Division Multiple Access 92.2.4 Duplexing 12

2.3 Digital Modulation 122.3.1 Binary Phase Shift Keying (BPSK) 142.3.2 Quadrature Phase Shift Keying (QPSK) 152.3.3 Frequency Shift Keying (FSK) 172.3.4 Gaussian-Filtered Minimum Shift Keying (GMSK) 182.3.5 Quadrature Amplitude Modulation (QAM) 182.3.6 DS-CDMA QPSK Transmitter 19

2.4 Design Parameters for Radio Receivers 192.4.1 Sensitivity 202.4.2 Intersymbol Interference 252.4.3 Selectivity 282.4.4 Dynamic Range 412.4.5 Gain and Interface to Digital Signal Processing 462.4.6 Image Rejection Ratio 512.4.7 Quadrature Demodulation 562.4.8 Special Topics in CDMA Communications 59

References 73

3 Receiver Architectures 763.1 Superheterodyne 773.2 Direct Conversion 803.3 Low-IF 863.4 Wide-Band IF 903.5 Direct Digital And Digital IF 923.6 Comparison of Architectures 97References 98

4 Direct Conversion Receivers 1044.1 Direct Conversion in Wide-Band Systems 104

4.1.1 DC Offsets and Flicker Noise 1044.1.2 Envelope Distortion 109

4.2 Radio Design 115

iii

4.3 Functional Blocks in Direct Conversion Receivers 1164.3.1 Low-Noise Amplifiers 1164.3.2 Mixers 1214.3.3 LO Generation and I/Q Balance 1234.3.4 Filtering 1294.3.5 A/D Converters 1314.3.6 Decoupling 135

4.4 Active Mixers in Direct Conversion 1374.4.1 Active Mixer Topologies 1374.4.2 Interfaces to LNA and Baseband 1414.4.3 Theoretical Characterization of IIP2 in Transconductance Mixers 1424.4.4 Switching Core 1554.4.5 BiCMOS Transconductance Mixer 164

4.5 Downconversion by Subsampling 1654.6 Single-Chip Radio Receivers 169

4.6.1 Frequency Planning in Mixed-Mode Implementations 1704.7 IC Implementations 176References 178

5 Circuit Implementations 1975.1 Subsampling Mixer 197

5.1.1 Circuit Description 1975.1.2 Measurement Setup 2015.1.3 Experimental Results 2025.1.4 Summary of the Subsampling Mixer 205

5.2 Low-Noise Amplifier and Interface to a Subsampling RF Front-End 2055.2.1 Low-Noise Amplifier 2065.2.2 Resonator Load with On-Chip Coupling Capacitors 2075.2.3 Current Biasing Circuit for the LNA 2095.2.4 Implementation 2095.2.5 Summary of the LNA and Interface to Subsampling Mixer 211

5.3 Chipset for Direct Conversion WCDMA Receiver 2115.3.1 Building Blocks of the Direct Conversion Receiver 2125.3.2 Layout 2175.3.3 Experimental Results 2185.3.4 Summary of the WCDMA Chip Set 222

5.4 Single-Chip Direct Conversion Receiver for WCDMA 2235.4.1 Circuit Design 2235.4.2 Experimental Results 2245.4.3 Summary of the Single-Chip Direct Conversion Receiver 226

References 227

iv

Symbols and Abbreviations

Symbols

amplitude, gain of one branch in image rejection receiversecond-order cross-modulation component at basebandthird-order cross-modulation component at basebanddc levelamplitude of the intermediate frequency signalamplitude of the second-order intermodulation productvoltage gain of a low noise amplifieramplitude of the local oscillator signalvoltage gain of a matching networkvoltage gain due to finite impedance levelsamplitude of the nth harmonic of a local oscillator signalamplitude of a radio frequency signalamplitudes of positive and negative radio frequency signalsdesired signal componentvoltage gainvoltage gain of a low noise amplifiervoltage gains of successive stagesgain scaling factors in active RC filterinput amplitudes in two-tone testgain of the other branch in image rejection receiverinformation bandwidtheffective noise bandwidthtotal radio bandwidth of a specific systemtransmission bandwidthspreading codescapacitor in the biasing networkon-chip capacitance between ground and supplycoupling capacitancepositive and negative coupling capacitancesdegeneration capacitancedecoupling capacitanceoff-chip capacitorsgate-source capacitancehold capacitancein-phase load capacitancequadrature-phase load capacitancecapacitance per unit area of the gate oxideparasitic capacitancecapacitance of a damped resonatoradditional sampling capacitorcapacitance to substratetotal capacitancebase-emitter capacitancecapacitors

v

control nodebalancing factordeterioration parameter for intersymbol interferencediameter of bondwireenergy per bitsampling noisefrequencynoise factorbit rate of the databandwidth of the desired channel at basebandblocking frequenciescenter frequency, cutoff frequencycutoff frequency of baseband filtercorner frequency of flicker noiseminimum channel spacingclock frequencynoise factor of device under testcutoff frequency of a highpass filterintermediate frequencyfirst and second intermediate frequenciesnoise factor of a low noise amplifierlocal oscillator frequencynoise factor of mth stageNyquist rate in samplingradio frequencyradio frequencies in two-tone testsampling frequency or ratesignal frequencyfrequency of a spurious componentnoise factor in subsamplingmaximum unity gain frequencynoise factor of the receiver chainoutput frequency of the transmitterupper limit of the signal bandnoise factors of successive stagesgate functionpower gaincoding gainimprovement in signal-to-noise ratio due to digital signal processingpower gain of a low noise amplifiergate function in mixingpositive and negative gate functions of commutating switchestransconductancetransconductances of positive and negative input stagesgain at the passband of the receivergain at the stopband of the receiverprocessing gainoutput conductancepower gains of successive stagestransfer functiontransfer function of a specific block

vi

impulse responsesinterference powercurrent matrixbalanced current in a two-portcollector currentsupply currentcollector currentsdrain currentdrain saturation currentemitter currentsinterference of the overhead channel from the own base stationsinterference in the CDMA reception due to cross-modulationinterference in the CDMA reception due to intersymbol interferenceinterference from non-CDMA transmissions or jammers at band of interestmodal current matrixin-band noise power in CDMA channelinterference from the traffic channels in other cells in CDMA systeminterference of the overhead channels from other near-by base stationsin-band interference of other CDMA traffic channels at the band of interestlowpass filtered negative output currentpositive and negative output currentslowpass filtered positive output currentinterference in the CDMA reception due to phase noiseinterference in the CDMA reception due to quantization noiseimplementation-oriented non-idealities at the received CDMA radio channelradio frequency currentsaturation currentsaturation currents of bipolar transistorstail current of a switching pairtail currentinterference in the CDMA reception from the transmitter leakageunbalanced current in a two-portdc parts of the collector currents in bipolar transistorsinput currents of a two-portinput compression pointintermediate frequencies in the receiver starting from the first IFsecond-order input intercept pointsingle-ended second-order input intercept pointthird-order input intercept pointthird-order input intercept points of successive stagesthird-order input intercept point at high signal levelspositive and negative inputsBoltzmann's constant, number of harmonic componentflicker noise factor, process and size parameter of a MOSFETinductance, length of gate in a MOSFETbondwire inductancecommon mode source inductancedegeneration inductanceemitter inductancegate inductanceinput inductance

vii

length of bondwireload inductanceinductance of a damped resonatorsource inductanceisolation between transmitter and input ports of the receiverinductorsmodulation index, number of bits, number of harmonic componentimplementation margin for digital algorithmsMOSFETsscaling factor, number of harmonic component, number of gate fingersincoming noise at the input of a analog-to-digital converternoise power of device under testinput noise powertotal input referred noise powerinternal noise power of the device or blockmeasured noise poweroutput noise powertotal phase noise power of the receiver in base stationtotal phase noise power of a receivertotal phase noise power of a transmitterquantization noisesubsampling ratiointernal noise power of spectrum analyzertotal number of traffic channels at the CDMA radio channelmaximum number of traffic channels at the CDMA radio channelthermal noise powerthermal noise floor of the transmitternoise power spectral densitynoise figurenoise figure of device under testtotal noise figure of the receivertotal noise figuremultiplication factor for the power, number of harmonic componentpower of the adjacent channelinput power of a blocking signalpower of a single traffic channel in CDMA transmissionpower dissipationprobability of bit errormultiplier matrixenvelope powerpower of the image frequency componentsecond- and third-order intermodulation productsinput referred second- and third-order intermodulation productsinput powermaximum acceptable input powerlocal oscillator powerpower of the lower sideband signalpower of the minimum detectable signaloutput powerpower at radio frequencypower at the sensitivity level of a receiver

viii

input referred power of a spurious componentpower of the upper sideband signalpower of the wanted signal componentsum termsmagnitude of electronic charge, number of harmonic componentmultiplier matrixquality factor of the input stage of a low noise amplifierbipolar transistorssum termsbipolar transistorsnumber of harmonic componentbase resistancebiasing resistancedecoupling resistancefeedback resistancegate resistanceinput resistanceseries resistance of a inductorload resistancepositive and negative load resistancesoutput resistanceparasitic resistancedamping resistance of a LC networksymbol rate, source resistanceswitch resistanceresistorssheet resistancepower spectral densitysignal at the input of a analog-to-digital convertercorrection factor for quantization noiseinput signal powerscattering parameter for differential matchingoutput signal powerpower spectral density of the radio frequency signalpower spectral density of the thermal noise in the systemspurious free dynamic range of the receiversignal-to-noise ratio at the output of a analog-to-digital convertersignal-to-noise ratio of the scrambled channelsignal-to-noise ratio of the correlated informationsignal-to-noise ratio at the inputminimum required signal-to-noise ratio for detection of a signalsignal-to-noise ratio at the outputsignal-to-quantization noise ratioscattering parameters of a two-port (reflection)scattering parameters of a two-port (transmission)absolute temperaturebit periodsymbol periodvoltage matrixbias voltagebase-emitter voltage

ix

dc-term of the base-emitter voltagebase-emitter voltagesbiasing voltagebalanced voltage in a two-portsupply voltagepositive and negative collector-emitter voltagescommon mode voltagedc voltagedc voltage at the outputsupply voltagedrain-source saturation voltage of a MOSFETgate-source voltagepositive in-phase input voltagenegative in-phase input voltageinput referred amplitude of second-order distortionoutput voltage of the third-order intermodulation productinput voltagedifferential input voltagepositive and negative input voltagesinput voltages of successive stagespositive input voltagenegative input voltagein-phase output voltagepositive in-phase output voltagenegative in-phase output voltagevoltage of the least significant bitvoltage of the local oscillator signalpositive and negative local oscillator voltagesmodal voltage matrixnoise voltageinput referred noise voltages of successive stagesoutput noise voltages of successive stagesnoise voltage of the sourceoverdrive voltageoutput voltageoutput voltage of the analog baseband processing blockpositive and negative output voltagesoutput voltages of successive stagespositive and negative output voltagesdc voltage of the virtual ground node in a differential pairpeak-to-peak voltagepositive quadrature-phase input voltagenegative quadrature-phase input voltagequadrature-phase output voltagepositive quadrature-phase output voltagenegative quadrature-phase output voltagemaximum input voltage of an analog-to-digital converter, reference voltagevoltage of the radio frequency signalpositive and negative radio frequency voltagesoutput voltages of the mixer coresource voltage

x

output voltage of a spurious tonethermal voltagethreshold voltageunbalanced voltage in a two-portparameter of a MOSFETinput voltages of a two-portvoltage of an amplitude envelopewidth of gate in a MOSFETbandwidth of the single sideband signalradio frequency input excitationinput excitationsampled input signalfrequency responsesoutput responseresponse of the hold functionresponse of the tracking functionimpedance matrixinput impedanceinput impedances of successive stagesload impedancemodal impedance matrixmodal z-parametersoutput impedances of successive stagessource impedanceinductance between supply railsz-parametersroll-off factor of a Nyquist filter, current gain factor, factorlow frequency leakage coefficient in the downconversioncoefficient of radio frequency leakage to local oscillator portnonlinear coefficientscoefficient of the fundamental tone in the presence of blockergain coefficient at basebandgain coefficient in downconversiongain coefficient at radio frequencynonlinear coefficients relative to fundamental toneenvelope coefficient at basebandsecond-order nonlinear coefficient at local oscillator portenvelope coefficient in downconversionenvelope coefficient at radio frequencytransconductance parameterphase error after the first downconversion in the image rejection receiverdenominator in z-to-S transformationgain error between quadrature branchesamplitude imbalance at radio frequencygain degradation from maximumdeviation from center frequency, frequency slotimbalance between transconductancessaturation current mismatchrelative input power compared to minimum detectable signalsecond- and third-order intermodulation products relative to fundamental

xi

relative resistor mismatchemitter resistance mismatchload resistance mismatchdeviation of the RC-product from nominaltime difference from nominalclock jitterthreshold voltage mismatchimbalance termdifference between duty cycles of positive and negative gate functionsdifference in phase error between two radio frequency tonesphase errors of differential input signalsphase error of the local oscillator signal in the direct conversion receiverdifference of the modulated tone from the carrierquantization noisephase responsenoise factor for MOSFETrelative pulse widths of positive and negative gate functionsduty cyclenominal duty cycle of gate functionsposivite and negative duty cycles of gate functionspermeabilitysurface mobility of the channel for the nMOS devicephase error of the first local oscillator signal in the image rejection receivertime delay, pulse widthmaximum passband group delay ripplegroup delaycarrier frequencyintermediate frequencyfrequency of the second-order intermodulation componentinput frequencylocal oscillator frequencylocal oscillator frequencies in the receiver starting from the front-endmodulation frequencyhighest frequency component of a modulated channel at basebandresonance frequencyradio frequencyradio frequencies in two-tone testresonancefrequencyexcitation frequencies in two-tone testfrequency exactly between input and local oscillator frequencies

Abbreviations

ac alternating currentA/D analog-to-digitalADC analog-to-digital converterAFC automatic frequency control

xii

AGC automatic gain controlAM amplitude modulationAMPS advanced mobile phone systemB bipolarBB basebandBC BiCMOSBDR blocking dynamic rangeBER bit error rateBFSK binary frequency shift keyingBiCMOS bipolar complementary metal oxide semiconductorBJT bipolar junction transistorBPSK binary phase-shift keyingBW bandwidthC CMOSC/A coarse acquisitionCDMA code division multiple accessCLCC ceramic leadless chip carrierCLK clockCMFB common mode feedbackCMOS complementary metal oxide semiconductorCMRR common mode rejection ratioC/N carrier-to-noise ratioCQFP ceramic quad flat packCR capacitor resistorCT-2 second generation cordless telephoneD/A digital-to-analogDAC digital-to-analog converterdc direct currentDCR direct conversion receiverDCS1800 digital communications systemDDS direct digital synthesizerDECT digital enhanced cordless telecommunicationsD-MESFET depletion-type MESFETDNL differential nonlinearityDSB double sidebandDS-CDMA direct sequence code division multiple accessDSP digital signal processingDS-SS direct sequence spread spectrumDUT device under testEGSM enhanced global system for mobile communicationsEHF extreme high frequenciesE-MESFET enhancement-type MESFETENOB effective number of bitsEVM error vector magnitudeFDD frequency division duplexingFDMA frequency division multiple accessFET field effect transistorFFT fast Fourier transformFH-CDMA frequency hopped code division multiple accessFH-SS frequency hopped spread spectrumFM frequency modulation

xiii

frequency shift keyinggallium arsenidegain bandwidthGaussian-filtered frequency shift keyingGaussian-filtered minimum shift keyingglobal positioning systemglobal system for mobile communicationshigh frequencieshighpass filterin-phaseintegrated circuitinput compression pointintermediate frequencyinput intercept pointintermodulation distortioninternational mobile telecommunications 2000integral nonlinearityimage rejection ratiointersymbol interferenceindustrial, scientific, medicalinterim standard 54interim standard 95inductor capacitorlow frequenciesleast mean squarelow-noise amplifierlocal oscillatorlowpass filterleast significant bitminimum detectable signalmetal semiconductor field effect transistormedium frequenciesmetal-insulator-metalmixermetal oxide semiconductormetal oxide semiconductor field effect transistormultiple phase shift keyingminimum shift keyingNorth American digital cellularnoise figuren-channel metal oxide semiconductor field effect transistorNordic mobile telephonenon-return-to-zerooutput compression pointoutput intercept pointoffset quadrature phase-shift keyingoversampling ratiopower amplifierpulse amplitude modulationprinted circuit boardpersonal digital cellular

xiv

FSKGaAsGBWGFSKGMSKGPSGSMHFHPFIICICPIFIIPIMDIMT-2000INLIRRISIISMIS-54IS-95LCLFLMSLNALOLPFLSBMDSMESFETMFMIMMIXMOSMOSFETMPSKMSKNADCNFnMOSNMTNRZOCPOIPOQPSKOSRPAPAMPCBPDC

probability distribution functionpersonal handy phone systemphase locked loopphase modulationp-channel metal oxide semiconductor field effect transistorpower spectral densityphase-shift keyingquadrature-phase, quality factorquadrature amplitude modulationquadrature phase-shift keyingresistor capacitorresistor capacitor polyphase networkresistor inductor capacitorradio frequencyroot raised cosine (filter)received signal strength indicatorswitched capacitorsource coupled FET logicspurious free dynamic rangesuper high frequenciessiliconsilicon germaniumsignal-to-noise and distortion ratiosignal-to-noise ratiosingle sidebandtime division duplexingtime division multiple accesstotal harmonic distortiontime hopped spread spectrumtuned radio frequencyultra high frequenciesuniversal mobile telecommunications systemvery high frequenciesvoltage-to-currentvery low frequenciesvery large scaled integrated circuitvariable spreading factorwide-band code division multiple accessvoltage controlled oscillatorwireless local area network

differentially encoded quadrature phase-shift keyingbinary frequency shift keyingthird generation partnership projectnumber

xv

PDFPHSPLLPMpMOSPSDPSKQQAMQPSKRCRC-PPRLCRFRRcosRSSISCSCFLSFDRSHFSiSiGeSNDRSNRSSBTDDTDMATHDTH-SSTRFUHFUMTSVHFV-IVLFVLSIVSFWCDMAVCOWLAN

2-FSK3GPP#

This page intentionally left blank

1 Introduction

Wireless communications is definitely one of the most significant driving forces in the analogelectronics. The large volume of the industry and new services coming to the market are settingnew demands also for traditional analog electronics. The main stream in the development of ICtechnologies has been focused on the digital signal processing and especially on the computerapplications. As a consequence the line widths of MOS processes have decreased, which meanssmaller sizes together with increased speed and processing capabilities. The improvement ofanalog processes has followed the evolution in the second wave. MOS technologies are alreadycapable of GHz-range analog signal processing while bipolar and BiCMOS processes are stilldominating the market and also benefiting from improved high-frequency properties. In analogapplications, the wireless communications have shown the direction in the development of ICprocesses. Although one ‘general’ technology for all applications would be desirable thedifferent characteristics of ideal analog and digital processes are difficult to combine. Anotherchallenge is the mixed-mode signal processing where sensitive analog blocks must tolerate thedistortion from digital rail-to-rail signals. These issues must be focused when the integrationlevel increases towards single-chip radios. The single-chip receiver is quite a conflictingdefinition. A chip connected directly to the antenna recovering the transmitted data bits fromthe received information is surely not feasible in the near future. At least some externalcomponents are needed. A more realistic question would be whether digital signal processingcould be done at all on the same chip with the sensitive analog RF front-end. More likely, amodern receiver should combine mixed-mode circuitry with RF as well as possible. Naturally,the minimized number of external components is a prerequisite.

Another dimension in the modern receiver design is the choice of the optimal architecture forthe implementation. The first century of the radio communications was mainly dominated bythe superheterodyne architecture since its invention over an eighty years ago. Although it is stillthe most sensitive and selective structure, the integration level is limited because of a number ofhigh-quality filters at the radio and intermediate frequencies. Therefore during the last ten yearsextensive research has taken place to achieve the corresponding performance with any otherpossible architecture more suitable for integration. The direct conversion receiver is a naturaland simple option. The improved IC technologies have actually brought direct conversion,which invention dates back to the same era with superheterodyne, as a serious candidate forcellular applications. However, the fundamental limitations do not allow as general designapproach as in the case of a superheterodyne receiver. The feasibility of direct conversion mustbe studied carefully in each system using parameters which are typically not considered whenthe overall system is specified. There are also some other possible structures, which will bediscussed in this book. The other trend in the evolution focuses towards a ‘digital’ receiver. Thedigital modulation methods have dominated the market since the GSM and other digitalcommunications systems became general. The next step would be the processing of a largernumber of channels digitally either at the baseband, at the intermediate or even at the radiofrequency. Hence, some analog nonidealities could be avoided. The increased speed andresolution requirements of digital signal processing and the interface to the analog circuitry arecritical issues in these direct digital or digital IF architectures. The scaling of the ICtechnologies constantly increases the speed and reduces the power consumption in the digitalcircuitry. The same benefit is however not easily achieved in analog circuits including theanalog-to-digital conversion.

In addition to the technological evolution and architectural aspects, the third main issue in thereceiver integration is the growing demand of wireless services. The wireless internet and

1

multimedia applications should be possible in the third generation systems. The increased andflexible data rates need different approaches than in the existing systems. The extension ofGSM to packet data services is one improvement. Another change will be the third generationsystems which use a wide-band CDMA radio channel. The trade-offs compared to narrow-bandsystems will be different. Those issues must be taken into account also in the radio design.

The focus of the book is on the design of wide-band radio receivers, and especially on the directconversion of the radio channel from the radio frequency down to the baseband. The mainemphasis is in the design of conventional direct conversion receivers, but also the limitations ofthe direct digital approach will be considered. Both issues are important and critical in thedevelopment of radio receivers for new and existing systems. The wide-band CDMA system forthird generation cellular communications, often called UMTS or WCDMA, is analyzed in detailin this book. However, the same principles are generally applicable to all CDMA systems andin most cases to all radio receivers.

This book is organized into five chapters. After the introduction, chapter 2 covers the basicbackground of the radio communications systems. The second part of the chapter focuses on thedesign parameters of the different analog blocks in a receiver at a fundamental level. Finally,the special requirements of wide-band CDMA receivers are analyzed.

Chapter 3 introduces different radio architectures and describes the performance of some recentIC implementations. The architectures include superheterodyne, direct conversion, low-IF,wide-band IF or image rejection, digital IF and direct digital receivers.

Detailed discussion about direct conversion receivers is given in chapter 4. First, system levelrequirements are introduced. Then, radio design and different functional blocks are described.The main emphasis is in the RF front-end circuitry. Separate sections are reserved for active andsubsampling mixers after the general considerations. At the end of the chapter the special issuesof single-chip receivers are dealt with followed by the comparison of reported direct conversionreceivers and RF front-ends.

Some IC implementations related to the topics of the book are presented in chapter 5. Asubsampling RF downconversion mixer is implemented with a digital GaAs MESFET process.A CMOS LNA and an interface to a subsampling mixer are realized for demonstrating ac-coupling methods and efficient resonator structures for the LNA load. The two last sectionscontain the design and experimental results of a direct conversion receiver for WCDMAapplications. The chipset and single-chip versions are presented separately. Both areimplemented using the same BiCMOS technology.

2

2 System Requirements for Radio Receivers in WirelessCommunications

The development of the mobile communications systems has come to the era when most of thesignal processing is performed digitally. The advantages of digital communications for currenttechnologies and requirements are evident. The wildest fortune-tellers are already proposing socalled direct digital front-ends for mobile communications. The radio architectures includingthe direct digital approach are discussed in the next chapter. The intention of this chapter is todescribe the signal environment and the most important phenomena, which must be consideredin the radio design. They are general requirements for all types of receivers in wirelesscommunications. Of course, the desired system and choice of the radio architecture havedifferent influence on these requirements. The emphasis of the text is to give a review of thewhole field, but concentrate especially on the specific issues in spread spectrumcommunications and their effects on the analog signal processing.

In this dissertation, the term radio receiver is designated for the traditional analog portion of thereceiver including the A/D converters. The digital core of the system is called as a digital signalprocessing block. Also, the term baseband is often used as describing only some digitalfunctions, and the whole analog part is called as radio frequency (RF) signal processing. This ismisleading or at least not a very precise expression. Hence, the analog receiver is distributed toRF, intermediate frequency (IF), baseband and A/D conversion blocks in this context.

2.1 Mobile Communications

All wireless systems operate in a troublesome environment of the electromagnetic radiation.The radio path itself has the strongest effect on the performance. The distance from thetransmitter, other transmitters and transmission conditions are variable parameters, whichcontinuously, and sometimes very rapidly, change the signals coming to the receiver. Antennatechnologies and digital estimation and detection techniques have been developed to tolerate thefading and multipath conditions in transmission. Even more sophisticated methods to maximizethe system performance will be adopted when the next generation of cellular systems will belaunched. Simultaneously, the complexity of the systems increases and their control becomesextremely difficult. Still the target is the same as in days of Marconi: To deliver informationeverywhere without any restrictions of wires. In the modern world, the efficiency and limitedamount of ‘cost-efficient’ radio spectrum forces to the strict control of the spectrum and to themethods maximizing the spectral efficiency in different systems. Partly therefore, the design ofa radio is and will be a challenge still over a hundred years after its invention.

A radio receiver selects a certain frequency band and detects the transmitted information at thatband from noise and other unwanted components shown in Figure 2.1. Radio spectrum isoccupied by different communications systems, which are divided to narrower radio channels.Each physical channel can contain one or several traffic channels depending on the multipleaccess method. The key issue in a radio receiver is to detect a weak traffic channel when otherchannels containing much more power are present. The antenna of the receiver has somefrequency selectivity and sometimes also directivity. Although its performance is important forthe whole receiver, the main function is to collect the electromagnetic information from arelatively wide band compared to a certain system. The actual frequency selection is performedlater in the receiver. Also, the other parameters described in this chapter are typically specified

3

for the receiver without an antenna for two reasons. First, they are much more difficult tomeasure and define when the results depend on the air interface. Second, the antenna has onlylittle effect on those parameters or the performance of the antenna can be specified separately.The antenna must be matched typically to impedance level, but that is the only parameterneeded for the interface to the receiver. The development of the adaptive antenna arrays andbeam forming techniques are changing this ideology. However, these issues concern mainly onthe digital signal processing part of the receiver, and the analog portion can be specified asearlier.

The wireless communications are today dominated by the different digital systems. Onlybroadcasting, television, and some older cellular or cordless systems still use analogmodulations. The advantage of coding the information efficiently and with high quality to theradio channel has promoted the digital applications, and enabled to transmit also other servicesthan voice in cellular systems. The block diagram of the transmitter and receiver are shown inFigure 2.2. The input data stream is first coded and interleaved in the transmitter. The formercodes each bit into a longer bit sequence, and the latter reorganizes the data stream to avoid theloss of two successive bits. Both techniques protect the transmission against the multipathfading in the radio channel. They are purely digital operations and improve the signal-to-noiseratio or tolerance against fading in the reception. Next, the signal is modulated and the digitalpulses are shaped or rounded in the filter in order to limit the output spectrum. Although themodulation, and typically also the pulse shaping, are digital operations, they must be consideredwhen receiver architecture and specifications are defined. The topic will be discussed later inthis chapter, and also in connection with the direct conversion receiver architecture in thefollowing chapters. Finally, the data is upconverted to the desired radio frequency, amplifiedand filtered. The duplex-filter prevents the transmitter power from leaking and compressing the

4

receiver. The upconversion, filtering and amplification can be distributed to several steps.However, the transmitter topologies are not included in this dissertation, and the simplifiedblock diagram is sufficient to describe the behavior.

The receiver selects the desired radio system with a duplex-filter. The receiver portion of theduplex-filter is often called as a preselection filter according to its function. This is actually thegeneral expression, because sometimes the transmitter can be isolated with a switch or thereceiver is a stand-alone unit. For example, in the positioning systems, like GPS, only thereceiver is portable, and hence duplexing is not required. Immediately after the first filtering,the signal is amplified to prevent the noise of the successive blocks from deteriorating thereception. Practically all high-performance radio systems require a low-noise amplifier (LNA)in the front-end. The signal is downconverted in one or several mixers depending on thearchitecture, and the desired channel is filtered before digital demodulation, deinterleaving, anddecoding. The channel filtering is performed at some intermediate frequency, at baseband orgradually along the chain, and it can be analog, digital or a hybrid of those. The alternatives ofthe channel filtering will be discussed later in detail.

The rapidly improved digital technologies and signal processing techniques allow morecomplex functions and applications in wireless terminals. The digital communication systemsare evolving quickly away from pure audio services to full multimedia centers. The traditionalreceiver is sometimes called only as a part of the radio interface in the system. It should bealmost negligible, and the interest is in the coding of efficient algorithms to improve theperformance and new applications for cellular systems. However, this ‘black box’ i.e. theanalog receiver still makes it possible to detect weak signals and relax the digital processing bylimiting the huge dynamic requirements of the cellular systems before the transformation to thedigital domain. The large harmonic content of digital signals after conversion to the analogdomain and strict requirements of spectral purity in the transmission call for an efficient analogprocessing unit both in the transmitter and in the receiver. Although the power consumption ofthe digital circuits is decreasing more rapidly than in analog processing, the reduced supplyvoltage limits the dynamic range in analog-to-digital conversion, and part of the advantage is

5

lost due to increased parallel processing. The key analog functions will be needed in the future,but partitioning of different functions between the analog and digital domain can be changed.

2.1.1 Wireless Systems

The wireless systems vary from broadcast and television transmission to cellular telephones andwireless local area networks (WLAN). The coverage area or in cellular systems the cell size hasreduced when personal messaging and rising data rates have been adopted. The individual needsand different services mean that the capacity must be shared to small units with variousmethods. The trend is towards the terminals, which can utilize different services and frequencyranges. The services can be divided at least to cellular phones, cordless phones, pagers,positioning systems and local area data networks. The cellular phones are the market drivers,but currently they provide not only voice services. Data services are increasing for example inGSM, and GPS-positioning will be installed to the same terminal quite soon. Finally, the thirdgeneration systems will try to combine the voice and different multimedia services directlyunder the same platform. The harmonization of the final specifications is still under discussionin the Third Generation Partnership Project (3GPP). The system uses direct sequence spreadspectrum multiple access. Often, the system is called Universal Mobile TelecommunicationsSystem (UMTS), which has been actually the name for the European proposal. Table 2.1collects some examples of the current wireless systems and different proposals for thirdgeneration systems are given in Table 2.2. For example, the chip rate of WCDMA has beenchanged later to 3.84 Mcps.

6

7

2.2 Multiple Access Methods and Duplexing

The multiple access method defines how the information in a single traffic channel is organizedwith respect to the other transmitted channels at the same band or elsewhere. The traffic channelmeans here the information of a single connection between two users in the system. Incommunications terminology, the traffic channel is normally called as a physical channel,which can contain one or more separate traffic channels. However, the traffic channel is a moredescriptive term in this context to describe actually a physical channel and it is used later in thismeaning. The multiple access gives a frame for the radio design, and it has a strong influenceon the choice of the radio architecture and on the specification of the analog receiver. In thissection, the different methods are compared when a fixed amount of information is transmitted,and also when flexible data rates are required. The multiple access can be done in thefrequency, time or code domain, and the different principles are illustrated in Figure 2.3. Thealternatives of the duplexing between the transmission and reception are briefly discussed in theend of this section.

8

2.2.1 Frequency Division Multiple Access

Frequency division multiple access (FDMA) is the basic form of the multi-band radiocommunications. The band is divided only to narrow frequency slots, and every transmitter-receiver pair has its own designated band. Pure FDMA is still used in broadcast and TVtransmission, for example. In digital cellular communications, tens or hundreds of users mustoperate in a relatively small frequency band. It would require very narrow passbands and sharptransition bands for the channel filters if every unit has an own frequency slot. The capacity of atraffic channel could be increased only if several adjacent frequency slots are reserved. Thiswould require reconfiguration of the hardware. In digital communications, the system would bealso very sensitive to fading. It is not either practical to keep the whole cellular band in onesystem as a single frequency slot, and hence the FDMA is typically at the background of otheraccess methods. The capacity of a radio channel, which is practical for implementations, can bedivided to several users either in the time or code domain.

2.2.2 Time Division Multiple Access

In time division multiple access (TDMA), each frequency channel is divided into time slots, andevery nth slot is reserved for a single traffic channel. For example in GSM, a 200 kHz radiochannel consists of eight time slots. Hence, every frequency channel can contain eight differenttransmissions, which relaxes the frequency allocation and re-use. In a TDMA system, thesynchronization of different mobile transmitters at a single carrier is required to prevent thetraffic channels from overlapping in time. There are however transients in the power level of thereception band all the time due to the switching of the TDMA channels. They may occur alsoduring the received burst because the different radio channels are not necessarily synchronized.This must be taken into account in the design of a receiver. In a TDMA system, the availablecapacity for a single user is defined well, but limited to a single time slot at a certain band. Thecapacity can be increased either when more than one slot is reserved for a single user or byimproving the efficiency of the data transfer. These methods are adopted, for example, incellular specifications including high data rate extensions for the GSM, which will come tomarket soon. However, the signal must be a certain amount above the noise and distortion at thereception band, and during the transmission no other traffic channel lies at that frequencysimultaneously.

2.2.3 Code Division Multiple Access

The code division multiple access (CDMA) systems are based on the pseudorandom sequencesof orthogonal codes. The code can be either a digital bit stream or a frequency pattern. Theformer method is called direct sequence spread spectrum (DS-SS), and the latter frequencyhopped spread spectrum (FH-SS). Also, time-hopping (TH-SS) is a possible coding method.Here, the discussion concentrates to the direct sequence, because it will be used in the thirdgeneration cellular systems and the integrated circuits presented later are designed for thatapplication. The basic principle of the frequency hopping is explained in the end of thissubsection. The time-hopping approach is rarely used and therefore not discussed in detail.

The CDMA principle relies on the set of known codes, which can be generated withcontrollable and relatively easy methods. These pseudorandom sequences resemble digital noiseto each other, and in the analog domain they have sinc-type of spectrum, which is defined bythe modulation and pulse shaping filter of the transmitter. The orthogonality between the codes

9

means that they have ideally no correlation with each other, and therefore other code channelsexcept the correct one behave like white noise at the reception band. When specifying theanalog functions of the receiver, it is appropriate to assume that there is no cross-correlationbetween the codes at any condition.

The principle of the direct sequence is shown in Figure 2.4. The transmitted data is multipliedwith the spreading code i.e. the pseudorandom sequence, which is at a higher data rate than theinformation. The ratio between the transmission bandwidth, which is inversely proportional toperiod of each pseudorandom symbol, and information bandwidth is called either spreadingfactor or processing gain, It is defined in [5] as

where and are the transmission and information bandwidths, respectively. The scramblingof the data spreads the information over a much wider band than necessary. In the receiver, theradio channel is multiplied again with the same code. The transmitted data correlates with thecode, and the narrow-band information is recovered. All uncorrelated information i.e. noise andother code channels are scrambled again, but their spectral response remains unchanged.Therefore the processing gain describes the improvement of the signal-to-noise ratio in thedespreading process as

where is the signal-to-noise ratio of the correlated information after the despreading andis the signal-to-noise ratio of the scrambled channel to any other signal, noise or

distortion at the transmission band. It should be notified that after the despreading, thedescribes only the signal-to-noise ratio at the narrow signal band, and noise outside the bandmust be filtered out. This property makes it possible to place different channels at the samefrequency band and detect the information, which is buried in the noise and other codechannels. To distinguish the information and spreading codes, the units of the information andthe spreading sequence are called a bit and a chip, respectively. The CDMA systems can bedesigned less sensitive to multipath interference, and they have tolerance against narrow-bandinterferers [1]. The latter means that any narrow-band interferer is scrambled in thedespreading. Hence, it can be considered as noise in the detection at least in the simplifiedanalysis, which is typically an appropriate first-order estimate. The military CDMA systemsalso benefit from the capability to transmit information below the thermal noise floor when theexistence of the transmission is difficult to detect by the enemy. Also, it is more difficult to jamthe opponents radio connections.

The chip rate is typically fixed, which defines a certain bandwidth of the radio channel. Thedata rate does not depend only from that bandwidth. By changing the bit rate, the processinggain varies but the signal at the radio band remains unchanged if we consider only the spectralbehavior. Hence, no reconfiguration of the hardware is required when variable data rates aretransmitted. Therefore, it is straightforward to provide services at different data rates in a DS-CDMA system. However, the number of orthogonal codes is limited, and the jamming has alsoeffect on the maximum number of traffic channels at the same band. The information at a highdata rate reserves several code sequences, and due to the smaller processing gain, a largerpower is required for the transmission at equal conditions.

10

In spread spectrum communications, the required output power of the transmitter does notdepend only on the distance and conditions at the radio path. The existence of other transmittersat the same band requires careful and continuous control of all power levels simultaneously.The power of each traffic channel should be minimized to avoid the jamming of the otherchannels. On the other hand, the connection must be insensitive to varying conditions, and newchannels at the band. Therefore, some jamming margin is always required, and the powercompetition of different transmitters should be avoided. Compared to the other access methods,the control of a CDMA system is dynamic and much more difficult to administrate. The powercontrol of the CDMA is the key element for the functionality and spectral efficiency of thesystem. At the system level the control is performed digitally, and the gain of the analog blocksboth in the transmitter and in the receiver are tuned according to that scheme. The properties ofthe spread spectrum communications with respect to the radio receiver design are discussed atthe end of this chapter.

In the frequency hopped CDMA communications, the spreading of the information isperformed with pseudorandom jumps of the transmission frequency inside the total systemband. One or more bits are transmitted at a certain radio channel, and then the oscillator movesthe transmission to another frequency. The time-domain frequency pattern of the oscillatorcorresponds to the bit code in the direct sequence CDMA. In a frequency hopped system, thebandwidth of a radio channel can be narrower than in the direct sequence, but the jumpingbetween the frequencies set strict requirements for the frequency synthesis. In principle, themulti-carrier approach can be used with both CDMA techniques to increase the capacity, but itrequires also extra hardware. In TH-SS, the spreading in the time domain is performed withrandom changes of the time slots in the transmission. However, in the conditions of multipletransmissions at the same band, the time hopping requires very efficient error correction andinterleaving schemes [1],

11

2.2.4 Duplexing

In all two-way communications with only one antenna, which is practically always the case inmobile terminals, the transmitter and receiver must be isolated from each other. Otherwise, theoutput power of the transmitter would saturate the sensitive receiver. Depending on the systemrequirements the duplexing is based either on frequency or time division.

The frequency division duplexing (FDD) means that the transmission and reception areaccomplished at different frequencies. This is done with a duplex filter, which has differenttransfer functions from the antenna terminal to the receiver and transmitter. FDD is typicallyused in cellular systems, because the filter attenuates also the transmitted powers from othernear-by terminals [4], and the control of the system is easier when the forward and reverse pathsare at different frequencies. High operation frequency and a relatively small space between thetransmission and reception bands restrict the available technologies for the implementations.The problems for the receiver design are also the limited isolation between the transmitter andreceiver ports and the inevitable loss at the passband of the filter.

The cordless phones, like DECT, use often time division duplexing (TDD). The transmissionand reception are at the same band but they do not overlap in time. In that case, a switch insteadof a filter is a sufficient component to split the two paths. Because, the transmission andreception are not enabled at the same time, the transmitter power does not corrupt the reception.In GSM, both FDD and TDD are used simultaneously. However, a duplex-filter is typicallyused in mobile terminals instead of a switch, due to the better immunity against signals fromother mobiles.

2.3 Digital Moduation

The increased capacity at a certain frequency band and a better accuracy in the presence ofnoise and distortion have changed the cellular communications from analog to digital since theearly 1990s. The characteristics, and especially the capacity requirements, of the differentsystems define how efficient modulation is needed. The spectral efficiency is typicallyimproved when complexity of the modulation increases. Except of the stricter requirements indigital signal processing and its timing, the design of the analog receiver becomes also morecomplicated. This section covers a brief introduction to digital modulations and their properties,which have effect on the analog circuit design. The main focus will be in the Quadrature PhaseShift Keying (QPSK) because it will be used in the traffic channels of the WCDMA systems.Some other methods are selected to introduce different aspects in their behavior. In thefollowing chapters, some properties of the modulations are discussed with respect to thereceiver architectures and their specifications.

The modulation codes the information at the radio carrier. In the case of one traffic channel at asingle frequency carrier in one time slot, the modulation in the radio channel is defined only bythe transmitted information, which is under reception. This is valid for other multiple accessmethods except for the CDMA. In the spread-spectrum communications, a certain trafficchannel has always a specified modulation, but each radio channel contains several trafficchannels, which can have non-equal powers. Hence, the received radio channel has differentmodulation characteristics than the traffic channel of interest, and former has actually moreinfluence on the analog performance. The complete analysis would require the knowledge fromthe statistical properties of the total radio channel rather than an analysis of a single modulation.However, the applied modulation can be used to model basic characteristics and estimate theworst case conditions.

12

The digital modulations are divided into phase and frequency modulations. Some of theadvanced types have also amplitude shifts to improve the spectral efficiency. The shape of thespectrum and amplitude characteristics must be taken into account in the analog design. Themodulation can contain amplitude-modulated (AM) term even though the detection is not basedon the amplitude shifts. Also, the angle of the smallest phase shift defines accuracyrequirements to some components. The modulation can transmit one or more bits at the sametime. The simultaneous bits form a symbol. Most of the modern cellular systems have two bitsin one symbol, which is a compromise between the spectral efficiency and accuracyrequirements. In that case, the capacity in the radio channel is doubled compared to the one bitcase. The quadrature modulator and two constellation diagrams are shown in Figure 2.5. Theconstellation describes the location of the symbols i.e. bit pairs with respect to the amplitudeand phase shifts. The in-phase (I) and quadrature-phase (Q) bits are distinguished with a 90°angle at RF. If the symbols are organized in the way that only I- or Q-bit can change at a time,the constellation never crosses the origin and amplitude is almost constant. Hence, theamplitude-modulated term is very small in the modulation with a constant envelope. The twoforbidden shifts in the constellation decrease the spectral efficiency or at least complicate thechannel coding. A quadrature modulation with a variable envelope allows all bit transitions atthe cost of a relatively large AM-term. If the absolute phase of the constellation must be knownin the receiver, the system has coherent detection. However, in the case of oversampling, theclock recovery can be done digitally, and a non-coherent analog part of the receiver is possible.

Before the modulator the bits are filtered to smooth the bit transitions. Without the pulsefiltering the spectrum of the modulation has the shape of a sinc-function with relatively highside lobes. The pulse shaping filter removes the side lobes, which would otherwise disturb weakadjacent channels. It has also effect on the AM-term and on the intersymbol interference (ISI),which will be discussed later in this chapter.

13

2.3.1 Binary Phase Shift Keying (BPSK)

In the digital phase modulations the phase angle of the carrier changes according to thetransmitted symbol. BPSK is the simplest form of the phase modulation. The symbol has onlyone bit, which rotates the phase by 180° when the input changes. The BPSK signal can begenerated in a mixer when the data is multiplied with the square wave at the carrier frequencyas in Figure 2.6. The constellation crosses always the origin when the data changes. This meansa large AM-component in the modulation and sharp transitions, which produce a wide spectrumrelative to the bit rate. For a non-return-to-zero (NRZ) data, the input changes randomlybetween the two logic levels. The random fashion in the signal means that instead of discretelines as is the case with periodical signals, the spectrum smoothly follows the sinc-shape. Thepower spectral density of the NRZ baseband signal is given as [2]

where A is the amplitude of the signal and the bit period. The bit period is inverselyproportional to the bit rate At the carrier frequency the power spectral density is

where is the carrier frequency. Only the fundamental mixing product is included in theequation. The other replicas will be filtered out in the transmitter. The power spectral density ofan unfiltered BPSK signal is presented in Figure 2.7.

14

2.3.2 Quadrature Phase Shift Keying (QPSK)

In the QPSK, two bits are modulated to the same carrier simultaneously as presented in Figure2.5. The data rate per symbol is doubled, and therefore the QPSK spectrum is condensed to halfof the BPSK when the same amount of data is transmitted as seen in Figure 2.8. All transitionsin the constellation are possible. Hence, the envelope is not constant, but the AM-componentcompared to the BPSK is much smaller, because the 90° phase shifts produce less amplitudedistortion than 180° transitions.

The performance of the modulation is evaluated with the probability of an error in the detection.The required energy per bit versus the noise power spectral density is compared to theprobability of a bit error The characteristic curves can be plotted for different modulationsbased on the statistical analysis. It is possible to estimate the effects of the different unwanted

15

properties when they are compared to the ideal curve. The is actually the same bothfor BPSK and QPSK modulations. The simulated curve is given in Figure 2.9. In wirelesscommunications the required bit error rate (BER) for speech transmission is typically i.e.one error in one thousand transmitted bits. In that case the must be about 6.7 dB for theQPSK. However, that performance is not sufficient for the data transmission, where the BERmust be in the order of in wireless connections. The BER is actually defined after decodingof the transmission. The channel coding has effect on the required For example, inWCDMA systems different coding methods will be used for speech and data transmissions. Asdescribed later, the coding can be estimated as a gain parameter like the processing gain whenanalog performance is calculated, and is useful also when certain parameters inanalog implementations are simulated. Unfortunately, in continuous-time systems the BERsimulations are heavy and time consuming, and therefore simplified behavioral models must beoften used.

In analog circuit design instead of the the signal-to-noise ratio (SNR) is a practicalmeasure when performance is estimated. The relation between these two is given in

where S/N is the signal-to-noise ratio, is the effective noise bandwidth of the receiver, andis the bit rate of the data. Theoretically, is equal to SNR when noise bandwidth is thesame as the data rate. Although the noise bandwidth is often somehow wider than the bit rate inthe implementation, it is an appropriate estimate for the hand calculations, which can beconfirmed with more accurate system simulations.

The pulse shaping filter removes most of the energy from the side lobes of the QPSKmodulation in practical systems to minimize the channel bandwidths and distances betweenadjacent channels. Simulated examples of unfiltered and filtered QPSK spectrum are given inFigure 2.10. Except of improving the spectral efficiency, the filter smooth out sharp transitionsin the time domain, which increases amplitude variations of the signal envelope [4]. Thelimiting amplifiers, which are desired due to their better efficiency as power amplifiers, tend toreduce the amplitude variations and hence destroy the band limitation. This is called spectral

16

regrowth. Therefore a linear power amplifier is typically needed in the systems with variableenvelopes. On the other hand, the small AM content is beneficial in some receiver architectures.

The spectral efficiency of a PSK modulation can be increased when the unit circle is dividedinto more than four possible sections. The angle between constellation points reduces, andhence a better phase accuracy is required. 8-PSK and higher order multiple phase shift keying(MPSK) modulations require theoretically larger for a certain than BPSK andQPSK.

2.3.3 Frequency Shift Keying (FSK)

Instead of abrupt changes between fixed phase angles, the bits can be coded as linear phaseshifts. Because frequency is the time derivative of the phase, the linear change in the phasemeans a constant frequency. Hence, the methods based on that principle are called digitalfrequency modulations. In the simplest form of FSK i.e. binary FSK (BFSK or 2-FSK), the 1and 0 bits have their designated continuous phase shifts, which modulate the carrier frequency.When the value of the bit changes, the sign of the phase variation is inverted. At the output ofthe modulator this can be seen as a change in the carrier frequency. However, the phase shift atthe carrier is smooth and the amplitude does not change. Hence, the envelope of an FSKmodulation is constant. If a symbol includes more than one bit, each symbol has a designatedfrequency around the carrier. The frequency spurs occur at the modulation frequencies aroundthe carrier. In addition to a constant envelope, the small power spectral density around thecarrier frequency compared to the spurs is of importance in the design of a FSK receiver.Frequency shift keying is the digital counterpart of the analog frequency modulation (FM). Thedifference is that the input of the modulator is binary data instead of analog information. TheBFSK is used for example in paging systems, but its efficiency is not sufficient for the high-performance cellular communications.

17

2.3.4 Gaussian-Filtered Minimum Shift Keying (GMSK)

The minimum shift keying modulations are actually hybrids of phase and frequencymodulations. They do not have narrow frequency spurs at the spectrum or rapid changes inphase. The carrier of a MSK signal changes phase gradually by during one bit period. Thephase shift is linear and advances by 90° if the bit is 1. When the bit is 0, the phase returns backby the same amount. The 90° phase shift is organized in the modulator by delaying the Q-databy a half symbol period compared to the I-data. Hence, the I- and Q-bits are never changingsimultaneously, and the modulation has a constant envelope.

Compared to QPSK, the MSK has a wider output spectrum for the same data rate. To limit thespectrum without destroying the good time domain response, a Gaussian filter can be adoptedfor pulse shaping. A reasonable Gaussian filter does not have the best possible stop bandattenuation, but the filtered signal is not very susceptible to spectral regrowth or intersymbolinterference either. Due to the compromising properties, the Gaussian-filtered Minimum ShiftKeying (GMSK) is used in GSM.

2.3.5 Quadrature Amplitude Modulation (QAM)

To increase the spectral efficiency, the modulations with more than two bits per symbol can beused. In PSK and MSK modulations, the phase differences at the unit circle become smaller,which increases the susceptibility to errors due to noise and distortion. A hybrid of phase andamplitude modulations is an alternative method. The quadrature amplitude modulations dividethe constellation points evenly, and every transition is possible. Hence, they are very efficient.The constellation for a 16-QAM modulation, which carries 4 bits in a symbol, is shown inFigure 2.11. QPSK is actually the same as 4-QAM. The complexity and accuracy requirementsof the hardware limit the use of QAM, and if the distance between adjacent points is constant,the transmission power of the higher-order QAM modulations is larger. Hence, the spectralefficiency trades off with the power. In CDMA communications, each radio channel containsnon-equal powers at different phases from various transmitters. Hence, the received informationbehaves more like multi-symbol QAM rather than a QPSK signal before the despreading.

18

2.3.6 DS-CDMA QPSK Transmitter

A block diagram of the QPSK direct conversion transmitter for direct sequence spread spectrumcommunications is given in Figure 2.12. The input data is split into parallel branches. Both I-and Q-branches have different spreading code sequences. This is a very simplified version ofthe actual CDMA communications systems. However, it is a sufficient model when the analogperformance of the receiver is estimated. Because the interest is in the receiverimplementations, the transmitter performance is assumed ideal including a linear poweramplifier. Figure 2.12 does not indicate the border between analog and digital signal processing.Typically, the pulse shaping filter implementation is digital, which requires an analog post-filtering after the DA-conversion to remove the digital replicas at the harmonics of the clockfrequency. Alternatively, the upconversion of the transmitted signal can be performed in severalsteps or the signal can be translated before the D/A conversion directly to some intermediatefrequency with a direct digital synthesizer (DDS). Some parameters concerning the modulationand pulse shaping will be discussed later.

2.4 Design Parameters for Radio Receivers

The function of a radio receiver is to detect the desired signal among noise and other sources ofelectromagnetic radiation. Here, the discussion will be limited inside any specificcommunications system. It is assumed that the preselection filter removes the power outside thesystem band completely. This assumption is necessary to restrict the environment. It is alsovalid if the known large out-of-band interferers are considered separately. In the tranceivers, theparasitic coupling of the transmitted power to the receiver input, which lies relatively close tothe reception band, is one of the most harmful sources of unwanted power. It must beremembered that within one system there are typically more than one operator controlling thetraffic. Therefore strict rules must be obeyed to maximize the traffic at the system band.

Typically, the specifications of different communications systems give fixed tests tocharacterize the functionality of the receiver at different conditions. The basic parameters of thereceiver can be calculated or simulated straightforwardly giving the block specifications for thecircuit designer. The intention of this section is to characterize different nonidealities at a moregeneral level with respect to the system behavior for two reasons. First, the final specifications

19

for the third generation cellular systems are still under negotiations, and the prototype design isbased on a rough frame of some basic properties. Second, traditionally the interferers arelocated at different radio channels, but in the CDMA communications the other in-band trafficchannels have also effect on the design of the analog radio part. The numerical examples in thissection are based on the measured performance of the WCDMA prototype receivers, which willbe described later in detail.

Depending on the distance to the transmitter and conditions at the radio path, the power of thedesired channel varies at the input of the receiver. The ratio between the highest and thesmallest possible input power can be in the order of 100 dB. The total dynamic range of thereceiver can be defined as described in Figure 2.13. However, as large variations in powerlevels as that are not allowed instantaneously. The instantaneous dynamic range describes theworst case conditions at a certain moment. Typically, the instantaneous dynamic range isspecified close to the sensitivity level of the receiver, but occasionally there are specificationsfor higher input power levels as well. There are several characteristics, which complicategeneral analysis. First, the instantaneous dynamic range does not depend only on the ratio of thelargest possible interferer to the desired channel but on the several different parameters whichconcern filtering and linearity. Besides that different radio architectures have differentlimitations. Second, the instantaneous dynamic range is hardly the same at the different powerlevels of the desired channel in cellular systems. For example when the mobile terminal is farfrom the base station, there can be much stronger signals from other base stations. On the otherhand, the own base station can transmit to another distant terminal with much higher powerwhen operating close to it. Third, at low power levels noise and other channels limit togetherthe dynamic range while at higher power levels the unwanted channels produce much strongerinterferers. Hence, the dynamic range of the receiver is a combination of controllableparameters and unavoidable characteristics of the system, which vary as a function of time. Forexample, the total dynamic range is typically optimized with an adjustable gain in the receiver.Then, the instantaneous dynamic range is defined for short time periods, which are determinedby the speed and efficiency of the system gain control.

2.4.1 Sensitivity

Sensitivity is the basic parameter in the radio design. It defines the minimum signal level, whichcan be detected, when there are not any interferers present and the performance is limited by thenoise. The total noise power is a combination of the thermal noise within the channel bandwidth

20

and the internal noise of the receiver. The noise factor of the receiver defines the ratio of theinternal noise to the thermal noise at the input.

Here, and are the signal-to-noise ratios at the input and output of the receiver,respectively. G is the total gain of the receiver and the internal noise of the receiver referredto the input. The noise factor in decibels is called the noise figure (NF). The thermal noise at theinput is

where k is the Boltzman’s constant T is the temperature in Kelvins, and isthe noise bandwidth of the channel selection filter. At the room temperature of 290 K, thethermal noise in decibels is

In the receiver design, the conditions at the receiver input define the overall systemperformance. The internal partitioning is only a method to meet these requirements. Therefore itis practical to refer all parameters to the input. It can be seen from Equation (2.6) that the inputreferred noise floor can be given in decibels as

In digital communications systems, the Minimum Detectable Signal (MDS) i.e. the sensitivityof the receiver is the smallest possible signal, which has a certain bit error rate (BER) in thepresence of noise. For example in QPSK, the typical BER specification of is achieved with

of 6.7 dB as shown earlier in Figure 2.9. can be approximated equal to SNR, whichis often called the carrier-to-noise ratio (C/N) in communications. Hence, the minimum SNRdepends strongly on the required BER and the used modulation. The minimum detectable signalcan be given in decibels as

where is the minimum signal-to-noise ratio for a certain BER. The parameterdescribes the improvement of the system performance due to the digital signal processing(DSP) methods like convolutional coding or interleaving. Also the processing gain in theCDMA systems is included in the The simplified description of the DSP functions isshown in Figure 2.14. Hence, the improvement of the DSP can be given as

21

where presents all digital functions except of despreading, and is the requiredimplementation margin for digital algorithms. Combining Equations (2.9), (2.10) and (2.11) thesensitivity of the receiver can be given as

The effect of the convolutional coding can be a couple of decibels, for example [6]. Both thecoding gain and implementation margin are not related to the analog processing, and it is notpossible to estimate the effect without the knowledge of the particular DSP architecture andsignaling conditions, which are not discussed here. Therefore they are neglected when theperformance is evaluated. In the CDMA systems, the processing gain can be in the order of tensof decibels, and a weak desired signal is buried totally below the noise. It must be taken intoaccount every time in the system calculations and simulations. With other multiple accessmethods the processing gain is always unity. Figure 2.15 describes the sensitivity in twodifferent cases. The input signal is presented in the left, the amplified output signal in themiddle, and finally the input referred performance of the receiver in the right.

22

The noise contribution of different blocks to the total noise factor of the receiver is given in theFriis’ formula [7]:

where are the noise factors of the successive blocks from the front-end of the receiver,and are their power gains. Because the noise contribution of each block is divided bythe preceding gain when referred to input, the noise figure requirements are relaxed in the back-end of the chain. The noise performance must be considered typically only close to thesensitivity level. In principle, it is possible to decrease the gain and simultaneously increase thenoise figure in the front-end when the input power rises. However, such situations should beavoided in the radio system design, because other parameters dominate the performance, andthe optimized noise figure does not necessarily give significant advantage in the powerconsumption or overall performance.

The Friis’ formula is defined for the available signal and noise powers. However, in theintegrated circuit design the power-matched interfaces are often not necessary. They arepractically needed only in the external connections. For example, the interfaces to the off-chipfilters, which require certain characteristic input and output impedances to maintain the shape ofthe transfer function, must be matched carefully. Instead, the distances between the on-chipblocks are so short at the 1-2 GHz frequency range compared to the wavelength that thematching is not necessary and the wires can be modeled with lumped elements. Also, theintegrated filters can be designed to an appropriate impedance level. The signal is typicallytransferred in voltage mode, and in the ideal case the zero impedance source drives directlyinfinite impedance. Therefore, the conversion gains and noise levels should be defined withvoltages and impedance levels rather than power throughout the receiver. The cascaded stagesof the receiver with arbitrary input and output impedances are shown in Figure 2.16. In thefollowing analysis, it must be taken into account that it is only valid when the noise componentsfollow the gain behavior if the impedance levels are changed. Especially, the noise matching inthe RF circuits limits the validity of the analysis to the impedance levels, which are close to thepoint where the noise is defined. Therefore, the noise of each individual block should bedefined with the source impedance, which corresponds to the output of the preceding stage.However, if the assumption is valid, the loss in the interface is almostinsignificant in this approximation.

23

The maximum voltage gain of each stage is given to the open load as

where and are the input and output voltages of the mth stage, respectively. It is notedthat the voltage gain is equal to the square root of the available power gain, if the bothinterfaces are matched to the same characteristic impedance. If the input and output levels aredifferent but still matched the square of the voltage gain must be multiplied by to getthe corresponding power gain. In the radio receiver, the circuits in the back-end of the receiverhave typically higher input impedances to reduce the current drive to the load. Therefore, thepower gain is much smaller than the voltage gain, which actually defines the performance. Itshould be also noticed that the impedance values are real and independent of the frequency inthe simplified notation. Especially in RF design, the amount of mismatch at the frequency ofinterest should be defined more accurately with reflection coefficient or scattering parameters,and transform the scalar value to impedance mismatch given below. The interfaces between thestages degrade the maximum voltage gain according to

where and are the output and input impedances of the cascaded stages. The noisefactor of an individual stage can be calculated to the open load from Equation (2.6) as:

where and are the total signal and noise voltages at the output, and are the signalsource and the noise from the source resistance, and is the internal noise of the blockreferred to input. If both the input and output are matched, Equation (2.16) is equal to thecorresponding noise factor using power quantities. The last expression in Equation (2.16) ispractical in the simulations because the total noise power and voltage gain from the source tothe output can be defined directly. In the matched conditions is 0.5, but it will depend onthe impedance mismatch as given in Equation (2.15). However, the mismatch reduces theamplified noise from the source to the output accordingly, but the input referred noise of theblock is independent of the mismatch as defined earlier. Therefore Equation (2.16) is valid aslong as the impedance mismatch does not change the internal noise properties of the block.Hence, the variations of the voltage gain due to impedance mismatch changes the noisecontribution of the following stages to the input, not the noise figure of the stage itself, if theassumptions given above are valid.

The noise contribution of the source and each stage in Figure 2.16 are combined at the output as

24

Hence, the Equation (2.16) can be rewritten for the receiver chain as

The equation resembles the original Friis’ formula, but it is valid only if the same sourceimpedance has been used when the noise factor is calculated from the input referred noisevoltages at each stage, and the loss due to the finite source impedance when defining noise isclose to the situation in the actual receiver i.e. For example, the noise factor istypically defined with a source impedance in the receiver calculations, which is smallcompared to the typical input impedances of the baseband blocks in the system as desired.Hence, the conversion from power to voltage mode signal processing in the receivercomplicates the noise figure calculations to some extent, but the Friis’ method is still applicablefor the definition.

2.4.2 Intersymbol Interference

The maximum capacity of the pulsed communications systems depends fundamentally on thebandwidth of the system according to the Nyquist bandwidth constraint [8]:

where is the bandwidth of the single sideband signal at baseband, and and are thesymbol period and rate of the transmitted information, respectively. Below that limit, the energyof the preceding and following pulses or bits inevitably distort the detection of the bit. Thiscrosstalk between the successive bits is called intersymbol interference (ISI). However, thebandpass-modulated radio signals, as QPSK, occupy twice the baseband bandwidth givenabove. Those are typically called double-sideband (DSB) signals, and the maximum capacity ofthe transmission is 1 symbol/s/Hz. The Nyquist constraint limits the number of symbols, not thenumber of bits, at a certain bandwidth. Hence, the use of more than two amplitude levels ordifferent phase angles to present several bits at a time improves the spectral or bandwidthefficiency as discussed earlier.

The maximal bandwidth efficiency requires a rectangular shape from the baseband filter i.e.H(f) is 1 when and zero elsewhere. Such a filter has a sinc-type impulse response[2]:

The impulse response describes the energy spread as a function of time. The maximum isreached when and at the multiples of the symbol rate the function crosses the x-axis.

25

Hence, the ideal moment for detection is at the maximum point, and if the data stream issampled exactly at the symbol rate, the energy of the other pulses is zero and no crosstalkoccurs as shown in Figure 2.17. The first zero is at the symbol period defined by the Nyquistbandwidth constraint.

The ideal brick-wall filter for Nyquist signaling is not realizable. The other problem is the slowdamping of the impulse response. A relative steep slope when crossing the x-axis makes thedetection sensitive to timing errors. A special class of Nyquist filters can solve the problem witha cost of extra bandwidth. The impulse response of a Nyquist filter is zero at each multiple ofthe symbol period, which is a necessary and sufficient condition for transmission without ISI. Araised cosine filter meets this criterion, and it is used in many communications systems. Thetransfer function of a raised cosine filter can be given as

where is the roll-off factor (marked sometimes with r). The roll-off defines the requiredexcess bandwidth for the transmission as seen in Figure 2.18. The minimum channel spacingbetween two adjacent channels is then

Practically, the spacing is slightly larger to allow feasible requirements for limiting thetransmitted power spectrum and for filtering the stronger adjacent channels in the receiver.

26

The impulse response of the raised cosine filter is defined in [9]:

The response is plotted in Figure 2.19. The roll-off value zero presents the ideal brick-wall asseen in Figure 2.18. The fundamental trade-off between the time and frequency domains isobserved. The fastest damping is achieved with the widest bandwidth. The type of the filter andthe roll-off are fundamental system specifications and the actual filter implementation shouldresemble the contradictory requirements with sufficient accuracy. Some of the trade-offs arediscussed and analyzed later. Often, the raised cosine filter is distributed between thetransmitter and the receiver. Each unit contains a root raised cosine filter, which transferfunction is a square root of the raised cosine response. The impulse response of the root raisedcosine filter does not have zeros spaced at the symbol period. At the system level, the signalpasses through two filters, which form the desired raised cosine response.

Instead of Nyquist filters, some systems like GSM use Gaussian filtering. Both frequency andimpulse responses follow the Gaussian bell-shaped curve, and hence there is no overshoot in thetime domain. However, the Gaussian filtering is spectrally less efficient than the raised cosineapproach.

Another dimension of the signal detection in the communications systems is the concept of thematched filters. The impulse response of a matched filter is a delayed version of the mirror

27

image of the signal [10]. A matched filter optimizes the signal-to-noise ratio at the samplinginstant but the maximum SNR does not depend on the shape of the pulse or the occupiedbandwidth [4]. The matched filters are related to the optimum detection of the signal, which isnot discussed here in detail.

2.4.3 Selectivity

While sensitivity describes the performance in the noisy environment and ISI the crosstalkbetween consecutive symbols, the selectivity defines the tolerance against other radiotransmissions. There are several different sources and methods of disturbance. First, theunwanted power at the nearby channels can not be filtered out because it is located too close tothe desired channel. Second, the power can alias to the same frequency with the desired channeldue to nonlinearities or sometimes due to the fundamental nature of the particular radioarchitecture. Third, the large interferer can saturate the gain of the receiver, which prevents thedetection of a weak signal. In addition to the previous, the other CDMA channels at the sameband and imbalance at the quadrature demodulation must be considered. The given topics willbe discussed in separate subsections.

The selectivity parameters are typically specified in each individual case for the signal, which is3 dB above the sensitivity level in the wireless systems. Hence, the interfering power can beequal to the noise power to meet the specification. This assumption is often appropriate, butactually it is valid only if the spectral distribution or other properties of the interferer do notvary the vs. curve.

2.4.3.1 Adjacent Channel

The power at the adjacent channel is filtered out with the channel selection filter. The distancebetween the adjacent channels, difference in power and the power spectral density of themodulated channels define the specifications for the filter. The adjacent channel power after thefiltering can be calculated as

where H(f) is the transfer function of the channel selection filter, S(f) the power spectral densityof the modulated channel and the spacing between adjacent channels. The transmitterfiltering is included in S(f). The filtering requirement is typically defined with a mask, as shownin Figure 2.20, which covers a larger band than only the adjacent channels. For example, inGSM the neighboring cells never transmit at adjacent radio channels, and therefore theattenuation requirement of the adjacent channel is considerably easier than the other radiochannels. However, due to the efficient use of the spectrum the channels are located as close aspossible, which leads to a complicated optimization process in the signaling environment of themodern wireless systems. The implementations of the channel selection filters trade off withavailable technologies, accuracy requirements, and contradictory performance criteria.

28

2.4.3.2 Transfer Function of the System

Two theoretical aspects, which define the filtering requirements of the transmission in thecommunications system, are discussed so far. The system specifications define the filter typeand roll-off for the system level filtering in the transmitter and in the receiver, and the level ofthe adjacent channel power at certain conditions. However, the realization of the given filterwith high precision may require excessive amount of hardware especially in the power limitedmobile terminals. On the other hand, several other filters and devices, which have band-limitingproperty, are practically always needed in the system before the detection of the signal in thereceiver. Therefore the system transfer function as a combination of different band-limitingblocks is discussed here. The system performance is finally defined for the transmission ofcertain number of bits at an acceptable bit error rate, and the system transfer function can varyfrom the ideal response within the BER limitation. Of course, the base station and mobileterminal must meet certain criteria separately because they should be compatible with alldifferent devices operating in the same system. The given discussion is mainly intended to helpthe optimization of the analog baseband filtering in the receiver treated in the next chapter.

The transfer function of the system is drawn at the block level in Figure 2.21, and it can begiven as

where the subscripts T and R indicate that the block is located in the transmitter and receiver,respectively. P is the subscript for the pulse shaping filter, D for the duplexer, C for the channelselection filter, and L for the band limitation of the LNA. All transfer functions are assumed tolocate at the baseband, which means that if any filtering is performed at an IF or RF frequency,like the duplexing, the actual response must be transformed first to the baseband. The frequencyresponses of the duplex filters and LNA are assumed to be wide-band compared to the channelbandwidth. In that case, the amplitude and phase responses over one channel can be consideredconstant with a sufficient accuracy. The worst case estimate for the system simulations can befound from the point where the combined gain of the duplex filters and LNA is at minimum

29

within the system band. Typically, the duplex filters have slight rippling at the passband andsteep transition bands especially between the transmission and reception bands. Hence, at leastthe outermost channels are potential candidates to cause problems. They are also susceptible tothe worst in-band phase variations. In the wide-band systems, there are only few channelswithin the passband of the duplex filter. For example in the UMTS, only 12 channels occupythe 60 MHz band. The assumption of the invariable conditions at the RF within a single trafficchannel is not necessarily valid anymore. Except of the last comment, which is not analyzedhere in detail, the RF filters can be excluded when the adjacent channel and intersymbolinterference are calculated.

The channel selection and pulse shaping are drawn as separate blocks in Figure 2.21. It isassumed that the function of the channel selection filter is to remove the power from allunwanted traffic channels, and the pulse shaping filter, which is typically matched with thetransmitter filter, is modifying information at the desired channel. The division is done only todistinguish the two separate tasks of the receiver filter. The channels are practically always soclose to each other that the channel selection and pulse shaping must be considered together. Itis more appropriate to distribute the filtering between the analog and digital domain due todifferent characteristics of the signal processing and define the combined transfer function. Thetopic will be discussed in the next chapter with respect to the number of bits required for theA/D conversion. The filtering functions of a single channel can be performed either at the RF,IF or baseband depending on the receiver architecture. However, the RF filtering is not afeasible solution because a high Q-value channel selection filter with sufficient linearity, tuningrange, accuracy and low noise is not realizable with current technologies.

The adjacent channel attenuation can be calculated directly from the amplitude response of thesystem transfer function. It is practical to normalize the total gain of the system to unity in thecalculations. The intersymbol interference is much more complicated to estimate at the systemlevel. Earlier in this chapter, the conditions for operation without ISI were defined. Thesynthesis of an almost ideal filter would be difficult especially if a power efficient structurewith a limited number of bits and a relatively slow clock rate is desired. The implementations ofthe different filters typically trade off with the adjacent channel attenuation and ISI both in thedigital and analog domain.

There are several methods to define how accurately the implementation should resemble theideal filtering without producing too much ISI. If a large amount of computing power and theknowledge of the digital back-end of the receiver are available, it is possible to simulate thewhole system and define BER as a function of the SNR. The method is very slow if severaloptions should be analyzed, but necessary for the confirmation of the correct operation after theoptimization. Also at the research phase, the back-end might not be available, and thereforeother methods are required to estimate the deterioration of the performance for differentstructures. Of course, the filtering simulations can be performed only at the baseband with fewblocks. Still the simulation of sufficient number of bits to achieve reliable BER estimates istime consuming.

30

The effect of the ISI can be observed from the eye diagram of the signal. A modulated bitsequence with no additional noise is passed through an ideal system filter to define the optimalbehavior. Then the frequency response of the filter is changed or other filtering blocks added tothe chain. The signal degradation because of the ISI is seen from the closing eye pattern in thediagram. The cost in the overall performance is calculated at the instants of the optimaldetection by comparing the amplitude of the opening to the ideal case. The sensitivity to timingerrors increases when the width of the eye reduces. The simulations can be performed in arelatively simple environment, and a smaller number of bits is required than in the case of BER.The method is used for calculating the effect of the highpass filtering in the direct conversionreceiver, for example [11].

Group delay is a common specification for analog filters to describe the time domain behaviorespecially in the pulsed mode communications [12]. The voltage transfer function of thecontinuous-time analog filters can be given under steady-state conditions as

where is the magnitude and the phase. Group delay is defined as a function offrequency as

It is a practical quantity for simulations and measurements, because of the easy access to phasedata either in the ac simulations or frequency response measurements. Group delay expressesthe delay of different frequency components in the system. If the phase changes linearly, delayis constant for all frequencies, which is one characteristic property of an ideal Nyquist filter.Hence, large variations at the group delay increase the susceptibility to ISI. The poles and zerosdefine the phase changes in the analog filters, and therefore the edges of the passband arecritical for the group delay behavior. The different filter prototypes have different group delaycharacteristics, and the filters with sharp transition bands tend to have the highest peaking. Thesame is valid also when the order of the filter increases. The problem with the group delay isthat it does not give a direct definition for ISI or its deterioration. According to other methodslarge peaking at the edge might be less severe for the ISI than the small rippling at thepassband. Hence, the definition of group delay is usable mainly when optimizing and checkingthe implementation of a certain filter prototype during the circuit design, or in the comparisonof measured data to the simulations.

The impulse response was used earlier to describe the optimum detection without ISI when nosignal energy of other symbols is obtained at the multiples of the symbol rate. The sameapproach can be used to estimate the amount of ISI in the circuit implementations. The impulseresponse of the system transfer function is defined and the square of the difference from zero ateach multiple of the symbol rate is summed. The result is compared to the maximum value ofthe response. Hence, the effect of ISI can be given as

31

where S/ISI is the signal-to-ISI ratio and is the impulse response of the system. The non-ideal impulse response is shown in Figure 2.22. It is assumed that the maximum is always when

Otherwise, the impulse response should be shifted in time to meet the criteria, because theclock recovery of the receiver detects the optimal sampling instant. To estimate the effect of theanalog baseband filtering only the filter itself and the ideal system filter should be included inthe transfer function. On the other hand, the optimization of the receiver filtering can beperformed using an ideal filter in the transmitter and a combined transfer function of the analogand digital filters in the receiver. The adjacent channel attenuation and the accuracy of thedigital filter depend on the number of bits and taps in the implementation and the oversamplingratio, which must be taken into account in the optimization. A corresponding method asdescribed here has been used earlier in the optimization of digital filters with the maximal error[13], and with the rms error [14].

S/ISI describes the ratio of the detected bit energy to the unwanted bits. Actually, the unwantedenergy is a sum of previous and successive bits at the moment They can be either 1 or –1giving a positive or negative impulse. Therefore the rms-value is used in the definition. In theworst case, all impulses sum at and the absolute values instead of their squares should besummed in Equation (2.28). Equation (2.28) can be modified to define the deterioration due toISI at the optimal sampling moment by comparing the rms-value of the unwanted impulses tothe ideal performance as

The result in Equation (2.29) is comparable to the method with the eye diagram, but no bit levelsimulations are required. The unwanted impulses describe the closing of the eye compared tothe optimum. With both methods a sufficient number of samples, either clock periods orunwanted impulses, should be included to achieve reliable results. However, in the impulseresponse method the summation converges quickly to zero, which restricts the number of termsand makes it easier to define the limits for the calculation.

32

So far, a perfect synchronization has been assumed. If the timing error is known, for examplethe clock jitter at the sampling instants of the A/D converter, Equation (2.28) can be rewritten inthe form

where is the jitter of the clock. A similar expression can be written for Equation (2.29) aswell. Equation (2.30) may lead to different results in the optimization because with rapidlydamping responses the timing requirements are relaxed. Unfortunately, a new parameter i.e. thejitter, which is not related to the filter itself, should be known or evaluated in advance. Theequation also assumes a fixed jitter and neglects the statistical properties. Therefore it can beused only for the comparison of different prototypes.

All the given definitions for the intersymbol interference of the different filters should beconsidered as figures of merit, which help the designer to choose an appropriate prototype forthe implementation. They should be used only for comparison. Group delay is maybe the easiestbut also the least descriptive definition. The S/ISI is illustrative for the radio designer, butsomehow misleading. It has a similar definition with the signal-to-noise ratio (SNR). However,a straight comparison to the required SNR value for a certain BER can propose an optimisticresult. Hence, ISI should not be treated as a noise parameter even in the simplified analysis.Therefore defined either from the eye diagram or from the impulse response is probably themost accurate description for ISI. Typically, the deterioration of the performance must bealmost negligible, and it should be related to the optimum detection of bits at the system level.Some simulated examples of ISI performance will be given in chapter 4.

2.4.3.3 Nonlinearity and Distortion

The nonlinear phenomenon in the radio receivers is connected to the aliasing of the power fromunwanted channels to the passband of the system. Before all other signals than the desiredtraffic channel are attenuated to a sufficiently low level, the linearity of the signal path is criticalfor the system performance. In that case, only weakly nonlinear structures are allowed in thereceiver with a large dynamic range. The manifestation of the nonlinearity is totally different inthe transmitter, because only internally controlled signals are processed with smallerinstantaneous dynamic range. The characterization of the distortion can be typically limited tosecond- and third-order products in weakly nonlinear receivers. However, the transmitted powerlevels are typically so high with simultaneous requirements of power efficiency that a muchlarger number of harmonics must be modeled and controlled properly. Here, the discussion isfocused on the system performance and dynamic range requirements in the receiver based onthe common block level parameters. The origin and modeling of the nonlinearity in analogintegrated circuits is a very complicated issue from the transistor level to the systemperformance [15]. Typically, only very simple structures can be calculated in the closed form,and simulations, which are confirmed with measurements, are needed in the circuit level design.Hence, it is important to understand the basic properties of distortion both from the circuit leveland system performance points of view.

33

Although the signal path of the received signal should be very linear, at least two fundamentallynonlinear operations are performed in the receivers used in the digital communications. Thefrequency translation in the mixers, either in one or several stages, and sampling in thecontinuous- to discrete-time or analog-to-digital conversion are both based on the switching ofthe signal path. However, the signal should experience a linear operation in the vicinity of theactual translation. The nonlinear characteristics of a memoryless system can be given in powerseries as

where is the excitation for the output and describe the coefficients of thedifferent orders of nonlinearity. Harmonic distortion is a measure for a single-tone excitation. Infrequency selective receivers the concept of harmonic distortion is not a sufficient definition.The components of the harmonic distortion fall rarely at the passband of the filter if the systemis properly designed. Instead, the intermodulation components of different excitations willinevitably alias at the passband at certain frequency combinations. Therefore a two-toneexcitation

serves the purpose better. The power series presentation gives a useful method to estimate theratios of different nonlinearities in the system [16]. The frequency components up to third-orderintermodulation products are collected to Table 2.3. The potentially detrimental products fall atthe passband of the system transfer function. Hence, they are inseparable from the desiredchannel in the frequency domain, and the total distorting power must be below the signal atleast by the minimum required SNR. The formation of different spurious tones is described forthe receivers with one and two downconversion stages in Figure 2.23. Only the thick lines arefalling at the passband of the channel selection filter because they are close to dc or LOfrequency, which converts the signal to baseband. Most of the products in Table 2.3 will beupconverted, and therefore they may cause problems only if they will be mixed with higherharmonics of the LO frequency. Those components are not significant because they will beattenuated due to parasitic effects at high frequencies, and the conversion efficiency is muchsmaller with a harmonic of LO, which has lower power than the fundamental. As seen fromFigure 2.23, the third-order harmonics can fall in the passband of the system at any stage beforesufficient filtering of the interferers. On the other hand, the second-order distortion will alwaysproduce a harmonic close to baseband when characterizing a relatively narrow system passbandat a high radio frequency. The second-order intermodulation product can be filtered out beforeoverlapping with the desired channel if it is far from that frequency. Therefore, the second-orderdistortion should be taken into account only with certain radio architectures. And as the effectof the third-order intermodulation is quite similar in all architectures, the second-ordercharacteristics are different depending both on the radio architecture and on the signaling in thesystem. The second-order intermodulation will be discussed later in detail.

34

35

The linearity performance in radio receivers is typically specified with the input referredintercept points shown in Figure 2.24. The third- and second-order input intercept points (IIP3and IIP2) are defined in the two-tone test when operating at the weakly nonlinear region. Itmeans that second- and third-order nonlinearities dominate, and if the input power or amplitudeis increased by 1 dB, the second- and third-order products rise 2 and 3 dB, respectively. This isa valid approximation at low signal levels when clearly one nonlinearity dominates. Above acertain signal level, different nonlinearities, which can be either higher order or from differentsources, begin to sum or cancel each other. Power amplifiers are typically designed at thatregion, which is not suitable for receiver operation. IIP3 and IIP2 are defined at the pointswhere the nonlinear product would be equal to the signal level if the components rise like at theweakly nonlinear region. The theoretical intercept points can be defined according to Table 2.3as

and

where iip3 and iip2 are absolute values. Typically they are given in decibels and the notationwith capitals is reserved for that. These hypothetical measures give unambiguous definition forthe selectivity against unwanted signals. The power levels of the intermodulation products canbe calculated from

36

and

where is the input power of one tone, the output power, G the power gain, and andthe respective powers of the intermodulation products at the output. The corresponding

power levels are referred to the input as and and are the differencesbetween the input power and the intermodulation product. All values are given in decibels. Thedefinition needs information only at one signal level, but to ensure the weakly nonlinearconditions several points should be used both in the simulations and measurements.

It is not just a common habit but also practical to refer all signals to the input of the receiver andconvert the voltage values to power levels, because the actual signal interface operates in thepower matched environment, and the impedance level is typically However, in the designof integrated receivers the input interface might be the only point where the definition makessense and the rest of the analog signal processing is performed for voltages. As described in thecontext of noise figure, different impedance levels should be taken into account in theconversion. Later, even the bit patterns of the ADC are sometimes converted to input powerlevels for the purpose of the complete analysis.

37

The connection between voltage and power values can be given by modifying Equation (2.35)as

where are rms voltages, the voltage gain and and the impedance levelsat the input and output, respectively. The impedance levels need not be real values as givenhere. It is necessary to convert all voltage levels to powers by using the same input impedanceas a reference when applying the voltage gain in the calculations. Also, the voltage gain shouldbe defined using real impedance values as earlier with the noise figure. The expression isrewritten for voltages as

The input intercept point of the cascaded stages can be calculated with an equation, whichresembles the Friis’ formula for noise performance as

where and are the input intercept point and power gain of the nth cascaded stage asabsolute values. The power gain should be replaced with the square of the voltage gain whennecessary. As the first stages dominate noise behavior, IIP3 becomes more critical when thegain in the chain increases. There are two design aspects, which must be taken into account.First, the external passive filters and other structures have almost infinite IIP3 compared toactive circuits. Therefore they can be omitted except of the contribution to the cascaded gain.Second, the filtering attenuates the interferers along the chain. Traditionally, all stages after thepassive channel selection filter can be neglected, because the unwanted tones are filteredsufficiently.

This is not the case with active baseband filters, and when optimizing the filtering functionsbetween the analog and digital domains a signal, which can produce unacceptableintermodulation products even at the input of the ADC, can exist. The spectral selectivityinvalidates the use of Equation (2.39) as it. Initially, two specified test frequencies located at

38

some distance from the desired channel should produce an unwanted tone at the passband. Theywill experience different amplifications in the filter, and the worst case estimate includes thelarger value in Equation (2.39) when evaluating the contribution of the following stages. Thismeans that will be replaced with a product of where is gain at passband and

is the gain difference of the larger test tone compared to This notation is useful if thetransition- or stop-band attenuation is alleviated.

Linearity is typically inversely proportional to the power consumption. Therefore trading thelinearity with the supply current along the cascaded stages as a function of the reduced dynamicrange is a possible optimization approach. It should be presumed that at least approximatetransfer functions can be defined for different blocks and that the other properties of the filterare not changing during the optimization. The method can also lead to increased designcomplexity. At system level, it is practical to define a linearity specification, which is requiredat the input of the first filter stage, and optimize the filtering as a function of power, linearity,gain and noise separately. This method is used in the design of the WCDMA direct conversionreceiver, for example.

If necessary the above discussion is valid for the second-order intermodulation as well withcertain exceptions. The IIP2 products do not fall directly at the signal band. Instead, theyconvert down to the baseband. Therefore the cascaded gain of an IIP2 product is differentcompared to the actual signal path. In differential circuits the prediction of the second-ordernonlinearity is difficult, because theoretically the components cancel each other and theperformance depends on the symmetry. Finally, the sensitivity to IIP2 depends not only on thetotal power but also on the modulation, multiple access and other signaling conditions. Hence,the characterization of the IIP2 is much more complicated issue than the third-order effects.

2.4.3.4 Blocking

The gain of the system begin to vary at a certain signal level when nonlinear components at thefundamental frequency have risen to the same order with the output amplitude The –1 dBcompression is defined at the point when the gain is dropped by one decibel from the first-orderbehavior. The input compression point (ICP) is often used for the same meaning. ICP can begiven for a single tone as

when the amplitude of the second tone is set to zero in Table 2.3. Comparing the ICP toEquation (2.33) the well-known approximation that ICP is 9.6 dB below the IIP3 is observed.However, the ratio depends only on a single nonlinear term, which is the same in both cases. Inpractice, several different components and their nonlinearities dominate the behavior, andalready by definition iip3 is measured at the signal levels, which are well below thecompression. Therefore the given value is only a rule of thumb, and the typical ratio incommunication circuits is 5-15 dB.

ICP gives an approximate upper range for the highest possible signal, but it does not necessarilyprevent the detection of a strong channel itself. That happens only after the internal cross-modulation i.e. spectral regrowth or some other phenomena prevents the demodulation anddecoding of the channel. Once again, the main concern should be paid to detection of weaksignals in the presence of strong channels. The behavior can be observed with a blocking test, inwhich the desired weak channel should be detected when a strong signal lies at some offset

39

from the weak channel. In cellular systems, the test is typically defined at several differentoffsets. The unwanted strong signal can be a sinusoid or carry a modulated channel. Twodifferent mechanisms for signal corruption can be found: desensitization and cross-modulation.In mixed-mode receivers where a sensitive RF front-end is on the same die with the digitalsignal processing, crosstalk should be considered as a third parameter in the blocking test. Thiswill be discussed later in connection with single-chip receivers.

The gain of the signal at in the presence of a high blocker, i.e. in Table 2.3, can begiven as

Hence, the performance is violated due to third-order nonlinearity also when a strong signal atany possible frequency compresses the gain. If the signal is located 3 dB above the sensitivitylevel in the blocking test, the -3 dB compression point is an appropriate measure rather than the-1 dB compression. Another effect, which should be considered, is the desensitization when thelow-frequency components are upconverted in RF amplifiers around a high frequency blockingsignal due to the second-order nonlinearity [17]. Although the out-of-band signals are filteredbefore the gain block, the upconversion of the internal low-frequency noise including the flickernoise of an RF amplifier might rise the noise to an unacceptable level. This can be tested with atwo-tone measurement when a high-frequency blocking signal and a low-frequencyexcitation generate a beat at the desired radio channel The both desensitizationeffects, gain compression and upconverted noise, are illustrated in Figure 2.25.

If another of the two interfering signals in the two-tone test carries a modulation, a part of it canbe transferred to the other carrier. The phenomenon is called cross-modulation. Thetransformation of the modulated channel to the other frequency can be formulated by adding asinusoidal modulation to the second term in Equation (2.32), aswhere m is the modulation index [4]. The fundamental frequency term can be rewritten as

40

The last term in Equation (2.42) indicates that the cross-modulation due to the third-ordernonlinearity may double the occupied bandwidth of the modulated channel, and therefore it cancause similar effects as spectral regrowth in power amplifiers. The IIP3 test should model theworst case behavior of the third-order nonlinearity for in-band signals. However, if there is astrong out-of-band tone, like power leakage of the power amplifier in simultaneous receptionwith the transmission, it may cross-modulate with an in-band blocker, which is close to thedesired channel. A part of the cross-modulated spectrum is susceptible to spread over the weakdesired channel, and hence deteriorate the performance. In some receiver architectures, thecross-modulation requirement may lead to a situation where LNA dominates the IIP3performance of the front-end rather than the downconversion mixer because the image filterbetween the two blocks attenuates the out-of-band blocker [18]. Compression and IIP3 dependon the total power level and therefore they can be defined straightforwardly. The specificationfor the cross-modulation requires again more detailed information on the signaling conditions inthe system. Although in most cases the cross-modulation does not dominate the third-ordernonlinearity in the receivers, the unexpected behavior might be possible to recognize bystudying the interaction of different modulated traffic channels.

2.4.4 Dynamic Range

It is not possible to give a single unique parameter, which defines the dynamic range of theradio receiver as seen from a number of different nonidealities described in this chapter. Maybethe most objective measure is the instantaneous dynamic range close to the sensitivity level ofthe receiver. This can be given as a spurious-free dynamic range (SFDR) or as a blockingdynamic range (BDR) at the input of the receiver [6]. The former, which is based on the third-order intermodulation and noise figure, is the most widely used. The definition omits the role ofthe gain control as a function of the incoming signal level. Therefore the total dynamic range ofthe receiver can be much larger. The instantaneous dynamic range for the signals well above thesensitivity level is restricted only due to large interferers but their contribution is worse becauseof the cubic dependence of the signal level in the IIP3 test. The total dynamic range and theinstantaneous dynamic range at large signal levels are discussed in the end of this subsection. Itshould be noticed that the gain control is significant for the unwanted channels, and hence forthe dynamic range, only before the channel selection. After that, the gain control is needed foran appropriate level shift. Therefore we limit the discussion here only to the previous.

The weakest possible signal is defined by the sensitivity of the receiver. Sensitivity isdetermined when only one channel is fed to the receiver. Hence, it is limited due to noise anddetection with a matched filter including proper timing, frequency response and ISI. In

41

principle, digital channel coding is required as well. However, the detection is typicallyassumed ideal in the discussion of the dynamic range. The minimum required SNR to detectbits at certain BER depends on the modulation, not on the properties of the receiver. Also, thechanges in the noise level typically dominate the deterioration of the performance rather thannonidealities in a properly designed DSP block. Finally, the optimization of the decoding is anindependent task in most cases, and therefore insignificant for analog designers. Hence, theinput referred noise defined with the noise figure in Equation (2.9) is appropriate for theanalysis. The input referred noise depends on the bandwidth, and therefore the transmitted bitrate should be taken into account when different systems are compared.

The spurious-free dynamic range is defined at the point where the third-order intermodulationproducts are equal with the noise power shown in Figure 2.27. This is actually the samedefinition, which is typically specified for the system i.e. the signal is 3 dB above the minimumSNR in the two-tone test, because the combined noise and distortion is now 3 dB above thenoise floor. It is assumed that the IIP3 limits the dynamic range in the test. The other selectivityparameters, like IIP2, should be checked separately. Another example given in Figure 2.27 isthe blocking dynamic range.

SFDR can be calculated directly from Equations (2.35) and (2.9) in decibels as

Similarly BDR is

SFDR rises slower than BDR when the linearity of the receiver is improved. Therefore thespurious-free dynamic range becomes more critical compared to the blocking test when a largedynamic range is required. For example, if the approximately 10-dB theoretical differencebetween IIP3 and ICP is assumed, a 60 dB SFDR corresponds BDR of 80 dB. It means that asingle blocker can be 20 dB higher than two tones generating IIP3. For a 80 dB SFDR, thedifference is already 30 dB. Hence, the direct comparison between different definitions does notgive much insight on the system performance. However, they can be used to estimate what is a

42

realistic ratio of signal levels in the two-tone and blocking tests. If not specified otherwise, thedynamic range refers always to SFDR hereafter.

The concept of the dynamic range in the radio receivers has significance only after thebandwidth, modulation, multiple access and a certain reference level, which is typically thesensitivity, are known. Sensitivity should be based on a realistic noise figure specification. Twoplots are given in Figure 2.28 to visualize the different constraints. In Figure 2.28(a), the IIP3requirement is given for two different noise figures in a narrow-band system, and separately fora wide-band system. The effect of the system bandwidth is described in Figure 2.28(b). Inprinciple, wide-band systems require a significantly higher IIP3, but the claim neglects thedifference in capacity according to the Nyquist bandwidth limitation and the fact that the wide-band systems are typically based on CDMA. Hence, the processing gain boosts the signal,which is buried in noise. Therefore, the actual dynamic range is improved by the amount ofprocessing gain compared to the definition of SFDR.

For the reasons given above, SFDR is not a very useful parameter to compare differentreceivers operating in different systems. The SFDR performance should be normalized to afixed bandwidth for the fair comparison because the inclusion of the bandwidth in the definitionof SFDR misinterprets the ratio of the circuit oriented parameters NF and IIP3. Also, whenspecifying the limits for a system, the characteristic differences between wide- and narrow-bandsystems must be taken into account. A feasible approach is to estimate the realistic performancefor the implementation, and limit the allowed power levels within the optimal limits. If weassume that NF is in the limits of 5-10 dB and IIP3 between –20 and –10 dBm, which aretypical numbers for current IC implementations, the SFDR is according to Equation (2.43) 61-71 dB for 200 kHz and 52-62 for 4 MHz bandwidths, respectively. The specification of thepower levels at a system requires knowledge both of the system characteristics and availabletechnologies. The specifications are based on exact power levels at certain conditions, whichdefine the required circuit performance. Hence, the dynamic range is only a secondaryparameter, which reflects the fundamental or natural limits of the system capacity rather thangives a universal method to compare receiver implementations in different systems.

The required dynamic range of different blocks in the receiver can be defined with thepreceding gain and total NF and IIP3 of the receiver. The contribution of different blocks to NFand IIP3 are given as a function of the preceding gain in Figure 2.29. The total NF and IIP3 aresummed from different terms in Equations (2.13) and (2.39). Therefore the partial contributions

43

are also given at the levels of 50 %, 10 %, and 1 % of the total value. The total NF and IIP3 ofthe receiver are assumed to be 5 dB and –10 dBm, respectively. The gain in the case of IIP3 isnot necessarily the same as for the signal, because the high intermodulation products must beattenuated before unreasonable linearity requirements. Figure 2.29 is a map for the receiverdesign rather than a behavioral model of the signal path as a function of gain.

By far, only the instantaneous dynamic range close to the sensitivity level has been covered.The realistic dynamic range is about 60-70 dB for current technologies. This meets the typicalspecifications of the current systems. However, the required total dynamic range is typicallylarger than that. This can be achieved with a proper gain control. The definition of the spurious-free dynamic range is not valid anymore because the SNR is larger than the minimum requiredvalue for the modulation. If it is assumed that the intermodulation product has approximatelythe same properties as noise in the detector, the signal-to-noise+distortion ratio (SNDR) can beused to estimate the required IIP3 for a certain dynamic range. The assumption is simplifying,because the modulated channel including digital information has not similar statisticalproperties as white noise. However, the first-order estimate gives quickly an initial value formore accurate system simulations. The definitions of SFDR and SNDR, which are given here,are not directly comparable to corresponding terms used in connection with A/D convertersbecause of different methods to determine the measures. However, in both cases they indicatethe dynamic range, and later indirect comparison will be performed when the receiver dynamicrange is referred to the required number of bits.

44

The problem at high signal levels is the cubic ratio between the third-order intermodulationproduct and the interfering tone when the power level is increased. Therefore if the sameinstantaneous dynamic range is required at high signal levels, IIP3 must be increased as well.This can be formulated by keeping the minimum required SNR constant when the power levelis increased as given in a linear scale as

where is the power of the minimum detectable signal and the relative input powercompared to MDS. The factor two is added because by the definition of the SFDR, thereference signal is 3 dB above the sensitivity level because the third-order product is equal withthe noise power. When this is applied to Equation (2.35) IIP3 can be given in decibels as

where means the required IIP3 at high signal levels. as a function of is given inFigure 2.30. There is only slight bending due to noise when operating close to the sensitivitylevel. It is evident that the dynamic range is dominated purely by the nonlinearities at highsignal levels. However, the linearity requirements become rapidly unreasonable when the powerlevel is increased. Therefore in the front-end of a receiver a large gain step is often available toachieve a better linearity in the reception and lower signal levels in the rest of the receiver. Thenthe noise figure should be estimated again, because the noise figure is hardly constant after thegain control close to the input of the receiver. If it is acceptable to reduce the instantaneousdynamic range at high signal levels, the SFDR term can be reduced in Equation (2.46). Therelaxed dynamic range is multiplied with factor 1.5 when specifying IIP3.

45

In the case of a constant dynamic range requirement at all signal levels, the total dynamic rangeis the sum of SFDR and This is typically not the manner how the existing systems arespecified. In some cases intermodulation tests have been defined at different power levels,which is an indication that an improved linearity is required at high signal levels. The purposeof the linearity characterization at high signal levels was to highlight the problems, which existoutside the range, which is often considered as the only significant limitation for performance,i.e. close to sensitivity. The optimization of the total dynamic range should not neglect that fact.

2.4.5 Gain and Interface to Digital Signal Processing

The maximum required analog amplification depends simply on the desired level in the detectorand the smallest possible input power of the receiver. In digital communications systems, thesignal level in the detector is practically the appropriate level either at the input of thecomparator or multi-bit A/D converter. First, it is assumed that all other signals except of thedesired channel and the in-band noise are filtered out in the analog domain. Also, the signalshould be sufficiently above the noise floor when the bits are determined. This means that thesystem does not use spread-spectrum techniques or the despreading is performed in the analogdomain, which is normally not the case at least in direct sequence. The typical input levels ofthe comparators with current technologies are in the range of which mean –2 to +10dBm power levels in the environment. For example, a system with a -100-dBm sensitivityrequires a 98-110 dB maximum analog gain.

A certain amount of clipping is acceptable, and even beneficial, at the comparator input toimprove the tolerance against offsets, which may vary the optimal 50 % duty cycle. A largergain than given above also ensures that the bit stream is a rail-to-rail signal in the single-bit A/Dconversion. However, some received signal strength indicator (RSSI) and analog gain controlmechanism is often needed to optimize the dynamic range before the channel selection. In theone-bit case, the difference between the strongest and weakest received signal gives an estimatefor the gain control range.

The use of a multi-bit A/D converter changes the analog gain specification of the receiver. AnADC can be utilized to improve the dynamic range in the digital domain when the channel

46

selection or a part of it is performed digitally, or to relax the analog gain control requirements.Of course, this increases the complexity and power consumption of digital circuits, but withmodern digital technologies it may be acceptable to some extent. The slow evolution fromanalog wireless communications to ‘completely’ digital structures is still on the way. Even morefunctions can be performed digitally than 5 or 10 years ago, but optimization due to differentcharacteristics of analog and digital signal processing is a complicated challenge.

To investigate the effect of the number of bits in the ADC on the gain specification, it can beassumed that the signal at the level of the least significant bit (LSB) provides the sameperformance as the maximum input of the comparator in the one-bit case. Also the maximumADC input, is similar to the comparator i.e. Hence, the voltage of the LSBcan be given as

where m is the number of bits. Hence, the voltage gain of the receiver can be reducedapproximately by So far, the effect of the quantization noise is neglected. If the quantizationnoise is assumed to have uniform distribution between which is independent of theinput signal, the quantization noise can be given as [19]

This expression is not valid generally, and as an approximation inaccurate at a small number ofbits. However, it is used here for a simple first-order evaluation, and the results match well withsome earlier reported simulations for DS-CDMA, which are discussed in the last subsection ofthis chapter. If the input signal is a sinusoid with as a peak-to-peak voltage, the SNR dueto quantization can be written as

which can be given with a well-known expression in decibels as

Next, the quantization noise and noise at the input of the ADC are combined assuming that theyare uncorrelated. The SNR at the output can be given as

where and are the signal and noise at the input of the ADC, respectively. Again,this is an approximation, and the direct summation of different types of noise is not statisticallyaccurate. Still the following results give reasonable numbers and simple expressions tounderstand the requirements in the system design of the receiver. They should be confirmedwith careful system simulations. Quantization noise depends always on the full-scale voltageand number of bits, but the desired channel is at that level neither in CDMA systems with

47

digital despreading nor when the channel selection is performed digitally. Therefore the inputlevel of the desired channel can be given as

where is the ratio between the full-scale input and the desired channel. It corresponds thedynamic range when the amplitude of the strongest unwanted channel is adjusted to the full-scale. Equation (2.51) can be rewritten as

At minimum, is actually the same as the when the minimum detectablesignal was defined earlier. Hence, the implementation margin, due to quantization is thedifference between the input and output SNR of the ADC. SNR at the output andimplementation margin are given as a function of the bits for two different input SNR’s of 6.7dB and 11 dB when dB in Figure 2.31. They correspond the required SNR for bit errorrates of and in the QPSK modulation.

The quantization noise correlates with the incoming signal with a small number of bits. Acorrection factor is defined in [20] to estimate the effect as

48

where the correction factor achieves values between 0 and 1. In the single-bit case,for a sinusoidal input. More than a single-bit conversion, and the random nature and

different statistical properties of the input signal prevent the accurate calculation of Hence,system level simulations are required. However, the can be rewritten for simplifiedanalysis as

The result is applied to Equation (2.53) and the effect is shown for with dashedlines in Figure 2.31. Even a larger implementation margin is required than earlier at a smallnumber of bits.

The output SNR is given for different dynamic ranges without the correction factor in Figure2.32. The curves follow exactly the earlier claim that the dynamic range increases by whenthe number of bits is increased. Hence, the gain of the analog part can be reduced by the sameamount because of the increased dynamic range. What is then the point of the previousanalysis? In the case of a one-bit detection clipping was considered to improve the performancebecause of the better precision in the duty cycle. Also, if the preceding gain is larger thannecessary the signal is clipped but the quantization noise is smaller compared to the input noise,and it is possible to operate with a smaller number of bits than predicted in Figure 2.31. On theother hand, if other channels are present clipping is probably not acceptable. Otherwise, twounwanted strong channels may produce an intermodulation product at the frequency of thedesired channel. Although the total harmonic distortion (THD) of the ADC meets therequirement of the dynamic range for a certain number of bits, the unacceptable intermodulationproduct can not be separated from the desired channel when the signal is filtered and decimatedin the digital domain. Therefore the linearity requirement in the A/D conversion does not allowovershoot from the which means about 2-4 extra bits. As seen from Figure 2.32 theinstantaneous dynamic range of 60 dB requires 12-14 bits for the conversion in the case when acomparator might be a possible converter if the channel selection is performed in the analogdomain. It means that the should be 74-86 dB, which is much higher than the dynamicrange of the input signals.

49

The above discussion is actually not valid generally because the effect of oversampling isneglected. Except of the CDMA systems, each traffic channel has a separate band for theoperation during the transmission. When several channels or the whole system band is sampledto the digital domain, the desired band occupies only a part of it. Therefore the desired channeland also the quantization noise is oversampled although the total input bandwidth ranges up tothe Nyquist frequency. This can be understood by averaging of the quantization noise when thesignal is decimated after the appropriate filtering. Each sample contains correlated informationof the desired channel, which has an effect on the digital code in the ADC. The quantizationnoise is averaged by the amount of oversampling when several samples are summed to onesymbol after the filtering. The same is valid also when only the desired channel is converted todigital. The oversampling in the Nyquist rate converters can be utilized to reduce thequantization noise contribution compared to the incoming signal, and hence diminish theimplementation margin of digital circuitry significantly. The effect of oversampling tocan be given as

where is the Nyquist rate or frequency of the ADC, the sampling frequency, and thebandwidth of the desired channel at the baseband, which is half of the RF bandwidth. Theoversampling ratio is or but it should not be directly compared to oversamplingin because the quantization noise is not shaped in Nyquist rate converters. Theeffect of oversampling is included in Equation (2.53) and the results are given for variousoversampling ratios at two different dynamic ranges in Figure 2.33. The correction factor hasnot been included in the plot. Equation (2.56) and Figure 2.33 indicate that oversampling byfactor of 4 corresponds one extra bit in the converter. According to Figure 2.33 oversampling isan efficient technique in the Nyquist-rate converters with small oversampling ratios but thebenefit is vanished at larger ratios because of the relationship to the power of 4. The 60-dBdynamic range still requires 10-12 bits at the oversampling ratio of 16.

A reasonable compromise is that an analog filter does not perform a complete channel selectionbut reduces significantly the required total dynamic range. The sensitivity to the third- andsecond-order intermodulation also reduces when the dynamic range between input tones issmaller. The 30-dB curve in Figure 2.32 is an example of it.

The cost of using multi-bit ADC’s is the fact that the power consumption increases quickly tounreasonable values especially for mobile terminals when the number of bits is increased. Theevolution of IC technologies allows faster operation with a smaller current consumption, butalso reduces the supply voltages, which makes the signal range even smaller than earlier. Inchapter 4, some examples of the reported multi-bit ADC’s will be given for comparison.Another limitation is the increased clock rate when the channel selection is performed digitally.Two ultimate alternatives are the conversion of a single channel or the whole system band at thebaseband. In GSM, the sampling rates for a Nyquist rate converter are 200 kS/s for a singlechannel and at least 25 MS/s for the whole band. The 25 MS/s sampling rate corresponds anoversampling factor of 125. The frequency allocations for GSM have been increased andtherefore at some bands the latter number can be even higher. In WCDMA, the correspondingnumbers are 5 MS/s and 60 MS/s, respectively.

50

The above discussion gives a very simplified analysis on the required dynamic range of an A/Dconverter. All signals are sinusoids in the mathematical representations, and clipping ormodulated channels are not taken into account in the calculations. Also, only Nyquist rateconverters are considered. However, the given numbers form a base for the system simulations.The instantaneous dynamic range is discussed so far, which means that the analog gain controlshould detect the power level and adjust the gain precisely for the converter. Otherwise, someextra bits should be reserved at least for quick changes in power levels. The nonidealities of theADC implementations have also been omitted. The standard linearity tests of the ADCs, whichconfirm the sufficient operation for a certain number of bits, are not necessarily the onlylinearity tests needed in the systems sampling complete system bands. A similar two-tone testthan for analog blocks may give a more realistic value for the attainable dynamic range, andranges for the acceptable clipping in different conditions, for example.

2.4.6 Image Rejection Ratio

An image rejection mechanism is needed in the most radio systems. For bandpass signals, theimage or mirror frequency is located on the opposite side of the LO either at RF or any possibleIF. Image frequency is mapped to a ‘negative’ frequency in the signal downconversion, and itwill alias into the same band with the desired channel if not removed properly. Indownconversion to the baseband, the concept of signal image relates more likely to thedemodulation of the symbol, which includes phase-dependent information. The differentreceiver architectures are actually defined based on the different ways to cancel the image. Theimage can be removed either by filtering or using appropriate phase shifts.

For historical reasons, the origin of the image rejection concept comes from the modulation anddemodulation of single-sideband (SSB) signals. Here, the focus is on the requirements fordifferent receiver architectures and demodulation of digitally modulated signals. In digitallymodulated channels, which carry a phase dependent component like QPSK or GMSK, the bits

51

from a symbol must be detected with appropriate phase shifts. Therefore, the signal must bedivided into quadrature branches at the latest when converting the signal down to baseband.With that perspective, they are considered SSB modulations although the energy of thebandpass signal is located at both sides of the final center frequency at dc. The in-phase (I) andquadrature (Q) components containing different bit streams are unwanted images to each otherin the demodulator. The available technologies and the frequency where either the filtering orphase shifting is performed are the practical constraints for implementations.

The image rejection by filtering refers to the superheterodyne principle. The image is removedwith a bandpass filter before the downconversion to avoid the spectral overlap as shown inFigure 2.34. The image rejection ratio (IRR) is simply the difference of the passband andstopband amplifications in decibels. Especially, the stopband attenuation varies at differentfrequencies, and the worst-case estimate should be used in the system characterization. If thedownconversion to baseband is done in several stages, the image frequency changes at each IFand a separate image rejection filter is needed in front of every mixer. On the other hand, at anystage the image cancellation can be changed to phase shifting techniques having differentconstraints. As described above, filtering techniques are not generally suitable for demodulationafter the conversion to baseband, and quadrature downconversion should be done before thedetection.

Two alternative methods, widely called as image-reject receivers, to remove the unwantedimage channel without filtering have been developed. Both use quadrature LO signals in thefirst downconversion, but they should not be mixed up with a quadrature demodulator. Thedemodulator suffers from similar phase and amplitude errors, but the restrictions are different.They will be discussed in the end of this subsection. The phasing method, which is also knownas Hartley receiver or architecture according to its inventor, is shown in Figure 2.35 [21]. Thesignals at the upper sideband i.e. above the LO are added at the summed output where as theimage at the lower sideband cancels itself. If both sidebands are of interest the subtractioninstead of summation recovers the lower sideband and cancels the upper one.

52

The perfect cancellation of the unwanted sideband is achieved only if the amplification is equalin both branches, and all phase shifts are ideal. The image rejection ratio for both sidebands canbe given as [22]

where and are the output powers of the image and wanted sidebands, respectively. Thereal factors A and B describe the proportional gains of two branches. The angle is the errorfrom the 90° shift in the quadrature LOs, and is the phase error after the downconversion. Theupper and lower signs in the cosine term present the upper and lower sideband signals,respectively. It means that if either of the phase errors dominate, IRR is equal for bothsidebands. Otherwise, the upper and lower sidebands experience different image rejection.When defining the gain error as IRR can be rewritten as

The image rejection ratio at different gain errors is given in Figure 2.36 when either or iszero. The combined effect is shown in Figure 2.37 for two different values when is sweptand As seen from Figure 2.36 both an excellent gain and phase balance are requiredto achieve good image rejection. The system requirements of an image rejection receiver arediscussed later in this subsection. In the case of an ideal amplitude balance, large differences inthe image rejection of the upper and lower band can be obtained if phase differences before andafter the frequency conversion can boost or cancel each other. The effect will be cancelled out ifamplitude errors dominate. In analog structures, the achievable IRR has been typically in therange of 30-40 dB if special techniques have not been adopted.

53

It is difficult to generate an accurate 90° phase shift for a modulated channel, which has arelatively wide bandwidth compared to the signal frequency. The problem exists at thedownconverted output of the Hartley receiver. Another issue is the variations of componentvalues in passive RC networks, which can perform an exact phase shift only at a fixedfrequency. To overcome the problems a third method for image rejection has been developed byWeaver [23]. The first method refers to filtering and second to phasing in this context. Insteadof the phase shift network in the signal path, the appropriate phase shifts are generated using asecond quadrature LO as shown in Figure 2.38. Now all necessary phase shifts are done onlyfor narrow-band LO signals, and relatively coarse lowpass filters are needed to remove theupconverted replica after the first mixers. The phase responses of the filters can be designed

54

insensitive to process variations at the relatively low frequency band of interest compared to thecutoff. Weaver architecture still suffers from the insufficient image rejection similarly asHartley receiver, but the analog implementation is somehow easier because all phase shifts areperformed for narrow-band signals. If the signal is not converted to the baseband after thesecond mixing stage, a secondary image can fall at the same band with the desired channelwithout any relative rejection [4]. It is located on the same side with the LO in the firstdownconversion and at the image frequency of the desired channel in the seconddownconversion. In that case, bandpass filters should be used instead of lowpass structures. Thebandpass filters can be also used to remove different dc offsets of the preceding stages, if thesecond downconversion produces a baseband signal. The baseband signal is often named also aszero-IF in the discussion of radio architectures.

The idea of using image rejection architectures to replace high-frequency image filters in thereceivers has been unattainable before the evolution of integration technologies. The improvedmatching properties and increased possibilities to use digital signal processing are reasons forthe recent development. For example, the 90°-phase shift can be performed almost ideally in thedigital domain with a reasonable amount of oversampling compared to the input signal. Hence,the low-frequency phase shifting problem of the Hartley receiver is avoided. Still the gain andphase accuracy in high-frequency circuits is the limiting factor in image rejection architectures.Some reported implementations, which are based on the image rejection, are discussed in thenext chapter.

The requirement for the image channel rejection depends on the system and the intermediatefrequency after the first downconversion. If we assume that the IRR specification can becalculated like the other selectivity parameters, which means that the desired channel istypically 3 dB above the sensitivity level, the IRR can be given in decibels as

where is again the dynamic range i.e. the ratio of the unwanted image frequency to thedesired channel. In the test, the noise level compared to the signal is 3 dB below the minimumrequired, and the image must be attenuated to the same level with the noise to meet the BERrequirement. Therefore the 3-dB term is needed. The IRR requirement depends on the selectedintermediate frequency if the spectral mask of the unwanted channels is not flat. Three differentcases are shown in Figure 2.39. The maximum power at the adjacent channel is typicallysmaller than at the other channels in most of the systems, which relaxes the IRR specification. Ifthe image channel is located outside the system band, the attenuation of a duplex or preselectionfilter attenuates the image, which comes from another system. In that case, the radio spectrum

55

of the image must be carefully examined in the frequency plan, because it may contain highpower levels and the attenuation of a preselection filter might be only in the order of 25-30 dB.

2.4.7 Quadrature Demodulation

Both image rejection architectures require a separate demodulator at the output of the structure.It means that the input is not a baseband signal, and the output should be divided again intoquadrature if needed in the demodulation. Therefore the quadrature downconversion in thedirect conversion or zero IF receiver should not be compared to the first downconversion stagein image rejection topologies. The direct conversion is the only architecture, which does notsuffer from the unwanted image problem. The RF downconversion stage is already ademodulator. The amplitude and phase accuracy is still critical, and more difficult to implementthan at low-frequency demodulators, but the specifications are significantly relaxed comparedto image rejection topologies. The demodulation process is basically similar in all receivers. Ahigh operation frequency and analog implementation increase the sensitivity to errors, butsufficient performance can be often achieved with a more efficient structure if powerconsumption or silicon area is compared. The faster development of digital technologies andhence processing capabilities gives a floating goal for optimization.

The limitations for phase and amplitude errors of a quadrature demodulator in digital systemscan not be given easily with a simple analysis. The accuracy requirements depend on themodulation and the complete implementation of the demodulator, which usually consists mainlyof digital structures. Therefore, a detailed analysis is often unattainable for an analog designer.However, some main concepts should be taken into account and the required performance forthe analog circuits should be defined based on the applied demodulator structure of the system.A block diagram of the QPSK demodulation principle is shown in Figure 2.40. For example, adigital signal processor can perform clock recovery and correct certain imperfectionsafterwards, which changes the structure of the implementation significantly. Theimplementations of different demodulators or detectors are not discussed here any further.

56

The phase and amplitude errors cause relative shifts between the locations of different symbolsin the constellation diagram. The variable errors caused by noise, nonlinearities and other time-variant measures are often given with the concept of error vector magnitude (EVM) shown inFigure 2.41. It gives the rms variation of the symbols from the ideal constellation points,typically in percents. EVM is the summation vector of different nonidealities. It is commonlyused especially when estimating the performance of the transmitter.

In the receivers, the fixed amplitude and phase errors between the channels in the quadraturedemodulation do not modify the magnitude of the error vector. Instead, the shape of theconstellation is changed. The effects of fixed amplitude and phase errors are described in Figure2.42. They bring certain constellation points closer to each other, which increases theprobability to false detection. Hence, the constant error vector can not be compared directly toEVM, because the effect on the BER is not necessarily the same as in the case of noise anddistortion. The error vector magnitude is useful when the effect of different nonidealities on thereceiver performance is measured, and the properties of the specific modulation are taken intoaccount. It can describe combined behavior, which is difficult to determine otherwise, but withlittle insight on the problems if the different phenomena are not studied also separately.

57

The effect of fixed phase or amplitude errors in the demodulator should be studied with BERsimulations rather than with EVM. Hence, it is not possible to determine initial estimates for thesame parameters with as simple analysis as in the case of IRR for image rejection architectures.The simulated effect of fixed phase error on BER for a WCDMA receiver is given in Figure2.43. In the simulations, an integrate-and-dump circuit with ideal sampling times has been usedas a detector. A phase error of 1° causes practically negligible deterioration on the performanceand with 5° error the degradation is less than 1 dB even at a low BER of The requiredperformance is significantly relaxed compared to image rejection receivers. Similar results aregiven for a direct conversion receiver operating in a paging system in [24]. The systemsimulations with an interpolation demodulator allow 10° phase errors with a 0.1-dB degradationin the performance for BER values down to The balance requirements should be met overthe total system band, which often requires special techniques to produce sufficiently widerelative band widths for structures generating the quadrature phases at RF.

58

2.4.8 Special Topics in CDMA Communications

As discussed earlier, the most distinct characteristics of a CDMA system are the simultaneoustransmission of several traffic channels at the same radio band, and the capability to detectsignals, which are buried in noise. Both properties are based on the coding of the transmittedinformation with a pseudorandom sequence, and on the effect of the processing gain in thedespreading with the same sequence. This subsection compares the CDMA communications toother methods and alleviates the trade-offs in the receiver design. The numerical examples arebased on the original WCDMA proposal given in Table 2.2. If not otherwise noted, the I- andQ-channels of the QPSK modulated signal are spreaded with two independent 4.096 Mcps codesequences. Hence, the 64 ksymb/s nominal symbol rate gives an 18-dB processing gain.

The basic property in third generation systems is the flexibility to use variable data rates in thetransmission. The multirate services can be provided in CDMA systems either by a variablespreading factor (VSF) or multicode [1]. The former means that the spreading factor, and hencethe processing gain, changes when the data rate is varied and the chip rate is constant. In themulticode scheme, the high-speed data is first divided to parallel branches, and each branch isspreaded with an individual code before summation. Hence, the spreading gain of each branchis larger. Neither of the methods is superior to each other, but they have different benefits anddrawbacks in comparison of signaling, power control and complexity. It is proposed that themulticode transmission is preferred for the forward link while variable spreading factor hasmore advantages in the reverse link [25]. The analog receiver is basically insensitive to thedifferences because the chip rate, and therefore the channel bandwidth, is constant with twoprecautions. The envelope variations with a large number of different code channels areincreased compared to a single spreading code. This is of importance especially for the linearityof a power amplifier in a mobile terminal. It can also increase linearity requirements in somereceiver architectures, but they are probably less significant, because the reception containsseveral independent traffic channels at the same band in all cases. The other implementationconstraint is the need of several parallel fingers in the despreading process of the multicodetransmission. However, the multiple fingers are typically implemented with digital techniquesin the direct sequence systems. Fundamentally, the higher data rates reserve more capacity fromthe radio channel in both cases, which means less users per channel.

All wireless communications using CDMA can be considered as wide-band systems becausethey occupy wider bandwidth for the transmission than required by the Nyquist constraint.Hence, the term WCDMA in connection to the third generation systems refers only to the factthat the radio channel is even wider than in the earlier commercial CDMA systems, and that thesystem is designed to provide also high data rate services besides of speech. The principle doesnot change, and the wider bandwidth allows only a reasonable processing gain for high datarates as well. Despreading recovers the transmitted narrow-band information and improves theSNR compared to all other signals by the amount of processing gain according to Equation(2.2), because the out-of-band signals can be filtered out afterwards. Besides that the narrow-band interferers will be spread over the whole band defined by the chip rate. Hence, their poweraverages, and can be compared to white noise. The effect of despreading in the presence ofnoise and a narrow-band interferer is visualized in Figure 2.44. Also, some implementationconstraints have less severe effects, because the wide-band channel is less sensitive to thefrequency dependent nonidealities, which average after the despreading over the bandwidthlimited by the chip rate. They will be discussed later in this subsection. To some extent theeffect of despreading can be compared to oversampling in the discrete-time signal processing.

The other traffic channels at the same band use orthogonal codes, which means ideally that theydo not correlate, and therefore behave like noise to each other. In the following analysis,perfectly orthogonal codes are assumed in all cases, and also that a sufficient number of

59

orthogonal codes is available at any moment. Both issues are important and critical for the radiosystem design. The capacity of a single radio channel is the key issue in CDMAcommunications. First, it is discussed for a single traffic channel with different data rates, andafter that several code channels are adopted at the same band. It should be remembered that thegiven equations are based on simplified assumptions, which do not take the properties of digitalsignals into account. However, in most cases this is sufficient, and gives enough information forthe specification of an analog radio interface in the ‘digital receiver’.

The sensitivity specification for a CDMA receiver can be defined uniquely only at onereference point with fixed data rate and bit error rate requirements. In multirate, multiservicesystems, all other cases are defined according to Equation (2.12). For example, if it is assumedthat the noise bandwidth is equal with the data rate, the 4.096 Mcps transmission with a 5-dBnoise figure of the receiver corresponds to a –103-dBm total input referred noise power. The18-dB processing gain and BER requirement for a QPSK signal gives the sensitivity of-114 dBm. The sensitivity as a function of different data rates and BER values is given at thisreference point in Figure 2.45. The dependence on the data rate is modeled with a variablespreading factor as described above. Over 30 dB variations in sensitivity can be obtainedbetween different services. Typically, reasonably low quality and low bit rates are accepted forspeech transmission compared to data. Hence, both extremes are theoretically possible. Theeffect of coding gain is neglected in Figure 2.45. WCDMA system uses different codingschemes for data and speech [1], which can have different influences on the sensitivity.

60

The selectivity both in the case of adjacent channel and other interferers can be definedsimilarly as with other systems. Again, it is assumed for convenience that the signal is 3 dBabove the sensitivity level when all selectivity parameters are defined. Hence, it is still buried innoise. The interfering signals can be equal with the noise level to cover the 3-dB margin asearlier. It means that the adjacent channel or other interferer can be at much higher levelcompared to the desired signal still at the input of a decorrelator. Therefore, the spurious-freedynamic range as given in Equation (2.43) is not an appropriate definition for the dynamicrange at the system level for two reasons. The narrow-band systems benefit from the bandwidthdependent term and the capacity of the system has not been taken into account. Hence, theSFDR should be rewritten for the receiver as

This gives an interesting result of the fundamental difference in the performance of CDMAsystems. In the comparison the same data rate is transmitted in the ‘conventional’ TDMA orFDMA system and in a DS-CDMA channel. The data rate is 64 ksymb/s and the expectedreceiver performance, which is relatively independent of the system, is defined with parameters

and The required is 7 dB, which corresponds to a -11 dB SNRrequirement for the CDMA channel at the 4.096 Mcps rate. The thermal noise floor is at the-126-dBm level in the narrow-band transmission if an ideal filtering is assumed, which gives a67 dB SFDR. The CDMA channel with a –108-dBm thermal noise achieves a 73 dB SFDRwith the same parameters. The improved SFDR indicates better immunity against out-of-bandinterferers. However, it is not achieved for free, because there are several transmissionssimultaneously at the same band, which provides different restrictions for the implementations.They will be discussed below with respect to analog circuitry. Also, the ‘coding efficiency’,which describes the ratio of the actual information to the additional coding needed for thesystem management, is neglected. It is out of the scope in this context. Another systemmanagement issue is the efficient use of potentially available performance, which is discussedin [26] from the UMTS perspective, for example. The comparison between SFDR values indifferent systems is shown as a function of the symbol rate in Figure 2.46.

61

The required IIP3 value for a CDMA system can be calculated from Equation (2.35) when thetest signal is 3 dB above the sensitivity level. The interfering signal is above the test signal bythe amount of The factor is now the dynamic range, which is actually the same as theSFDR for the CDMA system in Figure 2.46. The IIP3 value as a function of the dynamic rangeis given for two different processing gain values in Figure 2.47. The above discussion considersonly the instantaneous dynamic range at low signal levels. When the power level rises, the IIP3requirement behaves similarly as given earlier in Equation (2.46). The given analysis has shownthat the direct sequence CDMA systems have fundamentally a higher dynamic range in thepresence of out-of-band interferers than the other access methods when the transmitted data rateand receiver parameters are equal. However, this a conflicting argument to the fact that theexisting IS-95 system using DS-CDMA has probably the most stringent linearity requirementsof all cellular systems [27]. This is mainly due to a hostile signal environment rather than theCDMA characteristics. The existence of narrow-band high power signals, often called asjammers, define the most stringent linearity characteristics, which is the case both in [18] and[27]. The jammers come from other cellular systems, which exist at the same band close to thereceived radio channel. They can have larger, uncontrollable power levels, which increase thelinearity requirements. For example, if two systems are operating at the same band withdifferent noise figure but similar dynamic range requirements, the system with a lower averageand peak power levels suffers from the stronger one. The fact that 2-dB of added dynamic rangerequires a 3-dB improvement of IIP3 at high power levels is inevitable. Therefore, thecompatibility in power levels is maybe the most efficient way to optimize the systemperformance. The cross-modulation problem, described in [18], practically rules out allarchitectures without an image rejection filter after the LNA in IS-95. The cross-modulation ofthe leaked transmitter power around a jammer specifies IIP3 value of +4 to +5 dBm at the inputof the LNA. The IIP3 requirement would be multiplied with the LNA gain if the leaked powerfrom the transmitter can not be filtered efficiently after the LNA. In that case, LNA has morestringent IIP3 specification than the total IIP3 of the receiver.

So far, only the out-of-band interferers have been considered. They can be specified quitesimilarly as with other systems. However, the performance is referred only to a single trafficchannel at the desired band. It is a practical definition for sensitivity or selectivity, but notsufficient in the case of in-band interference in CDMA. First, the capacity is discussed based on

62

the number of different traffic channels at the same band. Later, some other limitations aredescribed.

To simplify analysis, it is assumed that all different traffic channels have equal data rates, whichis defined by the corresponding processing gain. They have also equal power levels at the inputof the receiver. The total number of traffic channels including the desired one is marked with

Now, the interference power due to other traffic channels can be written as

where is the power of each individual traffic channel. The smallest detectable channel inthe presence of noise and other traffic channels can be evaluated in absolute values as

is the in-band noise power including the thermal noise floor and the input referred noisefigure of the receiver. The required channel power as a function of total number of channels isgiven in Figure 2.48 (a). The limited capacity of a CDMA channel can be defined when axis arechanged and the maximum number of channels is calculated from Equation (2.62) in absolutevalues as

The plot of as a function of the channel power is shown in Figure 2.48 (b). The curves aresaturating to a fixed value after the signal power is sufficiently above the sensitivity level. Inthat case, the last term of Equation (2.63) is negligible, and the maximum number of channelsgives the capacity of the system [28]. The maximum capacity and the summed symbol rate ofdifferent traffic channels are given in Figure 2.49. The definition of capacity is inaccurate atlow processing gain values, which can be seen as a violation of the Nyquist bandwidthconstraint in Figure 2.49. Another important fact is that if the maximum capacity, i.e. thenumber of different users, is transmitted simultaneously, the total symbol rate at the radiochannel is far from the maximum because the different transmissions interfere with each other.On the other hand, the same frequencies can be used already in the adjacent cells, whichincreases the efficiency of the frequency reuse compared to other multiple access methods. Thehigh-speed transmission can be performed with low processing gains, but they reservepractically all the available capacity of the radio channel. Only one channel can be transmittedat the sensitivity level. Higher power levels must be used when several traffic channels areapplied at the same band. The available capacity for the signals, which are a certain amountabove the sensitivity level, are given in Figure 2.50. The channel power, gives thesensitivity when The power of each traffic channel is multiplied by p, which indicates thelevel above the sensitivity. The new channel power is placed in Equation (2.62), and themaximum number of channels can be rewritten as

63

The 20-dB curve follows the ideal with a good accuracy, and the loss is relatively small at the10-dB curve. However, this indicates that the average transmitted power is probablysignificantly larger than might be assumed according to sensitivity. Hence, the linearity maybecome a serious problem.

It is evident that if one traffic channel has more power compared to the others, the capacity willbe limited. The efficient power control mechanism is critical for the optimization of the CDMAsystem performance. However, the topic is not considered here any further. The gain control isassumed ideal, and the loss of performance is included in the digital implementation margin.Analog gain control techniques are probably needed, but the control at the system level is mostlikely digital. More important in the context of radio receiver design is the much wider in-banddynamic range than in the systems having only a single simultaneous traffic channel at the inputof the receiver. Some issues will be discussed next. The complexity of the system increasessignificantly, because the radio environment is changing rapidly, and static conditions can notbe allocated for each traffic channel. For example, the sizes of individual cells may vary as afunction of time depending on the current traffic in the cell and in its neighbors. However, theeffects of loading, voice activity etc. should be considered at a higher hierarchy level.

64

Only noise and other channels are considered so far with respect to the capacity of a CDMAradio channel. A deeper insight of the limitations can be given with an equation, which ismodified from the forward link budget calculations in [28]. The signal-to-interference ratio of atraffic channel can be given as

65

is now the power of the desired traffic channel. The signal-to-interference ratio is usedinstead of SNR only because naming of all interference sources as noise is confusing. Still, theS/I must be at minimum the same as to allow detection with the required BER. and

are the interferences of overhead channels from the own and other near-by base stations,respectively. The overhead channels contain for example pilot, possible paging andsynchronization channels at the same carrier. They are needed for system level control, andinevitably decrease the capacity of actual information channels. describes the other in-bandtraffic channels in the same cell as earlier, and is the total interference from the trafficchannels in other cells. The non-CDMA transmissions or jammers at the same band are markedwith The first five terms in the denominator are marked with but all values in thefollowing analysis are based on the calculations of as given earlier. The other termsdegrade the performance, but the actual values can be estimated only with a careful networkplanning. Therefore ‘optimal’ performance is a better reference in this context. is thesum of thermal noise and noise figure of the receiver as given in Equation (2.9). The last term,

is of interest for an IC designer because it contains all implementation-oriented non-idealities, which are typically assumed negligible at the system level. Other terms in thedenominator except of the noise figure and are system parameters, which can not beoptimized in the analog design.

As seen from Equation (2.65) the capacity is a complicated function of implementation andtraffic related factors. They are not totally independent of each other. In the optimal case, eachindividual channel transmits only minimum power, which is required to detect the channel at acertain BER. For example, if the noise figure of a receiver is low, less transmission power isneeded to detect the signal, which lowers the interference not only inside the current cell butalso in neighboring cells. Hence, all transmitters can lower their power. On the other hand, theopposite situation may lead to power competition. Inside the cell, the ‘worst’ terminal limits thecapacity besides of the traffic, and the performance reflects to other cells as well. However, thecomplexity of fading radio paths, variable distances of terminals from the base station and otherenvironmental issues probably dominate the performance more than the circuit implementationsif they follow certain limits. Therefore too detailed optimization between different restrictions isimpossible, but the understanding of different phenomena is still necessary. The abovediscussion considers the forward link and thus the performance of the receiver in a mobileterminal. In the reverse link, the overhead channels are not necessary because the base stationdoes not need system control signaling from the mobile. Otherwise, the same criteria as earlierare valid.

The effect of the implementation-oriented in-band interference can be divided at least tofollowing terms:

comes from the quantization noise, from intersymbol interference, from nonlineareffects of other traffic channels, interference from the transmitter, and from phase noise.Next, each of them will be discussed separately. Some of them depend on the traffic in the radiochannel. If the value of the parameter is a function of the total traffic, the worst-case conditionsshould be estimated. The in-band dynamic range of a CDMA radio channel is plotted as afunction of processing gain. Dynamic range is the difference between the processing gain andthe minimum SNR in the simple analysis. At sensitivity level, it is purely defined by the noise,but at higher signal levels by other interfering sources given in Equation (2.65).

66

The effect of quantization noise was analyzed earlier with respect to the dynamic range in thepresence of signals at other radio channels, which can be filtered out in the digital domain. Thenumber of bits, which is required for the demodulation of the received signal was neglected oractually assumed that a one-bit comparator is sufficient and the threshold is optimized. InCDMA systems, the signal characteristics have significant effect on the required number of bits.The input signal of the ADC consists of the desired traffic channel, additive white Gaussiannoise, and signals from other users, which have propagated through a multipath radio channel.Therefore, a simple approximation is not possible. It can be intuitively claimed without a proofthat the signals with a large amplitude envelope require larger word lengths in A/D-conversion.Hence, the problem is not limited only to CDMA systems and must be studied separately with arealistic signaling in each system.

The required word length is analyzed based on theory and defined with simulations for twodifferent DS-CDMA systems in [29]. The optimum threshold level compared to the maximuminput voltage of the ADC is first analyzed at constant conditions for different number ofbits. In the multibit case, the optimum signal level is 6-12 dB below the maximum and less witha two-bit word because LSB limits the dynamics, and the quantization noise is not distributeduniformly. At the optimum threshold, 4-6 bits is simulated to be sufficient when ideal raisedcosine filtering and synchronization is used. The performance degradation is 0.5 dB or less with4 bits and less than 0.1 dB with 6 bits in both cases. The results depend on the signaling, but thedegradation is referred to a despreaded signal. Therefore the given numbers can not be directlycompared to in Equation (2.66). Similar results are given for a WCDMA system in [1]. Theabove characterization is valid only for one radio channel. If out-of-band signals are not filteredin advance, the required dynamic range must be added to the word length taking into accountthat the threshold voltage, to which the dynamic range is referred, is not the full-scale input ofthe ADC.

The theoretical analysis of intersymbol interference is also complicated in a DS-CDMA system.The traffic channel is filtered in two stages. First, the wide-band radio channel is selected, andafter the despreading, the desired narrow-band data is filtered again. In principle, this can beunderstood as a chain of two matched filters with different bandwidths as shown in Figure 2.52.Only the first filter is typically of interest for an analog designer. The use of digital detectors inDS-CDMA systems, adopting several RAKE fingers etc., will be not discussed here. The wide-

67

band input signal should be synchronized to the spreading code, but this can be also done withdigital techniques in the receiver. The wide-band channel selection filter has different ISIrequirements than the narrow-band matched filter in the detector. The numerator in Equation(2.28) depends on the power of the desired traffic channel while the ISI term in the denominatoris a function of all in-band traffic channels. Hence, the denominator should be multiplied withthe in-band dynamic range On the other hand, the signal-to-ISI ratio improves by in thedespreading process, which means that the performance is improved by the of themodulation if the whole capacity is used and even more otherwise. The given argumentation isvalid assuming that other in-band traffic channels can be considered as pulsed data, andtherefore do not behave like noise. In principle, this would give slightly relaxed requirementsfor the wide-band matched filter specifications because of the averaging effect in thedespreading. However, complicated system simulations, which include appropriate signalstatistics, are required to confirm the claim.

The transmission in a CDMA channel contains several modulated signals. The requireddynamic range of a radio channel is small compared to out-of-band interferers as shown above,and the processing gain raises the signal above the interferers after the despreading. It may notbe necessary to characterize the in-band linearity requirements especially because the nonlinearproducts should never reach the signal power of the fundamental tones if the signal path is nottotally compressed. Hence, at least the signal compression should be avoided in the analogback-end. However, a receiver with an analog channel selection filter and ADC with aminimum number of bits for the signal detection, requires a large gain to achieve an appropriatesignal level at the input of the ADC. The last analog stages should handle large signalamplitudes with a relatively large dynamic range. Also, wide-band stages at the linear back-endmay consume a significant amount of power, which should be minimized without a degradationof performance. When operating at full capacity, there is practically no headroom available fornonidealities, and hence second-order effects should be probably 10-20 dB below the totalinterference level. Therefore some comments about in-band linearity will be given.

The modulated channel is described with as earlier in the discussionof cross-modulation in Equation (2.42). The model is useful in theoretical calculations, butspecific results would require system simulations and careful characterization of the modulationproperties. The interest is in the baseband signal processing, and the potential problems exist inthe stages just before the ADC. Therefore, the reactive elements can be neglected and the use ofpower series analysis instead of Volterra series is sufficient [30]. The power series according toEquation (2.31) is calculated for the modulated baseband signal i.e. The output is then

68

The nonlinear products are located at the modulation frequency, and its harmonics. Thedifferent terms according to their frequency are collected in Table 2.4. The components due tothe second- and third-order nonlinearities are calculated separately. The different harmonicsactually describe the spectral regrowth. If we assume that the modulation consists of differentindependent frequency components from 0 to having equal amplitudes, wherepresents the channel bandwidth, the rms-values of the spectral components can be integratedover the bandwidth. In that case, only half of the second harmonic and third of the thirdharmonic components are located at the passband. This is simplifying but a descriptivepresentation.

The dc term is neglected in the calculations. The cross-modulation because of the third-orderlinearity can be written as

The second and third harmonics of the are practically insignificant. The cross-modulationresult is compared to the desired signal given by in Table 2.4, and to the iip3 of the two-tone test calculated in Equation (2.33). The ratio between signal and the cross-modulation canbe given as

The terms and are practically the same in the previous equation, but in different roles.describes the required ratio between the maximum signal and cross-modulation. If

69

it is desired that the cross-modulation power should be 10 dB below other interferers i.e.and the modulation index is between 0 and 1, the ratio between iip3 and the signal level must be22-24 dB. The earlier estimate of optimal input level for ADC corresponding -1 to+10 dBm power levels referred to gives virtually a +20 to +35 dBm IIP3 requirement atthe ADC input. Assuming that the number of bits is defined for a sufficient dynamic rangeotherwise, the IIP3 of the ADC can be considered more likely as an OIP3 requirement of theanalog back-end. Although the given numbers may give a pessimistic or too stringentrequirement for the back-end, it alleviates importance of a linear signal path before thedespreading. More accurate analysis and exact values are out of the scope in this presentation.However, it should be taken into account that the in-band linearity either specified as IIP3 orICP is of importance in DS-CDMA systems. A similar characterization can also be given to thesecond-order nonlinearity as

and the ratio between the signal and cross-modulation is

The characterization of the cross-modulation gives an observation, which is actually aselectivity issue. The higher-order components of the adjacent channel i.e. the spectral regrowthcan be significant if the adjacent channel power is much higher than the detected signal. Theproblem is definitely not as serious as in power amplifiers, but not necessarily negligible either.

In CDMA systems both reception and transmission are typically continuous. Hence, thetransmitted power can be coupled to the receiver through the antenna or parasitic effects. Forexample, the isolation between transmitter and receiver ports in a duplexer is not infinite. Theisolation should be better than the difference of the maximal transmitted power and the ICP ofthe receiver to avoid the desensitization due to compression. Another problem, cross-modulation of the transmitter power with blocking signals at the reception band is describedearlier. The leakage power is typically an issue only in the first amplifying stages and filteredout to a negligible level immediately after that at the baseband. The large frequency offsetbetween transmission and reception bands relaxes the filtering requirements. The transmitterhas also a wide-band thermal noise floor at the output. Noise at the reception band isinseparable from other sources, and therefore decreases the sensitivity. The noise of thetransmitter is negligible if

where is the thermal noise of the transmitter, is the isolation between the transmitterand the input port of the receiver, and the total noise figure of the receiver.

The characterization of phase noise in wireless communications is of importance and a detaileddescription of different aspects is given in [31], for example. Here, only some brief commentsare given on the system requirements when narrow- and wide-band systems are compared. Thediscussion covers the possible degradation of signal-to-noise ratio due to phase noise. Thetiming accuracy issues are not treated. The reciprocal mixing in the receiver is compared inFigure 2.53 (a) and (b). In narrow-band receivers, the oscillator phase noise mixed with higher

70

near-by channels may alias an unacceptable amount of noise on the reception band of a weakchannel. In a wide-band receiver with the same phase noise performance, the effect is muchsmaller. The phase noise requirement is typically one of the most stringent specifications for themonolithic implementations. Hence, the specifications are relaxed in wide-band receivers. If thenarrow-band channels are located next to the wide-band channels, like typically in IS-95, mostof the benefit is lost. The phase noise of the transmitter has different characteristics in forwardand reverse links. The phase noise of different mobile terminals operating at the same CDMAchannel is summed in the receiver of the base station as shown in Figure 2.53 (c). Therefore themaximum phase noise power of the receiver in the base station can be given as

where is the phase noise power of each individual mobile transmitter, and thephase noise of the receiver in the base station. The phase noise of different transmitters isassumed equal. Hence, the LO of the mobile transmitter has probably the most stringent phasenoise requirement in the CDMA system with respect to SNR. There are only two independentsources of phase noise at each mobile receiver assuming that the phase noise of the transmitterin the base station is dominated by the LO of the last upconversion stage, and that the differenttraffic channels are combined on the same signal path before the conversion. The factor isthen one when calculating the phase noise in the mobile receiver based on Equation (2.73).

The effect of despreading has been discussed several times earlier. The significance inprotection against multi-path or fading effects in wireless transmissions is appreciated by thecommunications literature. In the receiver design, there are also some obstacles, which can beavoided or effect can be reduced when a wide-band channel is processed. The followingcomments apply only before the despreading of the wide-band channel. For example, if thefrequency hopped CDMA is used and the first downconversion mixer changes the frequencyaccording to the spreading sequence i.e. despreads the signal, all stages after that processcontain narrow-band information and the possible advantages are lost. The disadvantage of thewide-band channel is naturally larger power consumption because of the high speed and largerparasitics. However, the scaling of the analog circuits does not obey the same laws as a standarddigital CMOS logic, and the current technologies allow the MHz-range channel bandwidths atthe baseband with a reasonable power consumption.

71

The despreading can be considered either as oversampling or averaging, because one symbol iscoded into a longer sequence, and an error in a single bit averages out when the information isrecovered from a long bit sequence. Many digital modulations recover the information from thephase shifts, which can be understood as transformation from ‘positive’ to ‘negative’frequencies, or vice versa, at baseband. Often, the maximum average power is at dc if thechannel response is presented as a double-sided spectrum in the frequency domain. Hence, theremoval of the information around dc is even more critical than elsewhere. Unfortunately, somefundamental constraints in circuit implementations produce noise or distortion exactly at dc oraround it. They are of special importance in the receivers, which have much gain at analogbaseband stages, like in the direct conversion architecture. Flicker noise and static dc offsetsdue to circuit mismatches are both critical. The dc error averages efficiently out in a CDMAsystem because the detected BER does not depend on a single incorrect transmission over dc.

Different techniques can be used to remove the dc component. At the system level, theappropriate model for offset removal with capacitive coupling is a first-order highpass filter.Estimates for an unspreaded QPSK signal are given based on BER simulations and eye diagramin [32] and [11], respectively. Both suggest that only 0.1 %, or even less, can be removed fromthe spectrum without deteriorating the reception significantly. The percentage describes theratio of the bandwidth to the total symbol rate. Because the notch removes both ‘positive’ and‘negative’ frequencies the notch bandwidth is twice the –3-dB bandwidth of the highpass filter,which is another typical parameter to specify the filtering. The effect of despreading requiresheavy simulations, because a much larger number of clock cycles must be simulated to recoverthe final data. The performance is shown without the effect of despreading and with processinggain of 6 dB in Figure 2.54. The SNR is defined at the input, and the x-axis of the 6-dB curve isscaled according to the processing gain. The simulations for larger processing gains areunattainable, but the low processing gain indicates already improvement in performance. Thedifferent curves are closer to ideal when spreading is used, and a 2 kHz cutoff frequency givesnegligible degradation in performance. A 2 kHz cutoff corresponds to 0.1 % removal of thespectrum when compared to the chip rate. If the same data rate is transmitted without spreading,the filter would remove 0.4 % of the total band, which would degrade the performancesignificantly. The benefit of the high cut-off frequency is the smaller component values, whichare easier to implement, although even a 10 kHz notch would require special techniques ifimplemented on-chip [11].

72

Flicker or 1/f-noise contribution is reduced in a wide-band channel. The flicker noise iscompared to thermal noise in [11] as

where is the thermal noise of the system, is the cutoff frequency of the highpass filter,is the corner frequency of the flicker noise, and is the noise bandwidth of the system. Atcorner frequency flicker noise is equal with the thermal noise, and hence the factor Anarrow- and a wide-band receiver are compared in Table 2.5 with two corner frequencies of20 kHz and 200 kHz, which present typical values in monolithic receivers. The reference iscalculated by integrating the thermal noise from dc to and the noise degradation due toflicker noise is given in decibels. The cutoff frequency of the highpass filter is set to 0.1 % ofthe noise bandwidth in both cases. The benefit of wide-band signal processing is evident whenthe immunity against flicker noise is estimated.

The implementation of a CDMA system is a complicated challenge, because the properoperation requires dynamic control all the time and the efficient use depends on the carefulfrequency allocation. Most parameters concerning the analog radio receivers are similar indifferent systems if the scaling of the bandwidth is taken into account. The special topicscovered in this subsection give a frame to estimate the differences from the implementationpoint of view. There are clear benefits but also new restrictions when the CDMA is adopted.Many aspects are definitely not discussed, and more new challenges will be found when thenew systems are launched in few years.

References

[1] T. Ojanperä, R. Prasad, ed., Wideband CDMA for Third Generation MobileCommunications, Boston, London: Artech House, 1998.

[2] L. E. Larson, ed., RF and Microwave Circuit Design for Wireless Communications,Boston, London: Artech House, 1996.

[3] D. K. Shaeffer, A. R. Shahani, S. S. Mohan, H. Samavati, H. R. Rategh, M. d. M.Hershenson, M. Xu, C. P. Yue, D. J. Eddleman, T. H. Lee, “A 115-mW, CMOS GPSreceiver with wide dynamic-range active filters,” IEEE J. Solid-State Circuits, vol. 33, pp.2219-2231, December 1998.

[4] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice-Hall, 1998.

73

[5] R. C. Dixon, Spread Spectrum Systems With Commercial Applications, ed., NewYork: John Wiley & Sons, 1994.

[6] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M.Djafari, M.-K. Ku, J. Min, E. W. Roth, A. A. Abidi, H. Samueli, “A single-chip 900-MHzspread-spectrum wireless tranceiver in CMOS---part I & II,” IEEE J. Solid-State Circuits,vol. 33, pp. 515-547, April 1998.

[7] H. T. Friis, “Noise Figures of Radio Receivers,” Proc. of the I.R.E., vol. 32, pp. 419-422, July 1944.

[8] H. Nyquist, “Certain Topics in Telegraph Transmission Theory,” Trans. Am. Inst.Electr. Eng., vol. 47, pp. 617-644, February 1928.

[9] A. B. Carlson, Communication Systems, Singapore: McGraw-Hill, 1986.

[10] B. Sklar, Digital Communications, Englewood Cliffs, NJ: Prentice-Hall, 1988.

[11] B. Razavi, “A 2.4-GHz CMOS Receiver for IEEE 802.11 Wireless LAN’s,” IEEE J.Solid-State Circuits, vol. 34, pp. 1382-1385, October 1999.

[12] R. Schaumann, M. S. Ghausi, K. R. Laker, Design of Analog Filters, EnglewoodCliffs, NJ: Prentice-Hall, 1990.

[13] H. Samueli, “An Improved Search Algorithm for the Design of Multiplierless FIRFilters with Powers-of-Two Coefficients,” IEEE Trans. on Circuits and Syst., vol. 36, pp. 1044-1047, July 1989.

[14] J. Vankka, M. Kosunen, K. Halonen, “Multicarrier QAM Modulator,” in Proceedingsof the IEEE Int. Symp. on Circuits and Syst., vol. 4, pp. 415-418, June 1999.

[15] P. Wambacq, W. Sansen, Distortion Analysis of Analog Integrated Circuits, Boston,Dordrecht, London: Kluwer, 1998.

[16] K. A. Simons, “The Decibel Relationships Between Amplifier Distortion Products,”Proceedings of the IEEE, vol. 58, pp. 1071-1086, July 1970.

[17] R. G. Meyer, A. K. Wong, “Blocking and Desensitization in RF Amplifiers,” IEEE J.Solid-State Circuits, vol. 30, pp. 944-946, August 1995.

[18] B.-K. Ko, D.-B. Cheon, S.-W. Kim, J.-S. Ko, J.-K. Kim, B.-H. Park, “A 1.8 GHzBiCMOS RF Receiver IC Taking into Account the Cross Modulation for CDMA WirelessApplications,” in Proceedings of the European Solid-State Circuits Conf., pp. 346-349,September 1999.

74

[19] B. Razavi, Principles of Data Conversion System Design, Piscataway, NJ: IEEE Press,1995.

[20] R. van de Plassche, Integrated Analog-to-Digital And Digital-to-Analog Converters,Boston, Dordrecht, London: Kluwer, 1994.

[21] R. Hartley, “Single-Sideband Modulator,” U.S. Patent 1,666,206, April 1928.

[22] D. E. Norgaard, “The Phase-Shift Method of Single-Sideband Signal Reception,”Proceedings of the I.R.E., vol. 44, pp. 1735-1743, December 1956.

[23] D. K. Weaver, “A Third Method of Generation and Detection of Single-SidebandSignals,” Proceedings of the I.R.E., vol. 44, pp. 1703-1705, December 1956.

[24] Z. Chen, J. Lau, “Circuit Requirements of a Direct Conversion Paging Receiver,”IEEE Trans. on Circuits and Syst.—II: Analog and Digital Signal Processing, vol. 46, pp. 802-807, June 1999.

[25] E. Dahlman, K. Jamal, “Wide-Band Sercives in a DS-CDMA Based FPLMTSSystem,” in Proceedings of the IEEE Vehicular Technology Conf., vol. 3, pp. 1656-1660, May1996.

[26] T. Ojanperä, J. Sköld, J. Castro, L. Girard, A. Klein, “Comparison of Multiple AccessSchemes for UMTS,” in Proceedings of the IEEE Vehicular Technology Conf., vol. 2, pp. 490-494, May 1997.

[27] W. Y. Ali-Ahmad, “RF System Issues Related to CDMA Receiver Specifications,” RFDesign, pp. 22-32, September 1999.

[28] S. C. Yang, CDMA RF System Engineering, Boston, London: Artech House, 1998.

[29] R. D. Gaudenzi, F. Giannetti, M. Luise, “The Effect of Signal Quantization on thePerformance of DS/SS-CDMA Demodulators,” in Proceedings of the IEEE GlobalTelecommunication Conf., vol. 2, pp. 994-998, 1994.

[30] R. G. Meyer, M. J. Shensa, R. Eschenbach, “Cross Modulation and Intermodulation inAmplifiers at High Frequencies,” IEEE J. Solid-State Circuits, vol. 7, pp. 16-23, February 1972.

[31] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE J. Solid-StateCircuits, vol. 31, pp. 331-343, March 1996.

[32] A. A. Abidi, “Direct-Conversion Radio Tranceivers for Digital Communications,”IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, December 1995.

75

3 Receiver Architectures

The first radio receivers about a hundred years ago were detectors connected directly to theantenna [l]-[2]. The early coherers were replaced with crystal detectors, but the first separatecomponent improving the sensitivity of the receiver was a vacuum tube rectifier with theproperty of amplification. Further improvements were achieved with tuned radio-frequency(TRF) receivers using self-oscillating detectors, and later with regenerative andsuperregenerative structures. In a regenerative receiver, a tuned positive feedback reduces theeffective resistance of the signal path, and thus enhances the Q-value and amplification of thetuned input circuit. The superregenerative receiver has a separate quench oscillator controllingthe effective resistance of the signal path periodically [3]. The feedback structures inherentlysuffer from stability problems, and careful adjustment was required to overcome the issue. Theinvention of the heterodyne principle by Fessenden in 1912 and further developments during1910’s by several people leaded into the superheterodyne receiver, which was completed to itsfinal form by Armstrong [4].

The use of a separate local wave in the receiver producing a beat to an audible frequency withthe input signal in a nonlinear element is the principle of heterodyne. The beat frequency isdefined as an intermediate frequency (IF) in a superheterodyne receiver. Instead of directdetection, the signal can be amplified more at IF, and select a limited band with fixed filtering.The distributed amplification to more than one frequency made it possible to have more gain,because the cross-coupling between stages did not cause instability when operating at differentfrequencies. Also, the isolation between the amplifying stages is much easier at IF. Another,significant benefit is the narrower noise bandwidth after the IF filter. Due to these properties thesuperheterodyne receiver was the most sensitive structure for radio reception. According toArmstrong the major advantage of the superheterodyne for commercial applications was themuch simpler required tuning by an unskilled user than in any other architecture rather than asuperior performance. The superheterodyne receivers displaced all other structures almosttotally by the early 1930’s, and became the only practical alternative for systems requiring highsensitivity. The automatic volume control, nowadays more likely called as automatic gaincontrol (AGC), was another major invention improving the performance and usability of radioequipment during 1920’s.

Transistors replaced vacuum tubes as active elements in the radio receivers slowly during1950’s and 1960’s. It was not until 1980’s when the IC technologies developed to the levelwhen aggressive integration of different radio parts was possible. Starting from baseband, theevolution has brought integrated circuits to the most of the IF and RF blocks today. The rapidgrowth of the cellular systems has been the driving force of the receiver implementationsthrough 1990’s. The concept of radio receiver has been estimated again because of the distinctcharacteristics of IC technologies [5], and superheterodyne is not anymore the only potentialcandidate to implement high performance radios. However, it is still the most commonarchitecture with significant advantages. A small size and power consumption are keyspecifications in mobile terminals, and the current demands can not be met without extensiveintegration.

Almost all architectures in recently published academic papers, and high-end industrial productsrely on heterodyning, because the receivers use one or several internal LO signals fordownconversion. As an interesting exception, a superregenerative receiver has been re-established using BiCMOS technology and operating at 1 GHz [6]. The heterodynearchitectures can be divided into four categories based on the image and its suppression. Thefollowing subsections cover the basic advantages and drawbacks of superheterodyne, direct

76

conversion, low-IF and wide-band IF receivers with references to reported implementations.The low-IF and wide-band IF receivers are often called as image-rejection architectures. In theend of the chapter, aspects of direct digitization or IF digitization are discussed. It can not beconsidered as an individual architecture, because any architecture can be basically implementedwith digital instead of analog signal processing if a sufficient number of bits with a highsampling rate is available. Hence, the given discussion will focus on the new requirements of anRF front-end and some specific techniques. The main emphasis is in the direct conversion, andthe specific issues will be discussed in detail in the next chapter.

In the early advent of the radio receivers, the nonlinear devices in the RF front-end captured thewhole radio spectrum. The detectors were tuned to a specific channel manually, but interferencefrom other radio sources was not limited otherwise. Sensitivity was the main concern, and thefiltering at IF in superheterodyne gave a significant improvement in performance by limitingthe noise bandwidth before the detection. It also removed out-of-band interferers, but only afterthe signal downconversion. After the discovery of basic bandwidth constraints of the radiocommunications the spectral efficiency has been a key issue in the radio design. The growingdemand of radio spectrum has increased the operating frequencies, and decreased the frequencyallocations for each individual system. Also, the different channels are located almost at theminimum theoretical distance from each other. Practically all systems require some frequencyselectivity against incompatible systems before active elements. In transceivers, this is typicallydone with a duplex filter. The main emphasis is to isolate transmitted power from leaking toreceiver if operated simultaneously. Other requirements are low loss to minimize thedegradation of sensitivity in the receiver and to avoid unnecessary power losses in transmission,and small size in handsets. Besides that, the filter attenuates out-of-band systems, but theattenuation may be only in the order of 25-30 dB at certain frequencies. Hence, it is assumedthat such a filter precedes all different receiver architectures having equivalent properties. In thereception, the duplexer should provide sufficient out-of-band attenuation to confirm that the in-band interferers dominate the degradation of performance due to nonlinearity. With thisprecaution the out-of-band interferers carry less power in the receiver chain than in-bandcomponents. However, their contribution can still be detrimental if located at the imagefrequency. It is fair to assume that out-of-band interferers have in the worst case 10-15 dB lesspower than the largest in-band components after the preselection. Of course, it depends muchon the system itself. The duplex filters can not be implemented with modern IC technologies,and the currently available devices have fixed responses and require a certain impedancetermination, typically to to maintain the response. This gives a similar RF interface to allarchitectures. More generally, the component in the receiver should be called as a preselectionfilter, because the duplexing property is needed only in the two-way terminals using the sameantenna. Both terms are used here alternatively when speaking about the signal processing inthe receiver.

3.1 Superheterodyne

A superheterodyne receiver removes the image by filtering before each downconversion stageas described in the previous chapter. A block diagram of the superheterodyne receiver with aquadrature demodulator is given in Figure 3.1. The first mixer converts the desired channeldown to a fixed IF. The first LO signal is tunable over the system bandwidth, giving thesmallest possible relative tuning range for the oscillator. The implementation of voltagecontrolled oscillators (VCO) and complete synthesizers at RF has been difficult for ICtechnologies due to stringent phase noise requirements. The recent results indicate improvedperformance and integration level, but the topic is not included here any further. It can be

77

assumed that all architectures using a tunable first LO at RF require an equivalent phase noisebehavior.

The first IF frequency must be chosen such as the image at any possible LO frequency liesoutside the system band, and hence is attenuated by the preselection filter. The fundamentallimit for the first IF in a superheterodyne receiver can be given as

where is the bandwidth of a particular system, or in fact, the bandwidth of the preselectionfilter. The channel selection filter is located at IF. It attenuates all other channels to aninsignificant level compared to the desired channel. After that the selectivity is not an issueanymore. The last downconversion stage in Figure 3.1 converts the modulated channel tobaseband, and the gain depends on the appropriate level at the input of the detector. Thelowpass filter at the baseband presents matched filtering in the detector. The previous is anidealistic view. The conversion to the baseband can be performed in several IF stagesdistributing the adjacent channel attenuation and interference cancellation along the chain. Apart of it can be allocated also to the baseband or change the architecture to image rejection atany downconversion stage. The trade-off comes from the subject whether it is ‘cheaper’ withrespect to the fabrication cost or power consumption add another IF stage, includingdownconversion, amplification and filtering, than process the signal at a higher frequency withhigher parasitics and narrower relative bandwidths.

Due to different characteristics of various technologies the optimization is a very complicatedtask. The position as the most common architecture is based on two facts. The long-termexperience on the implementations of superheterodyne receivers for different systems isunquestioned. The reason for that is the capability to avoid the problems of the insufficientimage rejection and the offsets or increment noise in the baseband processing if designedcorrectly. All other architectures try to circumvent one or both of them, and they are developedmainly because the superheterodyne is incompatible to full integration with currenttechnologies. Due to the image frequency limitation, the first IF is typically at least 30 MHz,and sometimes over 100 MHz. The relatively narrow channel bandwidth requires selective andlinear IF filtering, which is not feasible on-chip.

The filter after the RF amplifier is needed if noise at the output of the amplifier is significant atthe image frequency. The selectivity of the amplifier output is typically not sufficient for thenoise reduction. Otherwise, noise from both sidebands folds at the same frequency in the

78

downconversion, and can double the noise contribution of the low-noise amplifier (LNA) in thesystem. Therefore, the filter is called as an image filter. The attenuation in the image filter is notas critical for sensitivity as in the case of preselection because a substantial amount of gain infront of the filter compensates the loss. The external filter requires matching of the LNA outputand mixer input. In some cases, the image filter must also attenuate some out-of-bandinterferers to avoid unreasonable linearity requirements of the mixer as discussed in connectionwith the cross-modulation in the previous chapter. The RF image filter can be replaced with animage-rejection front-end, which includes two mixers and appropriate phase shifters [7]. Theycancel the image at the IF output of the mixer with the cost of extra hardware. An excellentmatching is however required.

The definition for the noise figure of a downconversion mixer depends on the architecture. Ifthe signal is downconverted to baseband, the double sideband (DSB) noise figure should beused because the modulated signal and internal noise of the mixer are converted from the sameband located at both sides of the LO. This can be applied only to the last downconversion stagein Figure 3.1, where noise figure is not so critical. When the downconverted frequency differsfrom zero a mixer converts its internal noise from both sidebands to the same IF. Hence, thesingle sideband (SSB) noise figure is an appropriate definition. The input bandwidth of a mixeris normally wide enough that noise at both sidebands is almost the same. However, the noisesource at the input is only at one sideband, and therefore the difference between DSB and SSBnoise figures is always less than 3 dB [8]. For example, the equivalent SSB noise figure is12.8 dB if DSB noise figure is 10 dB and noise at the input of the mixer is flat.

The use of two or more oscillators operating at the MHz or GHz range and the synthesizerproducing a dense raster of high precision controls for a VCO at RF introduces the demand of acareful frequency plan. The internally generated signals also include the digital clock, and in thecase of a tranceiver the synthesizer and oscillators of the transmitter. The internal signals andtheir harmonics can mix with each other or with strong input interferers, and generate spurs atthe desired radio channel either at RF or any IF. The protection methods against mixing includeisolation of different signals, as small signal levels as possible, a sensible choice of frequencies,a small number of internal frequency references, and different averaging techniques, likeCDMA. The power levels or voltage swings of internal references can not be reducedsignificantly especially if compared to the supply voltage, which scales down along thetechnology. The reference signals are located closer to each other when the structures areminiaturized, which complicates the isolation. On the other hand, long interconnections withlarge inductive and capacitive coupling can be avoided. Hence, the problems are changing, butthe frequency planning is still needed. The superheterodyne receiver is the most vulnerablearchitecture because of the use of more than one high-frequency oscillator. The art of frequencyplanning is not discussed in detail. It would require specific data of the internal structure of thereceiver or tranceiver, and detailed knowledge of the signaling environment of the system. Onlysome comments on the so called ‘half IF’ problem are given [9]. An interferer, which is locatedexactly between LO and the desired channel i.e. can fall at IF with twodifferent mechanisms. It either mixes down with an LO and experiences second-ordernonlinearity as or its second harmonic mixes down with the secondharmonic of LO as Hence, the second-order nonlinearity may be significantalso in superheterodyne receivers although rarely considered as an issue. The half IF problemcan be reduced if the preselection filter attenuates the component in all cases. Then, the IF mustbe chosen as

79

which is four times the minimum IF given in Equation (3.1). Some reported IC implementationsof superheterodyne receivers or their front-ends are given in Table 3.1. It can be seen that theselection of the first IF is often based on the availability of certain commercial bandpass filtersfor channel selection. For example, all given DECT receivers use a 110 MHz first IF. On theother hand, a 71 MHz IF is a common design practice in GSM because it is larger than theoriginal 70 MHz operation range from 890 to 960 MHz including both up- and downlinktransmissions [10].

3.2 Direct Conversion

A direct conversion receiver converts the carrier of the desired channel to the zero frequencyimmediately in the first mixers. Hence, the direct conversion is often called also as a zero-IFreceiver, or a homodyne receiver if the LO is coherently synchronized with the incomingcarrier. The latter term is mainly historical in connection with the radio receivers. Thesynchronization of the LO directly to the RF carrier can be avoided with other techniques in

80

current applications, and in recent literature, homodyne is actually used mostly in opticalreception. Tucker proposed his own term ‘synchrodyne’ to be used in the case ofsynchronization of an ‘otherwise free oscillator’ to the incoming carrier [25]. However,Tucker’s own doubts about the possibility to change terminology have proved to be real.Because the synchronization of the high frequency LO is not necessary, the direct conversionand zero-IF are more generic terms to be used in this context. The condition for the directconversion can be defined uniquely as

The direct conversion reception has been initially considered already in the 1920’s, but the firstpractical application was established in 1947 for a measuring instrument [25], [5]. The inherentimperfections of direct conversion, discussed later in this section and in the next chapter,prevented the use of the scheme in most applications. It was not until the development of the ICtechnologies, which made it possible to adopt the direct conversion architecture in certainportable receivers. The evident benefit of the potential increase in the integration level to reducecost, and the rapid growth of the cellular market have been prominently focused the researchand advanced the knowledge from the 1980’s until today. The characteristic advantages anddrawbacks of the architecture are already recognized and collected in [26], [27]. Unlikesuperheterodyne, the direct conversion receivers are sensitive to several system dependentissues like modulation or duplexing. Every application has different prerequisites and thereforethe suitability and specifications must be considered in each case independently. This is actuallytrue for all architectures, which do not filter out the unwanted channels sufficiently at highfrequencies. Only the typical drawbacks vary between the different architectures. This sectiongives a general introduction of the characteristic properties in direct conversion receivers. In thenext chapter, some aspects are analyzed in detail and available techniques to solve the existingproblems are referred with special emphasis in wide-band CDMA systems. Also, differentbuilding blocks will be discussed.

A block diagram of the direct conversion receiver is given in Figure 3.2. Two downconversionmixers must be used for demodulation already at RF if a signal with quadrature modulation isreceived. Otherwise, a single-sideband signal with suppressed carrier containing quadratureinformation, like QPSK, would alias its own independent single-sideband channels inquadrature over each other as discussed earlier. This can be understood as the signal containsdifferent information below and above the carrier frequency, which should not interfere witheach other. Hence, the RF mixers are already a part of the demodulator although several otherprocessing steps are performed before the detection of bits. This is also a distinct benefit of thedirect conversion scheme, because the information at both sides of the carrier comes from thesame source having an equal power. Hence, the image power is always the same with thedesired signal and the quadrature accuracy requirements are only moderate as given in theprevious chapter. Thus, the required image rejection is realizable with IC technologies even athigh frequencies. A lowpass filter with a bandwidth of half the symbol rate is suitable forchannel selection. This can be implemented with an active on-chip structure. Because the signalpower is located at both sides of the carrier a DSB noise figure is applicable in downconversionmixers. This gives a noise advantage over the other architectures, and also no image noisefiltering is needed between the LNA and mixers. The external components in the signal path arenow limited to the preselection filter at the input. Hence, only the input of the LNA must bematched in order to maintain the filter response unchanged. The interfaces between other blockscan be optimized during the design independently to optimize the performance with respect tonoise, linearity and power. Of course, flexibility also increases the design complexity.

81

The drawbacks of the direct conversion, which limit the dynamic range and hence use in manyapplications, can be divided into two main categories. First, the interference can be exactly atdc. It can be removed for example with a very narrow highpass filter discussed in the nextchapter. Second, the distortion can be located around or close to dc but has a certain frequencyresponse, which covers a larger portion of the spectrum at the same band with the receivedchannel. The response can also vary in time, which makes it impossible or at least very difficultto separate from the desired signal. Direct conversion receivers suffer from the fact that the gainbefore the conversion to baseband is relatively small, which means that the amplificationrequired at the baseband before the detector or ADC is large, typically in the order of 60-100 dB. The gain at RF can not be increased arbitrarily, not only because of the unreasonablepower consumption but also mainly due to the linearity constraint. Several differentnonidealities are shown in Figure 3.3.

The constant dc offsets come either from the inevitable component mismatches in thedifferential signal path or from the self-mixing of the LO signal. The latter is caused by theleakage of the LO signal to the input of the mixers, which mixes then with itself and generates aconstant dc offset. The coupling mechanisms include capacitive coupling, coupling throughsubstrate and inductive coupling, for example through bondwires if the LO is brought from anoff-chip source to the mixers. The LO can leak directly to the RF port of the mixers or to theinput of the LNA. In the latter case, the leakage will be amplified by the gain of the LNA. Theleaked LO signal can also propagate to antenna because of the finite reverse isolation of theLNA and preselection filter and reflect back from the interfaces having mismatch. Finally, if theLO radiates from the antenna and reflects from other objects back to the receiver, the offset dueto self-mixing varies in time. Also, the dc offset varies if initial conditions in the receiverchange. The abrupt change in the LO frequency or gain setting typically charges or discharges

82

memory elements i.e. capacitors, requires a finite settling time, and defines a new level for theoffset.

The dc offset has two possible consequences. If not cancelled out, it will be amplified in thereceiver like the incoming signal. In the worst case, the offset compresses the circuits at theback-end of the receiver and hinders the detection. If this is prevented by the automatic gaincontrol, the amplification may be too low for the detection of a weak signal from thequantization noise of the detector. The offset component can be considered also as an in-bandinterferer if not removed with special techniques. Some cancellation techniques will bediscussed in the next chapter. The settling time is a typical trade-off in those schemes. Thepossible offset due to self-mixing can be estimated using the LO level in the mixers, LO-to-RFisolation and gain of the receiver. A typical isolation is 60 to 70 dB, and the required LO levelapproximately 0 dBm from a source. Hence, the LO leakage at the RF input is from-70 dBm to -60 dBm. If the total gain is 100 dB from which 30 dB is at RF, the voltage swingsat the input and output of the baseband are and respectively. The outputvalues are definitely not acceptable, but in this example it was assumed that the signal wouldreflect completely back from the input of the LNA. The sensitivity to offsets is howeverevident, and some cancellation method is practically always adopted in analog circuitry.

The spurious emissions from the antenna outside the transmission band are typically regulatedin the system specifications to avoid the interference in other radio equipment. In directconversion receivers, the radiation of the LO signal from the antenna is susceptible to produceinterference because the leaked LO is attenuated only by the passband loss of the preselectionfilter between the input of the LNA and antenna. For example, in GSM specifications themaximal spurious emissions caused by the receiver are 2 nW i.e. -57 dBm at the band from9 kHz to 1 GHz and 20 nW from 1 GHz to 12.75 GHz [29]. Those conditions are met in theexample given above.

The interference, which has frequency response around dc, has three main sources: flickernoise, envelope distortion and self-mixing of RF. They will be considered separately in the nextchapter with respect to the circuit design issues. Flicker noise originates from the basebandcircuitry, and should be taken into account already in the downconversion mixers. Especially innarrow-band receivers with a small RF gain, flicker noise can be the dominant noise mechanismas given in the previous chapter. RF self-mixing exists when an unwanted channel couples tothe LO port of the mixer and modulates the LO signal. The signal mixes with itself producing areplica around dc at the passband of the desired channel. Another mechanism, which produces asignal-dependent component at or around dc is the second-order nonlinearity as described in theprevious chapter. The source of the distortion in both cases can be located at any possiblefrequency passing the preselection filter, or actually it is a combined effect of all transmissionswithin one system. A conceptual view of the two different mechanisms and their sources in adirect conversion receiver is given in Figure 3.4. Ideal multiplication is assumed in the mixer.Linear and nonlinear signal processing paths are drawn in parallel only to distinguish thedesired and unwanted functions. The LO-to-RF leakage is placed before the nonlinear elements,but the choice is arbitrary because it can be assumed that the products of higher harmonics arenegligible compared to the fundamental self-mixing product. Before analyzing the differenteffects the concept of amplitude modulation must be reviewed briefly. In the previous chapter,an RF signal carrying an amplitude envelope was given as

where is the constant part of the amplitude and the amplitude envelope, whichmodulates the carrier. The input signal can also have phase or frequency modulated

83

components, but they are neglected in the given equation. In the constellation diagram, theyappear as a rotation of vector with a constant magnitude around the origin. If the modulatedsignal has a constant envelope, like GMSK, m is zero. Otherwise, the modulation caries avariable envelope, like QPSK, and the spectrum of the envelope spreads around the carrier ofthe modulated channel. Second-order nonlinearity generates two replicas of the modulatedchannel, one at dc and the other at as

Hence, a part of the envelope is converted down to dc due to the second-order nonlinearity andoccupies a bandwidth relative to the modulation. A weak signal can be buried under thedownconverted envelope preventing the detection. The channels having a constant envelope canproduce only a dc component relative to the square of the input power as seen from Equation(3.5). A modulated channel is not the only possible source of envelope distortion. Time-dependent effects like changes in the transmitted power, especially the power ups of newchannels, establish amplitude variations although the envelope is constant during thetransmission of data bits. Also, fading in the radio path should be considered as a source ofenvelope variations. Envelope distortion with respect to the circuit design parameters andselected modulations will be discussed in the next chapter.

The envelope distortion generated due to the second-order nonlinearity follows a differentpropagation path than the received channel because it is never at the same frequency exceptafter the conversion to the baseband. Also, the baseband and double-frequency componentsshould be considered separately in Figure 3.4. The received channel proceeds through the RFamplifier, downconversion mixer and baseband amplifier having a total gain ofbefore the channel selection. The envelope distortion at RF is split into two blocks, because ac-coupling can be used to block the baseband part of the distortion before the mixers. However,there are often active circuits between the coupling capacitors and the commutating switches,like current sources or active input stages stacked in the same supply current path. They can notbe removed before the conversion. An ideal mixer upconverts the components from the vicinityof dc and downconverts the distortion from the double-frequency to the LO. Hence, they can be

84

injected to the output only by secondary effects. The leakage of the baseband signal to theoutput is given with in Figure 3.4. It is caused by the deviation from the 50 % duty cycle inthe commutating switches. The sources can be nonidealities in the switching device, in the LOsignal or in the output load. The selected mixer topology determines the susceptibility to theseissues. The switches contribute also second-order nonlinearity to the output. They are included

If the arbitrary time delay in Figure 3.4 is zero, the self-mixing behaves like envelopedistortion. Only the term in Equation (3.5) will be replaced with The

order of 25 to 30 dB. Hence, dominates the performance if it is not much smaller thanin the given presentation because the signal is the same in both cases. However, the twomeasures are not directly comparable, and the argumentation alleviates only the significance ofboth parameters, which are difficult to distinguish in the practical implementations. The abovediscussion assumed correlated signals in the unwanted operations. It is true if the signal issquared in a nonlinear element. However, the time delay shifts mixed data streams with respectto each other. Hence, the information is not perfectly correlated any more in the case of self-mixing. Probably, this is not very significant if the consecutive symbols can be located at anypossible constellation points with an equal probability. However, in the transmission of aconstant envelope signal all transitions are not possible. The time shift can spread the envelopespectrum from a fixed dc offset in the case of self-mixing because different relative transitionsin the time-domain are possible.

The type of modulation and its filtering in the transmitter not only define the bandwidth of thechannel selection filter, but also give specific requirements for the downconversion mixers andthe analog baseband processing in direct conversion receivers. The spectral shape of themodulated channel has a direct impact on the possibilities to remove dc offsets. This has beenutilized in paging systems, which use binary frequency-shift keying (BFSK). The notch in thepower at the carrier frequency allows significantly relaxed highpass filtering possibilities forexample compared to QPSK or GMSK discussed in the previous chapter. The systems usingmodulations having a constant envelope are basically insensitive to wide-band envelopedistortion, but this does not guarantee the protection against envelope problems. A third factoris the filtering of the modulated channel in the transmitter. For example, the envelope of aQPSK signal transmitted using root-raised cosine filtering differs from the system level raisedcosine filter, which is a combination of the transmitter and receiver filters. This must be takeninto account when envelope distortion is evaluated. Examples of amplitude envelopes indifferent cases will be given in the next chapter.

Another parameter, which limits the RF-to-LO leakage besides of self-mixing is the LO pulling.It means that a strong near-by interferer, for example an adjacent channel, leaks to the oscillatorand injection locks the VCO to a slightly different frequency. The LO pulling must beprevented almost perfectly because of the tight frequency stability requirements in cellularsystems.

85

terms and describe the RF gain, conversion gain of the mixer and RF-to-LOisolation, respectively. The leakage must be small because the preceding gain is typically in the

in together with the baseband circuitry. The envelope distortion is an issue at the basebandbefore sufficient filtering of other channels. The double-frequency component generated at RFcan convert down with the second harmonic of the LO signal. The second harmonic is howevertypically much smaller than the fundamental tone and it converts only the second harmonic ofthe desired channel directly down to the baseband. This is probably not a serious issue in thedirect conversion scheme, but the conversion of noise from the second harmonic may degradethe sensitivity slightly.

3.3 Low-IF

A low-IF receiver violates the first IF selection criteria of the superheterodyne receiver given inEquation (3.1), but does not convert the signal directly down to baseband either. Hence, a low-IF receiver can be defined based on the first IF as

Frequency is the center frequency of a modulated channel. To avoid the self-aliasing of theradio channel due to the conversion on the both sides of the dc, the lower limit in Equation (3.6)should be Two different choices of the IF are given in Figure 3.5. If the lowest IFnext to dc is chosen, flicker noise, self-mixing and envelope distortion should be considered.Those topics will be discussed in the next chapter, which describes the direct conversionarchitecture in detail. In the discussion of low-IF receivers, especially the effects of amplitudeenvelope and self-mixing are often totally neglected. The power maximum is not at dc after thedownconversion, but the spectrally efficient modulations, like QPSK with a roll-off 0.22 inWCDMA, do not allow much space between dc and the lower edge of the modulated channel.The flicker noise contribution is probably negligible at least in wide-band systems, but thesignal envelope and self-mixing are of interest. A distinct benefit of low-IF compared to directconversion is the insignificance of the static dc offset component, which can be removedwithout severely deteriorating the modulated channel. If the maximal power of the adjacentchannel is much smaller than the other in-band channels, like in GSM, the lowest possible IF isa sensible choice, because the image rejection requirements are relaxed. It does not suffer fromthe half IF problem either. Flicker noise, self-mixing and envelope distortion can be avoided if ahigher IF is chosen. It has two significant drawbacks compared to previous. Half IF is apotential problem due to the second-order nonlinearity, and the image rejection requirementscan be much higher as shown in Figure 3.5. A strict image rejection requirement is the majordrawback of the architecture, which speaks for the choice of IF next to dc. Another option is toselect a LO which has the image between two adjacent channels. This gives a significantadvantage in the systems, which have a relatively loose channel spacing and smooth pulseshaping filters.

86

A block diagram of the low-IF receiver is given in Figure 3.6. The signal is divided intoquadrature branches in the first downconversion. Otherwise, the unwanted image is inseparablefrom the desired channel. The channel selection is performed with a bandpass filter. Because ofthe low frequency operation it can be integrated if the IF is located close to dc. In principle, alowpass response is sufficient for the IF next to dc, but a bandpass filter removes also staticoffsets and is therefore preferable. The unwanted image can be cancelled and I/Q data detectedeither with complex filtering at the low IF or with real filters and four mixers at the finalconversion to baseband [28]. These blocks are not shown in Figure 3.6. The background of thecomplex signal processing is described in [29]. Passive sequence asymmetric polyphase filtersare examples of analog filters, which are suitable for selection of positive and negativefrequencies in the processing of complex signals [30]. At low frequencies, a complex filter canbe synthesized with any available implementation technique, like an active-RC or switched-capacitor (SC). The digitization of an analog signal does not require extra bits or increasedoversampling if the image is cancelled before the A/D-conversion. The dynamic range betweenthe desired channel and the image should be added to the digital word length if cancellation isperformed digitally. The image noise at the output of the LNA is damped like the imagechannel, and therefore practically negligible. However, the SSB noise figure is a correctdefinition for the two independent downconversion mixers at the system level.

87

The specification of the image rejection ratio is not unambiguous, because it depends on thechosen IF and the system requirements. The system specifications cover the spectral mask, butdo not give direct values for acceptable image levels, because they are not a problem in a‘standard’ superheterodyne reception. Therefore, the specification must be calculated fromseveral independent prerequisites, and select the worst case condition. In the previous chapter,one possible method was given. It assumed a 3-dB rise of the signal level compared to thesensitivity specification and allowed that the image can contribute an equal amount of in-bandinterference as noise. An example is taken from the GSM specifications. The signal must beapproximately 9 dB above all unwanted in-band interferers in all cases, and the maximumpower levels at one, two and three channels away are 9, 41 and 49 dB above the desiredchannel, respectively. Hence, the IRR must be 18 dB to attenuate the adjacent channel to theacceptable level if it is located at the image frequency. In that case, the signal located twochannels away from the desired is adjacent to the image. If required that it should be only 9 dBabove the desired channel IRR must be 32 dB, which dominates the performance. Otherchannels are not significant with this selection. If the image is two channels away from thedesired, the IRR specification is 50 dB using the same argumentation. Constant IRR curves areplotted in Figure 3.7. They indicate the acceptable amplitude and phase errors for fixed IRRrequirements. The equation is given in the previous chapter.

88

Mismatches in analog circuits are inevitable and limit the image rejection. A high IRRperformance is not possible without special techniques even in modern IC processes. Themismatch due to cut-off frequencies in analog filters is possible to circumvent with widerbandwidths than necessary and adding extra bits in the A/D conversion. In the digital domainthe critical operations can be performed with a higher precision. The gain mismatch betweenlow frequency signal paths can be compensated with AGCs, but the phase and especiallyamplitude errors in high frequency structures need special attention in the low-IF architecture.With a double quadrature downconverter in Figure 3.8, a phase error less than 0.3° and anamplitude error of 0.5 dB is achieved from 500 to 900 MHz without any external tuning ortrimming [31]. Also, digital techniques using reference signals or blind adaptive cancellationare developed [32], [33], [34]. They compensate the I/Q imbalance in the digital domain. Thereported schemes predict 15 to over 20-dB improvement in the image cancellation.

A modification of the low-IF is the double-low-IF architecture [35]. It uses the Weaverarchitecture, but converts the low-IF signal up to a fixed IF in the second pair of mixers andsubtracts the I and Q branches before the channel selection. Hence, the image frequencies arelocated again around both sides of the LO, but instead of RF, at a relatively low frequency, andthe desired channel can be separated with a bandpass filter. The topology requires quadratureLOs for both mixers, and a lowpass filter to remove the image of the second LO beforeupconversion. At the output of the second IF, a 50-dB image rejection was reported althoughthe same group has given conflicting results of only 23-dB IRR for a slightly different setup in[36]. However, they claim that the performance meets the GSM specifications. The sameapproach has been earlier proposed for the direct conversion [37]. The signal is first converteddown to a zero IF and then upconverted using a Weaver architecture to a low IF.

A DCS-1800 front-end using CMOS has been developed based on the low-IF topology [38], Itincludes the LNA, quadrature mixers, lowpass filters and AGCs in the signal path, and VCO,synthesizer and quadrature generation structures. Also, a modulator and an RF preamplifier fora direct conversion transmitter are implemented on the same die. The lowest possible IF, i.e.100 kHz, was chosen and the reported phase and amplitude accuracy of the I/Q branches is 0.6°and 0.4 dB, respectively. A new version of the receiver is given in [39]. The reported worst-caseIRR was 32.2 dB and the power consumption excluding synthesizer was 113 mW from a 2 V

89

supply. The noise figure of 8.2 dB still suffers strongly on the flicker noise at 100 kHz. The 10-bit ADCs, final digital channel selection and demodulation are placed on a separate chip.

Another example of low-IF is a GPS receiver implemented also with CMOS [40]. In GPS, theCDMA transmissions using consumer and military codes are broadcast at the same 20 MHzband around 1.57542 GHz. The consumer code occupies however only 2 MHz of bandwidth,and no other interferer than the military GPS exists at the same band. The military code useslarger bandwidth and therefore smaller power spectral density. Hence, the image includes onlya side-lobe of the modulated consumer channel and a portion of the military channel if a low IF,like 2 MHz, is chosen. Therefore, the low-IF architecture is a sensible choice without the imagerejection problem for commercial GPS applications.

3.4 Wide-Band IF

An image-rejection receiver suitable for integration, which utilizes two consecutivedownconversion stages but performs the channel selection completely after the seconddownconversion, is proposed to reduce the problems of image signal or direct conversion to thebaseband [41]. Actually, the same idea has been given already in [42]. The first LO was set to

or In the former, the second stage uses the same LO in quadrature. The lattergenerates the second quadrature LO of from the first with two flip-flops and an inverter.The background for the proposal was to avoid the LO-to-RF leakage and self-mixing problemsof direct conversion. However, no experimental results were given on the paper. The secondapproach is reported recently for a paging receiver in [43]. Originally the topology was called asa dual-conversion or quasi-IF and later as a wide-band IF. The architecture, which has beenimplemented with CMOS, is given in Figure 3.9 [44]. It is actually the same architecture asinvented by Weaver with the exception of the quadrature information recovery in the seconddownconversion stage. The arrangement of the second downconversion is however the samecomplex mixer as can be used in the back-end of a low-IF receiver instead of a complex filter asmentioned in the previous section. The difference with the low-IF and a distinct benefit of thearchitecture is the adaptation of such a high IF that the image is outside the passband of thepreselection filter. Hence, the image is an out-of-band signal, which is attenuated before theactive circuitry. This allows feasible specifications for the IRR in a wider range of applications.

The wide-band IF architecture follows exactly the same frequency selection criteria for the firstIF as superheterodyne including the half IF issue. If the second mixer stage does not convert thesignal directly down to baseband, the secondary image is a potential problem [9]. Also, the in-band image channel is then a problem in the second downconversion, like in the low-IF.However, all designs except of one referred in this section use a zero IF after the mixers. Thechannel selection filters are placed after the second downconversion. The lowpass filtersbetween the mixers are only needed to suppress the upconverted product generated in the firstdownconversion. Typically, the limited output bandwidth of the RF mixers together with theinterconnection to the second mixing stage attenuate the high-frequency products sufficientlywithout any extra components. The desired sideband can be easily chosen when the polarities ofthe signals are reversed before the summation at the baseband [44]. The property has beenadopted using carefully selected frequencies to minimize the hardware in a dual-band receiver[45]. The wide-band IF does not necessitate the Weaver architecture. A single mixer can beused to convert the signal to the first IF, and quadrature mixers perform the finaldownconversion [46]. The structure saves three mixers, but mandates all image rejection to theselectivity of the preselection filter and the LNA load, which has a high Q in this case.

90

A fixed first IF was proposed in [44], which relaxes the phase noise requirements of the high-frequency LO. A wide-band phase-locked loop (PLL) can be used to suppress the phase noise toan acceptable level, because no fast settling times are required. Instead, the second LO musthave higher relative tuning range, and the spurs from the PLL may mix with undesired strongsignals at IF producing distortion at the channel of interest. The fixed first IF is however not anecessary condition for the wide-band IF. The desired channel can be converted to a fixed IFwith the VCO at RF as well. The use of two high-frequency LOs rises in any case the demandof a careful frequency plan discussed for example in [45]. The LO-to-RF leakage is howeverless important, because the first LO is outside the passband of the preselection filter like insuperheterodyne. Both the low-IF and direct conversion architectures can produce unacceptableemissions to the antenna due to the insufficient LO-to-antenna isolation.

The wide-band IF topologies transfer the typical downconversion problems of a directconversion into the second mixer stage. The only difference is that the critical operationfrequency is scaled down by a factor of 2 to 20. The distortion generated around dc in the firstmixers is not significant because the portion, which passes the possible ac-coupling between thestages, is mainly upconverted in the second mixers. Hence, the most critical blocks are thesecond mixers. They must handle all radio channels passing the preselection filter, which meansthat the linearity is a major concern. The lower operation frequency allows some moreflexibility in the transistor sizing, a smaller parasitic loading of different nodes, and possiblybetter matching between components. Otherwise, the problems are equivalent with the directconversion. The second-order nonlinearity causes envelope distortion around dc, and flickernoise can degrade the sensitivity at the output of the baseband. Therefore the benefit of thewide-band IF architecture compared to the direct conversion is subject to the fact whether it ispossible to increase the gain before the conversion to the baseband without degrading theoverall linearity or at least perform the same amplification with a smaller power consumption.Linearity becomes more critical when the gain increases, and the characterization shouldinclude both IIP3 and IIP2. It means that the wide-band IF trades-off with the similar problemsas the other receivers suitable for full integration having a slightly different prerequisites.Neither the possibilities to optimize the performance using a controlled gain at RF or IF changesignificantly because all interfering channels are present before the final conversion down to dc.The different recently reported implementations are compared in Table 3.2. The total voltagegain before the conversion to the baseband including the gain of the second mixers is in therange of 23-35 dB, which is comparable to the typical values in direct conversion receivers.

91

At the baseband, the signal must be amplified to the appropriate level for the detector or ADC,which means that the overall gain of the analog receiver should be the same as with any otherarchitecture using a similar interface to DSP. Hence, the problems of static dc offsets due tomismatches are not avoided if the combined RF and IF gain is not increased compared to theRF gain in direct conversion. The self-conversion of the second LO is however less significantif assumed that the parasitic coupling to the input of the mixer is smaller at lower frequencies.The same applies also for the self-mixing of the input signals.

The correct definition for the noise figure of different mixers is of importance. The first mixersconvert only one sideband down to IF while both sidebands carry information in thedownconversion to the baseband. Therefore, the SSB noise figure is correct for the first mixingstage while DSB should be used in the second stage. The LNA contributes noise only from onesideband if quadrature downconversion is used or the selectivity of the LNA load suppresses theother sideband sufficiently.

Recently, dual conversion and low-IF are combined in [47]. The out-of-band image rejectionfor a 190 MHz first IF is 75 dB including 40 dB in the preselection filter. The in-band imagerejection at a second IF of 5-15 MHz is 55 dB. The high numbers have been achieved usingaltogether 11 polyphase stages at both LOs and IFs. Five of them are located at the second LOproviding the in-band IRR.

3.5 Direct Digital And Digital IF

Digital signal processing would provide significant benefits compared to analog circuitry if theconversion to digital will be brought closer to the antenna. The matching problems ofquadrature branches are avoided as well as dc offset and flicker noise when the downconversionto baseband is performed digitally. However, the problems associated with the analog-to-digitalconversion and downconversion of the IF or RF signal are difficult to solve even withsubmicron technologies. The increased resolution and speed requirements to the powerconsumption of the A/D converters will be discussed in the next chapter. Also, the increasedcomplexity of digital circuitry should be considered carefully in the implementations. To

92

achieve the benefits mentioned above a higher speed, better resolution and more digital gatesare needed, which means at least a larger chip area and higher power consumption. Whether thetrade-off is reasonable or not using current technologies will not be considered here any further.In this section, different approaches of ‘digital’ receivers and general limitations of subsamplingtechniques in radio receivers will be discussed. Subsampling can also replace a conventional RFmixer, but the fundamental restrictions are basically similar compared to the digital approach.An RF subsampling mixer will be described in the two following chapters.

In principle, the digital receivers can follow any of the architectures discussed above withrespect to the frequency planning or filtering arrangements. Here, the alternatives are limitedonly to the digital IF in superheterodyne and digital RF in direct conversion. Hence, bothinclude only one digital downconversion stage. Block diagrams of the digital IF and RFreceivers are given in Figure 3.10. Later the term digital baseband will be used in connectionwith the A/D conversion. It means that practically all filtering except of antialiasing isperformed digitally, but the desired channel is downconverted either at the baseband or at somelow IF in the analog domain. The both topologies in Figure 3.10 actually assume that theNyquist-rate sampling is adopted in the ADC. Hence, especially at RF digitization the samplingrate must be unreasonably large i.e. 2-4 GHz in typical cellular systems, but aliasing at the inputof the ADC would not be a problem. There are no reported Nyquist-rate ADCs capable of RFreception and only few converters operating at or above 100 MS/s with 10 to 14 bits resolution[48], [49], [50]. Those are capable of digital IF reception if their resolution is sufficient for thespecific application.

In wireless systems, the band of interest is much narrower than the Nyquist rate in sampling.Hence, the bandpass converters are more suitable for digital receivers in cellularapplications [51]. They provide a large resolution only at a narrow band, but can tolerate largeinterferers within the Nyquist rate. Extensive research effort has been paid recently on thosesystems. For a 200 kHz radio channel an 11-bit ADC has been reported using 200 MHz IF[52]. For larger bandwidths, a 58-dB dynamic range is achieved in modulator using 85 MHzIF and 1.25 MHz input band [53]. A flexible input bandwidth up to 70 MHz using 55.5 MHz IFand 4 GHz sampling rate is reported in [54]. The feasibility of a digital RF receiver usingmodulator is studied in [55]. The modulator converts 200 kHz bandwidth at 950 MHz using 3.8GHz clock frequency. These examples show that digital IF receivers are already potentialcandidates in some applications, but ADC connected directly to RF front-end is still a futuristicvision.

93

Instead of sampling at twice the RF or IF frequency, a bandlimited signal can be also sampled ata lower rate. The information will not be aliased when the sampling rate is higher than twice thesignal bandwidth at the input of the sampler. Such a block is often called as a subharmonicsampler or a subsampling mixer. Subsampling allows a significantly lower clock rate, andhence potentially a lower power consumption. This discussion is limited only to mixing in anRF front-end, but subsampling can be adopted also in the downconversion from IF with lessstringent requirements [51]. Subsampling mixers have been used especially in microwave testinstruments [56], but several experiments have also been established for wireless receiverapplications. The subsampling mixer has been used as a stand-alone RF downconverter block in[57] and [58]. Higher linearity has been reported compared to a Gilbert-cell bipolar mixer.However, noise behavior is fundamentally poorer in bandpass sampling applications because ofaliasing [59]. This is clearly a dominant problem, and in both cases the reported noise figure ishigher compared to more conventional mixer structures. The subsampling mixer is also apassive structure and does not provide any gain, which would protect the receiver from noise ofthe successive blocks. A discrete-time analog front-end consisting of a downconversion stageusing subsampling and a narrow-band filter suffered from the 47 dB noise figure, which isabsolutely too high despite of any realistic RF amplification [60]. Subsampling is also used in aRF demodulator for a short-distance portable terminal [61]. Direct digitization using asubsampling ADC has been shown to be suitable for GPS reception in [62] and [63].

Noise aliasing is the most severe problem in the subsampling RF front-end. A simple model toestimate the performance is given in Figure 3.11. In the case of a wideband input, noise islimited by the first-order RC lowpass network consisting of a hold capacitor and a switchresistance in the conduction state The total noise of the sample-and-hold structure in the

94

discrete-time signal processing is at the output All that noise will be aliased within theNyquist rate in the sampling. Hence, the spot noise at the baseband can be written as

Noise figure of the subsampling mixer can be calculated from that by comparing the samplingnoise to the noise spectral density of the source resistance Thus, the noise factor is

The formula assumes that the gain of the desired signal is unity. It means that the RF signal iswell below the cutoff frequency of the sampler input bandwidth. Otherwise, the attenuation ofthe RF input signal degrades the noise figure. Hence, in the case of RF subsampling the pole ofthe sampler must be at the GHz-range. Basically, sampling rates of 50-100 MHz are sufficientto prevent aliasing of the signals after the preselection filter, but the noise figure is stillunreasonably high at that range as shown in Figure 3.12(a). The possible capacitor values forRF subsampling are around 1 pF, because the series resistance of the sampling switch can notbe made infinitely small with any applicable technology. Hence, the realistic noise figures forRF subsampling mixers range between 15-25 dB. This may be acceptable in some cases.However, the noise from the preceding stages will also alias in the subsampling process. Itmeans that noise should be bandlimited before the mixer. This can be done either with a RFbandpass filter or a narrow-band LNA. The external RF filters require typically matchedinterface to the sampler to maintain the frequency response. A separate buffering stage isprobably needed for matching, which on the other hand produces additional wide-band noise. Anarrow-band LNA may not be as efficient as a filter but the hold capacitor can be a part of theresonator. A method to optimize the interface between the LNA and a subsampler is given in[64]. The structure will be described in detail in chapter 5. Here, an estimate for the noise figureof the front-end will be given based on the equivalent noise bandwidth, of the LNA. It canbe calculated separately from the transfer function of the LNA. The presentation is simplifyingbecause it assumes that the noise spectrum is flat within the Nyquist rate at all frequencies. Forexample, with high-Q resonators this is not the case. However, a practical estimate for the noisefactor of a subsampling front-end can be given as

where is the voltage gain of the RF amplifier and the voltage gain of the matchingnetwork, which is ideally 0.5. The noise figure of the front-end is plotted as a function of theratio between the noise bandwidth and Nyquist rate in Figure 3.12(b). Matching is assumed tobe ideal, and the noise figure and voltage gain of the LNA are 3 dB and 20 dB, respectively.Three curves are plotted describing the noise figures of a subsampling mixer including theinternal noise aliasing. It is evident that a subsampling front-end would be feasible for wirelessapplications only if the filtering is very sharp or the noise figure requirements very loose. Thealiasing of the input noise is clearly the dominant source in the noise figure rather than theinternal noise of the mixer in most cases. An efficient technique to reduce noise aliasing due toLNA but to maintain a relatively slow sampling speed in a CMOS track-and-hold circuit isdescribed in [65]. The technological limitations including restrictions in high-speed sampling

95

and high-Q RF resonators limit the possibilities to utilize the subsampling approach. Hence, itcan not compete with conventional RF front-ends, but the same principle applied to IF signalprocessing is more realistic. A schematic of the subsampling front-end with all requiredfunctional blocks is given in Figure 3.13. In principle, the following signal processing can bedigital after an immediate A/D conversion, analog discrete-time or continuous-time. In the lattercase, the clock harmonics should be filtered out like double LO components in a traditionalmixer.

96

The subsampling concept is mainly limited by noise, but there are other important differencesas well compared to traditional receivers or mixers. The noise analysis presented above issimplifying and takes only the noise of the sampling switch and LNA into account. Other noisesources like the LO noise coupled to the output due a to time-varying channel conductance in aMOS switch is analyzed in [66]. As discussed earlier a higher linearity can be achieved thanwith other mixer topologies. A thorough analysis of the distortion in CMOS RF and IF samplersis given in [67] using time-varying Volterra series, and the results are utilized in an IF digitizer[68]. The clock jitter in high-speed systems is a distinct problem and comparable to the phasenoise in oscillators controlling switching mixers or multipliers. Fundamental requirements forhigh-speed sampling are analyzed in [69]. In the case of a subsampling mixer, jitterrequirements for the clock come from the high frequency input signal rather than from a slowersampling rate [51], [60]. Hence, the requirements resemble RF oscillators and differ from theNyquist rate sampling.

In a commutating mixer, the signals at dc or close to it will be ideally upconverted around LO,and only a small portion will leak through switches into output. In a sampling mixer this is notthe case. All signals located at the baseband at the input of the mixer will not be attenuatedcompared to the downconversion product at the output. Therefore especially in the directdownconversion, the LNA and mixer must be only ac-coupled. The coupling scheme mustblock all components effectively over the desired signal band around dc. Otherwise, the second-order intermodulation of the LNA would be also critical for the performance. A couplingmethod, which is capable to suppress MHz-range baseband signals using a small capacitor isgiven in [64] and discussed in chapter 5. Small coupling capacitor values are important in astandard CMOS process because the bottom-plate parasitics would otherwise limit the RFbandwidth significantly.

Division into quadrature is also problematic in the case of subsampling because the 90°-phaseshift at RF can not be performed with a comparable phase shift at the sampling rate i.e. at LO.Naturally, the phase shift can be done for the RF signal, but due to the loss and inaccuracy inthe operation it should be avoided. The required phase shift for the LO reduces when thesubsampling ratio increases and may be difficult to implement accurately. Two differentsampling arrangements have been proposed, which can solve the problem without increasingthe complexity significantly [70], [71].

3.6 Comparison of Architectures

A summary of the characteristic benefits and drawbacks of the different radio architectures aregiven in Table 3.3. Sometimes two alternatives are given, because different precautions mayapply depending on the design choices. Benefits are marked with plusses and drawbacks orchallenges with minuses. The table should be considered only instructive, and it reflects thediscussion given in the earlier sections. The digital receiver approaches are not includedbecause they are merely technological possibilities to perform some functions digitally, whichhave been traditionally done in the analog domain. The digital signal processing has differentprerequisites, and therefore the comparison would not be objective. It is not reasonable to makeany order between different architectures either. The choice is always a complex function of theearlier experience and the characteristics of the specific system.

97

References

[1] C. Buff, “Radio Receivers—Past and Present,” Proc. of the I.R.E., vol. 50, pp. 884-891, May 1962.

[2] W. O. Swinyard, “The Development of the Art of Radio Receiving from the early1920’s to the Present,” Proc. of the I.R.E., vol. 50, pp. 793-798, May 1962.

98

[3] E. H. Armstrong, "Some Recent Developments of Regenerative Circuits," Proc. of theI.R.E., vol. 10, pp. 244-260, August 1922.

[4] E. H. Armstrong, “The Super-Heterodyne—Its Origin, Development, and SomeRecent Improvements,” Proc. of the I.R.E., vol. 12, pp. 539-552, October 1924.

[5] A. A. Abidi, “Low-Power Radio-Frequency IC’s for Portable Communications,” Proc.of the IEEE, vol. 83, pp. 544-569, April 1995.

[6] P. Favre, N. Joehl, A. Vouilloz, P. Deval, C. Dehollain, M. J. Declercq, “A 2-V1-GHz BiCMOS Super-Regenerative Receiver for ISM Applications,” IEEE J. Solid-

State Circuits, vol. 33, pp. 2186-2196, December 1998.

[7] M. D. McDonald, “A 2.5GHz BiCMOS Image-Reject Front-End,” in ISSCC Digest ofTechnical Papers, pp. 144-145, February 1993.

[8] K. L. Fong, R. G. Meyer, “Monolithic RF Active Mixer Design,” IEEE Trans. onCircuits and Syst.—II: Analog and Digital Signal Processing, vol. 46, pp. 231-239, March1999.

[9] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice-Hall, 1998.

[10] J. Sevenhans, D. Rabaey, “The Challenges for Analogue Circuit Design in MobileRadio VLSI Chips,” Microwave Engineering Europe, pp. 53-59, May 1993.

[11] T. D. Stetzler, I. G. Post, J. H. Havens, M. Koyama, “A 2.7-4.5 V Single Chip GSMTranceiver RF Integrated Circuit,” IEEE J. Solid-State Circuits, vol. 30, pp. 1421-1429,December 1995.

[12] C. Marshall, F. Behbahani, W. Birth, A. Fotowat, T. Fuchs, R. Gaethke, E. Helmerl, S.Lee, P. Moore, S. Navid, E. Saur, “A 2.7V GSM Tranceiver ICs with On-Chip Filtering,” inISSCC Digest of Technical Papers, pp. 148-149, February 1995.

[13] T. Yamawaki, M. Kokubo, K. Irie, H. Matsui, K. Hori, T. Endou, H. Hagisawa, T.Furuya, Y. Shimizu, M. Katagishi, J. R. Hildersley, “A 2.7-V GSM RF Tranceiver IC,” IEEE J.Solid-State Circuits, vol. 32, pp. 2089-2096, December 1997.

[14] P. Orsatti, F. Piazza, Q. Huang, “A 20-mA-Receive, 55-mA-Transmit, Single-ChipGSM Tranceiver in CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 1869-1880,December 1999.

[15] S. Heinen, K. Hadjizada, U. Matter, W. Geppert, V. Thomas, S. Weber, S. Beyer, J.Fenk, E. Matschke, “A 2.7V 2.5GHz Bipolar Chipset for Digital Wireless Communication,” inISSCC Digest of Technical Papers, pp. 306-307, February 1997.

[16] M. Bopp, M. Alles, M. Arens, D. Eichel, S. Gerlach, R. Götzfried, F. Gruson, M.Kocks, G. Krimmer, R. Reimann, B. Roos, M. Siegle, J. Zieschang, “A DECT Transceiver ChipSet Using SiGe Technology,” in ISSCC Digest of Technical Papers, pp. 68-69, February 1999.

[17] S. Atkinson, A. Shah, J. Strange, “A Single Chip Radio Transceiver for DECT,” inProceedings of the IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications,vol. 3, pp. 840-843, September 1997.

[18] A. Hanke, K. Hadjizada, S. Heinen, G. L. Puma, W. Geppert, “A 2.7V Image RejectReceiver for DECT,” in Proceedings of the IEEE Radio Frequency Integrated CircuitsSymposium, pp. 93-96, June 1998.

[19] J. Durec, “An Integrated Silicon Bipolar Receiver Subsystem for 900-MHz ISM BandApplications,” IEEE J. Solid-State Circuits, vol. 33, pp. 1352-1372, September 1998.

[20] P. Katzin, A. P. Brokaw, G. Dawe, B. Gilbert, L. Lynn, J. M. Mourant, “A 900 MHzImage-Reject Transceiver Si Bipolar IC,” in Proceedings of the IEEE Radio FrequencyIntegrated Circuits Symposium, pp. 97-100, June 1998.

[21] F. Piazza, Q. Huang, “A 1.57-GHz RF Front-End for Triple Conversion GPSReceiver,” IEEE J. Solid-State Circuits, vol. 33, pp. 202-209, February 1998.

99

[22] F. Piazza, Q. Huang, “A 170 MHz RF Front-End for ERMES Pager Applications,”IEEE J. Solid-State Circuits, vol. 30, pp. 1430-1437, December 1995.

[23] R. G. Meyer, W. D. Mack, J. J. E. M. Hageraats, “A 2.5-GHz BiCMOS Transceiverfor Wireless LAN’s,” IEEE J. Solid-State Circuits, vol. 32, pp. 2097-2104, December 1997.

[24] J. A. Macedo, M. A. Copeland, “A 1.9-GHz Silicon Receiver with Monolithic ImageFiltering,” IEEE J. Solid-State Circuits, vol. 33, pp. 378-386, March 1998.

[25] D. G. Tucker, “The History of the Homodyne and Synchrodyne,” J. of British Inst. ofRadio Engineers, vol. 14, pp. 143-154, April 1954.

[26] A. A. Abidi, “Direct-Conversion Radio Tranceivers for Digital Communications,”IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, December 1995.

[27] B. Razavi, “Design Considerations for Direct-Conversion Receivers,” IEEE Trans. onCircuits and Syst.—II: Analog and Digital Signal Processing, vol. 44, pp. 428-435, June 1997.

[28] J. Crols, M. S. J. Steyaert, “Low-IF Topologies for High-Performance Analog FrontEnds of Fully Integrated Receivers,” IEEE Trans. on Circuits and Syst.—II: Analog and DigitalSignal Processing, vol. 45, pp. 269-282, March 1998.

[29] J. Crols, M. Steyaert, CMOS Wireless Transceiver Design, Boston, Dordrecht,London: Kluwer, 1997.

[30] M. J. Gingell, “Single Sideband Modulation Using Sequence Asymmetric PolyphaseNetworks,” Electrical Communication, vol. 48, pp. 21-25, 1973.

[31] J. Crols, M. S. J. Steyaert, “A Single-Chip 900 MHz CMOS Receiver Front-End with aHigh Performance Low-IF Topology,” IEEE J. Solid-State Circuits, vol. 30, pp. 1483-1492,December 1995.

[32] J. M. Páez-Borallo, F. J. Casajús Quirós, “Self Adjusting Digital Image RejectionReceiver for Mobile Communications,” in Proceedings of the IEEE Vehicular TechnologyConference, vol. 2, pp. 686-690, May 1997.

[33] J. P. F. Glas, “Digital I/Q Imbalance Compensation in a Low-IF Receiver,” inProceedings of the IEEE Global Telecommunications Conference, vol. 3, pp. 1461-1466,November 1998.

[34] L. Yu, W. M. Snelgrove, “A Novel Adaptive Mismatch Cancellation System forQuadrature IF Radio Receivers,” IEEE Trans. on Circuits and Syst.—II: Analog and DigitalSignal Processing, vol. 46, pp. 789-801, June 1999.

100

[35] M. Banu, H. Wang, M. Seidel, M. Tarsio, W. Fischer, J. Glas, A. Dec, V. Boccuzzi,“A BiCMOS Double-Low-IF Receiver for GSM,” in Proceedings of the IEEE CustomIntegrated Circuits Conf., pp. 521-524, May 1997.

[36] V. Boccuzzi, J. Glas, “Testing the Double Low-IF Receiver Architecture,” inProceedings of the IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications,vol. 1, pp. 370-374, September 1998.

[37] T. Okanobu, D. Yamazaki, C. Nishi, “A New Radio Receiver System for PersonalCommunications,” IEEE Trans, on Consumer Electronics, vol. 41, pp. 795-803, August 1995.

[38] M. Steyaert, M. Borremans, J. Janssens, B. D. Muer, N. Itoh, J. Craninckx, J. Crols, E.Morifuji, H. S. Momose, W. Sansen, “A Single-Chip CMOS Tranceiver for DCS-1800Wireless Communications,” in ISSCC Digest of Technical Papers, pp. 48-49, February 1998.

[39] M. Steyaert, J. Janssens, B. D. Muer, M. Borremans, N. Itoh, “A 2V CMOS CellularTransceiver Front-End,” in ISSCC Digest of Technical Papers, pp. 142-143, February 2000.

[40] D. K. Schaeffer, A. R. Shahani, S. S. Mohan, H. Samavati, H. R. Rategh, M. d. M.Hershenson, M. Xu, C. P. Yue, D. J. Eddleman, T. H. Lee, “A 115-mW, CMOS GPSReceiver with Wide Dynamic-Range Active Filters,” IEEE J. Solid-State Circuits, vol. 33, pp.2219-2231, December 1998.

[41] P. R. Gray, R. G. Meyer, “Future Directions in Silicon ICs for RF PersonalCommunications,” in Proceedings of the IEEE Custom Integrated Circuits Conf., pp. 83-90,May 1995.

[42] U. Bolliger, W. Vollenweider, “Some Experiments on Direct-Conversion Receivers,”in Proc. of the EEE International Conference on Radio Receivers and Associated Systems,pp. 40-44, July 1990.

[43] S. A. Sanielevici, K. R. Cioffi, B. Ahrari, P. S. Stephenson, D. L. Skoglund, M.Zargari, “A 900-MHz Transceiver Chipset for Two-Way Paging Applications,” IEEE J. Solid-State Circuits, vol. 33, pp. 2160-2168, December 1998.

[44] J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, P. R. Gray, “A1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless TelephoneApplications,” IEEE J. Solid-State Circuits, vol. 32, pp. 2071-2088, December 1997.

[45] S. Wu, B. Razavi, “A 900-MHz/1.8-GHz CMOS Receiver for Dual-BandApplications,” IEEE J. Solid-State Circuits, vol. 33, pp. 2178-2185, December 1998.

[46] H. Darabi, A. A. Abidi, “An Ultralow Power Single-Chip CMOS 900 MHz Receiverfor Wireless Paging,” in Proceedings of the IEEE Custom Integrated Circuits Conf., pp. 213-216, May 1999.

101

[47] F. Behbahani, J. Leete, W. Tan, Y. Kishigami, A. Karim-Sanjaani, A. Roithmeier, K.Hoshino, A. Abidi, “An Adaptive 2.4GHz Low-IF Receiver in CMOS for WidebandWireless LAN,” in ISSCC Digest of Technical Papers, pp. 146-147, February 2000.

[48] C. Moreland, M. Elliot, F. Murden, J. Young, M. Hensley, R. Stop, “A 14bl00MSample/s 3-Stage A/D Converter,” in ISSCC Digest of Technical Papers, pp. 34-35,February 2000.

[49] R. Jewett, K. Poulton, K.-C. Hsieh, J. Doernberg, "A 12b 128MSample/s ADC with0.05LSB DNL," in ISSCC Digest of Technical Papers, pp. 138-139, February 1997.

[50] K. Y. Kim, N. Kusayanagi, A. A. Abidi, "A 10-bit, 100MS/s CMOS A/D Converter",IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, March 1997.

[51] A. Hairapetian, “An 81-MHz IF Receiver in CMOS,” IEEE J. Solid-State Circuits, vol.31, pp. 1981-1986, December 1996.

[52] R. Maurino, P. Mole, “A 200MHz IF, 11 Bit, 4th Order Band-Pass ADC in SiGe,”in Proceedings of the European Solid-State Circuits Conf., pp. 74-77, September 1999.

[53] S. Bazarjani, S. Younis, J. Goldblatt, D. Butterfield, G. McAllister, S. Ciccarelli, “An85 MHz IF Bandpass Sigma-Delta Modulator for CDMA Receivers,” in Proceedings of theEuropean Solid-State Circuits Conf., pp. 266-269, September 1999.

[54] G. Raghavan, J. F. Jensen, R. H. Halden, W. P. Posey, "A Bandpass Modulatorwith 92dB SNR and Center Frequency Continuously Programmable from 0 to 70 MHz," inISSCC Digest of Technical Papers, pp. 214-215, February 1997.

[55] W. Gao, W. M. Snelgrove, “A 950-MHz IF Second-Order Integrated LC BandpassDelta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 33, pp. 723-732, May 1998.

[56] P. A. Weisskopf, “Subharmonic Sampling of Microwave Signal ProcessingRequirements,” Microwave Journal, vol. 35, pp. 239-247, May 1992.

[57] P. Y. Chang, A. Rofougaran, K. A. Ahmed, A. A. Abidi, “A Highly Linear l-GHzCMOS Downconversion Mixer,” in Proceedings of the European Solid-State Circuits Conf., pp.210-213, September 1993.

[58] A. Pärssinen, R. Magoon, S. I. Long, V. Porra, “A 2-GHz Subharmonic Sampler forSignal Downconversion,” IEEE Trans. on Microwave Theory and Techniques, vol. 45, pp.2344-2351, December 1997.

[59] R. G. Vaughan, N. L. Scott, D. R. White, “The Theory of Bandpass Sampling,” IEEETrans. on Signal Processing, vol. 39, pp. 1973-1984, September 1991.

102

[60] D. H. Shen, C.-M. Hwang, B. B. Lusignan, B. A. Wooley, “A 900-MHz RF Front-Endwith Integrated Discrete-Time Filtering,” IEEE J. Solid-State Circuits, vol. 31, pp. 1945-1953,December 1996.

[61] S. Sheng, L. Lynn, J. Peroulas, K. Stone, I. O’Donnell, R. Brodersen, “A Low-PowerCMOS Chipset for Spread-Spectrum Communications,” in ISSCC Digest of Technical Papers,pp. 346-347, February 1996.

[62] A. Brown, B. Wolt, “Digital L-Band Receiver Architecture with Direct RF Sampling,”in Proceedings of the IEEE Position Location and Navigation Symp., pp. 209-215, April 1994.

[63] D. M. Akos, J. B. Y. Tsui, “Design and Implementation of a Direct Digitization GPSReceiver Front End,” IEEE Trans. on Microwave Theory and Techniques, vol. 44, pp. 2334-2339, December 1996.

[64] A. Pärssinen, S. Lindfors, J. Ryynänen, S. I. Long, K. Halonen, “1.8 GHz CMOS LNAwith On-Chip DC-Coupling for a Subsampling Direct Conversion Front-End,” in Proceedingsof the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 73-76, June 1998.

[65] S. Lindfors, A. Pärssinen, J. Ryynänen, K. Halonen, “A Novel Technique for NoiseReduction in CMOS Subsamplers,” in Proceedings of the IEEE International Symposium onCircuits and Systems, vol. 1, pp. 257-260, June 1998.

[66] W. Yu, B. H. Leung, “Noise Analysis for Sampling Mixer Using StochasticDifferential Equations,” IEEE Trans. on Circuits and Syst.—II: Analog and Digital SignalProcessing, vol. 46, pp. 699-704, June 1999.

[67] W. Yu, S. Sen, B. H. Leung, “Distortion Analysis of MOS Track-and-Hold SamplingMixers Using Time-Varying Volterra Series,” IEEE Trans. on Circuits and Syst.—II: Analogand Digital Signal Processing, vol. 46, pp. 101-113, February 1999.

[68] A. Namdar, B. H. Leung, “A 400-MHz, 12-bit, 18-mW, IF Digitizer with Mixer Insidea Sigma-Delta Modulator Loop,” IEEE J. Solid-State Circuits, vol. 34, pp. 1765-1776,December 1999.

[69] M. Shinagawa, Y. Akazawa, T. Wakimoto, “Jitter Analysis of High-Speed SamplingSystems,” IEEE J. Solid-State Circuits, vol. 25, pp. 220-224, February 1990.

[70] J.-E. Eklund, R. Arvidsson, “A Multiple Sampling, Single A/D Conversion Techniquefor I/Q Demodulation in CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 1987-1994,December 1996.

[71] D. T. S. Darwin, C. C. Ling, “A 200-MHz CMOS I/Q Downconverter,” IEEE Trans.on Circuits and Syst.—II: Analog and Digital Signal Processing, vol. 46, pp. 808-810, June1999.

103

4 Direct Conversion Receivers

This chapter introduces the design specific issues for a direct conversion receiver operating inwide-band CDMA systems. The emphasis is in the characteristic nonidealities with respect tothe CDMA, in the optimization of the receiver architecture and in the building blocks. From thenonidealities described in the previous section dc offsets and envelope distortion are alleviated.Some comments are also given on the evolution of circuit structures for digital receivers and onthe design of single-chip structures having digital circuitry on the same die with an RF front-end. Finally, some reported direct conversion receivers and their properties are referred. Thedesigned IC structures presented in the next chapter rely on this discussion, and many designchoices are justified in this chapter.

4.1 Direct Conversion in Wide-Band Systems

The direct conversion architecture is an attractive candidate for wide-band CDMA receivers forseveral reasons. First, the radio channels have wider bandwidths, which makes the contributionof flicker noise less significant, and the filtering of the dc component is easier because a smallerportion of the spectrum is removed with the same highpass filter. Second, a larger dynamicrange is achieved because of the processing gain. The signal may lie inside the noise i.e. have anegative signal-to-noise ratio before despreading. Hence, the distortion from an unwantedinterferer should be compared to the noise rather than the signal. The dynamic range isimproved by the amount of processing gain when it is taken into account. In the case of anegative signal-to-noise ratio, a larger interferer compared to the power at the desired trafficchannel is acceptable with the same IIP3. Also, the transmitted power levels can be reducedbecause it is possible to detect the signal when buried in noise. In the case of smaller powerlevels the nonlinear effects are less significant. These issues are discussed already in chapter 2,and the benefit may be lost for example when non-CDMA systems are operated at the sameband or close to it. A third reason for the use of direct conversion is that the despreading of thedesired channel spreads the narrow-band interferers or notches as wide-band, noise-like signalswithin the chip rate. This happens even if they vary in time. The despreaded signal is actuallyan average of a bit sequence, and hence less susceptible to individual errors.

On the other hand, the CDMA transmission is typically continuous, which rules out somedesign methods to compensate internal nonidealities. The drawbacks and their possiblecontributions should be considered carefully also in the case of CDMA. Some important designtrade-offs are given in the following subsections.

4.1.1 DC Offsets and Flicker Noise

The problems and sources of different dc offsets were recognized and different solutions givenalready in the early attempts of direct conversion. In pager applications using 2-FSK with adeep and wide notch between the two power maximums, a highpass filter is an obvious choiceto block any dc component before the detection [1]. Before discussing about different offsetcancellation methods, the different types of offsets and their effects in different cases should becategorized.

The dc offset is by definition a component, which is located exactly at the zero frequency. Forexample, it can be measured as a voltage difference between the positive and negative output

104

nodes in a differential circuit. However, the offset is not necessarily constant all the time.Therefore the time-invariant and time-variant effects should be separated. Time-invariantoffsets consist of nonidealities in the circuitry like component mismatches between differentialbranches, or a slow temperature drift. They are constant as long as the internal settings of thereceiver are unchanged. The offset varies each time when the gain or LO frequency is changedabruptly during the reception. Therefore offset levels must be redefined after rapid changes. Theamount of offset variation depends on the implementation. An example of the measuredperformance is given in [2]. The offset varies at the output of the mixer less than whenthe LO is swept over a 300 MHz range at 1 GHz. This is only 3 % of the mean offset value of3 mV and therefore probably insignificant.

The LO self-mixing has been considered as a main contributor to the time-variant offset,because the amount of self-mixing may vary due to changed reflection coefficient for examplewhen the antenna is touched, or due to radiation from the antenna and reflection back to thereceiver from a moving object. A third phenomena, which is not typically considered as a time-variant dc offset is the constant part of the second-order distortion or RF self-mixing as depictedin the previous chapter. However, it meets similar precautions as the LO self-mixing, becausethe component is located exactly at dc and can vary slowly in time according to the incomingamplitude. A modulated signal with a constant envelope produces only the dc component whendetecting even-order nonlinearity while in the case of a variable envelope, a part of the powerspreads over a wider bandwidth. This spread portion creates the phenomena, which isconsidered as an envelope or AM distortion, and can not be separated with conventional offsetcancellation methods discussed in this section. Also, any other abrupt change in the inputamplitude of the receiver generates a variable envelope. The AM part of any interference shouldnot be mixed up with a time-variant offset. The envelope distortion and its sources will bediscussed separately in the next subsection.

What is then the definition, which separates time-variant offsets from the envelope distortion?An unambiguous categorization is not possible. The changes in time-variant offset are howeverso slow that the differences in the levels of subsequent symbols are negligible. This dependsalso on the properties of the detector and specific modulation. Spectrally the limit can bedefined as a portion of the baseband spectrum, which can be removed around dc withoutcausing significant deterioration in the reception in static conditions. Due to differentmodulations and transmission quality requirements the acceptable offset cancellation rangeneeds to be specified separately in each case. The time-domain and frequency-domain conceptsare illustrated in Figure 4.1.

105

As given above the acceptable dc offset depends on the demodulator. The BER as a function ofis simulated for the in [3], for the quaternary PAM in [4] and for the

16-QAM in [5]. All of them indicated that a reasonable loss from ideal behavior requires dcoffset levels, which are only a few percentages of the detected signal i.e. -20...-25 dBc at theinput of the demodulator. However, these numbers are significantly smaller than the potentialoffsets at the output of the analog receiver as discussed in the previous chapter when the desiredchannel is close to the sensitivity level and gain is at maximum. The offset of a few millivoltscan be 50-70 dB above the weak signal at the output of the downconversion mixers. Hence,there should be an offset cancellation mechanism, which can remove large offsets and thencompensate the residual part of the time-invariant and time-variant offsets to an acceptable levelbefore the detection. The offset above the largest signal level increases the dynamic rangerequirements of the analog back-end stages and the A/D conversion, and the word length orclock rate in DSP. It is one of the parameters, which must be taken into account when dc offsetcompensation arrangements are developed.

The most obvious method to prevent the propagation and amplification of the dc offsets is theac-coupling. Often a highpass filter is used for that purpose. The filter with a first-orderhighpass function performs the same band limitation as an ac-coupling capacitor driving aresistive node. Hence, the different terms are used alternatively also here. If the filter hashigher-order transfer characteristics it will be noted separately. As given above, the FSKmodulations in paging systems are suitable for ac-coupling because of the appropriate spectralshape. However, the slow data rates and narrow channel bandwidths require a narrow notcharound dc. Unreasonably large component values for the integration are needed to produce thenotch below 1 kHz with a passive CR-network. Therefore the coupling capacitors are typicallyexternal although active dc blocks are also developed to reduce the sizes of passive componentslike in [6]. Still 330 pF on-chip capacitors are required to produce the notch. Another solution tothe on-chip ac-coupling is given in [7]. Two 10 pF capacitors are needed to produce a 10 kHznotch in a single quadrature branch.

The systems using more efficient modulations like QPSK or GMSK have the power maximumat dc in the modulated spectrum and therefore the filtering possibilities are more limited. A

106

good rule of thumb is that 0.1 % or less with respect to the data rate can be removed from thespectrum around dc without deteriorating the performance too much [8], [9], [10], [11].However, wide-band DS-SS systems are less sensitive to the DC notch although usingspectrally efficient modulations. The spreading operation codes each bit over a pseudorandomsequence, which means that the loss of one information bit is an average over a period ratherthan a failure in a single transmission in the constellation. The averaging works better when theprocessing gain increases. In chapter 2, the simulated curves for the bit-error-rate were given inthe case of two different highpass filters. The spreaded data allows the removal of the dc from awider band compared to the data rate, and actually to the chip rate as well. About 1 % of thespectrum can be removed compared to the chip rate without a significant loss even whenprocessing gain is only 6 dB. That is probably the worst case condition because the highest datarate transmissions require BER in the order of and it must be achieved at a smallprocessing gain. The wide bandwidths and the averaging property of the DS-CDMA are clearbenefits from the implementation point of view. Corresponding results are also given in [12] fora cordless system operating at the 1.2 MHz baseband channel having a 30 kHz notch. Anotherconsequence of the high cutoff frequency in the ac-coupling is unreasonable group delayvariations, which increase ISI [8], [13]. The latter reference however avoids the problem in thecordless application by using a suitable signal coding, which allows fast settling in the time-division duplexing although using a high cutoff frequency. In the subsection of channelfiltering, it will be shown that the estimated deterioration of ISI due to the 2 kHz highpasscutoff is not very significant in the WCDMA receiver. Also demodulators, which are not verysensitive to the group delay, can be constructed as [14].

Instead of ac-coupling in the signal path, the cancellation can be implemented with a feedbackloop over one or several baseband stages in the receiver. The servo feedback loop has lowpasscharacteristics, and the negative feedback reduces the closed-loop gain at low frequenciescanceling the dc offset. The feedback loop has been applied for offset cancellation at least in[12], [15], [16] and [17].

The ac-coupling methods are efficient when the offset is removed in static conditions. Thedrawback of the ac-coupling or filtering is the slow settling in large signal conditions likeabrupt changes in power levels at the input or internal gain control steps in the receiver [9],[18]. The same trade-off applies also to dc cancellation with a feedback. The loop gain isalways a compromise between the settling time and the amount of offset cancellation [12]. Thesettling can be sped up by disconnecting the signal when the output signal goes out of theacceptable range, and then new values are charged to the coupling capacitors when the time-constants are reduced by many orders of magnitude. The technique has been used in [9].However the 2 ms compensation procedure causes an instant loss of several bits in continuoustransmission. Alternatively, the capacitor in the ac-coupling structure is placed betweendifferential nodes in [6]. The method speeds up the turn-on of the receiver and is insensitive tochanges in the common-mode levels, but does not allow any benefit against differential offsets.

The large analog component values, removal of a large portion of the signal spectrum, andgroup delay distortion are limitations, which call for alternative solutions. The constant offsetcan be removed with a very long term averaging process [19]. When the long-time average issubtracted from the incoming signal the bandwidth of the notch around dc can be only fewhertz. This is however again a trade-off with the rate of change in the dc value. Hence, rapidchanges in the offset can not be removed. In the digital averaging process and periodic discrete-time correction, the group delay is almost unaffected due to the notch [8]. With a specificaveraging technique the offset of less than 20 mV at the output of the receiver has beenachieved in [20]. The acceptable offset with the maximum gain at the input of the basebandblock is in that case. The approach is discussed in [21]. Also small wobbling ordithering of the LO frequency around carrier, which can be cancelled afterwards, has been

107

proposed to average out the effect of the notch [19]. However, an example of its efficiency hasnot been given.

In burst-mode communications, like GSM or DECT using TDMA, the reception is notcontinuous. Hence, the internal offsets of the receiver can be stored during idle time slots andsubtracted during the transmission [11]. The values at different gain settings can be alsocollected in a memory table and the specific offset is subtracted from the incoming signal [22].Also, the rough offset compensation can be performed at the beginning of each frame either as apart of the cancellation algorithm [18] or sampling and subtracting it from the incoming signalduring the burst before the ADC [23]. An algorithm, which is suitable for canceling high offsetlevels of 40 dB above the signal, is given for a 4-FSK signal in [24]. The dc component can beestimated using oversampling from a few tens of information bits in parallel with thedemodulation. The specific demodulator is also quite insensitive to offsets because a 65 %offset compared to signal is acceptable without a significant deterioration.

In continuous-time systems, like WCDMA, idle time intervals can not be utilized forcompensation. Hence, the highpass filtering or long-time averaging methods, which are bothsensitive to time-variant offsets, are available. The WCDMA direct conversion receiverdescribed in the next chapter uses a servo feedback offset compensation with a 2-kHz cutoff.The method removes efficiently large static offsets at the input of the receiver. The time-variantoffsets, for example due to the digital gain control, should be compensated separately in thedigital domain. In the measurements, the offset level changed but remained well inside the ADCoperation range when digital gain steps were tested. Also, the 1.5 MHz sinusoidal test signalwas only slightly distorted during the 6-dB gain step and recovered within one period of thetime-domain waveform.

The LO self-mixing component can vary the offset frequency because of the Doppler shift whengenerated due to the backward reflection from a moving object. This can be eliminated in theburst-mode transmission if the offset is compensated frequently enough i.e. the offset is almostconstant over each frame or other period, which defines the interval of compensation. In thecontinuous-time reception it may cause an additional constraint when the offset is compensatedwith a highpass filter [25]. However, the estimation of the worst-case conditions is difficult.Especially, the ratio of the shifted offset component compared to the maximum dc offset valuedepends on several antenna and operation environment specific issues. Therefore, a properestimate would require field-testing, and the topic is not discussed any further.

The methods given above are mainly concerned structures, which can remove offsets largerthan the signal. Those are needed to limit the number of bits in the A/D conversion, andperform an initial cancellation. The residual may however require additional cancellation in thedigital domain. Typically, the adaptive digital methods can cope with offsets of 50 % or lessfrom the detected signal, but the loss after the cancellation can be almost negligible compared toan ideal detector. The remaining offset should be then only a few percent or less from thesignal. The convergence speed is a critical factor in compensation. In [9], the dc is reconstructedby calculating the average length of the constellation vector i.e. the shift from the origin over along period and the result is compared with the incoming symbols. Fast convergence can beachieved if a known preamble can be used to estimate offset for example in the beginning of thedata burst [4]. Only 5-20 symbols are needed to correct offsets up to 40 % of the desired signalto an acceptable level. Preamble has been used for the correction of the residual also in [23]. If apreamble is not available the offset can be also averaged over the whole burst, and subtract theaverage from the next slot [22]. This is possible when the offset varies within acceptable levelsbetween successive bursts. The method given in [18] is memoryless and is capable of toleratinglarge offsets as well. The response is fast, and the cancellation can be performed before A/Dconversion after the initial offset level is detected in the beginning of the burst. Hence, the

108

dynamic range requirements of the ADC remain reasonable. The fast convergence in theprevious examples is based on the known behavior before the random data is detected. Incontinuous transmission, this may not be possible. An adaptive algorithm capable of operatingin continuous conditions is described in [5]. The least mean square (LMS) algorithm requiresmore than 100 symbols for compensation, and therefore the response may be too slow whenoffset changes abruptly.

The carrier offset is the shift of the LO frequency from the center of the channel. It is acombination of the small frequency errors in the synthesizers both in the transmitter andreceiver. Again, the acceptable range depends on the certain modulation, symbol rate and thespecific detector. A fluctuating carrier offset is a source of additional phase error and must betaken into account in the clock recovery. The effect of the carrier offset and automaticfrequency control (AFC) methods in various systems are discussed for example in [3], [14],[26] and [27]. The carrier offset at the input of the receiver gives frequency stabilityspecifications for the synthesizer together with the tolerable range of the detector. Both issuesare however unimportant for the design of the analog signal path in the direct conversionreceiver and therefore omitted here.

The presence of flicker noise at the signal band immediately at the output of thedownconversion mixers is a significant drawback of the direct conversion architecture. Theeffect was discussed and highpass filtering proposed to reduce the problem already in the earlytrials of the concept in [28]. The linearity requirements limit the acceptable RF gain typically to25 to 35 dB in the front-end, and hence the effect of flicker noise can not be eliminatedincreasing the gain. The fundamentally higher noise level and the simultaneous requirement ofexcellent linearity at baseband before the sufficient suppression of interferers make a trade-off,which needs increased power consumption. Therefore the benefit compared to thesuperheterodyne, which is achieved through the lower operation frequency and thus lowerparasitic leakage after the first downconversion, is partly lost. The wide-band channel inWCDMA introduces even more difficult demands although the flicker noise contribution isreduced to some extent. The optimization of the dynamic range requires careful selection andsizing of devices with respect to the power consumption. Different aspects will be discussed inthe following sections.

4.1.2 Envelope Distortion

The background of the envelope distortion, called also as even-order or AM distortion, is givenalready in the two previous chapters. This subsection is focused to estimate different sources ofthe envelope distortion, and the amount of amplitude envelope in selected cases. Finally, therelationship between the envelope distortion and the second-order input intercept point (IIP2) iscalculated in the case of a modulated channel with a constant power level. The discussion isconcentrated only on the spectral components, which alias over the desired channel outside dc.The dc part of the distortion is covered already in the previous subsection. Also, the mechanismof the envelope distortion is squaring rather than RF self-mixing in this context. In the formercase, the phase of the carrier is insignificant as depicted in [29]. The amount of self-mixinghowever depends on the delay in the leaked signal compared to the input of the mixer. Inprinciple, the opposite phase may cancel the effect as well. In balanced mixers, the amount ofself-mixing depends only on the differential leakage to the LO ports. The common-mode part,which is very likely much larger than the differential portion in integrated structures, iscancelled at the differential output with a proper common-mode rejection ratio (CMRR). On theother hand, the common-mode leakage modulates the LO, thus exhibiting AM-to-PMconversion in commutating switches, and possibly a larger leakage of the low-frequency signals

109

to the output of the mixer. The mixer structures for direct conversion receivers will be discussedlater in subsection 4.3.2 and in section 4.4.

A definite explanation of the AM demodulation in direct conversion receivers including thedemand of excellent balancing to cancel the effect was given already in [9]. The squaringremoves the phase information in the case of even-order distortion i.e. the distortion is always acommon-mode signal, and hence the envelope is detected only due to the imbalances in thedifferential structures. Also, the reference [30] discusses the issue, but gives only a measure thata –30 dBm signal with a 95 % AM content gives no audible hum in the analog receiver. Aninitial estimate for the IIP2 specification was given for a QPSK system in [31], and the spectralshape of the baseband beat was sketched roughly in [21] and [32]. However, the amount of theenvelope distortion compared to the modulated signal was not quantified in those cases.Practical aspects and circuit structures to improve balance or prevent the low frequency beatcomponents from propagating to the input terminals of the commutating switches are given in[7], [29], [31], [33]. Unfortunately, all those examples give only intuitive and sensibleexplanations, but not a detailed analysis of the behavior in downconversion mixers even in asimplified case. The significance of balancing and the unpredictable nature of the phenomenonin practical circuits are typically mentioned without further considerations of the matter as in[15]. It should be also remembered that not all radio systems are sensitive to the envelopedistortion as will be discussed below. In this subsection, some crucial aspects of the systemlevel issues will be given, while in section 4.4 the symmetry requirements of the active mixerstructures are estimated with respect to the specified IIP2.

The sources of AM distortion in cellular systems originate either in AM components at themodulated channels or in time transients due to the transmission of unwanted channels. Theformer is a problem only in AM modulated analog transmissions and in digital transmissionsusing non-constant envelopes, like QPSK. The latter is more likely an issue in burst-modecommunications as is the case with TDMA, for example in GSM. The source of AM distortioncan be at any frequency because the modulation spreads around dc always when the signal issquared and lies within the reception band in the direct conversion receiver if the difference ofthe beat components is equal or less than half of the signal band. Hence, it is appropriate toassume a single dominant source to present the worst case conditions and the source can be anyof those discussed above. However, the discussion is limited here only within a single radiosystem at a time because at least theoretically the preselection filter removes sufficiently all out-of-band interferers.

The envelope distortion in a real radio environment was studied for a paging system in [34].The measurements were performed both for static and fading conditions at the 280 MHz band.The nearby television broadcast was a potential source of AM distortion in that case but theamount of envelope was unknown. The analysis technique differed from the conventional IIP2methods, but from the given values it can be calculated backwards that in the case of staticconditions the measured envelope was about 20 dB below the interferer. On the other hand, themeasurements in the fading environment indicate that the envelope was almost equal with theinterferer. This adds one additional parameter for the specification of IIP2, which is typicallynot available for the circuit designer. Maybe therefore, the effect of fading is a rarely discussedissue in the case of integrated direct conversion receivers. Also, the results given in [34] do notgive much insight on the matter.

A more straightforward approach to estimate the problem from the system point of view is theenvelope of a modulated radio channel in static conditions. This can be simulated quite easilywith different softwares having tools for modulated channels. The envelope detector is simply asquaring circuit, and the results can be compared straightforwardly to IIP2 calculations whenthe undesired power to the total channel power is estimated. In Figure 4.2, the envelope of a

110

QPSK channel is simulated for 4.0 Msymb/s using a root-raised cosine filter with a 0.22 rolloff.The power of the envelope is referred to the total power of the modulated radio channel. Thethick line describes the total cumulative envelope power up to a certain frequency. Themaximum cumulative power of –10.5 dBc is achieved at about 4 MHz frequency, but at 2 MHzthe total power is only –15 dBc. It means that a significant part of the envelope distortion isfiltered out in the channel selection, which relaxes the requirement of IIP2. From now on, theenvelope power, is defined as the power of the modulated channel, which is aliased withinthe band of interest. The given description presents a situation averaged over a long period,because a large number of bits must be simulated to achieve the spectral shape of the envelope.Actually, the peak power in the envelope can cause a detection of a false bit. Hence, theprobability of certain peak power levels in the modulated channel should be considered ratherthan an average of the envelope, and BER simulations are finally needed to find the IIP2specification for the direct conversion receiver. Another method to describe the amount ofamplitude envelope in the modulated channel is the crest factor, which means the peak toeffective amplitude ratio. It can be also used to define the dynamic range of the ADC. Theenvelope power, differs from the crest factor because the bandwidth dimension is takeninto account, but both relate directly to the properties of the modulation and filtering in thetransmitter. However, both measures require also some function describing what is theprobability of a certain peak or envelope power. This probability function is not directly relatedto the BER of the receiver, and hence a more detailed analysis is needed. In CDMAcommunications, the envelope of a single traffic channel is not as important as the total trafficin the same radio channel. Thus, several properly coded data channels should be simulatedsimultaneously to find the correct envelope or to calculate the crest factor. Some issues on thecrest factor, and especially the peak limited dynamic range of ADC, are analyzed for severaluncorrelated QPSK signals in [35].

The envelope powers have been also measured using a signal generator producing differentdigital modulations. The device under the test was a standalone BiCMOS mixer with emitterfollowers buffering the output. The mixer was driven into compression and therefore thelinearity is badly degraded. The nonlinear distortion was hence clearly visible and the interestwas only to compare the differences between modulations and transmitter filters. Because theinput power of the mixer was the same in all cases, the absolute value of the IIP2 was notimportant. The output signal of the QPSK modulated channel at a 25-MHz IF is given in Figure4.3. The output bandwidth of the setup was about 30 MHz and the mixer did not limit the

111

bandwidth in this case. The envelope distortion around the dc and the third-order distortion onthe both sides of the IF are clearly present. The cumulative powers of BPSK, QPSK and256-QAM modulations are shown in Figure 4.4(a). All channels have equal symbol rate androot raised cosine filtering with a rolloff of 0.22. The smaller envelope of the QPSK channel isexplained with a smaller probability to cross the origin in the constellation diagram. With theBPSK it happens always when the value of the bit changes, and the 256-QAM modulationproduces about the same total envelope power as BPSK. Interestingly the slope at lowfrequencies is however not equal. The shape of the QPSK signal follows well the earliersimulation. The QPSK signal is measured also when the rolloff of the transmission filter ischanged. The effect of increased envelope power with narrower filtering is evident in Figure4.4(b). The rapid rise in the cumulative power at 4 MHz is due to the feedthrough of the dataclock. The cumulative power bends up already below 10 MHz because of the 15-MHz IF in thetwo last plots.

112

The variable envelope is not necessarily the worst case situation for the AM detection. Thetime-division multiple access has caused more severe problems in GSM. The abrupt change inthe transmitted power level causes an AM component, which can be detected in the directconversion receiver. Especially, this becomes severe when the transmission is bursty. Thenearby transmitter switches frequently on and off at another channel in a TDMA system.Because the unwanted source is not necessarily synchronized to the desired channel, theswitching can happen during the reception of the data bits. To prevent the detection of this largeenvelope the IIP2 of a GSM receiver must be in the range of 46-50 dB [36], [37]. Hence despiteof the constant envelope in the modulation, GSM is one of the most difficult systems to realizewith the direct conversion architecture. Of course, the transients must be characterized carefullyin the IIP2 specifications when new traffic channels are inserted or transmitted power ischanged also in CDMA systems. However, they are less susceptible to cause any problemsalthough the reception is continuous. Some theoretical curves of envelope power behavior in thetime domain are shown in Figure 4.5. All changes in the y-axis indicate always amplitudeenvelope, and the straight line presents the case when a vector with a fixed amplitude rotatesaround the origin in the constellation diagram.

The discussion has been limited so far only to the amount of envelope in some specific cases.Next, some comments will be given on the two-tone test as a method to define the beat tone andhow it relates to the envelope power. In the two-tone test, the sum of the sinusoidal RF testsignals with an amplitude A at frequencies and can be given as

113

where The equation has the characteristics of double-sidebandsuppressed-carrier AM modulation at the frequency of The lowpass filtered part of thesquared signal can be then given as

The power of a single test tone in the matched case is where is the sourceresistance. The envelope power in the low frequency beat according to Equation (4.2) is thentwice the input power in the two-tone test i.e. dB in decibels. This must be taken intoaccount when the two-tone test is compared to the envelope powers of the modulated channelsgiven above. The part of the distortion, which leaks to the output is referred to the input as

If the inputs in the two-tone test have different power levels, it isstraightforward to show that the cosine term depends on the smaller amplitude and thedifference increases only the DC component.

The connection of the IIP2 to the system specifications is reviewed briefly. In cellular andcordless systems the maximal interference level is typically specified for the signal, which is3 dB above the reference sensitivity level, of the receiver as

where N and I are the input referred noise and interferer power levels in decibels, respectively.To keep the BER unchanged, the interference can be at the same level with the noise. If weassume that the interference is dominated by the envelope distortion determined with IIP2, theinput power can be defined from the equation

where G is the gain of the system, and are the measured outputs, and is theinput referred value of the second-order distortion. Combining Equations (4.3) and (4.4) thelargest acceptable input power of the interferer is

where the signal-to-noise ratio, which here is equal to the signal-to-interference ratio, is theminimum to achieve a certain BER with a specific modulation. The envelope power has beenhowever 3 dB above the input power in the test. The last three terms in the summation actuallypresent the noise power at the sensitivity level as given in chapter 2. Processing gain improvesthe immunity in the spread-spectrum systems.

It has been shown that the specification of the acceptable immunity against envelope distortionis much more than a characterization of some specific test tones. A modulated channel or someother test may model the behavior well in practical cases, but the appropriate case for the worstcase conditions would not be easy to find because of a large variety of different parameters. Thetwo-tone test is still a simple and possible test for the envelope distortion but different powerlevels and test frequencies should be defined than for the third-order intermodulation. This hasnot been done in most of the specifications because they are mainly meant only for the

114

superheterodyne architecture, or the specifications have been completed later when problemsoccur. The complexity is often increased in new wireless systems, but typically the focus isquite far from the analog part of the radio receiver. To benefit from the advantages of directconversion architecture, a deep understanding of the complete system is necessary also for RFdesigners. The role as a part of the demodulator and the large number of other DCR specificissues are hence an essential part of the analog IC design in communications circuits, which cannot be omitted. The following sections relate some of these issues into the circuit design, andthe main focus is in the implementation of integrated direct conversion receivers and theirindividual blocks.

4.2 Radio Design

The design of the direct conversion receiver is based here on the initial specifications of the 3rdgeneration WCDMA wireless system. The most significant change to the original proposal isthe reduction of the 4.096 Mcps spreading rate to 3.84 Mcps. The two implementations use theformer chip rate, but the same design could be utilized when the sampling rate of the ADCs isreduced and the poles and zeros in the channel selection filter are scaled for the new cutofffrequency. The latter would require naturally a new processing round. The channel spacing ishowever not altered during the specification process.

The direct conversion receiver is the first reported prototype for the WCDMA system, and itwas originally published as a chip set in [38]. The RF bandwidth of the system was designedlarge enough that the same chip can be used in test beds both for base stations and mobileterminals. Later the same structures were placed on the single-chip version of the directconversion receiver including the signal path from LNA to ADCs [39]. An external synthesizeris used to generate the LO for downconversion mixers. Many issues were still open in thespecifications during the design, and therefore the results can not be directly applied to therecent versions of the specification. The initial design goal was also more likely to maximizethe overall performance with the modern IC technology rather than follow strictly a list ofdetailed specifications. The functional prototype was a more important design goal than a smallpower consumption, for example. The chips were implemented with a 25 GHzBiCMOS process. The process had four wiring layers providing high-quality metal-insulator-metal (MIM) capacitors and inductors with low resistive losses. As an exception the A/Dconverters in the chip set used a CMOS technology.

Details of the circuit design will be given in the next chapter. In this section, more generalissues on the receiver optimization will be given, and grounds for some topological and systemlevel choices are given. The main emphasis is in the optimization of the RF front-end, andespecially in the downconversion. Analog baseband processing and A/D converters are onlymentioned briefly. The dynamic range of the receiver was optimized in the receiver accordingto the gain diagram in Figure 4.6. The thick lines present the maximum and minimum voltagegains of the desired channel. The respective gains for the interfering signals at 3, 5 and 10 MHzoffsets are given in the case of maximum gain with dashed lines. The gain control mechanismwill be explained in the next chapter.

115

4.3 Functional Blocks in Direct Conversion Receivers

The functional blocks of direct conversion receivers from low-noise amplifier (LNA) to A/Dconverters will be discussed next in the separate subsections. Also, the different structures forquadrature generation are described although the synthesizer including the VCO will not becovered. In analog baseband processing, only the response of the channel selection filter is ofinterest in this context. The controlled gain at the baseband is merged with filtering, and will beexplained in the next chapter.

4.3.1 Low-Noise Amplifiers

In direct conversion receivers, the low-noise amplifier provides typically most of the gainbefore the conversion down to the baseband. Therefore the high gain without a significantdegradation in linearity is required. This must be achieved together with a low noise figure.Typically, the noise figure of less than 3 dB is required from the LNA, but the trend has beenrecently towards 2 dB or even less. The discussion is limited here only to basic topologies ofone-stage LNAs implemented either with bipolar or MOS devices. The recent results show thatboth bipolar and CMOS LNAs can have noise figures of less than 2 dB [40], [41], [42] and[43]. In the direct conversion architecture, the LNA drives directly the input port of the mixer,because external components are not needed. Hence, matching is not required and actually theLNA is driving a node, which consists of its own load and the input impedances of two mixersincluding parasitic loading. Hence, voltage gain is the appropriate definition as discussed inchapter 2, and the measurement of a stand-alone LNA would require a separate buffering stage.

116

Therefore LNAs used in direct conversion receivers are seldom measured individually andtypically the results are available only for the complete RF front-end.

Common-emitter or common-source configurations are the most common topologies because,at least theoretically, very low noise figures are possible. A cascode stage is also often used toensure stability. It also improves the reverse isolation of the LNA, which is important in DCRs.The load of the LNA is typically a resonator consisting of an inductor and either a lumped orparasitic capacitor. The inductors are however large, they may have high losses, and they maynot be available, or at least not modeled, in a standard CMOS process. Therefore resistors havebeen sometimes adopted as loads with a reasonable cost in the noise figure [44], [45], [46]. It isalso possible to use a gyrator circuit as an ‘active’ inductor [47] or to compensate the losses ofthe inductor with a negative conductance circuit [48]. The both alternatives however degradethe noise and linearity performance significantly. The load device can be avoided using an LNAwith a CMOS inverter type input stage [49]. The slower speed of the pMOS device limits theoperation range in this topology. The matching of common-emitter or common-sourcetopologies is discussed in the next subsection. A summary of some recently reported LNAsusing silicon technologies is given in Table 4.1. Another LNA topology is the common-base orcommon-gate configuration. It allows easier matching and better reverse isolation. However,the noise figure is theoretically limited to 1.78 dB in a common-base and to 2.2 dB in acommon-gate configuration only due to the input device [50]. The common-gate topology hasbeen used sometimes in direct conversion front-ends [2], [51].

A differential signal path is used also in the low-noise amplifier. This is not an optimal solutionfor the power consumption, but a preferable design trade-off to suppress the common-modedistortion induced through the substrate or coupled to a sensitive RF input in a mixed-modechip. The fully differential signal path is adopted in several reported mixed-mode receiversincluding an LNA on the same chip with the digital circuitry [15], [17], [39], [64]. Some

117

comments on the input induced clock distortion will be given in the section 4.6 and in the nextchapter discussing the single-chip version of the WCDMA receiver. Another drawback of thedifferential input is a need for an additional balun in front of the LNA. The loss of the balunshould be added directly on the noise figure of the receiver in a practical environment. Othersolution would be a preselection filter with a differential output. However, RF filters withdifferential outputs are not commonly available or widely used in commercial applications.

A conventional common-emitter cascode LNA using two differential branches and no commontail current source was used in the WCDMA receiver. The matching network, loadarrangements and other details of the topology will be given in the next chapter.

4.3.1.1 Input Matching

Matching of a common-emitter or common-source LNA is performed using two inductors andthe base-emitter or gate-source capacitance of the input device. Both topologies with the mostimportant matching components are given in Figure 4.7. The significant components arebasically the same in both structures, but for example the gate resistance in a MOS LNA istypically much smaller than the base resistance in the bipolar case. The well-known equationsfor the matched conditions are in the case of a common-emitter topology

and

The equations come directly from the input impedance of the LNA by requiring the imaginarypart to be zero and the real part to be equal with the source resistance, which is typically

The resonant frequency, gives the optimum point of the matching. Principally, adifferential LNA can be designed with the same method except that the source resistance is thendoubled. The single-ended case can be directly applied if the differential LNA is actually onlymade of two individual LNAs without any virtual ground. However, the situation may varysignificantly if parasitic coupling occurs between differential branches. Therefore, the isolationof differential ports is important. Most of the coupling between input ports may come from theoff-chip wiring and mutual coupling between input inductors. The unwanted coupling will bediscussed briefly with the measured results. The input inductor, is typically implementedwith a bondwire or with a combination of the bondwire and the package pin. In the former case,the inductance value can be chosen freely with certain tolerances. The value of the bondwirecan be calculated with the formula [56]

where is the permeability and dw are the length and diameter of thebondwire, respectively. For short interconnections with the standard gold wire, a goodrule of thumb is 1 nH/mm. In principle, a part of the input inductance can be realized on-chip,but the resistive losses in the inductors would cause degradation in noise figure. The emitter or

118

source inductors have typically much smaller values and they can be realized either on-chip orwith bondwires. The latter alternative may be difficult to implement because of shortbondwires.

The measurement of differential matching is slightly more complicated than with a single-endedLNA. The measured S11 is strongly dominated by an external balun if it is connected betweenthe network analyzer and the LNA. At least the scattering parameters of the balun must becharacterized separately before calculating the matching from the measured results. Thereliability may not be adequate with that method. A more straightforward technique is tomeasure both differential ports individually and combine the results mathematically afterwardswhen it is known that there is a virtual ground between the two specific ports. Hence, a singledifferential port requires a two-port measurement in the network analyzer. Because only onedifferential input port should be measured in the case of matching a standard two-port networkanalyzer is sufficient for the purpose. Some commercially available network analyzers havefour ports and allow the measurements of scattering parameters from two differential ports.They use the same mathematical calculations to define the differential performance from thefour data ports as used below.

The procedure to calculate the differential matching from the two-port measurements isdescribed next. The S-parameters are measured normally for two unbalanced ports representingthe differential input. Then the S-parameters are transformed to z-parameters. The inputvoltages, and and currents, and in the two ports are now divided into balanced andunbalanced terms because it is known that they are differential. Hence, they can be given as

119

The relation between unbalanced and balanced voltages and currents can be also given withmatrices:

The matrices and contain balanced and unbalanced information in separate terms. Therelationship between the two new matrices can be now written as

The balanced z-parameters, which are called also as modal z-parameters, are now calculated as

The last row shows that the information of the balanced part of the signal is now in the termThe other modal parameters describe the relationships between balanced and unbalanced

voltages and currents or the unbalanced behavior. The modal z-parameters are next transformedback to the S-domain, and the modal parameter gives the differential matching of thecircuit. is calculated from the modal z-parameters as

where

The calculations are relatively simple when only one differential port is of interest. It can beproved for example with the simulations that the given mathematical transformation for two-port S-parameters gives exactly the same result as S11 simulated for a differential input port

120

when the source resistance is doubled compared to the single-ended case. Hence, the method issuitable for measurements.

The measured results for the RF front-end of the direct conversion chip set are given in Figure4.8. The S11 and S22 curves are relatively close to the differential match, which is a sign ofsufficient isolation between the differential ports. The S21 and S12 curves describe the isolationbetween the ports. It is mainly dominated by the cross-coupling in the PCB, and the behaviorcan be modeled with good accuracy using coupled transmission lines in a standard RFsimulation software.

4.3.2 Mixers

The RF downconversion mixer in the direct conversion requires totally different optimizationapproach than in other architectures. The second-order nonlinearity is often the most criticallimitation, but several other parameters need special attention as well. A sufficient amplificationat RF must reduce the contribution of noise from the baseband circuitry to minimum, andsimultaneously provide high linearity. The noise problem relates both to the existence of flickernoise and to the inherently high noise levels of active stages, especially in filters. For thosereasons, active mixers were preferred already in [10], and active mixers are adopted in most ofthe reported direct conversion receivers as in [6], [7], [12], [15], [31], [57] and [58], forexample. Active mixers will be discussed separately in section 4.4.

Passive mixers provide in general a better linearity, but also often a demand for a higher LOdrive. The conventional passive structures i.e. diode or FET ring mixers are not discussed here.They have been used earlier in some test configurations [8], [9], [28], but not in recentintegrated implementations. Instead, an antiparallel diode pair mixer is utilized in a directconversion receiver to avoid the LO-to-RF leakage. This approach will be discussed in the nextsubsection with respect to the LO generation requirements. However, the reported results fromseveral test circuits indicate that it is difficult to achieve high linearity simultaneously with alow noise figure [59]. Subsampling mixers are a separate subcategory of passive mixers. Theircharacteristic properties and design issues will be discussed separately in section 4.5.

121

Another structure of interest is the four-quadrant CMOS multiplier cell in which the inputtransistors operate in the triode region and the LO is brought into the sources of input devices[60]. This type of a mixer is considered separately, because its principle of operation differssignificantly on the active Gilbert cell mixers and passive structures. A downconversion mixerwith a very high linearity but over a 30-dB noise figure has been reported with this topology upto the 1.5-GHz range [61]. The noise figure in a more recent implementation with the sametopology lies still in the range of 20-dB [62]. The four-quadrant multiplier is applied in a low-IFreceiver [45], which avoids partly the flicker noise problem. If the flicker noise contributionfrom the dc would be taken into account, the noise figure degrades even from the givennumbers. Hence, the noise performance is not sufficient for direct conversion applications inmost cases although the linearity, and especially the even-order performance, is potentiallymuch better than in a bipolar based Gilbert cell. The excellent even-order linearity performanceis based on the fact that the output depends linearly on the input signal even in the presence ofmismatch [61]:

where is the mismatch of the preceding term, is the feedback resistor at theoutput opamp, and and are the differential output, input and LO signals,respectively. The mismatch at the output generates only a term, which is proportional to thesquare of the LO amplitude. Hence, the mixer is ideally free from the second-order nonlinearityin all cases. However, the IIP2 is not necessarily much higher than with Gilbert-cell basedstructures and high linearity and the lowest possible noise can not be achieved in the same biasconditions [62].

The choice of a Gilbert cell based active mixer for the WCDMA receiver was obvious due tothe stringent noise requirements. The different alternatives to partition the front-end can beestimated using Figure 4.9. In the plot, the IIP3 of the LNA is nominally –5 dBm when

and the solid curves present cases when IIP3 of the mixer is 0, +10 and +20 dBm,and the IIP3 of the LNA is constant. NF of the LNA is 2 dB, and the thick lines present thecases when the NF of the mixer is 10 and 20 dB, respectively. A fixed IIP3 of the LNA as afunction of the gain is however not a very realistic design parameter. Hence, two othersituations as defined when IIP3 of the mixer is +20 dBm. The dotted curve describes linearitywhen OIP3 is constant as a function of the gain and the dashed curve presents the situationwhen the OIP3 is inversely proportional to gain. The former is valid when the nonlinearities atinput of the LNA dominate the behavior while in the latter, the output circuitry of the gain stageis dominant. Of course, in the case of a very large gain requirement a single-stage amplifier cannot meet the desired performance, and the given characterization gives only little insight intothe actual circuit design. Two regions are highlighted in the plot. It is assumed that about 30-dBof gain is required in the RF front-end of the direct conversion receiver to maintain the noise ofthe baseband circuitry at an acceptable level. Active mixers can contribute typically about 5 to10-dB of gain with a reasonable linearity. Hence, 20- to 25-dB amplification in the LNA issufficient. In that case, a 10 dB noise figure is still acceptable for the mixer, but 20 dB as in therecent CMOS four-quadrant multiplier [62] causes an unreasonable degradation in the noiseperformance. The fundamental loss of passive mixers is at least (3.9 dB), and in practicalimplementations 5 to 10 dB is a realistic estimate. Both the linearity of the LNA and of themixer itself are very critical issues. The optimal choice for current IC technologies is clearlycloser to the ‘natural’ range of active mixers, which explains clearly the dominance of activemixers in direct conversion applications.

122

The definition of the noise figure is different compared to the other architectures in directconversion mixers. The double sideband (DSB) noise figure can be used because both imagebands contain also desired signal besides of noise [2]. Theoretically, the DSB noise figure isalways less than 3 dB smaller compared to the corresponding single sideband (SSB) noisefigure, but 3 dB is a good rule of thumb when the noise figure is sufficiently large [63]. Anotherimportant difference in the design strategy is the interfaces to LNA and baseband, which do notneed matching to The issue has already been discussed in chapter 2 from the system pointof view. In the circuit design, more freedom to optimize the on-chip interfaces and theirimpedance levels separately is available. On the other hand, the design procedure is morecomplex because the contradictory requirements of different functions must be considered andoptimized simultaneously. Also, the testing of stand-alone blocks is difficult. The interfaces oftest equipment differ from the targeted environment causing degradation in performance. Thisis especially a critical issue in the RF and LO ports of the mixer.

The direct conversion architecture defines evident constraints on the mixer topology. Single-ended mixers can not be used for two reasons. First, the leakage of the tail current andespecially the second-order beat around dc are not cancelled at the single-ended output. Second,the isolation from the single-ended LO to RF input is very limited. Single-balanced and double-balanced architectures provide theoretically similar properties for the cancellation of the bothproblems mentioned above as long as the output is taken differentially. The possible RF to IFleakage is not a serious issue in the single-balanced structure because the leaked RF signals canbe filtered out easily from the baseband signal at the output of the mixer. The common trade-offs between the mixer topologies are discussed for example in [63], and some analysis is donewith respect to IIP2 in section 4.4.

4.3.3 LO Generation and I/Q Balance

Although I/Q balance requirements are only moderate compared to low-IF or wide-band IFtopologies they were a major concern in the early experiments of direct conversion, especiallyin discrete implementations. However, in some cases more than 1.5 dB amplitude and 12° phase

123

imbalances were acceptable with less than 1 dB penalty in the performance [3],[14]. Hence, therequired image rejection ratio would be only about 20 dB. A more realistic or at least a moreconservative estimate for IRR in quadrature demodulators is about 25 dB [65], [66], [11]. Itmeans either a 1-dB amplitude or a 6°-phase imbalance requirement or a combination of 0.7 dBand 3°, for example. Those numbers can be met with current IC technologies and carefuldesign. Even a better performance is achieved with compensation algorithms like in [5] and [9].Also a third signal path and a 120° phase shift between the channels has been proposed [67]. Itallows either an effective phase or amplitude imbalance correction using a DSP algorithm. Thisis however very uneconomical for the implementation because a third baseband channel isrequired.

As stated above, the acceptable I/Q-balance is not the most critical parameter in integrateddirect conversion structures. Some issues must however be considered in the implementation.The choice of the quadrature generator depends on the required bandwidth and operationfrequency. The imbalance must be within acceptable range over the whole band. Also, the LOleakage can be reduced with certain design choices as discussed later. Another source offrequency dependent imbalance is the mismatch of the cutoff frequencies in the basebandfilters. If the cutoff frequencies between the I- and Q-channels vary only by 1 %, the phase andamplitude imbalances increase significantly from the passband value close to the cutoff. Thegravity of the problem is not discussed here, but the matching of the cutoff frequencies is anadditional design parameter in the analog baseband filter design.

The division into quadrature branches at RF is the most critical block for the I/Q-balance. Thedivision can be performed in principle either for the RF or LO signal. The latter is howeveralmost always used because no additional loss exists at the signal path and only a narrow-bandsignal should be divided into quadrature. Two common techniques to implement a quadraturegenerator are a RC-CR network and a master-slave flipflop generating the 90°-phase shift froma double-frequency LO [50], [68]. Also, some voltage-controlled oscillators (VCO) can providequadrature outputs without a separate quadrature generator. A four-stage ring oscillator is anobvious option [69], [70]. Despite of the extensive research and analysis of its jitter or phasenoise [71], [72], [73], [74], [75], [76], [77], the ring oscillators tend to have too high phase noisefor RF applications [78], [79]. Also other types of VCOs with quadrature outputs have beenimplemented [80], [81], [82]. Recently, excellent phase noise results have been achieved with amulti-stage LC-oscillators connected to a ring [83]. The structure can replace the ring oscillatorwith a superior noise performance.

The RC-CR networks provide a 90° phase shift at a wide band, but the amplitude is equal onlyat one frequency of The structure in Figure 4.10(a) has a relatively narrow band andthe operation frequency is sensitive to absolute component values of R and C. In the case ofdifferential input signals, the phase shift network is connected into a bridge as in Figure 4.10(b)[84]. A similar configuration with differential outputs is utilized in [85] using also an activephase corrector. The phase shift can be also included in the LO buffering. The buffers with aresistive and capacitive degeneration provide quadrature signals for two upconversion mixers in[86]. However all structures given above suffer from limited I/Q balance because of differentmismatches. An effective amplitude and phase corrector for RC network is reported in [87]producing phase and amplitude errors of approximately 0.1° and 0.1 dB, respectively.

124

The symmetry of an RC network is improved using a polyphase filter. A single-stage of thetopology is shown in Figure 4.10(c). The sequence asymmetric polyphase networks areoriginally proposed for a single sideband modulator operating at the signal path [88], but theycan perform the appropriate phase difference for the LO signal as well. The benefit of apolyphase network is the reduced sensitivity to the absolute values of R and C due to asymmetric structure. The balanced quadrature outputs are generated also when either the I- orQ-input port is grounded. Hence, the circuit operates as a quadrature generator [89]. Thecascaded stages of polyphase networks improve the quality of quadrature signals, and thebandwidth can be increased if the frequency defined by the RC-product is varied at differentstages [88]. The latter property is utilized to produce a high IRR for the wide-band signal in thelow-IF configuration using altogether five polyphase stages [90]. In that case, the polyphasenetwork improves only the quality of quadrature balance, and hence the suppression of negativefrequencies. The preceding mixers have already provided the quadrature downconversion.Similar approach was proposed earlier for the low-IF receiver in [91] using an active polyphasefilter described in [92]. The polyphase network can be used also to suppress the third harmonicof the LO signal, which is already divided into quadrature as given in [78].

The effect of cascaded stages is simulated and shown in Figure 4.11(a) for the amplitudebalance in ideal case. The balanced input signal is fed into the in-phase (I) port through atermination and the quadrature port (Q) is grounded. The phase difference is 90° over the wholeband already after the first stage as should be in the ideal case. In Figure 4.11(b), the RC-product is changed from the nominal design value by in one- and two-stageconfigurations. The change is to the same direction in both stages of the two-stage network. Theresult indicates two reasons for the choice of a two-stage structure in the WCDMA receiver,which should cover a wide-band from 1.920 GHz to 2.170 GHz including reception bands ofboth the mobile terminal and the base station. First, in a one-stage network the amplitudebalance changes over 1 dB between the lower and upper edge of the desired band even in thenominal case. Second, the process variations may cause unacceptable variations between thesamples due to the absolute variations in the RC-product. A two-stage network providessufficient performance even in the case of process variations. The relative bandwidths in

125

different cases are collected in Table 4.2. The nominal values of R and C are and 0.8 pF,respectively. The center of the polyphase filter at 2.04 GHz is in the middle of the desired band.For comparison, the values are also defined for a two-stage network when RC-products are notthe same. The differently valued resistors and in successive stages performdifferent resonant frequencies located in the middle of the two reception bands. However, thebenefit is practically negligible in our case. Therefore the amplitude accuracy was simulatedalso when and The increment of the bandwidth is about 10 % whenrequired accuracy is 0.2 dB or more. The uneven resonance values however prevent bettermatching over the band even in an ideal case. Hence, the differently valued RC time constantsdo not provide any added value in the reported WCDMA application. The absolute variation ofthe RC time constants from chip to chip is an important parameter when choosing the numberof stages for the polyphase structure, and clearly a two-stage network is required in the case ofWCDMA. Another design issue is the random process variations between the component valuesof the same polyphase network. The variations are typically within a few percentages, but theycause both amplitude and phase imbalance. The former is typically less significant compared tothe absolute variation over the band of interest, and also the phase error remains in anacceptable level for the requirements of direct conversion. A thorough study for the polyphasenetworks using Monte Carlo simulations and different mismatches is given in [93].

126

The major drawback of the RC phase shifting networks, including the polyphase approach, isthe fundamental loss of 3 dB per stage. The loading of the network, which is typicallycapacitive and given as and in Figure 4.10(a), should be also designed to avoidadditional attenuation of the signal. For these reasons the quadrature generator at highfrequencies is typically placed in the LO signal path in direct conversion receivers. An exampleof the opposite approach is the pager, which uses a low-Q LC structure between the LNA andmixers for quadrature generation [6]. The use of an RC network may require additional powerconsumption because the attenuation must be compensated either by adding a buffering stage infront of the mixer or using a higher output swing in the VCO. The WCDMA receiver uses atwo-stage polyphase filter to generate the quadrature LO signals from an external balancedinput [94]. The structure provides sufficient performance over the range of interest as confirmedby the measurements. Both stages use the same nominal component values given above.

The double-frequency LO approach is a wide-band structure by the nature and a good I/Qbalance is possible, but it requires a higher LO frequency and a high-speed divide-by-twocircuitry. This trade-off is however considered better than the RC networks in many recentdesigns [17], [95] and [96]. Especially, the wide input bandwidth of 950-2150 MHz in the lastexample does not allow narrow-band passive structures. The LO is outside the RF input band ofthe receiver in the double frequency configuration. This reduces the LO radiation problembecause the divide-by-two circuit can be operated locally close to the downconversion mixersallowing improved possibilities to isolate the actual LO [30]. The divide-by-two structure needsa perfect 50 % duty cycle at the LO input to operate properly. The problem can be avoided withanother divide-by-two operation, but the required frequency of four times the LO is probablynot practical any more [68]. This is however utilized at the low-frequency channels in [96]because the double-frequency tone would otherwise fall at the passband of the receiver, and thesufficient LO is readily available to be used with the uppermost channels. A method to correctthe errors in the double-frequency structure is presented using a level-locked loop in [97].

The LO radiation must be kept within acceptable limits as discussed earlier in section 3.2. Thescale of the problem is discussed for different receiver configurations and radio environments in[30] and [34]. The isolation depends on the shielding of the VCO, LO-to-RF isolation of themixer, reverse isolation of the LNA and leakage through the substrate in integrated structures.In direct conversion receivers the preselection filter provides only little attenuation, whichexhibits more stringent specifications on the other structures. The off-chip LO signal may cause

127

additional problems because of the mutual inductances between the bondwires and packagepins. Also the finite isolation of the printed circuit board (PCB) is a potential route for theunwanted leakage. Excellent isolation can be achieved with an external LO by bringing the LOsignal into the chip orthogonally to the RF wiring, and grounding the LO input properly on bothsides [12], [94]. The recent results indicate over 70 dB LO-to-RF isolation at the operationband, which means less than –75 dBm LO radiation from a –5 dBm LO [39]. This is anacceptable level in most radio systems.

An alternative method to double frequency LO, which avoids the in-band VCO, usessubharmonic mixers [30]. A subharmonic mixer, or more likely an even-harmonic mixer, uses aVCO, which operates at the half of the LO frequency and hence outside the system band. Aconventional structure for a subharmonic mixer is an antiparallel diode pair [98]. The passivetopology does not allow conversion gain, and is typically used in millimeter-wave applicationsto reduce the required oscillator frequency [99]. However direct conversion mixers withantiparallel diode pairs have also been developed for 1-2 GHz range applications [59], [100].An active even-harmonic mixer is also established for direct conversion receivers using anemitter-coupled transistor pair [101]. The quadrature generation at the half frequency LO needsan unconventional structure because the 90°-phase shift at the RF corresponds to a 45° shift atLO. The problem can be circumvented with quadrature generation for the RF signal as in [100]with consequences described above. Alternatively, the 45° phase shifters for the LO signals aredeveloped in [29]. Besides of the reduction in LO radiation, the even harmonic mixers do nottheoretically suffer from the LO self-mixing problem either, because the half-frequency input iscancelled when downconverted with itself. Only the second harmonic of the LO, which is muchlower than the fundamental, may cause self-mixing in the ideal case.

By far, the discussion is concentrated on the required I/Q balance, techniques to generatequadrature signals, and finally on some aspects on the LO radiation and self-mixing in differentstructures. The I/Q balance at the LO ports of the mixer is however not a measure for thequality of the quadrature signal path. The conversion efficiency of the mixer does not dependdirectly on the LO amplitude. Typically, a mixer is operated in a region where the conversiongain has reached the maximum value or is very close to it. For example, the slope of the gainversus the LO amplitude is less than 0.2 dB/dB in the nominal operation point of differentmixer structures implemented for the WCDMA receiver. The measured gain versus LO poweris shown for the single-chip WCDMA receiver in Figure 4.12. Hence, the amplitude balance ofthe direct conversion receiver is dominated by the mismatches at the signal path rather than theimperfections in the quadrature generator if located at the LO path. Of course, a mixingoperation can be performed with a multiplier as well, and for example the Gilbert cell basedtopologies are multipliers when the LO drive is at a sufficiently low level. Besides of lowergain, the linearity decreases with the reduced LO in a Gilbert cell operating as a multiplier.Hence, multipliers are not discussed as potential mixers for direct conversion. The amplitudeerror in the LO signal is however very important because the amplitude difference, or actuallythe slew rate, of the signal causes unequal phase delay in the node with a limited bandwidth[102]. This leads to a problem of AM-to-PM conversion in the buffering stages andcommutating switches of the downconversion mixers [50]. A limiting amplifier can be used toreduce the potential amplitude imbalances due to the process variations in a single-stage RC-network like in [12] and [103]. In that case the phase response of the limiting stage is criticalinstead of the commutating switches and the possibilities to correct the imbalance are thereforerather restricted. The AM-to-PM conversion is discussed here as a source of a fixed phase errorin the signal path although the amplitude modulated distortion in the LO signal may cause moresevere consequences. The harmonic content of the LO signal is another source of phase andamplitude errors in a narrow-band quadrature generator in addition to the mismatches asdepicted in [50].

128

4.3.4 Filtering

The channel selection filter in a direct conversion receiver can be implemented with an activelowpass filter. However, the sufficient attenuation of unwanted channels and the characteristicsof matched filtering are very difficult, if not impossible, to realize simultaneously with ananalog filter. Besides that the noise and linearity specifications for the baseband processing areharsh. The possible solutions for the channel selection include at least digital filtering withanalog antialias stage, analog filtering with phase equalization either in analog or digitalmethods, combination of analog and digital filters or only an analog structure. The firstalternative would require a large number of bits as discussed in chapter 2. Hence, the powerconsumption of a Nyquist rate converter would be unreasonable especially because the clockrate is also significantly increased. The on the other hand, have significantlysmaller power consumption with high clock rates, but the signal bandwidth may not suffice inwide-band systems. It means that some analog filtering is necessary at baseband in a directconversion WCDMA receiver. One alternative solution is to adopt directly an analog matchedfilter using for example switched-capacitor (SC) integrators [104]. The 8 MS/s clock raterequires still effective antialiasing before the filter, but no fast ADC is needed afterwards. Moredetailed analysis of analog and digital matched filters is given in [105].

Although the power consumption of digital filters scales down with the evolution of CMOStechnology, the most obvious alternative for the channel selection in wide-band systems is anactive analog filter based on some prototype. It should meet the two opposite criteria. First, thecutoff frequency must be low enough that it does not pass a significant amount of unwantedpower to ADC. Second, the phase response should not increase ISI. Often, this is solvedchoosing a prototype, which meets the adjacent channel requirement with the smallest groupdelay indicating the phase behavior. Digital or analog phase equalization should correct thephase afterwards if the performance is not sufficient otherwise. Another strategy is to rise thecutoff frequency at higher frequencies in order to shift the peaking in the group delay out fromthe signal band. This typically destroys badly the channel selection function. In a WCDMAreceiver, the 5th-order Butterworth filter with a separate pole at the input is a compromise of theanalog approach. The performance of this topology is compared to some other prototypes in

129

Table 4.3. Their properties are calculated from the arrangement in Figure 4.13 using parametersspecified in chapter 2. The first row presents the ideal raised cosine response as a reference. It isevident that all analog prototypes are far from the ideal performance. Also the effect of timingerrors calculated in the last column with a jitter of the sampling rate is much smaller inthe ideal case. Interestingly, the group delay behavior does not directly follow the parameterscalculated from the impulse response. Especially, the effect of highpass filtering in two lastrows gives totally different results. As predicted earlier the 2 kHz cutoff frequency in the dcoffset removal does not degrade the performance in the 5th-order Butterworth filter with a pole,and with an ideal raised cosine filter the total performance is still much better than with anyother prototype. The digital signal processing in CDMA systems has effect on the filterspecifications, and therefore it is not fair to speculate any longer with the acceptability of acertain prototype if the specific digital part is not included in the estimate. It is also possible tosynthesize filters, which resemble the raised cosine response better than any conventionalprototype [106].

In a direct conversion receiver, the channel selection filter is a part of the baseband processingblock. The baseband also amplifies the signal to an appropriate level before conversion todigital. The distribution of gain and filtering is the key issue when the dynamic range of thefilter is optimized. The type of the filter i.e. the IC architecture is another constraint for thedynamic range. In most cases continuous-time filters are used in reported direct conversionreceivers, but also a discrete-time SC-structure has been proposed [107]. The implementationissues of continuous-time filters are discussed generally in [108] and will not be emphasizedhere any longer. In the WCDMA receiver the active RC topology was chosen because itprovided a superior performance when both low noise and high linearity were required [16].The gain was embedded directly in filtering stages, which minimized the number of operationalamplifiers and optimized the linearity. Also, the digital gain control was included into thebaseband block without changing the frequency response at different gain values. A separatepreamplifier with an additional pole was though needed for noise reasons. The gain diagram ofthe baseband block including each stage is given earlier in Figure 4.6, and more details of theimplementation will be given in the next chapter.

130

4.3.5 A/D Converters

The new wireless systems and also radio architectures, which bring the A/D conversion closerto the antenna, are changing the requirements of the A/D converters in cellular communications.In the second generation mobile systems, the digital interface operates typically at severalhundreds of kHz or couple of MHz sampling rate and uses a reasonable number of bits even ifthe channel filtering is partly performed digitally. In the third generation systems, the widerbandwidths require higher sampling rates and only the despreading needs 4-6 bits from theconverter. The specifications of the A/D converter change completely if practically all filteringexcept of the preselection in the RF front-end is performed digitally. Both the resolution and thesampling rate are drastically increased. In this subsection, a comparison of different reportedA/D converters is given. They are divided into two categories: Nyquist rate and converters.The focus is only in their performance as a part of the radio system. Wireless communicationsare however just a single application for A/D converters. Therefore many structures areoptimized for other purposes. The converter architectures are not discussed here. A tutorial ofthe topic especially for telecommunications is given in [109].

The performance of the A/D converters is specified and measured with different quantities andtesting methods than other blocks in the receiver chain [110]. The differential (DNL) andintegral (INL) nonlinearities describe the maximum deviation from the ideal difference betweentwo consecutive transition points and from the ideal line over the total input range, respectively[111]. The both parameters should be within half of the LSB to meet specifications for a certainnumber of bits. However, they can not be directly transformed to IIP3 values in the receiver,which is needed if several channels with large differences in power levels are converted. Hence,the issue must be focused in the case of a purely digital channel selection. One of the purposesin this ADC comparison is to study the feasibility of such a converter. A brief discussion of theADC linearity from the receiver point of view is given already in [112]. The compression of theconverter is simply modeled as a limiting function, which is a theoretical quantity. Probably thenonlinearity would require a more sophisticated characterization. Here, it is however assumedfor simplicity that the linearity of the different ADCs is sufficient and no other measure than thenumber of bits is required to define the dynamic range. The effective number of bits can becalculated from the measured signal-to-noise and distortion ratio (SNDR) as

131

SNDR and spurious free dynamic range (SFDR) are more important parameters for ADCs inwireless communications than DNL or INL, which describe the static properties. The effectivenumber of bits may be smaller than the value of implemented bits in the converter. However,the latter is used in the following plots because of the common habit to report the results.Another significant limitation is the input frequency range in practice. Theoretically the Nyquistrate converters operate up to the half of the sampling rate, but in many cases they have beentested only for significantly smaller frequencies. The theoretical limit has been used here, but itmay give a too optimistic figure of merit for high frequency behavior. A converter can alsohandle input signals up to the Nyquist rate in its input without aliasing, but the desired signalband is limited due to the shaping of the quantization noise as

where is the sampling rate (or frequency), OSR is the oversampling ratio and the signal bandis This is again a theoretical value. In the bandpass converters, the desired signallies around some IF instead of dc as given above. In the following comparison, the performancemetrics are slightly in favor of the A/D converters because the numbers are theoreticaloptimums rather than measured values of the implementations. The necessary data for the latterapproach is however not available in a unified form and therefore comparison would be evenmore difficult.

Totally 68 converters published in academic conferences and journals between 1987 and 2000are included although most of them are from the year 1995 or later [113]-[180]. The numberconsists of 49 Nyquist rate converters and 19 converters. The total power dissipation isplotted in Figure 4.14 for different converter types and resolutions when the product of thesampling rate and the number of bits is given in the x-axis. This method allows thecategorization of the A/D converters for different systems and architectures in the x-axis.Instructive requirements for those are given in Table 4.4. The terms digital baseband, IF and RFmean that all filtering is performed digitally and that the whole system band from dc is insidethe Nyquist limit. Hence, the possibility to subsample a bandlimited IF or RF is not considered.The ovals in Figure 4.14 describe only roughly the range of interest and the dimensions in the y-axis are arbitrary. The recent focus in the academic research has been mainly in the converterstowards the digital baseband giving the high-end performance. The circuits for the 2ndgeneration systems are already mature structures, and the information for those could be foundfrom the data sheets of commercially available products. The dots in Figure 4.14 form a fuzzycloud. Therefore some trend lines have been drawn whenever at least three samples are givenfor each resolution. The solid lines present 6,8,10,12,13 and 14 bit Nyquist rate converters anddashed lines 11 and 12 bit structures.

The A/D converters used in the chip set [94] and in the single-chip [39] versions of theWCDMA direct conversion receiver are also included in the plot. They were specified also forhigher chip rates meaning a higher clock frequency. Therefore both converters are locatedoutside the typical area for the required 3rd generation performance. This explains the relativelyhigh power consumption in the standard WCDMA operation. Compared to their optimalperformance as given in Figure 4.14, the consumption is less than average. When operated atlower clock frequencies the total power consumption scales down very poorly in somearchitectures.

132

The Figure 4.14 indicates clearly the rapidly increasing power consumption when therequirements of the ADC increase. This is evident and distinct merit on behalf of analog signalprocessing. In power critical applications, the role of the analog signal processing will remainvery important because of the high cost in analog-to-digital conversion. Consequently, theevolution of conversion techniques has brought more digital architectures available for otherapplications. Still, the digital RF is not a very feasible solution although some converters areapproaching that area.

To observe the different effects of resolution and sampling rate the power consumption per bitis plotted as a function of sampling rate in Figure 4.15(a). The trend lines, which are plotted forthe same resolutions as earlier, show the incremental power consumption when the number ofbits is increased. Even more significant is the effect of the sampling rate. The 6-bit convertersgiven in Figure 4.15(a) are emphasized mainly for very high sampling rates, and the obscurebehavior is explained with a single sample below 100 MHz. The effect of the technologyscaling on the performance is studied in Figure 4.15(b). As a measure the power consumption isdivided with the sampling rate for 10-bit Nyquist rate converters. The technology does not seemto provide any decreasing trend when the structures are reduced. Hence, although the digitalpower consumption scales down with faster technologies the A/D converter is still a bottleneckfor the reduction in the total power dissipation.

133

134

4.3.6 Decoupling

The supply voltage node must provide a good ground for high frequency signals in unbalancedcircuits and also for common-mode signals in differential structures. Also, a stable supply isrequired to prevent noise and power transients from coupling to analog signals. This is criticalespecially in large digital or mixed-mode ICs with high peak currents in digital supplies. Thedecoupling capacitor, either on-chip or external, may not be adequate for the purpose because ofan unwanted resonance formed with the inductive bondwires or package pins. Hence, carefulanalysis and more complicated structures are needed to avoid the problem. Decouplingstrategies have been analyzed thoroughly for digital CMOS circuits in [181], and protectionagainst supply noise in mixed-mode ICs is discussed in [182]. Here some comments are givenof the decoupling strategies for the RF front-end in a mixed-mode structure.

The impedance between the supply rails in the chip can be given with a simple model in Figure4.16(a). The inductance gives the total series inductance of external supply and groundinterconnections to the chip. The external impedance between the ground and the supplyinterconnections is assumed zero for all frequencies except dc. If the approximation is notaccurate enough more passive R, L, and C elements are needed, which complicates the analysis.The capacitor presents the parasitic capacitance between the supply and ground in thecircuit and the possible high-quality on-chip decoupling capacitor. To avoid the resonance at thefrequency an RLC decoupling method is proposed in [182]. The principle isshown in Figure 4.16(b). If the value of the resistor is chosen correctly, the bothresonances of the structure are damped i.e. no peaking is observed and the impedance betweenthe supply and ground rails settles to an acceptable level at all frequencies. The structure avoidsthe power supply loss compared to the case when the resistor is connected directly in series withthe supply rail. The same effect with a different frequency response is achieved with a simplerstructure in Figure 4.16(c). The large on-chip decoupling capacitor is damped with a smallresistor The impedance between the supply and ground, can be now given as

It is evident that can have resonance only when both the real and imaginary parts of thedenominator are simultaneously zero. The real part is zero when and theimaginary one when If peaking is not possible and hence unwantedresonances with high Q values are avoided in all cases. The damping resistor however has effecton the maximum possible impedance. The given structure avoids the external tuned RLC-network and is insensitive to component variations. The small resistance can be implementedon-chip with a large number of parallel resistors in series with a large decoupling capacitor.This is the decoupling strategy, which has been used in the WCDMA receiver.

The simulated impedance is given for different cases in Figure 4.17. The nominal resonancefrequency of the LC-network is chosen to be 2 GHz in the simulations. The values of thedamping resistance are swept from zero to both for the RLC and RC damping networks.The other values are and The resonance andcomponent values were the same as in the unwanted resonance in the case of RLC network. Thetwo high peaks are easily damped with small resistors, and the flat response was achieved with

At higher values the resistor dominates the maximum impedance point. The RCnetwork damps as efficiently the high resonances as the RLC method. In the simulations thevalue of the decoupling capacitor is small compared to the high-quality capacitance. Thispresents the worst-case condition and the smallest impedance maximum is only slightly below

135

However, if the coupling capacitor is enlarged, which is typically the case, the maximumimpedance can be easily dropped below This shows that the efficiency of the simpler RC-structure as a decoupling network is about the same as with the RLC method. The extrainductor is definitely not desired if it can be avoided with another technique.

In single-ended structures, the resonance of the decoupling circuit is in series with the loadresonator of the LNA. The frequency response of the LNA will change if the unwantedresonance appears close to the desired operation frequency and the maximum is very sensitiveto component variations. This is a second reason for the use of a damped decoupling network inthe RF front-end.

136

4.4 Active Mixers in Direct Conversion

In this section, active mixers for direct conversion are discussed, and the main emphasis is inthe IIP2 analysis with respect to some topological constraints. As depicted earlier, symmetry isa key issue to restrict dc offsets and envelope distortion at the output as much as possible. Itshould be taken into account throughout the design from the choice of topology to layout.Especially, if IIP2 is a critical design parameter even a small deviation from the perfectsymmetry may cause unacceptable corruption in the performance.

4.4.1 Active Mixer Topologies

The term active mixer is somehow misleading by itself. Actually, switching mixers exhibitfundamentally loss in the commutating switches, but conversion gain can be obtained betweeninput and output terminals because an amplifying stage is included in the mixer. If the voltageconversion gain is of interest, only the impedance transformation to a higher level canoverwhelm the loss in the switching. On the other hand, the ideal switching function as an LOgives always the largest possible conversion gain. The nearly ideal switching shifts tomultiplication between the two input signals when the LO excitation is decreased. That reducesconversion efficiency between the RF port and the IF output from the maximum and the circuitoperates as a multiplier. If the other tone i.e. LO is constant, the structure can be still used as amixer. For linearity and noise reasons, the multiplier operation is however not very commonlyused as a downconverter. Another example, the four-quadrant CMOS multiplier discussed insubsection 4.3.2 operates in the multiplication mode, but can provide a much larger gain withthe same linearity than the more widely used switching structures. The definition of itsconversion efficiency however differs from the conventional as given in [62], and the efficiencydepends on the external connections like with all other topologies.

Why giving all the pedantry above? An active mixer can be defined as a structure in which thecore transistors are biased so that the supply current flows through them when the switch isoperating as a pass transistor. However, the term active mixer is often connected intuitively tothe structure given in Figure 4.18. First, the input voltage is transformed to current in a V-Iconverter. Then the current is multiplied with the gate- or LO-function, and finally convertedback to voltage in the load. Often but not necessarily all blocks are stacked in the same supplypath. This description is simplistic and obvious, but useful for modeling theoretical performancein subsection 4.4.3. The term active mixer in this subsection is limited to this structure, which isdefinitely most commonly used in the integrated radio receivers. Both single-balanced anddouble-balanced structures are considered.

137

All active mixers originate somehow from the four-quadrant multiplier, which is generallycalled as a Gilbert-cell [183]. The topology is shown in Figure 4.19. The double-balancedstructure was developed to reduce the distortion at the output compared to the common emitterdifferential pair. With current IC technologies the improvement in the performance using thedouble-balanced structure is not necessarily very significant. Therefore, the single-balancedtopology is often used to avoid single-ended to differential conversion at RF. Also, MOSdevices are adopted instead of bipolars in many recent RF applications. Because both single-and double-balanced topologies are discussed, a transconductance mixer is a more appropriateterm for general use instead of the Gilbert mixer in this case.

The linearity of a transconductance mixer depends on the V-I converter and the switching quad.The former is typically considered as a dominant part if switching in the LO transistors isarranged properly. The conducting switch operates as a cascode stage half of the LO period andthe transitions between the on and off states are abrupt. This is however a too simplistic modelfor practical cases. The characterization of the nonlinear switching operation requires complexdifferential equations including several device parameters as analyzed for a bipolar core in[184]. The theory predicts that the third-order intermodulation distortion achieves a minimum ata certain LO voltage drive level. This can be observed as a maximum in IIP3 characteristics inFigure 4.20. The result is measured for a bipolar core from the direct conversion RF front-endin [185], which is a part of the WCDMA receiver [94]. The degradation in linearity is howeveronly a couple of dBs at higher drive levels. Only the third-order intermodulation products are ofinterest in a RF mixer of the superheterodyne receiver. The significant spectral replicas arelocated at the band of interest both before and after the downconversion. The performance is notsensitive to small mismatches between components, and therefore the IIP3 can be simulatedwith a good accuracy if precise transistor models are available. In a direct conversion receiver,the IIP3 behavior does not significantly vary from the previous. Only the parasitic effects areless significant at the output because of the lower operation range. Also, the preliminaryfiltering of the high out-of-band interferers can be easily performed with a RC-poleimmediately at the output of the mixer. Instead, IIP2 is always infinite in the ideal case, and thedistorted signal is located around baseband or double-frequency after the nonlinear element asdiscussed earlier. Hence, the characterization differs significantly on the third-order nonlineareffects. The requirements of component match and IIP2 will be discussed in the next twosubsections.

138

The V-I converter operates typically in the active region if bipolar devices are used, and insaturation in the case of MOS transconductance stages. A transconductance stage biased in classAB can be used with bipolar devices to increase the compression point and hence the blockingperformance [186]. This technique however does not benefit the small signal IIP3 behavior, andwill not be discussed or utilized later. The theory behind the small signal linearity of bipolar andMOS devices is thoroughly discussed in [187], and a detailed analysis focused more specificallyon the bipolar transconductance stages in active mixers is given in [188]. A known fact is thatthe linearity of a bipolar transconductance stage both in common-emitter and differential-pairconfigurations is very limited and not necessarily sufficient for RF downconversion mixers. Themost common linearization technique is the emitter degeneration at the cost of gain and noisefigure. Typically, this is done with a resistor increasing the internal emitter resistance of thedevice. It has been shown however that a better performance can be achieved with inductivedegenaration [189]. Another important statement in the given analysis was that the common-emitter transconductance stage achieves the same gain and linearity as the correspondingdifferential pair configuration with a lower current consumption.

Bipolar differential pairs can be linearized also using parallel, differently sizedtransconductance stages, which increase the acceptable input signal range [190], [191]. Thetechnique is called according to Gilbert as the multi-tanh principle, but also other terms likeunbalanced emitter-coupled pairs is used. A tutorial of the technique, and different circuittopologies are given in [192]. A third well-known technique to improve the linearity of the V-Iconverter in variable-gain amplifiers and transconductance mixers provides extra supply currentfor the converters from a separate source [193]. Recently, the linear range is extended using acommon-emitter/common-base transconductance stage described in [194] and [195], andapplied to a superheterodyne receiver in [196]. The topology is often called as a micromixeraccording to [195]. It performs also the single-ended to differential conversion for the RF input.

The evolution of IC technologies has increased the operation range of MOS devices up to GHz-range. In a BiCMOS process, this can be utilized by selecting the most suitable device for eachfunction also at RF. MOS devices in the V-I converter exhibit fundamentally better linearitythan bipolars if the overdrive voltage is sufficiently large. Thereforedegeneration is not absolutely necessary in RF downconverters. Also, a properly sized deviceprovides a higher transconductance than a degenerated BJT [197]. The input devices can be alsoconnected directly to the circuit ground without a common tail current source as in [2], for

139

example. The improved linearity is achieved with the lack of common-mode rejection. Hence,the following stages should tolerate common-mode signals. It can be summarized that the MOStransconductance stages are excellent V-I converters, and with submicron technologies theiroperation range reaches quite easily 2 GHz. Hence, the frequency range does not limit thechoice between different devices in a transconductance mixer. If the large overdrive voltage isnot acceptable, because of too high current consumption or limited biasing conditions due to thelow supply voltage, for example, similar linearization techniques as multitanh-principle forbipolar devices are developed for low-frequency applications [198], [199]. The fundamentaldifferences between linearized differential pairs using either bipolar or MOS devices isdiscussed in [200]. However, sufficient input range has been achieved in recently reporteddouble-balanced mixers for receiver applications using NMOS V-I converters withoutadditional linearization [2], [64], [94]. The effect of technology scaling on the linearity ofmixers is discussed for example in [201]. The deep submicron MOS devices will still providebetter performance than bipolars as V-I converters although the difference is reducedsignificantly below gate lengths. A modified version of the micromixer adapted toCMOS was established due to the single-ended interface to a double-balanced mixer rather thanbecause of insufficient linearity in [202].

Only common-emitter and common-source stages are discussed so far. Especially insuperheterodyne receivers, which require a input match, a common-base or common-gateinput stage would be an optimal choice also for the linearity performance [44]. In the directconversion that is not necessary. In circuits with a low supply voltage, the transconductancestage can use a separate supply path like in [203]. In that case, the single-ended to differentialconversion is possible to establish with a LC-network at the input of the mixer core [204]. Otherlow-voltage techniques include replacement of the tail current sources with LC-tanks [205],[206], folded structures [199], and use of a transformer to bring the single-ended input to adouble-balanced mixer [52]. The references to linearization and low-voltage techniques are notcomprehensive, but present some important techniques and recent areas of interest.

In direct conversion mixers, the second-order distortion generated in the V-I converter is also ofimportance. However, the signal path to output differs from the desired signal as discussed inthe previous chapter. The second-order nonlinear components lie either at the double-frequencyor at the baseband. The former replica can be downconverted to dc if Theunwanted distortion is based on the second harmonic of the LO signal. This may be significant,but the interest is here only at the baseband product. It will be observed at the output ifdifferential branches are not perfectly matched. This behavior will be discussed in the next twosubsections. To cancel the contribution of the V-I converter to IIP2, a bipolar Gilbert mixer wasestablished in which the baseband and double-frequency beats from the V-I converter werefiltered with a passive LC network [33]. The measured results indicate over 20-dB improvementin performance, and the IIP2 of the mixer with LC-filtering was about +50 dBm. Similarapproach was taken in [31], but only the low-frequency part was filtered with a couplingcapacitor. A direct conversion mixer having a separate transconductance stage with a LC-tankload, which utilizes the bottom plate parasitic of the ac-coupling capacitor in the tank circuit, ispresented in [207]. The structure adopts the principle given in [33], and inverts the large,unwanted bottom-plate parasitics of the capacitor in a standard CMOS process into efficientuse. The different filtering approaches however do not give unambiguous results of theperformance improvement although the number of potential sources or at least theircontribution is reduced. Hence, the switching core and the mismatches at the output are equallyof importance. The results from direct conversion receivers using a conventionaltransconductance mixer report similar performances as with special techniques [2], [7], [15],[17], [94]. However, in all given examples MOS transistors are operating as V-I converters andon-chip LNA is connected directly or though a coupling capacitor to the input of the mixer.

140

4.4.2 Interfaces to LNA and Baseband

The RF interface between the LNA and mixer is critical even though the on-chipinterconnection should have small parasitics. The interconnection can be normally modeledwith a lumped RC-network including the capacitive input of the two V-I converters, andresistive losses of the wiring. The two transconductance elements model the I- and Q-mixers.The RC-time constant is not an appropriate model for the interface, if the load of the LNA is atank circuit, which is typically the case. The wiring and the input impedance of the mixers arethen a part of the tank. Hence, the interface should be an inseparable part of the LNA design,but it has also a significant effect on the linearity of the mixer.

Another critical factor is the coupling mechanism. In a standard CMOS process, direct couplingmay be needed because the large bottom-plate parasitics of the coupling capacitors may lead toan unacceptable trade-off in the sizing of the coupling element. The desired signal will leakthrough the low-resistivity substrate to the ground if the capacitor is too large. On the otherhand, a small capacitor leads to an unacceptable voltage loss over the capacitor at the signalfrequency in the division with the mixer load. An analysis of the different design strategiesusing a standard CMOS process with poly-capacitors in the ac-coupled RF interface is given in[208]. The coupling capacitor is then an essential part of the tank circuit. The results aresummarized in the next chapter. In the given example, the subsampling mixer caused additionalrequirements for the interface, but the methods are basically applicable to other mixertopologies as well. Similar trade-offs have been considered briefly also in [207] as discussedabove. The modern BiCMOS processes intended on the RF integration can contain high-qualitymetal-insulator-metal (MIM) capacitors. Their capacitance density is high, losses of the platesare low compared to polysilicon and the small area with a better substrate reduce parasiticlosses of the bottom plate to an acceptable level. MIM capacitors were available in theWCDMA receiver implementations, and therefore the ‘traditional’ RF design trade-offs couldbe followed instead of tricks necessary in a standard CMOS.

A mixer can be biased independently of the LNA if coupling capacitors are used. Otherwise, theload of the LNA determines also the biasing conditions of the input terminal in a V-I converter.In CMOS, this is possible and implemented at least in [7], [15], [51]. Large overdrive voltageimproves linearity, but on the other hand limits the supply range due to increased forexample. The design trade-offs in low-voltage conditions is discussed in the case of CMOS-only Gilbert cell in [209]. Also regulated biasing is needed in double-balanced structures toimprove matching [51].

In the simplest form, the downconverted current is transformed back to voltages for basebandprocessing with resistive loads. The possibility to use current-mode signal processing in thebaseband circuitry will not be considered here. The resistor approach requires excellentmatching for load devices in direct conversion receivers due to the IIP2. It will be discussed inthe next subsection. Because of the matching requirements the load resistors may not befeasible with all processes. The used BiCMOS process in the WCDMA receiver provided high-quality polysilicon resistors with small deviation in adjacent component values. The otheroption uses high-impedance current sources connected to the supply rail, and the load for signalis located between the positive and negative outputs as in [2], for example. The resistive load iseither a lumped resistor or a transistor operated in the triode region. The separate currentsources allow the biasing of the mixers to be independent of the load. The current sources andtransistor loads are however noisy and nonlinear. Especially, the minimization of flicker noiseis critical at the output and large devices are required.

In direct conversion receivers, the large out-of-band interferers can be attenuated preliminarywith a passive pole at the output of the mixer. This arrangement relaxes the linearity

141

requirements of the baseband if the pole is located relatively close to the actual cutoff frequencyof the channel selection filter. In that case, the passive pole should be included in the filterprototype and the matching of its cutoff frequency is critical for the linearity performance. Innarrow-band systems, the capacitor should be implemented with an external component like in[57], but in a wide-band receiver an on-chip structure is feasible [94]. The noise of the channelselection filter is often a dominant source of the noise performance in a direct conversionreceiver [15]. The optimum noise and linearity conditions may significantly differ from theoutput impedance and bias point directly available from the mixer. Therefore a buffer, typicallyan emitter or source follower, is required between the mixer and baseband [15], [94]. Thereduced impedance level however requires a significant amount of supply current, and bufferingstage can be the dominant source for the power consumption even in on-chip structures. Thebaseband circuitry requires also a stabile dc-level, which is independent of the supply voltage atits input. A common-mode feedback circuit (CMFB) can be used to control the dc level at theoutput of the mixer. The acceptable dc-level at the output of the mixer limits the supply rangemore than the linearity or gain performance in the WCDMA direct conversion receiver althougha CMFB is used [185]. The supply range can vary only about from the nominal 2.7 Valthough the gain and linearity are unchanged down to 2.1 V as given in Figure 4.21.

4.4.3 Theoretical Characterization of IIP2 in Transconductance Mixers

The analysis of second-order nonlinearity and how it appears in the direct conversion receiver isnot as straightforward as other nonlinear characteristics of the circuit. In a perfectly balancedcase, IIP2 is infinite and the result is independent of any other parameter as long as the balanceis not violated. This is a well-known fact and the mismatch behavior for analog multipliers hasbeen analyzed at least in [183] and [210] for bipolar and in [199] and [211] for MOS circuits.The given analyses are based on the large signal input-output transfer functions and they can beapplied to the mixer core. The traditional method to present the nonlinear behavior is to plot thesignal level at the output as a function of input as shown in Figure 4.22, and the results aretypically given in percentages from the ideal curve. It can be thought as an analog eye-diagramalthough the precision requirements are of course much stricter than with digital structures.

142

However, the method neglects the frequency transformation characteristics, and the results donot give much insight on the required matching in the case of a direct conversion mixeroperating in the switching mode. In this subsection a simple, functional model for a switchingmixer is described. The mixer core is replaced with a mathematical gate-function, which givesmore insight on the frequency transformation characteristics. Both the single-balanced and thedouble-balanced behavior will be discussed. In the next subsection, the gate-function is replacedwith the large signal model for a differential pair in the single-balanced mixer core. Theanalysis gives better understanding in the choice of devices for the core, although only a verysimple model is adopted. Also, the difficulty to model the frequency transformation even withquite simple mathematical equations becomes obvious.

The second-order intercept point was a problem already in the transmission of cable TVchannels some thirty years ago. The large signal levels of amplitude modulated channels andthe requirement of over a 66-dB relative attenuation of second-order beats were a problem forpush-pull amplifiers. They were used instead of individual amplifier stages to lower the outputpowers of each stage. The sum term was a more important problem at that time, but the analysisgiven in [212] does not take the frequency characteristics into account. This is because onlyamplifiers are characterized, the output response is wide-band, and the potential channelscausing the problem are known in advance. However, many aspects of the analysis are valid forthe downconversion mixers, but some complementary aspects are needed. In the amplifieranalysis, the mismatch parameters between the two signal paths were the amplitude error, andthe phase errors before and after the nonlinear element.

Three observations follow from the analysis in [212]. First, an individual imbalance term causesrapid degradation from ideal as the imbalance increases. The IIP2 curve drops according to

in dB scale, where is the imbalance term plotted in the x-axis and n the scalingfactor. The scaling factor depends on the type and position of the imbalance in the system.Second, two simultaneous phase errors shift the maximum IIP2 in the x-axis if one imbalanceterm is constant and the other is swept. Third, the amplitude error causes saturation of themaximum IIP2 value if either one or both of the two individual phase imbalances are not zero.The IIP2 follows then a bell-shaped curve instead of peaking in one individual point. Theseobservations will be of importance also for downconversion mixers. The variables modeling theimbalance are changed in the analysis and the results are specified for the mixer applications.Only the difference beat is considered in this case, but the corresponding results could becalculated also for the sum term if the second harmonic of the LO will be taken into account.Lambert names the phenomenon as a second-order improvement in [212], but it is only a matter

143

of terminology. Instead, the IIP2 is generally used in receiver applications. It should be noticedthat the analysis resembles also image rejection calculations discussed earlier, but the results arespecified for another purpose.

The analysis is performed here for a simple behavioral model given earlier in Figure 4.18. TheV-I converter is modeled with an ideal voltage controlled current source having also a nonlinearterms as

where is the transconductance of the V-I converter and is the nth-order nonlinear termwith respect to the fundamental. The relative terms are used for convenience in the analysis, andthe corresponding fundamental and higher-order terms in chapter 2 are andrespectively. In weakly nonlinear structures, as is the case with the V-I converter, three termsmodel the behavior with a sufficient accuracy. It is assumed in this model that all nonlineareffects in the transistor can be included in this equation independently of their source. Also, theoutput conductance is assumed to be infinite, and hence the operation of the transconductanceelement is totally independent of the state in the commutating switches. The ideal switchesperforming the frequency conversion are controlled with mathematical gate functionsand and the output current is converted back to a voltage with two load resistors.

A simplified behavioral model is shown in Figure 4.23, and it divides the structure in threeindependent parts as discussed earlier in subsection 4.4.1. The tail current, describes thebiasing of the V-I converter. If we compare the behavioral model to the transistor level design,it neglects all reactive elements. They are needed in the simulations of RF mixers, but theirinclusion complicates the analysis too much. Secondly, the active devices should be assumed tooperate in the saturation in the case of MOS and in the active region in the case of BJT whenthe transistors are ON. This is a valid condition for practical mixers. However, the actualchannel conductance and early effects should be included at least in the simulations. Also, themodel assumes that the quiescent current is zero when the commutating switches are OFF, andthat the transitions between the states are abrupt in the switches. It is obvious that this model istoo simple for circuit design purposes, but on the other hand it gives much information aboutthe fundamental restrictions of the IIP2 behavior, which can be applied directly to moreelaborate circuit models in the simulations. Some of the idealized parameters will be consideredwith more realistic models in the next subsection.

144

The analysis can be made simple because the switching operation in each switch is ideal and thesecond-order intermodulation component (imd2) is observed at the output only due toasymmetric conversion back to voltages or due to non-ideal timing of the switching moments.Hence, the analysis is actually based simply on the leakage of the difference beat to the output,but similar equation can be used for the sum term of imd2 or when using nonlinear switchmodels also in the commutation process. However, the combination of different nonlinearreplicas is not straightforward, although the signal source is the same, because the replicas aregenerated in different elements. Hence, only one nonlinear element is preferred, and the IIP2 isestimated in the case of one or more constant imbalances at a time.

Before calculating the IIP2, some comments will be given with respect to noise analysismethods for mixers as given in [213], [214], [215] and [216]. It is a well-known fact from themixer noise analysis that when the both commutating switches are ON simultaneously, thenoise from the core transistors is visible at the output [213]. That can be reduced with a steeperslope in the switching function by increasing the LO power. After a certain LO level thedownconverted noise from the input stage becomes dominant. It has been shown recently thatthe noise from the core transistors at large LO levels is not negligible either due to the finitecapacitance current from the common-source node of the commutating switches to ground[216]. This is significant especially in the direct conversion because the flicker noise of thecommutating switches drifts into the output through the mechanism. The noise analysis of themixers is a complicated issue due to the nonlinear time-varying characteristics, which leads tocyclostationary behavior of the output noise. However a single nonlinear function, which isindependent of the switching function, allows more simplified analysis and gives stillinstructive results. The different statistical properties of noise and distortion together with thefact that the noise behavior depends typically only slightly on the mismatch are the mainreasons for the need of a different approach.

4.4.3.1 Single-Balanced Mixer

The gain of an ideal balanced switching mixer can be calculated from a Fourier seriesexpansion of the symmetric square wave as given in [2] and [64], for example. The fundamentalconversion loss of and the voltage gain of

follow directly from the analysis. All even-order terms are however zero, which means that thispresentation gives an infinite IIP2 in all cases independently of other parameters. Therefore thegate function must be modified to include the time when both switches are ON and also unequalconduction times for each switch. The former can model the dc-leakage through the mixer andthe latter asymmetries in the switching operations. Such functions should be given separatelyfor positive and negative gate functions as

145

and

where and are the duty cycles of the positive and negative gate functions, andThe ideal gate functions are presented in Figure 4.23. The different duty cycles

model the unequal conduction times. They can be given as

and

where is the nominal value of the duty cycle and is the difference in the duty cyclesbetween the positive and negative gate functions. The differential gate function

returns to the Fourier series given in [2] and [64] when andThe positive and negative gate functions for and are presented in Figure

4.24(a) when the curves are plotted up to the second and fourth harmonic in the Fourier seriesof the LO. In this analysis, the interest is in the downconversion of the fundamental signal,which defines the gain, and in the even harmonics. For the calculation of the small-signal gain,only the from the odd harmonics is required in the gate function. On the other hand,the envelope distortion component is the same at the baseband and at after the idealnonlinear operation as given in chapter 2. Hence, the possible dc leakage should be compared tothe downconversion gain from The amplitudes of the second and fourth harmonic of theLO in the Fourier series are compared to the dc leakage at the single-ended output and plottedas a function of duty cycle in Figure 4.24(b). In the range of interest i.e. around 0.5, theharmonics are almost negligible compared to dc. Hence, the higher harmonics are omitted inthis analysis, but in practical cases the condition is not necessarily valid. The effect of the

should be checked in the two-tone measurements by an appropriate choice of testfrequencies.

146

The currents in the positive and negative branches can be now calculated for the terms ofinterest. The RF input signal is given as The interesting currentcomponents at the lowpass filtered outputs are

and

where is the downconverted signal and is the low-frequencybeat. The second mismatch term, in addition to an unequal duty cycle, is the imbalance in theload devices. The load resistors are given by

and

where is the nominal value of the load resistance and the relative mismatch. Using thesetwo mismatch terms the differential output voltage can be given as

147

It is assumed that the common-mode term is rejected sufficiently at the output and it can beignored. The voltage gain gets a complicated form

However, it is quite easy to show that the latter term is negligible if which is arealistic assumption. Also, the cosine part from the former term is typically close to unity.Hence, gain is almost independent of mismatches, but degrades to some extent when bothcommutating switches are simultaneously ON. The gain degradation as a function of thenominal duty cycle is given in Figure 4.25. Also, two fixed and relatively large mismatches areplotted in the same figure. They have only minor effect on the performance as stated above.

148

The second-order input intercept point can be now calculated from the fundamental and theimd2 terms as

The value is a rms-voltage quantity. Usually, it is practical to refer the value to the inputpower i.e.

In decibels, the corresponding in the impedance level. The IIP2depends only on the imbalance in the system. For the simulations it is not a very usefulestimate, because the IIP2 result requires always a certain imbalance parameter defined inadvance and the MonteCarlo simulations in the case of harmonic balance are very slow for acomplete mixer. The quality of the circuit against second-order distortion can be easily dividedin two different quantities i.e. the fundamental distortion and the effect of balancing. Theformer can be defined for example from the single-ended output of the mixer. It is not directlythe of the transconductance because of the switching function. The single-ended iip2is defined here from the positive output in the nominal conditions i.e. as

This term is independent of the balancing and can be simulated with the same confidence as theother nonlinear effects. A larger value indicates always a smaller sensitivity against envelopedistortion. Direct measurement is also possible, and therefore the effect of imbalance can beseparated from the fundamental nonlinearity. A similar approach can be used also for double-balanced configurations by applying only a single-ended signal to RF input. To alleviate thenecessity of excellent balancing, a quantity of balancing factor is defined here as

The balancing factor depends on the matching properties of the devices in the IC process andthe layout of the circuit. If the probability distribution functions (PDF) of the different processvariations are known and the sources of mismatches are recognized in the circuit topology, thebalancing factor can be used to estimate the yield of certain IIP2 value, for example. The otherimportant parameter in the direct conversion mixer i.e. the dc offset at the output can be alsodefined from the above calculations as

It shows clearly the part, which depends on the input signal amplitude. IIP2 is plotted as afunction of a single imbalance with different parameters in Figure 4.26(a). The mismatch in the

149

load is a significant reason for the IIP2 degradation, but the fundamental nonlinearity is alsovery important for the performance. The single-ended IIP2 is +20 dBm in the nominal case. Theboth imbalances are included simultaneously in Figure 4.26(b). It shows that two imbalancesmay degrade the performance significantly from a single mismatch if they are summed. On theother hand, the maximum of the IIP2 shifts as a function of the other mismatch as expected.

4.4.3.2 Double-Balanced Mixer

In the case of double-balanced mixers, the calculation of IIP2 requires some more effort. On theother hand, new variables of imbalance can be adopted. The following analysis includes thetransconductance mismatch of the V-I converter and the amplitude and phase imbalances of theRF input signal. The double balanced mixer is basically the Gilbert-cell in Figure 4.19 in whichthe transistors are replaced with ideal models as in Figure 4.23. The V-I converters in eachbranch are however independent voltage controlled current sources instead of a differential pair.Hence, there is no common-mode rejection available in the input stage and the tail current isalways divided equally between the devices. This is a slightly artificial approach but still usefulto alleviate some issues. The transconductance stage can be replaced with a transistor leveldifferential pair in a more sophisticated analysis. Some properties of differential pairs will bediscussed in the next subsection. In that case they are operating as nonlinear switches ratherthan as weakly nonlinear input stages.

The input signal is given separately for positive and negative input terminals as

150

and

The presentation takes into account the effect of a 180°-power divider without any insertionloss, but the amplitude and phase imbalances are included. The amplitude imbalance is assumedequal for both signals in the two-tone test, and the amplitudes at the positive and negative inputsare given as

and

where is the amplitude imbalance. The phase error is included only in the negative inputand the difference in phase errors between the two different tones is

Because the two tones have the same signal path and the relative frequency difference betweenthe tones is typically rather small the difference term can be assumed to be much smaller thanthe phase error of an individual tone. The total transconductance of the V-I converter isassumed to be the same as in a single-balanced mixer and hence the transconductances of inputdevices can be given as

and

The nonlinear terms, are assumed equal in both branches. The given precautions should becharacterized separately with respect to biasing and other transistor level parameters if acomparison of properties between the single- and double-balanced mixers is made. However,they are sufficient when the theoretical differences in the IIP2 behavior are analyzed.

If only one fundamental component, and the low frequency terms are given, the outputcurrents of the V-I converters are

151

and

The differential output is then given as

After lowpass filtering the output can be written as

where

The and term collect the IF components and and the low frequency components. If itis assumed that the gain is relatively independent of mismatch, which can be calculated fromthe above presentation, the voltage gain of a double-balanced mixer can be given as

152

It differs only by a factor of from the single-balanced, which is due to the single-ended todifferential conversion. The second-order intermodulation term however achieves a complicatedform

If the second and third factors of each term are multiplied and the components, which have asquared mismatch term or multiplication of two different mismatch terms, are consideredinsignificant in the summation, IIP2 can be written as

Still the equation is quite complicated and contains a large number of independent variables.When the sum term in the denominator is calculated and assumed that theimbalance terms multiplied with it can be neglected. Hence, the IIP2 simplifies to

There is one important difference in this analysis compared to the single-balanced case. Thedenominator is zero when Hence, the maximum of IIP2 is achievedwhen the resistance mismatch is about one decade smaller than other imbalances. If differentimbalances are at the same range in percentages, the maximum shifts far from the ideal situationas shown in Figure 4.27, and the IIP2 value is saturated almost to a constant level in the vicinityof circuit balance. However, rather small changes in a single mismatch term may significantlychange the ‘saturated’ IIP2 value. In Figure 4.27, a single-balanced and a double-balancedmixer is compared as a function of Nominal conditions are the same as used earlier. Theslightly better performance of the double-balanced mixer is due to the smaller gain. The phaseimbalance at the input of the mixer is practically negligible. The interesting curves are those,

the same position, which makes sense, and therefore is kept zero in Figure 4.27.

153

which are plotted for fixed Input amplitude and transconductance mismatches are in

The analysis shows that it may be difficult to achieve a high IIP2 even when tuning is used.Theoretically it may be possible but this analysis gave only one possible reason for thesaturation of IIP2 and a rather limited set of mismatches. More complicated models areprobably necessary. The characterization of different mismatches and their relation is extremelydifficult if very small imbalances may shift the ideal point of IIP2 far from the nominal as thismodel predicts. Although this behavior is observed only in the case of a double-balanced mixer,it is reasonable to predict that similar cases can be found also for the single-balanced case. Inthe case of single-balanced mixer the dc offset at the output was dependent on the samemismatch parameters as IIP2. In the analysis of double-balanced mixer the dc offset, whichdepends on the tail current is directly

The signal dependent part is neglected, but it follows the imd2 behavior like earlier. The dcoffset from the tail current does not depend on which is natural for a double-balancedstructure. It also shows that the dc offset and IIP2 are not necessarily tied together.

Because only a simple behavioral model is used, it is too early to make very definitiveconclusions. However, the issues discussed here can be intuitively combined with themeasurements performed throughout the receiver project. Also, it is possible to connect theresults to some earlier experiments reported in literature although very little background andpractically no analysis have been given on those IIP2 tuning trials. In [31], a 15-dBimprovement up to +50 dBm at the input of the mixer was reported using bias adjustment. Adigital tuning circuit and 3-bit DAC controlling the tail currents of direct conversion mixer in[29] resulted into about 10 dB better IIP2 of +37 dBm at the input of mixer compared to theuncompensated case. The dynamic matching technique in [217] provided also about 15 dBimprovement but the IIP2 of +72 dBm is the best reported result so far.

The given discussion is valid for double-balanced mixers. The behavior of transconductancestages, which perform also the single-ended to differential conversion like the micromixer

154

[194], [195], is more likely a combination of two parallel single-balanced mixers when IIP2 isanalyzed. The second-order nonlinearity should be analyzed separately for the two differentsignal paths between the input and the core. The symmetry conditions in the sense of IIP2 aremore complicated to achieve and not discussed here any further.

4.4.4 Switching Core

So far, only the frequency conversion properties of the core transistors have been characterizedusing idealized models. In this subsection, some basic properties of bipolar and MOS transistorsare discussed when they operate as commutating devices in a direct conversion receiver. Theeffect of LO amplitude on the conversion gain is given, and the IIP2 is calculated for a single-balanced mixer using a bipolar differential pair as a core. The discussion is limited only tosingle-balanced structure in order to restrict the number of variables and to keep the analysissimple. It is also assumed that the V-I converter is the dominant source of nonlinearity, and onlythe mismatch of the differential pair is taken into account.

The first-order large signal model for the collector current of a bipolar transistor operating as aswitch in the mixer core can be given as

where is the saturation current depending on the process parameters, emitter area and basewidth. The thermal voltage, is 26 mV in the room temperature, is the base-emittervoltage in the biasing point when no LO is applied and is the differential LO voltage inthe switching pair. It is assumed that the core transistor operates always in the active regionwhen it is ON. The transfer function of the switching pair follows then the well-known

behavior [218]. If the LO voltage is sufficiently large the conversion efficiency ofthe mixer comes directly from the ideal switching function as given earlier. Otherwise, theamplitude of the LO signal has effect on the voltage gain. The degradation from the maximumgain is given in [188] as

where is the differential amplitude of the LO signal. The curve is plotted in the roomtemperature in Figure 4.28. With a sufficiently low LO amplitude, the structure is not aswitching mixer but a multiplier as can be seen from the figure.

155

The analysis of a MOS mixer core is not as straightforward because the overdrive voltage,has a more complicated relation to the current division in the differential pair than in

the case of bipolar devices. The large signal transfer function of a MOS differential pairoperating as mixer core can be given as [187]

using the level 1 MOS model in which the drain current of MOS switches in saturation issimply

voltage of each individual device, is the threshold voltage and is the tail current of theswitching pair. A relatively simple approach to analyze the differential pair as a switching coreis taken in [64]. The gain degradation is calculated based on the time when both switches aresimultaneously ON for a short while. The gain degradation can be given as

The above formula however assumes that the amplitude of the LO signal is sufficient for perfectswitching and only the simultaneous conduction degrades the gain from A moreelaborate model is given in [214] including the effect of LO swing and short-channel effects ofMOS devices. For a sinusoidal LO the gain degradation can be written as

156

where is the process and size parameter, is the time-varying gate-source

where is a function of device and process parameters and biasing including the tail currentand overdrive voltage of the switching pair. should be always larger than in the mixer.The latter analysis is however rather complicated for comparison between the MOS and bipolardevices. The simple characterization of V-I transfer functions as in Equation (4.59) gives moreinsight on the matter. The transfer function in the case of MOS devices depends on theoverdrive voltage in the biasing. The large overdrive voltage, which is often desired, requires alarger LO amplitude for the switching. The transfer functions are plotted for bipolar and MOSswitching pairs in Figure 4.29. The product of load resistor and tail current is unity in bothcases. This corresponds to a 1 mA tail current and load resistors, for example. The MOScurves describe only the upper formula in Equation (4.59), which is not valid when

The limitation is evident in the plot. Although the overdrive voltage is anadditional parameter compared to bipolar implementations and gives some flexibility in design,the required LO amplitude is typically much larger for the MOS core in the switching operation.This is a well-known trade-off, which prefers the use of bipolar devices in the core. However,the required source power is not directly connected to the amplitude because of different inputcharacteristics of the various devices. In principle, it is also possible to operate the MOS core inthe weak inversion in which the behavior resembles a bipolar one. However, large devicesbiased to a low current are needed. This option is not very feasible in the RF design andtherefore only mentioned here. The gain degradation is plotted as a function of LO amplitude inFigure 4.30 using the both MOS equations and compared the results to the bipolar core. Thethin lines presenting Equation (4.62) are plotted for V and 1.1 V. The latter is calculateddirectly for the MOS devices biased with a 5.6 mA tail current as given in [214],and the former is realistic with a smaller biasing current.

157

Although the required LO amplitude is of importance when the core transistors are chosen theflicker noise contribution of the switching devices is practically a more difficult issue in directconversion receivers. The inherently higher flicker noise of MOS devices is a serious problemespecially in narrow-band systems if the modulated information is located around dc and thenoise figure requirement of the receiver is very low. The low flicker noise requires large MOSdevices, which may have too large parasitics for the GHz-range operation. The flicker noisecontribution is significantly reduced if the channel can be highpass filtered up to tens of kHzlike in [15]. The 11 MHz bandwidth at baseband in [7] is large enough to restrict the flickernoise contribution much below 1 dB. However, the total noise figure of the receiver is still over8 dB. Even in low-IF topologies care must be taken into flicker noise. It is reasonable at100 kHz in [219], but deteriorates badly the information below 80 kHz. As discussed in [51]and analyzed more detailed in [216], the flicker noise in MOS mixers can not be eliminatedeffectively even when high LO signal levels and hence abrupt switching is used. The recentresults of dynamic matching to improve the IIP2 in a direct conversion receiver seem to workefficiently also in the cancellation of flicker noise in MOS structures [217]. Still the use ofbipolar core is strongly preferred in the mixer because an acceptable flicker noise performanceis achieved with relatively small devices. Hence, the capacitive effects remain small providingfast transitions between the states and high frequency operation.

4.4.4.1 IIP2 Analysis for Single-Balanced Mixer Using Bipolar Core

The core transistors have effect on the IIP2 in the direct conversion receiver as depicted earlier.However, the nonlinearity in the signal path can not be modeled with the first-order transistormodels as given above because the signal current is directly multiplied with harmonics of thegate function and only the frequency conversion is included in the multiplication. The nonlinearproducts of the signal have been generated always before the gate function. Hence, morecomplicated models should be used. A large variety of different effects are described in the caseof weakly nonlinear behavior both for bipolar and MOS devices in [187]. However, the

158

characterization of the switch in the ON-state as a cascode stage and in the OFF-state as anopen circuit is definitely not very accurate especially because many nonidealities in the mixercome from the strongly nonlinear switching operation. Unfortunately, the nonlinearcharacterization of the core leads to complicated equations, which can be only solvednumerically [184]. In the case of IIP2, the equations should be combined with mismatchanalysis and the results do not probably give more insight on the nature of the phenomenon thana simplified analysis presented next.

The simple model in Equation (4.20) is still used as the only nonlinear function. In addition tothe load mismatch, the saturation current mismatch, of the bipolar switching pair isincluded as another mismatch term in the analysis. It is in the same role as the duty cyclemismatch, used earlier giving a more realistic model for the core. Some simplifications willbe made in the analysis to avoid some problems. The limitations will be discussed during theanalysis and it follows in many cases the approach for emitter-coupled pairs given in [218]. Thedc analysis is assumed appropriate for the large signal behavior, which is of course a roughsimplification. The model for the analysis is given in Figure 4.31 and the output conductancesof active devices are all negligible. The emitter resistors of the core transistors are also omittedbecause the solution in a closed form would be otherwise impossible. The collector-emitter

The base current is assumed to be much smaller than the collector current in the givenequations. The relationship between the LO and collector currents in each branch can be writtenas

where

is the nominal biasing and

159

voltages and collector currents of and can be given as

in each branch. The nominal base-emitter voltage is equal at dc in both devices and themismatch is included only in factors. The current ratio between the differential branches canbe now written as

The current equation in the emitters of the core transistors is now

The last expression is valid because is close to unity when the current gain of the transistor islarge. Then, the output signal of the mixer can be written as

The saturation currents of core transistors are given as

160

and

The difference and sum terms in Equation (4.72) are then

and

The output voltage can be written now as

161

The last approximation is valid if it is assumed that the multiplication of two mismatch factorsis negligible when summed with a single mismatch. It is evident that the tanh-function presentsthe transfer function of odd harmonics and the other terms describe the dc leakage and evenharmonics in the downconversion. The factor multiplying the current and load resistance isactually the gate function for the bipolar core. However, the separation of different frequencycomponents is practically impossible if a sinusoidal LO signal is used in the analysis. TheTaylor series expansion for a function in the form of requires a very largenumber of terms to find the correct factor for the desired frequency component if islarge. The last condition is actually the definition for a switching mixer. However, it is stillpossible to use the gain degradation function in Equation (4.58) when approximating thefundamental downconverted signal. Hence, the amplitude of the IF output is given as

The same problems as above apply also for Taylor series of However, theinterest is here only in the dc leakage term of the gate function because the nonlinearity comesfrom the V-I converter. Also, the possible downconversion from the second harmonic of LO isneglected. Hence, the dc term of the can be given simply asThe amplitude of the imd2 term at the output can be now written as

DC offset at the output follows again the same mismatch behavior. Only the tail current isadded to the RF dependent term as

The second-order input intercept point is then

162

The result can be now plotted as a function of LO amplitude. Several curves according to valuesgiven in Table 4.5 are collected to Figure 4.32. Some peaking in the IIP2 value is observedbelow the maximum gain. In some conditions it is negligible, but may lead to a high maximumif mismatches cancel perfectly. Maybe a more important result from the analysis is that only a

variation in can change IIP2 about 10 dB in the switching as seen from curves 1-3. Onthe other hand, curves 6-8 indicate that IIP2 can degrade or improve when LO amplitude isincreased depending on the mismatch. The sensitivity of IIP2 even to small mismatches isshown again with a more realistic model. Still, the model is a very simplified version comparedto practical situations and more variables is probably needed. However, the simple approachallows practical means to calculate some selected sources of mismatch and study theirconsequences on the IIP2 behavior. This approach can be extended to double-balances circuitsor MOS switches. Unfortunately, the large-signal modeling of the commutating switches isdifficult and even quite simple functions as used here cause difficulties in the analysis. It is verylikely that these observations can be utilized in a practical circuit design, for example to select agood strategy for simulations, which are typically very heavy for mixer circuits.

163

4.4.5 BiCMOS Transconductance Mixer

The given discussion has pointed out several critical factors in the design of direct conversionmixer. In the case of a BiCMOS process, the use of MOS input stages and bipolar coretransistors as shown in Figure 4.33 provides an optimal topology for the circuit design. TheMOS input stages are more linear and a channel length is sufficient for the 2 GHzoperation. Likewise, bipolar devices in the commutating switches can be relatively small andstill have low enough flicker noise even when the total noise figure of the receiver is about 5dB. The BiCMOS mixer has been therefore used both in the direct conversion chip set [94] andsingle-chip version of the same WCDMA receiver [39].

Some mismatch simulations have also been done for this structure. Those are plotted in Figure4.34. The mismatch of 1 % in the load resistors drops the IIP2 already below 60 dB in thisconfiguration. Also, the emitter resistances in bipolar core have almost equal effect. Theimbalance in the V-I converter is modeled here as a variation in the threshold voltages of theinput devices. The same relative mismatch causes less degradation in the performance, whichindicates that the two former mismatches are more important for the IIP2. The simulations wereperformed only for a single mismatch at a time. The combined consequences of severalparameters should be characterized separately with carefully selected combinations.

164

4.5 Downconversion by Subsampling

The basic principles and limitations of subsampling as a mixing operation were describedalready in the previous chapter in connection with direct digital receivers. In this section, theconversion efficiency of a subsampling mixer is calculated. In comparison to other passivemixer structures the fundamental loss can be smaller due to the hold property and narrowaperture time of the sampling gate. This condition is valid for all subsampling mixersindependently of the following circuitry. If the subsampling mixer is followed by discrete-timesignal processing, either analog or digital, the behavior follows the special case when the dutycycle is zero because only discrete samples are processed afterwards. The finite aperture timehowever limits the tracking of the incoming signal and hence the high frequency behavior. Thediscrete-time case is a natural condition for subsampling and definitely most often used. Thecontinuous-time circuitry after a subsampler would necessitate the filtering of the unwantedreplicas around each clock harmonic. The intention is here mainly on the continuous-timeapproach because it is more general and allows straight comparison to other RF mixers. Indirect conversion receivers, all typical constraints like flicker noise or dc offsets are present insubsampling as well. In addition to that, wide-band noise aliasing, direct dc feedthrough fromRF circuitry and I/Q demodulation cause distinct problems in downconversion by subsampling.

In the sampling process, harmonic components, generated in the switching operation, mix withthe band-limited input signal and produce replicas over a wide range of frequencies. A replica,located at baseband or close to it, can be used as a downconverted signal in baseband or IFsignal processing. Therefore, in comparison to classical continuous-time mixers, an additionaldegree of freedom for LO frequency selection is available. To prevent aliasing of signalreplicas, a sampling frequency at least twice the signal bandwidth must be chosen. Byappropriate choice of the switch duty cycle a small conversion loss for a passive structure canbe achieved.

To produce the desired IF frequency a set of sampling frequencies can be chosen given by theequation where n is an integer. In Figure 4.35 two different samplingfrequencies produce the same IF. The clock harmonics of sampling pulses and possible spectralreplicas for the analog signal processing are shown in the picture. The amplitudes of thedifferent replicas depend on the gate function in the sampling as will be shown below. Thehigher sampling frequency produces less harmonic components close to the desired IF. Themore significant benefit of using a high sampling frequency comes from the fact that everyswitching harmonic converts noise around it to the baseband. Because one source of the noise isthe switch resistance of the sampler, the internal noise aliasing problem can only be reduced byincreasing the sampling frequency or by reducing the on-resistance of the switch if possible.

165

The conversion efficiency of a subsampling mixer can be obtained from the simplest possibledescription of a sampler including only the switch resistance and hold capacitor in Figure 4.36.The circuit has two operation modes, which depend on the switch position. When the switch isclosed the output tracks the input and the operation corresponds to first-order lowpass filtering.There is thus no frequency translation. Opening the switch turns the sampler to the hold mode,and the output retains the final value of the input until the switch turns on again. The sequenceof samples forms a hold envelope in the time domain at the intermediate frequency according to

where m is the harmonic component of the sampling frequency closest to the RF frequency.Thus, the hold mode converts the signal power down to the desired IF by appropriate choice ofsampling frequency. Because of fast transients during the changes between two operationmodes, the signal spreads over a wide range of frequencies. Theoretically it can be shown thatthe desired IF component can be designed to be much larger than the unwanted spuriousresponses thus yielding a small conversion loss for a passive structure. Before that, thefollowing conditions must be met to validate the simple analysis and give the first level designprerequisites. Signal bandwidth is limited to the half of the sampling frequency to avoid spectralaliasing. That is typically done with the preselection filter located directly after the antenna inthe receiver front-end. In the circuit, the time constant for charging the hold capacitance mustbe small compared to the time duration while the switch is closed in order to track the input.The falling edge of the sampling pulse must be steep enough so as not to limit the inputbandwidth. The circuit output should be terminated with a high impedance buffer to minimizesignal droop during hold. The behavioral model given here assumes infinitely fast rise and falltimes of the sampling pulses. The shape of the sampling function and its effect on the highfrequency behavior has been analyzed specifically for a MOS switch in [220].

In the track mode the input signal is multiplied directly with a rectangular gatefunction. For a single tone input the output is

166

where is the interval between samples and is the width of the pulse. The effect of thehold can be obtained when the rectangular hold function, which is non-overlapping with thegate function, is convolved with the sampled values taken at the moment when the switch turnsoff giving

The clock duty cycle is taken as a separate parameter used later in the analysis. Trackand hold mode waveforms are non-overlapping in time and therefore the output can be definedby their superposition both in the time domain and in the frequency domain. The Fouriertransform of the output is thus

For the sinusoidal stimulus Equation (4.85) can be rewritten by using theFourier transform of the input

To calculate the conversion efficiency at zero IF, first the set of outputs which can produce zerofrequency components must be defined. It happens only when is an integer multiple of thesampling frequency, called m according to Equation (4.82). We get

It produces the replica at DC when m=-n and hence the downconverted component is

167

When the desired IF is much smaller than half of the sampling frequency, the previous formulaapproximates the transfer function at low intermediate frequencies accurately and simplifiesanalysis. The subsampling ratio of the signal is defined as

where is the incoming signal frequency, which should be below the sampler -3dB point andproduce an integer value for Thus, the power conversion efficiency for an arbitrary samplingpulse width and ratio is

The theoretical conversion efficiency is shown in Figure 4.37 as a function of the clock dutycycle. The thick solid line describes the case when the subsampling ratio is very large and thetwo last terms in Equation (4.90) are negligible. The first term comes from the hold functionand the two last terms describe the tracking behavior. If the subsampling ratio is relatively smallthe tracking terms are significant for the conversion efficiency. Their correlation to the holdfunction has not been studied, but the extreme cases when the track and hold function sum, as inEquation (4.90), or subtract are plotted with dashed lines in Figure 4.37 when the subsamplingratio is 8. The zero duty cycle represents the case when discrete-time signals processing followsthe mixer immediately after the downconversion.

Equation (4.87) shows that any input frequency located at some harmonic of the samplingfrequency will alias down to the baseband. The input bandwidth of the sampler limits the noiseat high frequencies like a first-order lowpass filter, and the aliasing from external sources istheoretically avoided with the bandpass filter in the receiver front-end. But the noise generated

168

after the filter will be aliased as any other input frequency, and hence the noise performancewill deteriorate as a function of the subsampling ratio. In practical receivers operating in the 1-2GHz range, the stopband attenuation of the prefilter is far from ideal, and the front-endamplifier introduces noise outside the RF-band as well. In principle, a noise filter in front of thesampler would reduce the previous phenomena, but the noise generated by the switch can not beavoided. Therefore, the noise aliasing is an inherent problem for subharmonic samplers and canbe seen in the noise figure performance. The implementation of a continuous-time subsamplingmixer will be described in the next chapter.

4.6 Single-Chip Radio Receivers

Single-chip is a very flexible concept in connection with the radio transceivers. Sometimes acombination of two independent blocks on the same chip may be sufficient for advertisingsingle-chip operation. However, strictly speaking a single-chip receiver would require all digitalcoding necessary to separate the transmitter data bits from the channel coding on the same ICwith the LNA. It is anyway appropriate to exclude the antenna and preselection filter. Therecent results have been shown that the integration level in the receivers has been increasedsignificantly. Still there are only few examples of the RF front-ends on the same chip withdigital circuits operating during the reception [15], [17], [39], [64] and [95]. The single-chipreceiver is hence used here when the LNA is operating on the same chip with switching digitalcircuits. The analysis is not limited only on the direct conversion architecture, but is applicablefor all single-chip receivers having small signal levels at the input.

It will be assumed that the clock signal and its harmonics are the worst possible interferersbecause the clock switches from rail-to-rail even when the sensitivity is measured. All otherspurious tones, which are generated in the mixing of the clock and unwanted input signals, aredefined with blocking and intermodulation tests. Those tests allow higher spurs because ofincreased signal levels. Subsection 4.6.1 discusses more detailed about the issue, and it will beshown that the difference between sensitivity and other receiver tests is significant in thepresence of clock spurious.

Relatively little discussion has been given earlier on the possible effects of the clockfeedthrough on the receiver performance. The frequency-hopped direct conversion receiver in[15] has only limiting amplifiers on the back-end of the analog signal path and the digitaldemodulation is performed on a separate chip. However, a direct digital frequency synthesizeroperating with about 100 MHz clock is placed on the same die. Unwanted signals at the inputgenerate a baseband replica with the spurs of the frequency synthesizer. The performance wasmeasured at certain frequency offsets from the LO. In the worst case, the signal at 43 dB abovethe reference level produced the same response as the desired at the baseband output. Theharmonics of the clock do not directly fall on the 902-928 MHz band of interest. The otherpapers do not mention any potential problems considering the effect of clock feedthrough on thereceiver performance.

The focus is here on the integration of the A/D converter on the same die with the RF front-endincluding the LNA. This subsection explains some backgrounds, and especially the frequencyplanning issues. The measurement results of the single-chip WCDMA receiver will be given inthe next chapter. The RF front-end operates at 2 GHz range and the 6-bit ADC is clockednominally at 16.384 MS/s i.e. four times the chip rate. However, the ADC was designed also forhigher channel bandwidths and can be clocked up to 65 MS/s. This necessitates higher rise andfall times from the digital circuitry increasing the harmonic content of unwanted spurs.

169

4.6.1 Frequency Planning in Mixed-Mode Implementations

In principle, the frequency plan of a direct conversion receiver is more straightforward than inthe case of other receiver architectures due to the absence of the intermediate frequencyprocessing and the strong image frequency components. However, the integration of the radioreceiver on a single chip including the A/D converters combines strong clock signals with thesensitive RF front-end on the same die. Hence, the coupling of the digital signals to the RFinput port becomes an additional parameter in the design. The clock feedthrough is consideredhere as a new source of spurious tones, which decreases the sensitivity of the receiver.

In the analog signal processing environment, the possible harmonic combinations of thedifferent tones can be given as

independent blockers in the system input, and the output frequency of the transmitter. Thefactors k, m, p, q and r are positive integers. However, only a few of them are susceptible tocause unwanted spurious distortion in the passband of the receiver. The desired IF frequency is

It is assumed that the relatively narrow-band preselection filter removes all out-of-band harmonics in the antenna to the level, which does not cause any unwanted spurious withother tones in the receiver. Also, the relatively linear nature of the radio receiver preventsefficiently the generation of the higher harmonics from the desired signal, which can distort thereceived waveform itself. Instead, the spectral regrowth problem occurs in the efficientnonlinear power amplifiers. Because the wanted nonlinearity, which performs thedownconversion, is designed to be much stronger than any other nonlinear phenomena in thesignal path, it is appropriate to assume that the desired RF signal can not generate any harmfulspurious with any other tone in the receiver. Therefore, the term can be ruled out from thepossible spurious frequency components.

A blocking signal can occur at any frequency, and the receiver must operate in the vicinity ofnumerous strong interferers. In CDMA systems, also the other code channels at the same radiochannel can be considered as blockers to some extent. Of course, their power levels are strictlycontrolled in the system. To keep the spurious generation mechanisms at a general level,Equation (4.91) initially contains two different blockers, which represent all possiblecombinations. However, the two different blocking signals at the passband of the preselectionfilter can be replaced with a single tone because the nonlinear behavior of those two input tonesis limited already in the third- and second-order intermodulation tests. The intermodulation testsdetect again the dominating source of the nonlinearity caused by two input tones in the system,and hence rule out the susceptibility of other mechanisms. Also, because of the band limitationat the input of the receiver and relatively linear characteristics in the signal path, thefundamental tone of the blocker is the most probable source in the generation of spurious tones.

The interference from the transmitter is insignificant in the TDMA systems, which can use timedivision duplexing. In CDMA systems, which typically do not have the time duplex division,the transmission and reception are continuous and the transmitted power can leak to the receiverand distort the reception. Due to the simultaneous operation, the transmitter power leakage isnot allowed to desensitize the receiver, or in a strict sense not to deteriorate the sensitivity of thereceiver at all. Hence, the power leakage to the input of the receiver should be below thereceiver –1 dB compression. If the receiver avoids the desensitization due to the transmitterleakage power, the tone itself is filtered out in the channel selection filter later. Hence, theleaked transmitter power can be considered as a blocking signal, and in the harmonic analysis

170

where is the desired channel, the local oscillator (LO) frequency, and are the

the possible blocker can exist either in the reception band or at the corresponding duplexfrequency.

Hence, the Equation (4.91) can be simplified as

It is appropriate to assume that the significant high frequency LO harmonics are limited up tothe third-order products. It can be seen from Equation (2) that if the blocking signal is notlocated in the offset which is smaller than the channel bandwidth from the LO frequency or itsharmonics, the spurs will be filtered out in the channel filter. That necessary condition isnaturally avoided as explained above.

The analysis becomes complicated immediately when the clock signal and its harmonics areadded to the analysis. The high-speed clock requires fast rise and fall times, which produce awide range of harmonic components up to the RF frequencies. The harmonic contents and theparasitic leakage depend on several factors, which are difficult to predict. The parasitic couplingthrough substrate or between long metal wires, the mutual inductance of the bonding wires orthe pins of the package and the coupling outside the chip, including the printed circuit board,are all possible mechanisms for unwanted leakage. An overview of substrate coupling issuesand floorplan strategies for mixed-mode circuits is given for example in [221]. Potentially, themost sensitive node to the distortion is the RF input port, because the in-band interferers areamplified with the same large gain before the A/D conversion as the weak desired signal. Also,the clock signal can couple to the LO port, modulate the LO, and hence downconvert anunwanted blocker to the baseband. The single-chip receiver with potential interferers is shownin Figure 4.38.

Depending on the clock waveform the even and odd harmonics of the clock signals behavedifferently. For example, the input amplitude and the clock interface to the chip may have astrong effect on the harmonic content. The ratio between even and odd harmonics generated in

171

the interface can vary when the amplitude of the clock generator is changed. Either even or oddharmonics can be stronger on-chip interferers following the distorted shape at the clockinterface. Careful spectral analysis is hence required for all clock harmonics, and the possibledominating spurious of the single-chip direct conversion receiver can be given as

The potential clock harmonic can be in the order of several hundred of mV. Differentpossibilities to downconvert the unwanted spurious tones in the mixer are described in Figure4.39.

Before analyzing the blocking problems, the mixing products of the clock and LO signal areconsidered. Both signals have very large amplitudes and therefore they are the most susceptiblesources of unwanted spurious. Also both signals are always present, which means that thesensitivity of the receiver can be deteriorated. Because the LO signal is close to the puresinusoid, we can expect that the component is the dominant spurious. Typically,the digital clock is at the symbol rate or some multiple of it. If the LO is a multiple of thesymbol rate, the distortion will always be located at DC, and the component is filtered out withother DC offsets in a direct conversion architecture. However, it is not possible to placeadjacent channels in the radio communications exactly at the distance of the symbol rate,because otherwise perfect brick wall filters would be required both in the transmitter andreceiver to limit the band. On the other hand, doubling the distance between the adjacentchannels would waste the radio spectrum too much. Hence, it is always possible to find achannel, which is sensitive to the mixing products of the clock and LO due to the spurious tonesat the passband of the channel selection filter, if the clock frequency is not raised above thesystem bandwidth. That would increase the power consumption of the digital circuitry andADC, which is probably not acceptable. Theoretically, the other option is to use anasynchronous clock, which samples the ADC at a multiple of the channel bandwidth. Thefeasibility of such an arrangement is not in the scope in this context, but the synchronization tothe chip rate must be recovered with digital multipliers and dividers, for example. The differentsignals and their strong harmonic components are shown in Figure 4.40 for the RF input, LOand clock. The possible spurious frequencies caused by the fundamental tone of the LO and theharmonics of the clock are shown in Figure 4.41 for the lower WCDMA band. The triangularcurve describes the spurious frequency when the LO is swept, and the circles show the actual

172

LO frequencies spaced at 5 MHz. The channel selection filter attenuates the spurious above2 MHz, and hence only two LO frequencies out of twelve are potential candidates to deterioratethe performance.

The degradation of the sensitivity due to the clock distortion can be defined by measuring thenoise figure or the sensitivity when the is exactly at dc, and thenchanging the LO slightly, which moves the spurious to the passband of the channel filter. InCDMA systems, the narrow-band spurious will be spread over the band when the channel isdecorrelated. Hence, the effect should be determined by integrating the noise and distortionover the channel bandwidth. However, it is important to define the frequency of the narrow-band tone to distinguish the possible source of the spurious.

In the measurements, the output of the A/D converter can be transferred to the frequencydomain with the fast Fourier transform (FFT). If the narrow-band spurious tone is considerablyhigher than the noise floor at the output, the degradation of the performance due to the spurious

173

can be determined directly from the rms-value of the spurious tone with a sufficient accuracy.The tone is compared to the total noise voltage at the output or it can be referred to the inputpower with the associated gain and impedance level of the input. Of course, the noise floordepends on the resolution of the FFT. The input referred power as a function of the spurioustone at the output is given at 95 dB of total gain in the receiver Figure 4.42.

Because in CDMA systems the spurious tones can be compared to noise, it is possible to definethe noise factor, which includes the effect of the spurious as

where is the noise figure without a spurious component, the input referred power ofthe spurious tone and the thermal noise at the input i.e. kTB. Because the system noisedepends on the bandwidth, the wide-band systems are less sensitive to spurious tones, whichcan be seen in Figure 4.43. However, even in the case of wide-band systems the spur must bebelow at the input of the ADC. This means about 130-dB isolation requirement of thedigital rail-to-rail signal to the RF input with 2.7 V supply and 95-dB total gain. Thedegradation of the sensitivity due to a spurious tone is defined here as the difference of

and It will be used later when the measured results are given.

174

Equation (4.94) is an appropriate definition of the receiver noise figure when the spurious iscaused by internal distortion as is the case with LO and clock signals. If the spurious containsan external blocking signal, the tone should be compared to the allowed noise and distortionlevel for the specific test. It is typically 3 dB higher than the noise level. However, the leakageof the transmitter power should be considered as an internal source, because it is always presentwhen the system is operating if the transmission is continuous.

If the unwanted channels are attenuated sufficiently before the clock or any other switchingsignal than LO is connected or coupled to the direct conversion receiver, a blocking signal canonly compress the weak desired channel by reducing the gain of the system. In a single-chipreceiver, a blocker can also generate spurious tones at the baseband with the clock signal. FromEquation (4.93), two potential mechanisms can be observed. Either the blocker and the nthharmonic of the clock directly generate a spurious tone, or the LO signal is involved in theprocess. In the former case, n is large, but in the latter both the blocker and LO are at the samefrequency range and hence the order of the harmonic of the clock can be small. When theblocking signal is located at the distance of the clock frequency from the LO, the fundamentalof the clock is a part of the baseband product as The two different mechanismscan not be separated at the baseband because the LO frequency is converted to DC, and hence ifn can be any integer value, the closest frequency component of from either LO orDC locates at the same frequency. The blocking signals are typically modulated channels, andtheir bandwidth must be taken into account in Figure 4.41.

Thus, in the case of a single-chip direct conversion receiver the blocking test shouldcharacterize two different phenomena i.e. compression of the desired channel anddesensitization of the reception due to spurious tones at the passband. It will be shown in themeasurements of the single-chip DCR that the desensitization due to spurious tones dominatesthe upper signal range with some specific frequency combinations.

175

4.7 IC Implementations

Finally, several reported direct conversion receivers and RF front-ends for direct conversionreceivers mainly for cellular applications are collected in Table 4.6. The direct comparison isunjustified because of the different radio frequencies, channel bandwidths etc. in variousapplications. It is evident that for example in pagers the direct conversion has been a maturearchitecture already for a long time while in some systems it is still an unrealistic solution. Itshould be also highlighted that all given direct conversion receivers are very different entities.For example, the implemented blocks on the reported structures vary a lot, which directlyreflects in power consumption etc. Some specific details are commented separately, but thegiven notes are definitely not very complete. The number of chips in Table 4.6 counts only theanalog chips including the A/D converter. Digital parts are not discussed. Sometimes thetransmitter is placed on the same chip, but the interest is here only on the receiver applications.The given baseband bandwidth indicates the cutoff frequency of the lowpass filter. Thereferences [38] and [39] are the chip set and the single-chip version of the WCDMA receiverdiscussed here. The specific results of the RF front-end are given also in [185]. Thosereferences are highlighted in Table 4.6.

176

177

References

[1] I. A. W. Vance, “Fully integrated Radio Paging Receiver,” IEE Proceedings, vol. 146,pt F, no. 1, pp. 2-6, February 1982.

[2] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, A. A. Abidi, “A 1 GHz CMOS RFFront-End IC for a Direct-Conversion Wireless Receiver,” IEEE J. Solid-State Circuits, vol. 31,pp. 880-889, July 1996.

[3] K. Anvari, M. Kaube, B. Hriskevich, “Performance of a Direct Conversion Receiverwith Modulated Signal,” in Proceedings of the IEEE Vehicular Technology Conf.,pp. 822-827, May 1991.

[4] S. Sampei, K. Feher, “Adaptive DC-Offset Compensation Algorithm for Burst ModeOperated Direct Conversion Receivers,” in Proceedings of the IEEE Vehicular TechnologyConf., pp. 93-96, May 1992.

[5] J. K. Cavers, M. W. Liao, “Adaptive Compensation for Imbalance and Offset Lossesin Direct Conversion Transceivers,” IEEE Trans. on Vehicular Technology, vol. 42, pp. 581-588, November 1993.

[6] J. F. Wilson, R. Youell, T. H. Richards, G. Luff, R. Pilaski, “A Single-Chip VHF andUHF Receiver for Radio Paging,” IEEE J. Solid-State Circuits, vol. 26, pp. 1944-1950,December 1991.

[7] B. Razavi, “A 2.4-GHz CMOS Receiver for IEEE 802.11 Wireless LAN’s,” IEEE J.Solid-State Circuits, vol. 34, pp. 1382-1385, October 1999.

[8] A. Bateman, D. M. Raines, “Direct Conversion Tranceiver Design for Compact Low-Cost Portable Mobile Radio Terminals,” in Proceedings of the IEEE Vehicular TechnologyConf., pp. 57-62, May 1989.

[9] U. Bolliger, W. Vollenweider, “Some Experiments on Direct-Conversion Receivers,”in Proc. of the IEE International Conference on Radio Receivers and Associated Systems,pp. 40-44, July 1990.

178

[10] G. Schultes, A. L. Scholtz, E. Bonek, P. Veith, “A New Incoherent Direct ConversionReceiver,” in Proceedings of the IEEE Vehicular Technology Conf, pp. 668-674, May 1990.

[11] B. Razavi, “Design Considerations for Direct-Conversion Receivers,” IEEE Trans. onCircuits and Syst.—II: Analog and Digital Signal Processing, vol. 44, pp. 428-435, June 1997.

[12] C. D. Hull, J. L. Tham, R. R. Chu, “A Direct-Conversion Receiver for 900 MHz (ISMBand) Spread-Spectrum Digital Cordless Telephone,” IEEE J. Solid-State Circuits, vol. 31, pp.1955-1963, December 1996.

[13] P. S. Mclntosh, “The Design and Development of a Spread Spectrum Digital CordlessTelephone for the Consumer Market,” in Proceedings of the Virginia Tech’s Fourth Symposiumon Wireless Personal Communications, pp. 97-105, June 1994.

[14] G. Schultes, E. Bonek, A. L. Scholtz, P. Kreuzgruber, “Low-Cost Direct ConversionReceiver Structures for TDMA Mobile Communications,” in Sixth International Conf. MobileRadio and Personal Communications, pp. 143-150, 1991.

[15] A. Rofougaran, G. Chang, J.J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M.Djafari, J. Min, E. W. Roth, A. A. Abidi, H. Samueli, “A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in CMOS—Part II: Receiver Design,” IEEE J. Solid-StateCircuits, vol. 33, pp. 535-547, April 1998.

[16] J. Jussila, A. Pärssinen, K. Halonen, "An Analog Baseband Circuitry for a WCDMADirect Conversion Receiver", in Proceedings of the European Solid-State Circuits Conf., pp.166-169, September 1999.

[17] T. Cho, E. Dukatz, M. Mack, D. MacNally, M. Marringa, S. Mehta, C. Nilson, L.Plouvier, S. Rabii, “A Single-Chip CMOS Direct-Conversion Transceiver for 900 MHz Spread-Spectrum Digital Cordless Phones,” in ISSCC Digest of Technical Papers, pp. 228-229,February 1999.

[18] B. Lindquist, M. Isberg, P. W. Dent, “A New Approach to Eliminate the DC Offset ina TDMA Direct Conversion Receiver,” in Proceedings of the IEEE Vehicular TechnologyConf., pp. 754-757, May 1993.

[19] A. Bateman, D.M. Haines, R. J. Wilkinson, “Linear Transceiver Architectures,” inProceedings of the IEEE Vehicular Technology Conf., pp. 478-484, June 1988.

[20] D. Haspeslagh, J. Ceuterick, L. Kiss, J. Weinin, A. Vanwelsenaers, C. Enel-Rehel,“BBTRX: A Baseband Transceiver for a Zero IF GSM Hand Portable Station,” in Proceedingsof the Custom Integrated Circuits Conf., pp. 10.7.1-10.7.4, May 1992.

[21] A. A. Abidi, “Direct-Conversion Radio Tranceivers for Digital Communications,”IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, December 1995.

179

[22] H. Yoshida, H. Tsurumi, Y. Suzuki, “DC Offset Canceller in a Direct ConversionReceiver for QPSK Signal Reception,” in Proceedings of the IEEE Int. Symp. on Personal,Indoor and Mobile Radio Communications, vol. 3, pp. 1314-1318, September 1998.

[23] V. Comino, D. Schulman, S. J. Walker, S. Kasturia, M. Prise, “A Baseband IntegratedCircuit for Homodyne Cordless Phones,” in Proceedings of the Custom Integrated CircuitsConf., pp. 423-426, May 1998.

[24] B. Wang, H. M. Kwon, J. Mittel, “Simple DC Removers for Digital FM Direct-Conversion Receiver,” in Proceedings of the IEEE Vehicular Technology Conf., pp. 1222-1226,May 1999.

[25] J. H. Mikkelsen, T. E. Kolding, T. Larsen, T. Klingenbrunn, K. I. Pedersen, P.Morgensen, “Feasibility Study of DC Offset Filtering for UTRA-FDD/WCDMA Direct-Conversion Receiver,” in Proceedings of the Norchip Conf., pp. 34-39, November 1999.

[26] K. Takahashi, M. Mimura, M. Hasegawa, M. Makimoto, K. Yokozaki, “A DirectConversion Receiver Utilizing a Novel FSK Demodulator and Low-Power-ConsumptionQuadrature Mixer," in Proceedings of the IEEE Vehicular Technology Conf., pp. 910-915, May1992.

[27] Z. Chen, J. Lau, “Circuit Requirements of a Direct Conversion Paging Receiver,”IEEE Trans. on Circuits and Syst.—II: Analog and Digital Signal Processing, vol. 46, pp. 802-807, June 1999.

[28] P. Estabrook, B. B. Lusignan, “The Design of a Mobile Radio Receiver Using a DirectConversion Architecture,” in Proceedings of the IEEE Vehicular Technology Conf., pp. 63-72,May 1989.

[29] T. Yamaji, H. Tanimoto, H. Kokatsu, “An I/Q Active Balanced Harmonic Mixer withIM2 Cancelers and a 45° Phase Shifter,” IEEE J. Solid-State Circuits, vol. 33, pp. 2240-2246,December 1998.

[30] N. C. Hamilton, “Aspect of Direct Conversion Receiver Design,” in Proceedings of theFifth International Conference on HF Radio Systems and Techniques, pp. 299-303, 1991.

[31] C. Takahashi, R. Fujimoto, S. Arai, T. Itakura, T. Ueno, H. Tsurumi, H. Tanimoto, S.Watanabe, K. Hirakawa, “A 1.9 GHz Si Direct Conversion Receiver IC for QPSK ModulationSystems,” in ISSCC Digest of Technical Papers, pp. 138-139, February 1995.

[32] C. Takahashi, R. Fujimoto, S. Arai, T. Itakura, T. Ueno, H. Tsurumi, H. Tanimoto, S.Watanabe, K. Hirakawa, “A 1.9 GHz Si Direct Conversion Receiver IC for QPSK ModulationSystems,” IEICE Trans. Electron., vol. E79-C, pp. 644-649, May 1996.

180

[33] J. M. Moniz, B. Maoz, “Improving the Dynamic Range of the MMIC Gilbert CellMixers for Homodyne Receivers,” in Proceedings of the IEEE Microwave and Millimeter-Wave Integrated Circuits Symposium, pp. 103-106, June 1994.

[34] H. Tsurumi, T. Maeda, “Design Study on a Direct Conversion Receiver Front- End for280 MHz, 900 MHz, and 2.6 GHz Band Radio Communication Systems,” in Proceedings of theIEEE Vehicular Technology Conf., pp. 457-462, May 1991.

[35] C. Muschallik, “System Considerations on SCPC for Digital Satellite Receivers withDirect Conversion,” IEEE Trans. on Consumer Electronics, vol. 45, pp. 956-964, August 1999.

[36] J. Hyyryläinen, L. Bogod, S. Kangasmaa, H.-O. Scheck, T. Ylämurto, “Six-Port DirectConversion Receiver,” in Proceedings of the European Microwave Conference, pp. 341-346,October 1997.

[37] S. Laursen, “Second Order Distortion in CMOS Direct Conversion Receivers forGSM,” in Proceedings of the European Solid-State Circuits Conf., pp. 342-345, September1999.

[38] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. Halonen, “A Wide-Band DirectConversion Receiver for WCDMA Applications,” in ISSCC Digest of Technical Papers, pp.220-221, February 1999.

[39] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. Kivekäs, K. Halonen, “A Wide-Band Direct Conversion Receiver With On-Chip A/D Converters,” in Symposium on VLSICircuits Digest of Technical Papers, pp. 32-33, June 2000.

[40] K. L. Fong, “Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers forWireless Applications,” in ISSCC Digest of Technical Papers, pp. 224-225, February 1999.

[41] Q. Huang, P. Orsatti, F. Piazza, “Broadband, CMOS LNAs with Sub-2dB NFfor GSM Applications,” in Proceedings of the Custom Integrated Circuits Conf., pp. 67-70,May 1998.

[42] B. A. Floyd, J. Mehta, C. Gamero, K. K. O, “A 900-MHz, CMOS Low NoiseAmplifier with 1.2-dB Noise Figure,” in Proceedings of the Custom Integrated Circuits Conf.,pp. 661-664, May 1999.

[43] G. Gramegna, A. Magazzù, C. Sclafani, M. Paparo, “Ultra-Wide Dynamic Range1.75dB Noise-Figure, 900MHz CMOS LNA,” in ISSCC Digest of Technical Papers, pp. 380-381, February 2000.

[44] R. G. Meyer, W. D. Mack, “A 1-GHz BiCMOS RF Front-End IC,” IEEE J. Solid-StateCircuits, vol. 29, pp. 350-355, March 1994.

181

[45] M. Steyaert, M. Borremans, J. Janssens, B. D. Muer, N. Itoh, J. Craninckx, J. Crols, E.Morifuji, H. S. Momose, W. Sansen, “A Single-Chip CMOS Tranceiver for DCS-1800Wireless Communications,” in ISSCC Digest of Technical Papers, pp. 48-49, February 1998.

[46] J. Janssens, J. Crols, M. Steyaert, “A 10 mW Inductorless, Broadband CMOS LowNoise Amplifier for 900 MHz Wireless Communications,” in Proceedings of the CustomIntegrated Circuits Conf., pp. 75-78, May 1998.

[47] Y. J. Shin, K. Bult, “An Inductorless 900MHz RF Low-Noise Amplifier inCMOS,” in Proceedings of the Custom Integrated Circuits Conf., pp. 513-516, May 1997.

[48] C.-Y. Wu, S.-Y. Hsiao, “The Design of a 3-V 900-MHz CMOS Bandpass Amplifier,”IEEE J. Solid-State Circuits, vol. 32, pp. 159-168, February 1997.

[49] A. N. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-StateCircuits, vol. 31, pp. 1939-1944, December 1996.

[50] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice-Hall, 1998.

[51] T. Melly, A.-S. Porret, C. C. Enz, M Kayal, “A 1.3V Low-Power 430 MHz Front-EndUsing a Standard Digital CMOS Process,” in Proceedings of the Custom Integrated CircuitsConf., pp. 503-506, May 1998.

[52] J. R. Long, M. A. Copeland, “A 1.9 GHz Low-Voltage Silicon Bipolar Receiver Front-End for Wireless Personal Communications Systems,” IEEE J. Solid-State Circuits, vol. 30, pp.1438-1448, December 1995.

[53] D. K. Shaeffer, T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE J.Solid-State Circuits, vol. 32, pp. 745-759, May 1997.

[54] A. R. Shahani, D. K. Shaeffer, T. H. Lee, “A 12-mW Wide Dynamic Range CMOSFront-End for a Portable GPS Receiver,” IEEE J. Solid-State Circuits, vol. 32, pp. 2061-2070,December 1997.

[55] J.-J. Zhou, D. J. Allstot, “A Fully Integrated CMOS 900MHz LNA UtilizingMonolithic Transformers,” in ISSCC Digest of Technical Papers, pp. 132-133, February 1998.

[56] R. Mittra, C. Gordon, “Electrical Design of Packaging Systems,” in PhysicalArchitecture of VLSI Systems, R. J. Hanneman, A. D. Kraus, M. Pecht, Ed. New York: JohnWiley & Sons, 1984; Ch. 8, pp. 461-539.

[57] J. Sevenhans, A. Vanwelsenaers, J. Weinin, J. Baro, “An Integrated Si Bipolar RFTransceiver for a Zero IF 900 MHz GSM Digital Mobile Radio Frontend of a Hand PortablePhone,” in Proceedings of the Custom Integrated Circuits Conf., pp. 7.7.1-7.7.4, May 1991.

182

[58] H. Wang, M. Banu, “3V, 28mW Si-Bipolar Front-End IC for 900 MHz HomodyneWireless Receivers,” Electronics Letters, vol. 31, pp. 265-266, February 1995.

[59] K. Itoh, M. Shimozawa, N. Suematsu, O. Ishida, “Even Harmonic Type DirectConversion Receiver ICs for Mobile Handsets: Design Challenges And Solutions,” inProceedings of the IEEE Radio Frequency Integrated Circuits Symposium, pp. 53-56, June1999.

[60] B.-S. Song, “CMOS RF Circuits for Data Communications Applications,” IEEE J.Solid-State Circuits, vol. 21, pp. 310-317, April 1986.

[61] J. Crols, M. S. J. Steyaert, “A 1.5 GHz Highly Linear CMOS Downconversion Mixer,”IEEE J. Solid-State Circuits, vol. 30, pp. 736-742, July 1995.

[62] J. Janssens, M. Steyaert, T. Ohguro, “A CMOS I/Q-Channel DownconversionMixer with Active Coil for DCS-1800 Applications,” in Proceedings of the European Solid-State Circuits Conf., pp. 56-59, September 1998.

[63] K. L. Fong, R. G. Meyer, “Monolithic RF Active Mixer Design,” IEEE Trans. onCircuits and Syst.—II: Analog and Digital Signal Processing, vol. 46, pp. 231-239, March1999.

[64] J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, P. R. Gray, “A1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless TelephoneApplications,” IEEE J. Solid-State Circuits, vol. 32, pp. 2071-2088, December 1997.

[65] K. Voudouris, J. M. Noras, ”Effects of Amplitude, Phase, and FrequencyImperfections on the Performance of a Direct Conversion Receiver (DCR) for PersonalCommunication System,” IEEE Microwave and Guided Wave Letters, vol. 3, pp. 313-315,September 1993.

[66] J. Crols, M. Steyaert, CMOS Wireless Transceiver Design, Boston, Dordrecht,London: Kluwer, 1997.

[67] R. K. Loper, “A Tri-Phase Direct Conversion Receiver,” in Proceedings of the IEEEMilitary Communications Conf., pp. 1228-1232, October 1990.

[68] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge,UK: Cambridge University Press, 1998.

[69] A. W. Buchwald, K. W. Martin, “High-Speed Voltage-Controlled Oscillator withQuadrature Outputs,” Electronics Letters, vol. 27, pp. 309-310, February 1991.

183

[70] F. L. Martin, “A BiCMOS 50-MHz Voltage-Controlled Oscillator with QuadratureOutputs,” in Proceedings of the Custom Integrated Circuits Conf., pp. 27.4.1-27.4.4, May 1993.

[71] T. C. Weigandt, B. Kim, P. R. Gray, “Analysis of Timing Jitter in CMOS RingOscillators,” in Proceedings of the IEEE International Symposium on Circuits and Systems, vol.4, pp. 27-30, June 1994.

[72] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE J. Solid-StateCircuits, vol. 31, pp. 331-343, March 1996.

[73] J. A. McNeill, “Jitter in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 32, pp.870-879, June 1997.

[74] A. Hajimiri, T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,”IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, February 1998.

[75] F. Herzel, B. Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,”IEEE Trans. on Circuits and Syst.—II: Analog and Digital Signal Processing, vol. 46, pp. 56-62, January 1999.

[76] A. Hajimiri, S. Limotyrakis, T. H. Lee, “Jitter and Phase Noise in Ring Oscillators,”IEEE J. Solid-State Circuits, vol. 34, pp. 790-804, June 1999.

[77] S. L. J. Gierkink, E. A. M. Klumperink, A. P. van der Wel, G. Hoogzaad, E. A. J. M.van Tuijl, B. Nauta, “Intrinsic 1/f Device Noise Reduction and Its Effect on Phase Noise inCMOS Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 1022-1025, July 1999.

[78] A. Rofougaran, G. Chang, J.J. Raerl, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M.Djafari, M.-K. Ku, E. W. Roth, A. A. Abidi, H. Samueli, “A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in CMOS—Part I: Architecture and Transmitter Design,”IEEE J. Solid-State Circuits, vol. 33, pp. 515-534, April 1998.

[79] M. Thamsirianunt, T. A. Kwasniewski, “CMOS VCO’s for PLL Frequency Synthesisin GHz Digital Mobile Radio Communications,” IEEE J. Solid-State Circuits, vol. 32, pp. 1511-1524, October 1997.

[80] C. J. M. Verhoeven, “A High-Frequency Electronically Tunable QuadratureOscillator,” IEEE J. Solid-State Circuits, vol. 27, pp. 1097-1100, July 1992.

[81] R. Duncan, K. Martin, A. Sedra, “A 1 GHz Quadrature Sinusoidal Oscillator,” inProceedings of the Custom Integrated Circuits Conf., pp. 91-94, May 1995.

[82] A. Rofougaran, J. Rael, M. Rofougaran, A. Abidi, “A 900 MHz CMOS LC-Oscillatorwith Quadrature Outputs,” in ISSCC Digest of Technical Papers, pp. 392-393, February 1996.

184

[83] J. J. Kim, B. Kim, “A Low-Phase-Noise CMOS LC Oscillator with a Ring Structure,”in ISSCC Digest of Technical Papers, pp. 430-431, February 2000.

[84] M. D. McDonald, “A 2.5 GHz BiCMOS Image-Reject Front-End,” in ISSCC Digest ofTechnical Papers, pp. 144-145, February 1993.

[85] J. Sevenhans, D. Haspeslagh, A. Delarbre, L. Kiss, Z. Chang, J. F. Kukielka, “AnAnalog Radio Front-End Chip Set for a 1.9 GHz Mobile Radio Telephone Application,” inISSCC Digest of Technical Papers, pp. 44-45, February 1994.

[86] M. Steyaert, R. Roovers, “A 1-GHz Single-Chip Quadrature Modulator,” IEEE J.Solid-State Circuits, vol. 27, pp. 1194-1197, August 1992.

[87] I. A. Koullias, J. H. Havens, I. G. Post, P. E. Bronner, “A 900 MHz Transceiver ChipSet for Dual-Mode Cellular Mobile Terminals,” in ISSCC Digest of Technical Papers, pp. 140-141, February 1993.

[88] M. J. Gingell, “Single Sideband Modulation Using Sequence Asymmetric PolyphaseNetworks,” Electrical Communication, vol. 48, pp. 21-25, 1973.

[89] J. Crols, M. Steyaert, “A Fully Integrated 900 MHz CMOS Double QuadratureDownconverter,” in ISSCC Digest of Technical Papers, pp. 136-137, February 1995.

[90] F. Behbahani, Y. Kishigami, J. Leete, A. A. Abidi, “CMOS 10 MHz-IFDownconverter with On-Chip Broadband Circuit for Large Image-Suppression,” in Symposiumon VLSI Circuits Digest of Technical Papers, pp. 83-86, June 1999.

[91] J. Crols, M. S. J. Steyaert, “A Single-Chip 900 MHz CMOS Receiver Front-End with aHigh Performance Low-IF Topology,” IEEE J. Solid-State Circuits, vol. 30, pp. 1483-1492,December 1995.

[92] J. Crols, M. Steyaert, “An analog Integrated Polyphase Filter for a High PerformanceLow-IF Receiver,” in Symposium on VLSI Circuits Digest of Technical Papers, pp. 87-88, June1995.

[93] S. H. Galal, H. F. Ragaie, M. S. Tawfik, “RF Sequence Asymmetric PolyphaseNetworks for RF Integrated Transceivers,” IEEE Trans. on Circuits and Syst.—II: Analog andDigital Signal Processing, vol. 47, pp. 18-27, January 2000.

[94] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. A. I. Halonen, “A 2-GHz Wide-Band Direct Conversion Receiver for WCDMA Applications,” IEEE J. Solid-State Circuits,vol. 34, pp. 1893-1903, December 1999.

185

[95] F. Op ‘t Eynde, J. Craninckx, P. Goetschalckx, “A Fully-Integrated Zero-IF DECTTransceiver,” in ISSCC Digest of Technical Papers, pp. 138-139, February 2000.

[96] A. Jayaraman, B. Terry, B. Fransis, P. Sullivan, M. Lindstrom, J. O’Connor, “A FullyIntegrated Broadband Direct-Conversion Receiver for DBS Applications,” in ISSCC Digest ofTechnical Papers, pp. 140-141, February 2000.

[97] S. Navid, F. Behbahani, A. Fotowat, A. Hajimiri, R. Gaethke, M. Delurio, “Level-Locked Loop, A Technique for Broadband Quadrature Signal Generation,” in Proceedings ofthe Custom Integrated Circuits Conf., pp. 411-414, May 1997.

[98] M. Cohn, J. E. Degenford, B. A. Newman, “Harmonic Mixing with an AntiparallelDiode Pair,” IEEE Trans. on Microwave Theory and Techniques, vol. 23, pp. 667-673, August1975.

[99] K. Itoh, A. Iida, Y. Sasaki, S. Urasaki, “A 40 GHz Band Monolithic Even HarmonicMixer With an Antiparallel Diode Pair,” in MTT-S International Microwave Symposium Digestof Technical Papers, pp. 879-882, June 1991.

[100] M. Shimozawa, K. Kawakami, K. Itoh, A. Iida, O. Ishida, “A Novel Sub-HarmonicPumping Direct Conversion Receiver With High Instantaneous Dynamic Range,” in MTT-SInternational Microwave Symposium Digest of Technical Papers, pp. 819-822, June 1996.

[101] T. Yamaji, H. Tanimoto, “A 2 GHz Balanced Harmonic Mixer for Direct-ConversionReceivers,” in Proceedings of the Custom Integrated Circuits Conf., pp. 193-196, May 1997.

[102] R. J. van de Plassche, P. Baltus, “An 8-bit 100-MHz Full-Nyquist Analog-to-DigitalConverter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1334-1344, December 1988.

[103] P. Orsatti, Q. Huang, “A 170 MHz Quadrature-Downconverter in BiCMOS forVery Low Power Pagers,” in Proceedings of the European Solid-State Circuits Conf., pp. 270-273, September 1999.

[104] D. Senderowicz, S. Azuma, H. Matsui, K. Hara, S. Kawama, Y. Ohta, M. Miyamoto,K. Iizuka, “A 23mW 256-Tap 8MSample/s Matched Filter for DS-CDMA Cellular TelephonyUsing Recycling Integrator Correlators,” in ISSCC Digest of Technical Papers, pp. 354-355,February 2000.

[105] M. D. Hahm, E. G. Friedman, E. L. Titlebaum, “A Comparison of Analog and DigitalCircuit Implementations for Use in Portable Wireless Communications Terminals,” IEEETrans. on Circuits and Syst.—II: Analog and Digital Signal Processing, vol. 44, pp. 498-506,June 1997.

[106] M. Bank, J. Gavan, “Practical Realisation of a Raised-Cosine Filter,” ElectronicsLetters, vol. 32, pp. 438-440, February 1996.

186

[107] P. J. Chang, A. Rofougaran, A. A. Abidi, “A CMOS Channel-Select Filter for a Direct-Conversion Wireless Receiver,” IEEE J. Solid-State Circuits, vol. 32, pp. 722-729, May 1997.

[108] Y. P. Tsividis, “Integrated Continuous-Time Filter Design—An Overview,” IEEE J.Solid-State Circuits, vol. 29, pp. 166-176, March 1994.

[109] J. Sevenhans, Z.-Y. Chang, “A/D and D/A Conversion for Telecommunication,” IEEECircuits and Devices Magazine, vol. 14, pp. 32-42, January 1998.

[110] J. Doernberg, H.-S. Lee, D. A. Hodges, “Full-Speed Testing of A/D Converters,” IEEEJ. Solid-State Circuits, vol. 19, pp. 820-827, December 1984.

[111] B. Razavi, Principles of Data Conversion System Design, Piscataway, NJ: IEEE Press,1995.

[112] J. K. Cavers, S. P. Stapleton, “A DSP-Based Alternative to Direct ConversionReceivers for Digital Mobile Communications,” Proceedings of the IEEE GlobalTelecommunication Conf., pp. 2024-2029, November 1990.

[113] S. S. Lewis, P. R. Gray, "A Pipelined 9-bit 5-MSample/s Analog-to-DigitalConverter", IEEE J. Solid-State Circuits, vol. 22, pp. 954-961, December 1987.

[114] R. J. van de Plassche, P. Baltus, “An 8-bit 100-MHz Full-Nyquist Analog-to-DigitalConverter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1334-1344, December 1988.

[115] Y.-M. Lin, B. Kim, P. R. Gray, "A 13-b 2.5-MHz Self-Calibrated Pipelined A/DConverter in CMOS," IEEE J. Solid-State Circuits, vol. 26, pp. 628-635, April 1991.

[116] C. Conroy, D. Cline, P. Gray, "An 8-b 85-Ms/s Parallel Pipeline A/D Converter inCMOS," IEEE J. Solid-State Circuits, vol. 28, pp. 447-454, April 1993.

[117] M. Yotsuyanagi, T. Etoh, K. Hirata, "A 10-b 50-MHz Pipelined CMOS A/D Converterwith S/H," IEEE J. Solid-State Circuits, vol. 28, pp. 292-300, March 1993.

[118] A. N. Karanicolas, H.-S. Lee, K. L. Bacrania, "A 15b 1-MSample/s Digitally Self-Calibrated Pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, pp. 1207-1215, December1993.

[119] J. Yuan, C. Svensson, "A 10-bit 5-Ms/s Successive Approximation ADC Cell Used ina 70-Ms/s ADC Array in CMOS," IEEE J. Solid-State Circuits, vol. 29, pp. 866-872,August 1994.

[120] W. C. Song, H. W. Choi, S. U. Kwak, B.-S. Song, "A 10-b 20-MSample/s Low-PowerCMOS ADC", IEEE J. Solid-State Circuits, vol. 30, pp. 514-521, May 1995.

187

[121] T. B. Cho, P. R. Gray, "A 10 b, 20 MSample/s, 35 mW Pipeline A/D Converter", IEEEJ. Solid-State Circuits, vol. 30, pp. 166-172, March 1995.

[122] K. Nakamura, M. Hotta, L. R. Carley, D. J. Allstot, "An 85 mW, 10 b, 40 MSample/s,CMOS Parallel-Pipelined ADC", IEEE J. Solid-State Circuits, vol. 30, pp. 173-183, March1995.

[123] T.-H. Shu, B.-S. Song, K. Bacrania, "A 13-b 10-MSample/s ADC Digitally Calibratedwith Oversampling Delta-Sigma Converter," IEEE J. Solid-State Circuits, vol. 30, pp. 443-452,April 1995.

[124] K. Nagaraj, H. S. Fetterman, R. S. Shariatdoust, J. Anidjar, S. H. Lewis, J. Alsayegh,R. G. Renninger "An 8-Bit 50+ MSamples/s Pipelined A/D Converter With An Area AndPower Efficient Architecture", in Proceedings of the Custom Integrated Circuits Conf., pp. 423-426, May 1996.

[125] A. G. W. Venes, R. van de Plassche, "An 80MHz 80mW 8b CMOS folding A/DConverter with Distributed T/H Preprocessing," in ISSCC Digest of Technical Papers, pp. 318-319, February 1996.

[126] T. Kumamoto, O. Matsumoto, M. Ito, T. Okuda, H. Momono, T. Miki, K. Okada, T.Sumi, "A 10-bit 50 MS/s 300 mW A/D Converter Using Reference Feed-ForwardArchitecture", in Proceedings of the European Solid-State Circuits Conf., pp. 220-223,September 1996.

[127] P. C. Yu, H.-S. Lee, "A 2.5V 12b 5MSample/s Pipelined CMOS ADC", in ISSCCDigest of Technical Papers, pp. 314-315, February 1996.

[128] S. I. Lim, S. H. Lee, A. Y. Hwang, "A 12b 10MHz 250mW CMOS A/D Converter", inISSCC Digest of Technical Papers, pp. 316-317, February 1996.

[129] D. W. Cline, P. R. Gray, "A Power Optimized 13-b, 5 MSamples/s Pipelined Analog-to-Digital Converter in CMOS", IEEE J. Solid-State Circuits, vol. 31, pp. 294-303,March 1996.

[130] K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, R. G. Renninger, "A 250-mW8-b 52-MSample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers,"IEEE J. Solid-State Circuits, vol. 32, pp. 312-320, March 1997.

[131] K. Bult, A. Buchwald, J. Laskowski, "A 170mW 10b 50MSample/s CMOS ADC in" in ISSCC Digest of Technical Papers, pp. 136-137, February 1997.

[132] K. Y. Kim, N. Kusayanagi, A. A. Abidi, "A 10-bit, 100MS/s CMOS A/D Converter",IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, March 1997.

188

[133] P. Vorenkamp, R. Roovers, "A 12b 50MSample/s Cascaded Folding and InterpolatingADC," in ISSCC Digest of Technical Papers, pp. 134-135, February 1997.

[134] R. Jewett, K. Poulton, K.-C. Hsieh, J. Doernberg, "A 12b 128MSample/s ADC with0.05LSB DNL," in ISSCC Digest of Technical Papers, pp. 138-139, February 1997.

[135] S. U. Kwak, B.-S. Song, K. Bacrania, "A 15b 5MSample/s Low-Spurious CMOSADC," in ISSCC Digest of Technical Papers, pp. 146-147, February 1997.

[136] W. Bright, "8b 75MSamples/s 70mW Parallel Pipelined ADC Incorporating DoubleSampling," in ISSCC Digest of Technical Papers, pp. 146-147, February 1998.

[137] D. Fu, K. Dyer, S. Lewis, P. Hurst, "Digital Background Calibration of a 10b40MSample/s Parallel Pipelined ADC," in ISSCC Digest of Technical Papers, pp. 140-141,February 1998.

[138] K. Dyer, D. Fu, S. Lewis, P. Hurst, "Analog Background Calibration of a 10b40MSample/s Parallel Pipelined ADC," in ISSCC Digest of Technical Papers, pp. 142-143,February 1998.

[139] A. Wada, K. Kato, K. Tani, H. Shimizu, "A 10b 50-MSample/s CMOS ADC in ASICProcess," in Proceedings of the European Solid-State Circuits Conf., pp. 252-255, September1998.

[140] J. Ingino, B. Wooley, "A Continuously-Calibrated 10MSample/s 12b 3.3V ADC," inISSCC Digest of Technical Papers, pp. 144-145, February 1998.

[141] I. Opris, L. Lewicki, B. Wong, "A Single-Ended 12b 20MSamples/s Self-CalibratingPipeline A/D Converter," in ISSCC Digest of Technical Papers, pp. 138-139, February 1998.

[142] K. Nagaraj, F. Chen, T. Le, T. R. Viswanathan, “Efficient 6-Bit A/D Converter Usinga 1-Bit Folding Front-End,” IEEE J. Solid-State Circuits, vol. 34, pp. 1056-1062, August 1999.

[143] Y. Tamba, K. Yamakido, "A CMOS 6b 500MSample/s ADC for a Hard Disk DriveRead Channel," in the Digest of Int. Solid-State Circuits Conf. 99, pp. 324-325, February 1999.

[144] K. Yoon, S. Park, W. Kim, "A 6b 500MSample/s CMOS Flash ADC with aBackground Interpolated Auto-Zeroing Technique," in ISSCC Digest of Technical Papers, pp.326-327, February 1999.

[145] M. Waltari, K. Halonen, “An 8-bit Low-Voltage Pipelined ADC Utilizing Switched-Opamp Technique," in Proceedings of the European Solid-State Circuits Conf., pp. 174-177,Sepember 1999.

189

[146] B. Brandt, J. Lutsky, "A 75mW 10b 20MSample/s CMOS Subranging ADC with59dB SNDR," in ISSCC Digest of Technical Papers, pp. 322-323, February 1999.

[147] H. van der Ploeg, R. Remmers, "A 3.3V 10b 25MSample/s Two-Step ADC inCMOS," in ISSCC Digest of Technical Papers, pp. 318-319, February 1999.

[148] B. W. Lee, G. H. Cho, “A CMOS 10Bit 37MS/s Pipelined A/D Converter with CodeRegeneration and Averaging,” in Proceedings of the European Solid-State Circuits Conf., pp.314-317, September 1999.

[149] G. Hoogzaad, R. Roovers, "A 65mW 10b 40MSample/s BiCMOS Nyquist ADC in" in ISSCC Digest of Technical Papers, pp. 320-321, February 1999.

[150] P. Rombouts, S. Audenaert, L. Weyten, “A CMOS 12-bit 15 MSample/s DigitallySelf-Calibrated Pipelined A/D Converter,” in Proceedings of the European Solid-State CircuitsConf., pp. 326-329, September 1999.

[151] S. Paul, H.-S. Lee, T. Alailima, D. Santiago, "A Nyquist-Rate Pipelined OversamplingA/D Converter," in ISSCC Digest of Technical Papers, pp. 54-55, February 1999.

[152] D. U. Thompson, B. A. Wooley, “A 15-bit Pipelined Floating-Point A/D Converter,”in Proceedings of the European Solid-State Circuits Conf., pp. 170-173, September 1999.

[153] K. Nagaraj, D. A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, T. R.Viswanathan, “A 700MSample/s 6b Read Channel A/D Converter with 7b Servo Mode,” inISSCC Digest of Technical Papers, pp. 426-427, February 2000.

[154] K. Sushihara, H. Kimura, Y. Okamoto, K. Nishimura, A. Matsuzawa, “A 6b800MSample/s CMOS A/D Converter,” in ISSCC Digest of Technical Papers, pp. 428-429,February 2000.

[155] J. Ming, S. H. Lewis, “An 8b 80MSample/s Pipelined ADC with BackgroundCalibration,” in ISSCC Digest of Technical Papers, pp. 42-43, February 2000.

[156] H. Pan, M. Segami, M. Choi, J. Cao, F. Hatori, A. Abidi, “A 3.3V, 12b, 50MSample/sA/D Converter in CMOS with over 80dB SFDR,” in ISSCC Digest of Technical Papers,pp. 40-41, February 2000.

[157] L. Singer, S. Ho, M. Timko, D. Kelly, “A 12b 65MSample/s CMOS ADC with 82dBSFDR at 120 MHz,” in ISSCC Digest of Technical Papers, pp. 38-39, February 2000.

[158] M.-J. Choe, B.-S. Song, K. Bacrania, “A 13b 40MSample/s CMOS Pipelined FoldingADC with Background Offset Trimming,” in ISSCC Digest of Technical Papers, pp. 36-37,February 2000.

190

[159] I. E. Opris, B. C. Wong, S. W. Chin, “A Pipeline A/D Converter Architecture withLow DNL,” IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 281-285, February 2000.

[160] H.-S. Chen, K. Bacrania, B.-S. Song, “A 14b 20MSample/s CMOS Pipelined ADC,”in ISSCC Digest of Technical Papers, pp. 46-47, February 2000.

[161] C. Moreland, M. Elliot, F. Murden, J. Young, M. Hensley, R. Stop, “A 14b100MSample/s 3-Stage A/D Converter,” in ISSCC Digest of Technical Papers, pp. 34-35,February 2000.

[162] J. Jensen, G. Raghavan, A. Cosand, R. Walden, "A 3.2GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology," IEEE J. Solid-State Circuits, vol. 30,pp. 1119-1127, October 1995.

[163] F. Chen, B. Leung, “A 0.25-mW Low-Pass Passive Sigma-Delta Modulator with Built-In Mixer for a 10-MHz IF Input,” IEEE J. Solid-State Circuits, vol. 32, pp. 774-782, June 1997.

[164] T. L. Brooks, D. H. Robertson, D. F. Kelly, A. Del Muro, S. W. Harston, "A 16bPipeline ADC with 2.5MHz Output Data-Rate," in ISSCC Digest of Technical Papers, pp. 208-209, February 1997.

[165] A. R. Feldman, B. E. Boser, P. R. Gray, “A 13-Bit, 1.4 MS/s Sigma-Delta Modulatorfor RF Baseband Channel Applications,” IEEE J. Solid-State Circuits, vol. 33, pp. 1462-1469,October 1998.

[166] Y. Geerts, A. Marques, M. Steyaert, W. Sansen, "A 3.3V 15-bit Delta-Sigma ADCwith a Signal Bandwidth of 1.1MHz for ADSL-Applications," in Proceedings of the EuropeanSolid-State Circuits Conf., pp. 168-171, September 1998.

[167] H. Tao, J. M. Khoury, "A 100MHz IF, 400 MSample/s CMOS Direct-ConversionBandpass Modulator," in ISSCC Digest of Technical Papers, pp. 60-61, February 1999.

[168] Y. Kobayashi, K. Furukawa, K. Yamakido, “A 1mW Delta-Sigma ADC with FullyIntegrated Baseband Module for GSM Application,” in Proceedings of the European Solid-StateCircuits Conf., pp. 178-181, September 1999.

[169] A. Namdar, B. H. Leung, "A 400MHz 12b 18mW IF Digitizer with Mixer Inside aModulator Loop," in ISSCC Digest of Technical Papers, pp. 62-63, February 1999.

[170] L. J. Breems, E. J. van der Zwan, E. C. Dijkmans, J. H., Huijsing, "A 1.8 mW CMOSModulator with Integrated Mixer for A/D Conversion of IF Signals," in ISSCC Digest of

Technical Papers, pp. 52-53, February 1999.

191

[171]

90dB SNR, 2.5MHz Output Rate ADC Using Cascaded Multibit Modulator at 8xOversampling Ratio,” in ISSCC Digest of Technical Papers, pp. 338-339, February 2000.

[173] Y. Geerts, M. Steyaert, W. Sansen, “A 2.5MSample/s Multi-Bit CMOS ADC with95dB SNR,” in ISSCC Digest of Technical Papers, pp. 336-337, February 2000.

[174] A. K. Ong, B. A. Wooley, "A Two-Path Bandpass Modulator for Digital IFExtraction at 20MHz," in ISSCC Digest of Technical Papers, pp. 212-213, February 1997.

[175] G. Raghavan, J. F. Jensen, R. H. Halden, W. P. Posey, "A Bandpass Modulatorwith 92dB SNR and Center Frequency Continuously Programmable from 0 to 70 MHz," inISSCC Digest of Technical Papers, pp. 214-215, February 1997.

[176] W. Gao, W. M. Snelgrove, “A 950-MHz IF Second-Order Integrated LC BandpassDelta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 33, pp. 723-732, May 1998.

[177] D. Tonietto, P. Cusinato, F. Stefani, A. Baschirotto, “A 3.3V CMOS 10.7MHz 6th-Order Bandpass Modulator with 78dB Dynamic Range,” in Proceedings of the EuropeanSolid-State Circuits Conf., pp. 78-81, September 1999.

[178] S. Bazarjani, S. Younis, J. Goldblatt, D. Butterfield, G. McAllister, S. Ciccarelli, “An85 MHz IF Bandpass Sigma-Delta Modulator for CDMA Receivers,” in Proceedings of theEuropean Solid-State Circuits Conf., pp. 266-269, September 1999.

[179] J. van Engelen, R. van de Plassche, E. Stikvoort, A. Venes, "A 6th-Order Continuous-Time Bandpass Modulator for Digital Radio IF," in ISSCC Digest of Technical Papers, pp.56-57, February 1999.

[180] R. Maurino, P. Mole, “A 200MHz IF, 11 Bit, 4th Order Band-Pass ADC in SiGe,”in Proceedings of the European Solid-State Circuits Conf., pp. 74-77, September 1999.

[181] P. Larsson, “Resonance and Damping in CMOS Circuits with On-Chip DecouplingCapacitance,” IEEE Trans, on Circuits and Syst.—I: Fundamental Theory and Applications,vol. 45, pp. 849-858, August 1998.

[182] M. Ingels, M. S. J. Steyaert, “Design Strategies and Decoupling Techniques forReducing the Effects of Electrical Interference in Mixed-Mode IC’s,” IEEE J. Solid-StateCircuits, vol. 32, pp. 1136-1141, July 1997.

192

S. Lindfors, M. Länsirinne, T. Lindeman, K. Halonen, “A Two-Bit with83dB SNDR for Digital Cellular Telephones,” in Proceedings of the European Solid-StateCircuits Conf., pp. 334-337, September 1999.

[172] I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, S.-I. Chan, “A

[183] B. Gilbert, “A Precise Four-Quadrant Multiplier with Subnanosecond Response,”IEEE J. Solid-State Circuits, vol. 3, pp. 365-373, December 1968.

[184] R. G. Meyer, “Intermodulation in High-Frequency Bipolar Transistor Integrated-Circuit Mixers,” IEEE J. Solid-State Circuits, vol. 21, pp. 534-537, August 1986.

[185] J. Ryynänen, A. Pärssinen, J. Jussila, K. Halonen, “An RF Front-End for the DirectConversion WCDMA Receiver,” in Proceedings of the IEEE Radio Frequency IntegratedCircuits Symposium, pp. 21-24, June 1999.

[186] K. L. Fong, C. D. Hull, R. G. Meyer, “A Class AB Monolithic Mixer for 900-MHzApplications,” IEEE J. Solid-State Circuits, vol. 32, pp. 1166-1172, August 1997.

[187] P. Wambacq, W. Sansen, Distortion Analysis of Analog Integrated Circuits, Boston,Dordrecht, London: Kluwer, 1998.

[188] B. Gilbert, “Design Considerations for Active BJT mixers,” in Low-Power HFMicroelectrinics; A Unified Approach, G. A. S. Machado, Ed. London: IEE Circuits andSystems Series 8, 1996; Ch. 23, pp. 837-928.

[189] K. L. Fong, R. G. Meyer, “High-Frequency Nonlinearity Analysis of Common-Emitterand Differential-Pair Transconductance Stages,” IEEE J. Solid-State Circuits, vol. 33, pp. 548-555, April 1998.

[190] G. L. Baldwin, G. A. Rigby, “New Techniques for Drift Compensation in IntegratedDifferential Amplifiers,” IEEE J. Solid-State Circuits, vol. 3, pp. 325-330, December 1968.

[191] J. C. Schmoock, “An Input Stage Transconductance Reduction Technique for High-Slew Rate Operational Amplifiers,” IEEE J. Solid-State Circuits, vol. 10, pp. 407-411,December 1975.

[192] B. Gilbert, “The Multi-tanh Principle: A Tutorial Overview,” IEEE J. Solid-StateCircuits, vol. 33, pp. 2-17, January 1998.

[193] W. M. C. Sansen, R. G. Meyer, “An Integrated Wide-Band Variable-Gain Amplifierwith Maximum Dynamic Range,” IEEE J. Solid-State Circuits, vol. 9, pp. 159-166, August1974.

[194] J. Durec, E. Main, “A Linear Class AB Single-Ended to Differential TransconverterSuitable for RF Circuits,” in MTT-S International Microwave Symposium Digest of TechnicalPapers, pp. 1071-1074, June 1996.

193

[195] B. Gilbert, “The MICROMIXER: A Highly Linear Variant of the Gilbert Mixer Usinga Bisymmetric Class-AB Input Stage,” IEEE J. Solid-State Circuits, vol. 32, pp. 1412-1423,September 1997.

[196] J. Durec, “An Integrated Silicon Bipolar Receiver Subsystem for 900-MHz ISM BandApplications,” IEEE J. Solid-State Circuits, vol. 33, pp. 1352-1372, September 1998.

[197] S. Wu, B. Razavi, “A 900-MHz/1.8-GHz CMOS Receiver for Dual-BandApplications,” IEEE J. Solid-State Circuits, vol. 33, pp. 2178-2185, December 1998.

[198] A. Nedungadi, T. R. Viswanathan, “Design of Linear CMOS TransconductanceElements,” IEEE Trans. on Circuits and Syst., vol. 31, pp. 891-894, October 1984.

[199] J. N. Babanezhad, G. C. Temes, “A 20-V Four-Quadrant CMOS Analog Multiplier,”IEEE J. Solid-State Circuits, vol. 20, pp. 1158-1168, December 1985.

[200] K. Kimura, “Some Circuit Design Techniques Using Two Cross-Coupled, Emitter-Coupled Pairs,” IEEE Trans. on Circuits and Syst.—I: Fundamental Theory and Applications,vol. 41, pp. 411-423, May 1994.

[201] Q. Huang, F. Piazza, P. Orsatti, T. Ohguro, “The Impact of Scaling Down to DeepSubmicron on CMOS RF Circuits,” IEEE J. Solid-State Circuits, vol. 33, pp. 1023-1036, July1998.

[202] F. Piazza, Q. Huang, “A High Linearity, Single-Ended Input Double-Balanced Mixerin CMOS,” in Proceedings of the European Solid-State Circuits Conf., pp. 60-63,September 1998.

[203] B. Razavi, “A 1.5V 900MHz Downconversion Mixer,” in ISSCC Digest of TechnicalPapers, pp. 48-49, February 1996.

[204] H. Komurasaki, H. Sato, N. Sasaki, T. Miki, “A 2-V 1.9-GHz Si Down-ConversionMixer with an LC Phase Shifter,” IEEE J. Solid-State Circuits, vol. 33, pp. 812-815, May 1998.

[205] T. Manku, G. Beck, E. J. Shin, “A Low-Voltage Design Technique for RF IntegratedCircuits,” IEEE Trans, on Circuits and Syst.—II: Analog and Digital Signal Processing, vol. 45,pp. 1408-1413, October 1998.

[206] M. Harada, T. Tsukahara, J. Yamada, “0.5-IV 2GHz RF Front-End Circuits inCMOS/SIMOX,” in ISSCC Digest of Technical Papers, pp. 378-379, February 2000.

[207] B. Razavi, “A 900-MHz CMOS Direct Conversion Receiver,” in Symposium on VLSICircuits Digest of Technical Papers, pp. 113-114, June 1997.

194

[208] A. Pärssinen, S. Lindfors, J. Ryynänen, S. I. Long, K. Halonen, “1.8 GHz CMOS LNAwith On-Chip DC-Coupling for a Subsampling Direct Conversion Front-End,” in Proceedingsof the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 73-76, June 1998.

[209] P. J. Sullivan, B. A. Xavier, W. H. Kuhn, “Low Voltage Performance of a MicrowaveCMOS Gilbert Cell Mixer,” IEEE J. Solid-State Circuits, vol. 32, pp. 1151-1155, July 1997.

[210] J. H. Huijsing, J. A. van Steenwijk, “A Monolithic Analog Exponential Converter,”IEEE J. Solid-State Circuits, vol. 15, pp. 162-168, April 1980.

[211] D. C. Soo, R. G. Meyer, “A Four-Quadrant NMOS Analog Multiplier,” IEEE J. Solid-State Circuits, vol. 17, pp. 1174-1178, July 1982.

[212] W. H. Lambert, “Second-Order Distortion in CATV Push-Pull Amplifiers,”Proceedings of the IEEE, vol. 58, pp. 1057-1062, July 1970.

[213] C. D. Hull, R. G. Meyer, “A Systematic Approach to the Analysis of Noise in Mixers,”IEEE Trans. on Circuits and Syst.—I: Fundamental Theory and Applications, vol. 40, pp. 909-919, December 1993.

[214] M. T. Terrovitis, R. G. Meyer, “Noise in Current-Commutating CMOS Mixers,” IEEEJ. Solid-State Circuits, vol. 34, pp. 772-783, June 1999.

[215] Y. Hu, K. Mayaram, “Behavioral Models for Noise in Bipolar and MOSFET Mixers,”IEEE Trans. on Circuits and Syst.—II: Analog and Digital Signal Processing, vol. 46, pp. 1289-1300, October 1999.

[216] H. Darabi, A. A. Abidi, “Noise in RF-CMOS Mixers: A Simple Physical Model,”IEEE J. Solid-State Circuits, vol. 35, pp. 15-25, January 2000.

[217] E. Bautista, B. Bastani, J. Heck, “Improved Mixer IIP2 Through Dynamic Matching,”in ISSCC Digest of Technical Papers, pp. 376-377, February 2000.

[218] P. R. Gray, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed.,New York: John Wiley & Sons, 1984.

[219] M. Steyaert, J. Janssens, B. D. Muer, M. Borremans, N. Itoh, “A 2V CMOS CellularTransceiver Front-End,” in ISSCC Digest of Technical Papers, pp. 142-143, February 2000.

[220] H. O. Johansson, C. Svensson, “Time Resolution of NMOS Sampling Switches Usedon Low-Swing Signals,” IEEE J. Solid-State Circuits, vol. 33, pp. 237-244, February 1998.

[221] R. Singh, “A Review of Substrate Coupling Issues and Modeling Strategies,” inProceedings of the Custom Integrated Circuits Conf., pp. 491-498, May 1998.

195

[222] A. Abidi, A. Rofougaran, G. Chang, J. Rael, J. Chang, M. Rofougaran, P. Chang, “TheFuture of CMOS Wireless Transceiver,” in ISSCC Digest of Technical Papers, pp. 118-119,February 1997.

[223] T.-P. Liu, E. Westerwick, N. Rohani, R.-H. Van, “5GHz CMOS Radio TransceiverFront-End Chipset,” in ISSCC Digest of Technical Papers, pp. 320-321, February 2000.

[224] J. Ryynänen, K. Kivekäs, J. Jussila, A. Pärssinen, K. Halonen, “A Dual-Band RFFront-End for WCDMA and GSM Applications,” in Proceedings of the Custom IntegratedCircuits Conf., pp. 175-178, May 2000.

196

5 Circuit Implementations

In this chapter four different circuit implementations are described. Two of them are involved inthe design of direct conversion subsampling RF front-ends and the other two are moreconventional direct conversion receivers for third generation wide-band CDMA systems. Thecircuits are presented in the chronological order. The first chip is a subsampling mixerimplemented with a digital GaAs MESFET process. Low loss was achieved using narrow andsharp strobe pulses for sampling. The second circuit is a differential LNA for a subsampling RFfront-end using CMOS. The main emphasis was to build an optimized ac-coupledinterface to a parallel track-and-hold network for RF subsampling. Unfortunately, themeasurement results of the chip were not satisfactory, and the characterization is heretheoretical. The optimization techniques described in section 5.2 are however straightforwardand applicable to interfaces between the LNA and a direct conversion mixer in general. Theyare especially useful in standard CMOS processes without high-quality passive components.The last two sections cover the circuit design and experimental results of a direct conversionWCDMA receiver. The both versions are implemented with a 25-GHz BiCMOSprocess. In the first version, the RF front-end and analog baseband circuitry are placed ondifferent dies, and the separate 6-bit A/D converters use CMOS. In the second chip, allfunctional blocks from the LNA to 6-bit digital outputs are on the same die. The circuitstructures originate from the former chipset. The single-chip receiver can handle channelbandwidths up to 8 MHz at baseband with 65-MS/s ADCs and tunable channel selection filters.The background for all the implementations is described already earlier and only the circuitdesign aspects and experimental results will be given in this chapter.

5.1 Subsampling Mixer

Subharmonic samplers in the RF frequency range have been used up to 1 GHz as a separatemixer [1], as a part of the receiver front-end including filtering [2] and in a picocell wirelessterminal prototype [3]. Some recent direct digitization GPS receivers use the same principle inthe front-end at 1.5 GHz [4], [5]. Here, a fully integrated subharmonic mixer with an on-chipstrobe pulse generation circuit capable of handling input signals up to 2 GHz with smallconversion loss and high third-order intercept and compression points will be described [6]. Ituses a pair of two-diode bridges and operates with a single 3-V power supply, which is low fora diode bridge sampler. This approach uses a relatively high sampling frequency to reduce thenoise aliasing problem inherent in subharmonic samplers. The highest available samplingfrequency 1.5 GHz is at the range of a typical input signal bandwidth of a mobile receiver.

5.1.1 Circuit Description

Sampling circuits can be roughly divided to two categories according to the switch type. Diodeswitches are often used when high-speed switching is needed, but at lower sampling frequenciestransistor switches are the dominant choice. Most subsampling mixers use CMOS switchedcapacitor track-and-hold circuits [1], [2], [3]. This topology limits the clock frequencies toapproximately 100 MHz, and hence the input bandwidth of the mixer is close to the Nyquistlimitation for wireless communication systems like GSM which have a 30 MHz receivebandwidth. The intention was here to use a topology capable of operating at smaller

197

subsampling ratios in order to reduce the effect of noise aliasing and to minimize the conversionloss.

The circuit consists of two sampling bridges, an output buffer, and the strobe pulse generationcircuit. Figure 5.1 shows the block diagram of the downconverter. The differential highfrequency input signal is divided to two separate single-ended samplers, which have a commondifferential buffer at the output. Differential signal processing, although expensive in terms ofpower, is preferable in RF circuitry because of the insensitivity it provides to common-modedistortion from the substrate and supply voltages. Isolation is very important when high-speedclocks are present in the RF circuitry. In addition to that there is a requirement for separateanalog and digital supplies. Although the strobe pulse generation is implemented withdifferential structures, the top and bottom nodes of the sampling bridge are finally controlled bytwo separate single-ended pulses, which have opposite phases. A slight asymmetry betweenpulses is inevitable. At small input signal levels, the asymmetry dominates charging the holdcapacitor from sample to sample to one direction and thus limiting the dynamic range. With twoseparate bridges the error cancels out in the output buffer when the differential branches arerecombined. The strobe pulses are generated on-chip from an external signal source.

5.1.1.1 Sampling Bridge

Diode bridge design with FETs and a low supply voltage has the problem that it requires largeamplitude sampling pulses. Schottky diodes are easily implemented in a MESFET process, butthe commonly used four-diode bridge requires current sources on the top and bottom of thebridge to supply sufficient current during the track mode. Hence at turn on, two diodes and twocurrent source transistors in saturation are in the stack between the supply rails simultaneously.The minimum saturation voltage of a depletion mode transistor biased at is close to 1 V in atypical MESFET process. Hence, the smallest possible supply is theoretically 3.4 V. DCisolation between the bridge and current sources is not possible because the discharging of thecoupling capacitors is too slow while tracking and the continuous charging of the capacitorsfrom sample to sample destroys the operation. The trend towards low supply voltages requiresthe use of alternative topologies in diode bridge samplers implemented with MESFETtechnologies.

198

The two-diode bridge [7] in Figure 5.2 is capable of operating with a low supply voltagebecause the strobe pulse circuit can be ac-coupled. The initial design specification was 3 V, butin the measurements the strobe pulse generator was insensitive to supply variations from 2.7 Vup to 5 V. The diodes conduct when the sharp strobe pulses pull the voltage over the turn-onpoint. The current from the pulse generator charges the hold capacitor to a voltage proportionalto the input. The falling edge of the strobe turns off the diodes and switches the sampler to holdmode. In the hold mode, the hold capacitor connected to a high impedance buffer keeps itsvalue with a small droop. Simultaneously, the coupling capacitors discharge through the bridgeresistors because the output node of the bridge is at a virtual ground for the strobe circuit. Theresistors also keep the voltage at the top and bottom of the bridge equal to the output during thehold mode, and therefore no reverse biased bootstrap diodes are needed.

5.1.1.2 Output Buffer

In a subsampling mixer followed by continuous-time circuitry, discharging of the capacitorduring the hold mode decreases the conversion efficiency. On the other hand, if discrete-timesamples are processed after the circuit the same effect can be handled as a reduced voltagevalue directly proportional to the time constant. In both cases, a high impedance buffer after thesampler is needed to minimize the droop during the hold mode. A differential common sourceamplifier with resistive loads was used followed by two emitter followers driving theloads in the measurements. A common source stage provides a high input impedance and goodcommon mode rejection. The bias to the input transistors is brought through the bridge to avoiddischarge through the biasing circuit. The simulated buffer gain is 4 dB.

5.1.1.3 Strobe Pulse Circuit

As given in the previous chapter, the conversion loss is minimized when an infinitely narrowsampling pulse is used. However, the hold capacitor can not be charged instantaneously to thefull input voltage. In the two-diode topology, the time constant charging the hold capacitordepends on the current from the strobe pulse generator. Therefore a strong clock buffer isrequired to optimize the circuit performance. The sampling pulses are generated by a Source-Coupled FET Logic (SCFL) differential delay chain coupled to an OR gate as shown in Figure5.3 [8]. A sinusoidal LO input of approximately 0 dBm is amplified, and the delayed edges ofthe LO produce positive and negative sampling pulses as illustrated in the timing diagram. Thegenerator produces strobes with fixed pulse widths at different LO frequencies. The simulatedpulse width values of approximately 350 ps give enough time for the circuit to set up the trackmode when the switches are on with the designed clock buffer. Thus, the duty cycle at a

199

500 MHz sampling frequency is 0.18, which gives the theoretical conversion loss of 2 dB.Except in the clock buffer, standard SCFL cells with resistor loads are used to avoid the effectsof uncorrelated process variations between enhancement and depletion transistors. The clockbuffer shown in Figure 5.4 amplifies the pulse swing above the diode turn on point and feedssufficient current to the bridge. Because of the capacitive coupling to the bridge, only therelative swing between the positive and negative branch is important, relaxing the absolute dclevel requirements with low supply voltages. In this case transistor loads are required in theintermediate stage to produce sufficient amplitude swings.

5.1.1.4 Layout and Fabrication

The circuit has been fabricated using E/D-MESFET process designed for digital VLSIcircuits. The process did not support inductors, and the capacitors built from three wiring layershad small capacitance per unit area and large parasitics to substrate. The capacitors wereimplemented using a ‘sandwich structure’ shown in Figure 5.5 to minimize the area and

200

parasitics. The top and bottom metal layers were connected together forming two parallelcapacitors with the middle plate. The coupling capacitors between diode bridges and clockbuffer require special attention because the parasitic capacitance from the signal nodes toground is unavoidable. The parasitic capacitance from the bottom plate to the substrate is of theorder of 50% of the capacitance value between two metal layers. By placing the bottom metalon the clock buffer side a significant part of the strobe current will flow into ground ruining thecircuit performance. Connected the other way around the parasitics do not have significanteffect on the strobe pulse swing and current in the bridge. The photograph of the fabricatedcircuit is shown in Figure 5.6. The active circuit area is including 77transistors.

5.1.2 Measurement Setup

Spectral measurements were done to evaluate the circuit performance. A 180°-power splitterand biasing blocks were connected between the circuit and the RF synthesizer to produce thedifferential input. The output was combined with a discrete 180° hybrid. Due to the dc-block atthe output, the lower frequency limit was fixed at 100 kHz in the measurements, and the directconversion performance must be evaluated based on this low IF. Most of the measurements

201

were done at a 5-MHz IF output. A separate synthesizer using the crystal reference from the RFsource generated the LO for the sampler. Noise figure measurements of a subsampling mixermust be also done with a spectrum analyzer because the large number of harmonics anddifferent mixing principles interfere with the operation of a noise figure meter in the mixermeasurement modes, and thus the results are not reliable. Many modern spectrum analyzershave a separate noise spectral density measurement mode, which is accurate and takes intoaccount the filtering in the analyzer itself, for example. Often, the internal noise of the spectrumanalyzer exceeds the output noise of the device under test, and a separate low-noise amplifier isneeded to amplify the noise from the DUT up to the measurable range. If the differencebetween the analyzer noise and the output noise is small the result can be scaled to correspondto the desired noise value when the internal noise floor is known

where is the measured value including both circuit, and spectrum analyzer noise,in dBs. is the gain of the low-noise amplifier. The noise measurement setup is shown inFigure 5.7. The noise figure of the downconverter is calculated by definition from the measuredoutput noise, circuit gain and -174 dBm/Hz input noise spectral density introduced by thetermination.

5.1.3 Experimental Results

The circuit met the design objectives of 2-GHz input bandwidth with a small conversion loss,and the measurements matched well with the simulations. The input response is defined to afixed IF in Figure 5.8(a) at a 500-MHz sampling frequency. To achieve sufficient resolution inthe measurements at relatively small sampling rates, the LO frequency is adjusted to the closestpossible value that produces the desired IF when the RF is swept over the band. The notch at2 GHz is due to the imperfections of the probe card used in the measurements. This means thatthe mixer is capable of operation at two or more different frequency bands using the samesystem configuration. Of course, the system requires separate preselection filters, and tominimize the noise, the input bandwidth must be restricted up to the highest frequency band.The IF band of the circuit was limited by the external configuration in the measurement system.The IF frequency selection does not have a significant effect on the conversion gain over themeasured range shown in Figure 5.8(b).

202

The circuit was measured with two different LO-frequencies of 500 MHz and 100 MHz. Theresults are summarized in Table 5.1. The 1-dB conversion loss is small for a passive structureand shows good correspondence with the theory and simulated performance. The slightlysmaller system gain at the 100 MHz sampling frequency is the effect of signal droop during thelonger hold period. The linearity has been measured both with one and two input tones inFigure 5.9. The former yields results comparable to [1] and the latter is normally used to specifythe intermodulation performance of a mixer. The single-tone test actually gives the unwantedmixing product when the harmonic of the input signal mixes with a high harmonic of the clockrather than intermodulation of two in-band interferes. This may be a serious problem in wide-band mixers where the second harmonic of the signal is not attenuated sufficiently by the RC-product of the input. A high linearity has been achieved when compared to typical integratedcontinuous-time mixers. The compression point of +7 dBm is close to the theoretical maximumof the topology defined by the diode turn on caused by the input signal swing.

203

The circuit can operate with a large range of sampling frequencies from 40 MHz to 1.5 GHz,and the minimum required LO input power is -2 dBm. The LO power fed to the samplingbridges is spread over the harmonics of the sampling frequency in the strobe pulse generator.The spectrum depends mainly on the digital clock circuitry including the buffering. The LOharmonics which leak to the circuit input can be divided into two categories whether thecomponent is located inside or outside of the prefilter passband in the receiver front-enddescribed in Figure 5.10. The LO leakage to the RF input is measured, and different harmonicsare summed to give the total leakage power at 100 MHz and 500 MHz as -64 dBm and-56 dBm, respectively. In direct conversion receivers, self-mixing is a serious problem becausethe mixing product will be located at baseband together with the received signal [9]. In asubsampling mixer, all the leaked LO harmonics can self-mix down to baseband if reflectedback before the preselection filter, and they can be treated equally at all sampling frequencies.The reflections from the mismatch in the antenna and the power from external reflections ornear-by transceivers operating at the same frequency will be filtered out, and all harmonicsexcept the one located at the passband of the preselection filter will be attenuated significantly.Although the internal self-mixing can be stronger, the spurious responses from external sourcesare more difficult to predict and compensate later with digital techniques. Because the powerspreads over a larger number of harmonics, reducing the power per component when a lowersampling frequency is used, the low sampling rate gives even more benefit than the total LOleakage power indicates. In that case the harmonic in the prefilter passband is much smallerthan the corresponding component when a high sampling frequency is used. In the describedsampler, when operating at 1.5-GHz RF-input, the in-band harmonic leakage will be -61 dBm at500 MHz sampling frequency and 15-dB smaller at 100 MHz. The difference is approximatelythe same at other harmonics as well.

The nominal supply voltage is 3 V but the digital supply for the strobe pulse generator can be aslow as 2.7 V. The strobe pulse generator dissipates 125 mW of power which is much lower thanin some earlier diode bridge samplers [10], [11]. The output buffer needs to drive loads,and therefore consumes 102 mW. For an on-chip load the dissipation would be significantlysmaller.

204

5.1.4 Summary of the Subsampling Mixer

The described subharmonic mixer based on a diode bridge is capable of operating at mobileradio frequencies up to 2 GHz. A small conversion loss for a passive mixer (1 dB) has beenachieved with high linearity. The circuit operates from a 3 V power supply and dissipates lesspower than many other diode bridge samplers. Noise aliasing is an inherent problem insubharmonic sampling, but it can be reduced by using high sampling frequencies. On the otherhand, LO leakage to input is smaller at low sampling frequencies, which has specialsignificance in direct conversion applications. Subsampling downconverters can replacetraditional continuous-time mixers and use a low frequency LO synthesizer in superheterodyneor direct conversion receivers.

5.2 Low-Noise Amplifier and Interface to a Subsampling RF Front-End

The design of a 1.8 GHz CMOS LNA with an optimized interface to a direct conversion mixeris given in this section [12]. The LNA is designed to drive a capacitive load such as the load ofa subsampling mixer. The output resonator limits the mixer input noise bandwidth, which isnecessary to optimize the system noise figure. ac-coupling, an essential function in a directconversion front-end, is realized with an on-chip structure, which has low sensitivity to parasiticeffects. The subsampling mixer, which is on the same chip with the LNA, is reported in [13].The hold capacitor of the track-and-hold circuit is a part of the load resonator of the LNA.

The most harmful part of the offset in the direct conversion comes from the second-ordernonlinearities, which mix any combination of the two non-desired channels passing the pre-selection filter directly to a dynamic error at baseband. A large coupling capacitor can be usedto remove the dc offset caused by the second-order nonlinearities from the LNA. An on-chiprealization would require a large area and the parasitic bottom plate capacitance to siliconsubstrate would destroy the signal swing in the interface between the LNA and the mixer.

205

5.2.1 Low-Noise Amplifier

The low-noise amplifier uses the most common architecture i.e. inductive degeneration schemewith a cascoded input shown in Figure 5.11. Matching criteria for differential amplifierdescribed in the previous chapter was used. The gate resistance was not included in the MOSmodel, but it was minimized fingering the large input devices. The value was estimated usingthe effective gate resistance given by [14]

for a transistor with the total gate width W, length L, and n number of fingers in the layout eachhaving gate contacts only at one end of the transistor. is the sheet resistance of the gatepolysilicon. The gate noise contribution can be reduced by a factor of four when contacting thegates at both ends. The thermal noise current for a MOSFET operating in saturation is

where the factor is 2/3 for a long channel device. In submicron technologies the hasbeen shown to be significantly larger than the above value and the value depends on the biasingconditions in saturation [15]. The commonly used approximation of 2.5 was used in thesimulations. The power consumption versus noise figure has been optimized with the methoddescribed in [16]. The quality factor for the input stage is defined by

gate width based on the optimization was for the transistor M1 at the input signalfrequency of 1.8 GHz.

206

where is the resonance frequency of the matching network. and are the gate and sourceinductors, respectively. The M1 bias current was chosen to be 7 mA for a 3 V supply, and the

5.2.2 Resonator Load with On-Chip Coupling Capacitors

In most cases, an LNA drives an inductive load, in Figure 5.11, which is matched to aoutput with a series capacitor or with a separate buffer. An inductor load is ideally noiseless andallows a large signal swing at the output even with a low supply voltage. In this case, the LNAis driving a sampler, which has a capacitive input. The sampler processes the input signal as avoltage value over the capacitor, and therefore an output matching to a lower impedance level isnot required. On the other hand, the sampler has a wideband input. As a subsampling mixer,which has the bandwidth at least up to the desired input frequency, it aliases all the incomingnoise down to the Nyquist domain defined by the sampling frequency. Any structure limitingthe noise band at the input of the sampler will improve the system noise performance. Hence,the sampler input can be designed to operate as a parallel resonance circuit at RF.

Typically, the coupling capacitor required in the RF front-end is as large as possible andtherefore negligible at the signal frequency, or it can be used as a series matching element. Inideal case, the same is also valid for the capacitive load because of the capacitive voltagedivision between the coupling and sampling capacitances would reduce the voltage swing at theoutput. The integrated capacitor has a large parasitic bottom plate capacitance in series witha substrate resistance to ground. The parasitic effects shunt the signal to ground, and theymay significantly shift the center frequency and ruin the Q-value of the resonance circuits. Theparasitic capacitance was estimated to be an eighth part of the based on the available processdata of the applied CMOS. If the value of is in the same range with the samplingcapacitor, i.e. and hence the resonance peak will be strongly dependent on smallvariations of and The reduction of the coupling capacitor to be smaller than minimizesthe effect of the both parasitics, and the simulations showed improved performance compared tothe large case with excellent insensitivity to value. The inductor can be placed either tobring the bias current for the transistors M1 and M2, or to avoid the gain degradation, on theother side of the in parallel with the capacitive output as shown in Figure 5.12. The formerpresents a traditional LNA architecture having the benefits described in the beginning of thissection. The latter suffers from the need of a separate bias current network.

To compare the two given alternatives the small signal equivalent circuits were simulated. InFigure 5.13, a detailed model is shown for the resonator of Figure 5.12(b). Hence, the resonatoris not any more a simple LC-tank, and the performance must be optimized taking care of theadditional capacitors and parasitic effects. In the simulations, the on-chip inductor was modeledwith the resistive loss of to give a realistic approximation for the available Q. The case

207

when the inductor is located in parallel with the sampling capacitor gives a better performancecompared to the traditional topology as shown in Figure 5.14. The gain maximum with thesame current is improved over 5 dB, and a much better isolation around DC can be achieveddue to the pole, which locates closer to the resonance peak. The gain advantage comes from thehigh impedance of the parallel resonator, which allows the use of a small series capacitorwithout significant voltage drop over it. mitigates the effects of and In an integratedstructure, the benefits of the described alternatives can not be combined using two inductors,because the two resonators should be perfectly matched to avoid collapse in performance. Theresonator structure in Figure 5.12(b) was chosen and the biasing problem was solved separately.

208

5.2.3 Current Biasing Circuit for the LNA

The bias circuit should be negligible for the resonator, which means a high output impedance atwide range of frequencies. In principle, an inductor can be used for biasing but the requiredvalue would be too large to realize even with an external component. Another choice is theLNA topology with a complementary input [17]. However, the PMOS in the desired processwas too slow for 2 GHz operation. Therefore, PMOS was used as a load. The PMOS noisecontribution can deteriorate the noise performance significantly. An LC-tank, formed by and

in Figure 5.15, degenerates the PMOS channel noise current. The simulations indicate thatthe PMOS noise contribution is insignificant. The resonance frequency of the LC-tank isdefined to be equal with the actual resonance to optimize the performance. Because the tank isnot directly connected to the output, the resonator mismatch has little impact on the LNA gain.

5.2.4 Implementation

The circuit is designed for a standard CMOS process. A differential structure was usedbecause the subsampling mixer uses an SC track-and-hold circuit, which requires a balancedinput. It also improves the insensitivity to common-mode noise from the substrate and supplies.The input matching inductors and are implemented with the bond wires. performsalso common mode rejection. The components inside the dashed line in Figure 5.15 areintegrated on the same chip with the subsampler. In the simulations, a simple lumped ten-element model for the on-chip inductors was used [18]. The parameters were extracted from themeasured test structures. The resonance frequency depends significantly on the inductorparasitics, and therefore an accurate experimental model is necessary. The microphotograph ofthe subsampling front-end is given in Figure 5.16 and the simulated performance is collected inTable 5.2. The frequency response is shown in Figure 5.17. The low-frequency isolation isexcellent, and follows the theoretical curve in Figure 5.14. The different noise sources of theLNA were analyzed in the circuit simulator. The result indicates that the PMOS load with thedegeneration circuit adds only 0.2 dB to the total noise figure and therefore does not deterioratethe noise performance.

209

210

5.2.5 Summary of the LNA and Interface to Subsampling Mixer

The on-chip RF interface between the LNA and downconversion mixer with a capacitive inputcan be optimized using a small coupling capacitor. The LNA noise band has been limited withan output resonator to reduce the aliasing problem in the subsampling front-end. The on-chipcoupling capacitor scheme eliminates also the feedthrough of the second-order nonlinearitiesinto the output of the subsampling downconverter in a direct conversion receiver. The giveninterface is especially suitable for the standard CMOS processes, which do not have high-quality passive components for the RF design. The LNA noise figure of 3.4 dB and 17-dB gainwas achieved in the simulations. In the measurements, the spectral shape was roughly recoveredas designed. The problems in the testing of the whole subsampling front-end however preventedthe complete characterization of the LNA block as it. A PMOS load transistor delivers the draincurrent for the gain stage without interfering with the actual resonator. The PMOS noisecontribution to the output was degenerated with a second on-chip resonator.

5.3 Chipset for Direct Conversion WCDMA Receiver

The chip set described in this subsection is the first prototype receiver published for the 3rdgeneration cellular systems [19], [20]. The system is often called either Universal MobileTelecommunication System (UMTS) or International Mobile Telecommunications 2000(IMT-2000). Later the term 3GPP (Third Generation Partnership Project) according to thestandardization organization is also used in the meaning of the new system. In Europe andJapan, the Wide-Band Code Division Multiple Access (WCDMA) scheme will be adopted inthe air interface. In the United States a slightly different path called cdma2000, which isbackwards compatible to IS-95, has been followed in the standardization of wide bandwidthwireless systems. Although a lot of effort has been done to unify the different proposals, thefuture of the 3rd generation communications will be probably a family of systems for wide-band communications rather than a single universal specification.

The specifications of the chip set are based on the technical aspects of the WCDMA proposal inits original form, but the given structures can be easily applied to all systems using wide-banddirect sequence spread spectrum (DS-SS) radio access. The major change from the originalproposal is the reduced chip rate from 4.096 Mcps to 3.84 Mcps. However, the channel spacingis still 5 MHz. Hence, the required changes for the new specifications would be scaling of thecutoff frequency in the channel selection filters and reduction of the sampling rate in the ADCs.Table 5.3 collects the system characteristics of the original WCDMA proposal. In this approach,the receiver is also capable of handling wider channel bandwidths with a 10 or 20 MHz channelspacing to increase the chip rate and capacity of a single carrier. The extended data rates at thebaseband and a higher sampling rate of the ADCs lead to different optimization criteria of thereceiver blocks. Especially the power consumption of the ADCs depends on the sampling rateand reduces only little when clocked at a smaller rate. Therefore the power consumption is notoptimized for the smallest bandwidth although almost all results are given with that nominalcondition.

211

The direct conversion architecture is adopted in the WCDMA receiver capable of operatingboth in mobile terminals and base stations using the proposed frequency ranges, channelbandwidths, data rates and modulation for the 3rd generation mobile telecommunicationssystem. The receiver consists of the analog signal processing circuitry including analog-to-digital converters, which suppresses sufficiently the adjacent channel and other interfererspassing the preselection filter before digital signal processing. Coherent detection, pulseshaping, decorrelation, decoding, and demodulation are performed in the digital domain.

5.3.1 Building Blocks of the Direct Conversion Receiver

The direct conversion receiver in Figure 5.18 is distributed on four dies to avoid substratecoupling between the sensitive blocks. The low-noise amplifier (LNA) and quadrature mixerson the radio frequency (RF) die amplify and convert the signal for the baseband chip, whichincludes quadrature paths of filtering and controlled gain in a merged manner. The 6-bit analog-to-digital converters (ADC) give enough headroom for efficient digital signal post-processing.The RF and analog baseband blocks use a 25 GHz BiCMOS process with a MOSminimum channel length while the ADCs are implemented with a CMOS technology.The external components are limited to input matching and supply decoupling at RF, andground stabilization and four servo feedback capacitors at baseband.

212

Highly integrated direct conversion CDMA receivers for lower data rates and narrower radiochannels have been published for direct sequence [21] and frequency-hopped [22] ISM band(902-928 MHz) test systems. The WCDMA receiver is designed to operate in commercialcellular bands at the 2 GHz range, and the channel spacing can be digitally selected from 5 to20 MHz. A digital signal post-processor is needed to despread and detect the data with variablerates in the third generation mobile communications. The direct sequence spread spectrumsystem provides a straightforward trade-off between the transferred data rate and the quality ofservice or the cell size by changing the processing gain in the constant chip rate transmission.The robust, digitally controllable analog front-end allows flexibility in the overall radio systemdesign.

The trade-off between noise and linearity at the baseband signal processing has been optimizedusing a merged filtering and controlled gain scheme after the downconversion. The appliedscheme does not violate the filter transfer function, and the number of amplifiers is minimized.The measured results prove that the integrated baseband block does not significantly limit thehigh dynamic range of the receiver.

5.3.1.1 LNA and Downconversion Mixer

The RF front-end in Figure 5.19 has a differential bipolar LNA, which provides 20-dB gain, anduses bondwire inductances L3-L7 for matching and cascode transistors Q3 and Q4 to isolate theresonator load from the input. The inductor L5 is bonded directly between the emitter pads toincrease the required component values. Otherwise the small emitter degeneration inductors(<1 nH) are very sensitive to variations and short wires are difficult to bond on the PCB. Theon-chip resonator load consists of 1.7-nH inductors L1 and L2, and 2.7-pF capacitors Cl andC2. The LC-load has too narrow bandwidth for operation both in mobile terminals and basestations. To avoid external tuning of the resonators, they are de-Qed with on-chipparallel resistors Rl and R2 to achieve over 500 MHz bandwidth with a negligible degradationin the noise performance. The two 60-MHz frequency bands at a 190-MHz duplex separationcan be covered with this arrangement and the process variations have only a minor effect on thelow-Q resonator load. The biasing of the LNA is done using current mirrors from an externalsource. The LNA draws 4-mA supply current.

213

The quadrature mixers use a modified double-balanced Gilbert cell topology in Figure 5.20.The NMOS input devices Ml and M2 provide high linearity and sufficientgain with a 4 mA of total mixer core current. On the other hand, the use of bipolar transistors ascommutating switches minimize the critical flicker noise. To relax the linearity requirements ofthe baseband block, the 70-pF on-chip capacitors Cl and C2 form a pole with load resistors Rland R2 at 6 MHz. The high-quality metal-insulator-metal coupling capacitors block the low-frequency noise and distortion from the RF section and the local oscillator (LO) inputs of themixers, and hence the low frequency leakage into the mixer output comes mainly from internalsources. The external LO is divided in quadrature by a second-order polyphase filter (RC-PP),and differential pair buffers compensate the loss of the polyphase filter. The RF chip operatesdown to a 2.1-V supply with negligible degradation in the gain and linearity.

214

5.3.1.2 Interface to Baseband

A relatively low impedance level is required at the baseband input to keep the noise at anacceptable level. At the highest gain setting the differential input resistance of the basebandblock is Therefore, low impedance output buffers are required to feed the baseband. Thebuffer gain drops 1 dB from the maximum when driving the baseband, which is a trade-offbetween the gain and current consumption. The DC level of the mixer output is set with acommon-mode feedback (CMFB) circuit, which compares the node to the basebandvoltage reference, and adjusts the DC current through the mixer loads Rl and R2 until the DC-level at the buffer output is correct. The two-stage amplifier used in the CMFB-circuit is shownin Figure 5.21. The CMFB limits the RF supply range from 2.5 V to 3.0 V when operated withthe baseband circuitry, which requires input DC-level accuracy of approximatelyThis has been shown already in the previous chapter when the interface to baseband isdiscussed.

5.3.1.3 Baseband Processing

The analog channel filtering is always a compromise between the adjacent channel rejectionand inter-symbol-interference (ISI). Based on the discussion in the previous chapter the 5th-order Butterworth response was chosen as a prototype. In the baseband circuitry, Figure 5.22, apreamplifier is needed in front of the filter to reduce the filter noise contribution at high gainvalues. The pole of the preamplifier at the filter cutoff frequency relaxes the linearityrequirements of the following stages. At lower gain values the pole moves to higherfrequencies. The active RC filter implementation has high linearity and insensitivity to parasiticeffects, and the Miller-compensated opamps are suitable for low supply voltage operation andachieve low noise. The merged filtering and controlled gain stages in Figure 5.23 optimize thenoise and linearity performance of an active RC filter, and minimize the number of amplifiers atthe baseband circuitry. The 78-dB gain control range can be adjusted digitally in 3-dB steps.The gain ranges and step sizes of different stages are collected in Table 5.4. The control isimplemented with switched resistor matrices, and the shape of the filter frequency response isunaffected at all gain settings. The gains of the integrators are changed by scaling the inputresistors. The shape of the response is kept constant by an opposite change in the feedbackresistors as shown in Figure 5.23. In practice, the finite GBW of the amplifiers slightly changesthe shape of the frequency response at high gain values. A corresponding technique can beimplemented also with SC-filters as in [23].

215

216

The filter can be programmed to three bandwidths from 2 to 8 MHz, which allow datatransfer at the rates of 4.096, 8.192 and 16.384 Mcps. The channel bandwidth is selected andthe filter frequency response tuned with binary-weighted 7-bit switched capacitor matrices. Thefrequency response tuning is 5-bit [24], [25], [26]. The channel bandwidth is selected by

shifting the 5-bit tuning code. At the channel bandwidth of 2 MHz, the five most significant bitsof the 7-bit code are used for the tuning of frequency response. The on-chip frequency responsetuning circuitry is based on a single-ended time-domain test integrator [26]. The reference forthe tuning comes from the same accurate external clock, which is used in the A/D converters. Inthe filter, the opamp GBWs are tuned according to the channel bandwidth by scaling the biasingcurrents. This optimizes the power consumption at different channel bandwidths.

The servo loop, which filters out the dc component at the input and compensates the internaloffsets of the baseband, is connected over the whole baseband excluding the output buffersshown in Figure 5.22. The servo amplifier is an active RC integrator with two 220-nF off-chip

receiver is distributed on four chips. Test structures on the RF die and large standardcells driving the ADC output are excluded from the given area. The layout symmetry in thedifferential RF block and the first stages of the baseband is the key element to achieve a highimmunity against even-order distortion. For example, dummy crossings between differentwiring layers are used to keep the capacitive loading equal in critical RF parts. Hence, the IIP2depends mainly on the matching of the adjacent components, because no IM2 cancellationcircuitry is used as in [30]. The RF and LO inputs are grounded properly on both sides andbrought orthogonally onto the chip to minimize the LO-to-RF leakage due to the mutualinductance of the bond wires. The LO-to-baseband isolation is improved by placing the outputbus far from the LO wires between the LNA and mixer. The long signal wires are drawn with athick, low-resistivity top metal layer, which is used for inductors as well. In the baseband, thefrequency tuning and reference blocks are placed between the channels to reduce the crosstalkbetween I- and Q-branches.

217

capacitors and on-chip high-ohmic polysilicon resistors. The highpass pole is located at2 kHz with the highest gain setting and moves down when the baseband gain is decreased.Offsets up to 300 mV at the input of the baseband circuitry can be tolerated at all gain settings.The baseband block has been implemented completely with MOS transistors excluding thebipolar emitter followers as output buffers.

5.3.1.4 A/D Converter

The weak CDMA signals are buried in noise before despreading. Although the gain controladjusts the input level to an appropriate value for the ADC input, several bits are required todetect the desired channel, which is below the noise and different user signals propagatedthrough multipath channels. It is estimated that 4- to 6-bit converters have adequateperformance in the WCDMA environment [27]. The DCR uses two A/D converters, whichemploy a 1.5-bit/stage pipeline architecture with digital correction and interstage gain [28]. Thepipeline architecture allows the use of low supply voltage and scaling of the capacitor valuesand amplifiers of the stages along the converter to minimize the power consumption in the high-speed medium resolution ADCs. The A/D converter was originally designed to have aresolution of 8 bits at a nominal sampling rate of 40 MS/s [29]. Hence, the power consumptionis not optimized for 6-bit 16-MS/s operation used in the WCDMA receiver. The capacitorvalues, switches and amplifiers of the last three pipeline stages are scaled to compromisebetween the design complexity and power dissipation.

5.3.2 Layout

The microphotographs of the circuits are shown in Figure 5.24. The active silicon area of the

5.3.3 Experimental Results

The four chips are mounted on two different printed circuits boards (PCB). The RF chip isglued and bonded directly on the PCB. The bondwires are used for input matching and severalbonding pads are used for ground and supply to keep the parasitic inductance at an acceptablelevel. The simulated 0.5-dB loss of the RF input wires on the PCB is not extracted from theresults. Due to the size limitations of bonding instruments the baseband and ADC chips areplaced on a separate board. The baseband and ADC chips are in the standard CQFP64 andCLCC44 ceramic packages, respectively. The DCR is characterized with the 6-bit ADC clockedat 16 MHz for the 4.096-Mcps channel. External baluns are used at the RF and LO inputs. Thebits were captured from the ADCs with a logic analyzer and transferred to the frequencydomain with an FFT as depicted in Figure 5.25.

218

The differential matching is defined as described in the previous chapter. The differential S11 iscompared to the simulated value together with the measured S11 and S22 in Figure 5.26(a). Thematching is better than 10 dB in the 1.9 to 2.4-GHz range. The response of the RF chip isshown in Figure 5.26(b), and the shift from the targeted 2 GHz maximum gain rises the noisefigure of the receiver by about 1 dB. The measured IIP3, IIP2, and –1 dB compression are –9dBm, +43 dBm, and -25 dBm, respectively at –5-dBm LO power. The LO-to-RF isolation isbetter than 66 dB at all frequencies, and less than 1° and 0.6-dB I/Q phase and amplitudeimbalances meet the requirements of the DCR.

219

The baseband frequency responses at several different channel gain settings and bandwidths areshown in Figure 5.27(a). At the 27-dB gain setting, the 4- and 8-MHz channel responses forhigher chip rates are also given. The frequencies below 10 kHz could not be measured at thehighest gain due to the limited dynamic range of the measurement equipment. The largestabsolute gain and gain step errors are less than 3 dB and 0.4 dB, respectively. The basebandIIP3 and IIP2 of +14 dBm and +60 dBm would dominate the receiver performance without thepole at the output of the mixer. The 6-MHz pole damps 10- and 20-MHz interferers, and henceimproves the overall linearity. The measured I/Q phase imbalance indicates better than 1 %accuracy in the time-constants in all cases. The gain error is less than 0.2 dB. The input referrednoise at all gain values is compared to the simulation in Figure 5.27(b). The steep slope abovethe 40-dB gain is the effect of the preamplifier, which brings the noise down for weak signals.The ADCs can operate up to 50 MS/s, and the differential input range is 1.6 Vpp. The measuredSNDR and SFDR are 35.7 and 45.5 dBc in the 6-bit mode. DNL and INL are 0.42 and 0.36LSB, respectively.

The DCR channel response is shown for a 2-GHz RF signal in Figure 5.28(a). The receivervoltage gain is 94 dB and the DSB noise figure 5.1 dB. With the maximum gain of 96.5 dB at1.7 GHz, the noise figure is decreased to 3.9 dB. In the two-tone test in Figure 5.28(b), thethird- and second-order intercept points –9.5 dBm and +38 dBm indicate high linearity andexcellent immunity against envelope distortion. The measured blocking performance withoutthe band select filter is shown in Figure 5.29 at the maximum gain. The –107-dBm test signal iscompressed by 1 dB due to a blocker. Below 10 MHz, the channel filter dominates the behaviorwhile the RF compression limits the maximal level to –25 dBm at large offsets from the LO. At20-Hz offset the input compression is –47 dBm, which is much above the possible LO leakage.Hence, the DCR is not sensitive to a –5-dBm LO signal with over 66-dB LO-to-RF isolation.The measured DCR performance is summarized in Table 5.5. From the 128 mA supply current,the LNA and two mixers take 17 %, channel filters 26 % and two ADCs 36 %. The rest isneeded for buffering between stages. As described earlier the filter current is scaled up at higherbandwidths.

As given in chapter 2, the sensitivity can be calculated for the receiver from the thermal noisefloor at the RF band, receiver noise figure, processing gain at the desired bit rate and theminimum required SNR for a certain BER. For example, the BER requires a 6.7 dB SNRwhen QPSK signals are detected. With a 128-kb/s data rate and 5.1-dB NF of the receiver, -114dBm sensitivity is achieved for the 4.096-Mcps transmission. The sensitivity changes as afunction of data rate and BER requirement as given already in chapter 2. The high transmissionrate and high quality requirements in the data transfer are possible only with much higher signallevels than for speech at the input of the receiver.

220

221

5.3.4 Summary of the WCDMA Chip Set

The direct conversion architecture is suitable for wide-band communications even in spectrallyefficient modulations like QPSK, because the dc offset cancellation is easier than in narrow-band systems, and continuous transmission avoids some transient problems of TDMA.

222

Although the spread-spectrum systems are relatively insensitive to narrow-band interferers, ahighly linear, selective and sensitive analog processing unit is required due to manytechnological limitations, and it efficiently reduces the number of bits of the A/D converter,simplifies digital processing and reduces DSP power consumption. The receiver performance isoptimized embedding the required gain inside the channel selection filter and merging thedigital gain control along the filter chain. The high linearity and tolerance against envelopedistortion is achieved with modified Gilbert-cell mixers having NMOS transistors as inputstages, careful layout design, and optimization of the baseband processing. TheBiCMOS process with high-quality passive components allows effective methods to combinedifferent transistor types, and low losses for high-performance applications. The directconversion receiver described in this section reflects the requirements of the third generationwireless communications and shows a high-performance integrated solution with a state-of-the-art technology for such a system.

5.4 Single-Chip Direct Conversion Receiver for WCDMA

This section introduces the implementation of a single-chip direct conversion receiver based onthe circuit design in the previous section. The main emphasis is to study the presence of digitalcircuits on the same chip with a sensitive RF front-end and to prove the performance with acareful characterization. The single-chip direct conversion receiver is published in [31].

5.4.1 Circuit Design

The circuit design is based on the chip set where the RF, analog baseband and ADC blockswere on separate dies [19]. The different blocks of the receiver are described already in section5.3. Only minor modifications have been done for the RF and baseband blocks, but A/Dconverters are redesigned for the new process using the same architecture as earlier. The single-chip version, in Figure 5.30, consists of a common-source LNA, two Gilbert-cell mixers withMOS input stages, quadrature LO generation from an external source using a polyphase filterand buffers, active RC-filters with a digitally adjustable gain and 6-bit pipeline ADCs. Thebandwidth of the 5th-order Butterworth lowpass filter is tunable to 2, 4 or 8 MHz bandwidthsand the ADC operates up to 65 MS/s. The differential receiver achieves 95-dB gain with a25-GHz BiCMOS technology. External components include RF input matching withbond wires, four servo feedback capacitors and decoupling structures. The RF circuitry isplaced opposite to the ADCs on the chip in Figure 5.31. The RF input and LO pads aregrounded on the both sides, and the digital blocks of the baseband and ADCs are isolated fromthe with an layer connected to The digital output pad drivers areoutside the protection well.

223

5.4.2 Experimental Results

The chip is bonded directly on the PCB, and the bits from the ADC are captured with a logicanalyzer. The signals are analyzed with FFT without despreading. Noise figure is measuredover the entire WCDMA band at the LO frequencies, which are multiples of the 16.384 MHzADC clock, and at a 1 MHz offset from the clock harmonics. The first measurement gives thenoise figure without a spurious tone, because the servo loop removes the offset and spurs below2 kHz, and the second test gives a reference with a spur at the passband. The noise figurewithout the clock distortion is plotted in the middle of Figure 5.32(a). The two curves aremeasured separately from the I- and Q-channels. The same custom is followed throughout themeasurements of the single-chip receiver. The variations between adjacent testing pointsindicate the accuracy of the FFT method without averaging. The upper curves in the figure

224

arbitrarily. The spur at downconverts to about 1 MHz IF in each case and it wasalways the strongest spurious signal at the band of interest. However, there were other possiblecombinations of LO, clock and blocking signals, which can produce the same tone as well.Unfortunately, the slow measurement method did not allow more testing frequencies. The -1 dBcompression of the -99 dBm desired RF input signal was measured with a -24 dBm blockingsignal in all cases. If the desired signal is 3 dB above the noise floor in the blocking test, theunwanted spurious can be at the same level with noise. In this case, the spurious tones below

are acceptable at the input of the ADC. The value was calculated in the previouschapter. The blocking power was swept at all test frequencies, and in the worst case thespurious tone reached the maximum acceptable level with a -29 dBm input as given in Figure5.33. On the other hand, at some frequencies the effect of the spurious was negligible beforecompression. Hence, unwanted spurious tones desensitizing the receiver are a problem, whichmust be carefully considered. Here, only a slight deterioration in the blocking test wasmeasured, but especially in the narrow-band systems a better isolation between clock signalsand RF input is necessary.

225

present the levels of the downconverted clock harmonics at the frequencies wheren is the order of the clock harmonic, which alias at or closest to dc. The effect of those spurs onthe noise figure is plotted also in Figure 5.32(a). Less than a 1-dB deterioration from the 5.5-dBnoise figure was typically obtained, and in the worst case the degradation was below 2 dB. It isimportant to observe that the even and odd harmonics of the clock signal behave differently.The situation was sensitive to the amplitude of an external clock signal, which indicates that thecoupling to the RF input is most likely dominated by the unmatched clock interface rather thansubstrate leakage. The 1.975-1.990 MHz LO-range was measured with a tighter raster to definethe effect of the baseband filter response on the noise figure in Figure 5.32(b). The notch in thespur amplitude is at the clock harmonic, which downconverts directly to dc.

In the blocking test, the gain compression and spurious tone were defined at the offsets of 15and 115 MHz with LO frequencies at 2015 and 2115 MHz. The test tones were chosen rather

5.4.3 Summary of the Single-Chip Direct Conversion Receiver

The measured performance of the receiver is given in Table 5.6. The numbers are alsocompared to the earlier chip set. The different IIP2 values in the I- and Q-branches indicate thetypical sensitivity to mismatches in double-balanced mixers. Other parameters are comparableto the earlier chip set. The direct conversion receiver with the on-chip A/D converters achievesan excellent performance although the noise figure and blocking behavior are slightly degradedcompared to the chip set. Also, the gain compression with the maximum gain at the passband ofthe channel selection filter was measured. As given in Table 5.6, the limited input range of the6-bit ADC dominates the compression behavior. The layout and floorplan issues are critical inthe implementation, but they were considered already in the previous implementation. Onlylittle changes were done on the layout in the single-chip version. Multiple supply and groundconnections were used, and especially the separate analog and digital supply voltages of theADCs were isolated from other structures. The testing of single-chip receivers is much morecomplicated than with other direct conversion structures. One important factor is the largenumber of potential unwanted spurious falling at the passband of the channel selection filters.On the other hand, the values measured using a realistic A/D converter of the system give thereal performance without a need to any mathematical combination of different blocksafterwards.

226

References

[1] P. Y. Chan, A. Rofougaran, K. A. Ahmed, A. A. Abidi, “A Highly Linear 1-GHzCMOS Downconversion Mixer,” in Proceedings of the European Solid-State Circuits Conf., pp.210-213, September 1993.

[2] D. H. Shen, C.-M. Hwang, B. Lusignan, B. A. Wooley, “A 900-MHz RF Front-Endwith Integrated Discrete-Time Filtering,” IEEE J. Solid-State Circuits, vol. 31, pp. 1945-1953,December 1996.

227

[3] S. Sheng, L. Lynn, J. Peroulas, K. Stone, I. O’Donnell, R. Brodersen, “A Low-PowerCMOS Chipset for Spread-Spectrum Communications,” in ISSCC Digest of Technical Papers,pp. 346-347, February 1996.

[4] A. Brown, B. Wolt, “Digital L-Band Receiver Architecture with Direct RF Sampling,”in Proceedings of the IEEE Position Location and Navigation Symp., pp. 209-215, April 1994.

[5] D. M. Akos, J. B. Y. Tsui, “Design and Implementation of a Direct Digitization GPSReceiver Front End,” IEEE Trans. on Microwave Theory and Techniques, vol. 44, pp. 2334-2339, December 1996.

[6] A. Pärssinen, R. Magoon, S. I. Long, V. Porra, “A 2-GHz Subharmonic Sampler forSignal Downconversion,” IEEE Trans. on Microwave Theory and Techniques, vol. 45, pp.2344-2351, December 1997.

[7] R. Y. Yu, M. Case, M. Kamegawa, M. Sundaram, M. J. W. Rodwell, A. W. Gossard,“275 GHz 3-Mask Integrated GaAs Sampling Circuit,” Electronics Letters, vol. 26, pp. 949-951, June 1990.

[8] G. Seehausen, “Generating Short Pulses Using Delay Line Coupled GaAs NORGates,” Electronics Letters, vol. 28, pp. 2235-2237, November 1992.

[9] A. A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications,”IEEE J. of Solid-State Circuits, vol. 30, pp. 1399-1410, December 1995.

[10] G. Rohmer, J. Sauerer, D. Seitzer, U. Nowotny, B. Raynor, J. Schneider, “An 800MSps Track and Hold Using a AlGaAs-HEMT-Technology,” in Proceedings of theIEEE GaAs IC Symp., pp. 236-239, November 1994.

[11] K. Poulton, J. S. Kang, J. J. Corcoran, “A 2 GS/s HBT Sample and Hold,” inProceedings of the GaAs IC Symp., pp. 199-202, November 1988.

[12] A. Pärssinen, S. Lindfors, J. Ryynänen, S. I. Long, K. Halonen, “1.8 GHz CMOS LNAwith On-Chip DC-Coupling for a Subsampling Direct Conversion Front-End,” in Proceedingsof the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 73-76, June 1998.

[13] S. Lindfors, A. Pärssinen, J. Ryynänen, K. Halonen, “A Novel Technique for NoiseReduction in CMOS Subsamplers,” in Proceedings of the IEEE International Symposium onCircuits and Systems, vol. 1, pp. 257-260, June 1998.

[14] B. Razavi, R.-H. Yan, K. F. Lee, “Impact of Distributed Gate Resistance on thePerformance of MOS Devices,” IEEE Trans. on Circuits and Syst.—I: Fundamental Theory andApplications, vol. 41, pp. 750-754, November 1994.

228

[15] A. A. Abidi, “High-Frequency Measurements on FET’s with Small Dimensions,”IEEE Trans. on Electron Devices, vol. 33, pp. 1801-1805, November 1986.

[16] D. K. Shaeffer, T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE J.Solid-State Circuits, vol. 32, pp. 745-759, May 1997.

[17] A. N. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-StateCircuits, vol. 31, pp. 1939-1944, December 1996.

[18] H. Ronkainen, H. Kattelus, E. Tarvainen, T. Riihisaari, M. Andersson, P. Kuivalainen,“IC Compatible Planar Inductors on Silicon,” IEE Proceedings—Circuits Devices Syst., vol.144, pp. 29-35, February 1997.

[19] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. Halonen, “A Wide-Band DirectConversion Receiver for WCDMA Applications,” in ISSCC Digest of Technical Papers, pp.220-221, February 1999.

[20] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. A. I. Halonen, “A 2-GHz Wide-Band Direct Conversion Receiver for WCDMA Applications,” IEEE J. Solid-State Circuits,vol. 34, pp. 1893-1903, December 1999.

[21] C. D. Hull, J. L. Tham, R. R. Chu, “A Direct-Conversion Receiver for 900 MHz (ISMBand) Spread-Spectrum Digital Cordless Telephone,” IEEE J. Solid-State Circuits, vol. 31, pp.1955-1963, December 1996.

[22] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M.Djafari, M.-K. Ku, J. Min, E. W. Roth, A. A. Abidi, H. Samueli, “A Single-Chip 900-MHzSpread-Spectrum Wireless Tranceiver in CMOS—Part I & II,” IEEE J. Solid-StateCircuits, vol. 33, pp. 515-547, April 1998.

[23] T. B. Cho, G. Chien, F. Brianti, P. R. Gray, “A Power-Optimized CMOS BasebandChannel Filter and ADC for Cordless Applications,” in Symposium on VLSI Circuits Digest ofTechnical Papers, pp. 64-65, June 1996.

[24] A. M. Durham, J. B. Hughes, W. Redman-White, “Circuit Architectures for HighLinearity Monolithic Continuous-Time Filtering,” IEEE Trans, on Circuits and Syst.—II:Analog and Digital Signal Processing, vol. 39, pp. 651-657, September 1992.

[25] H. Khorramabadi, M. J. Tarsia, N. S. Woo, “Baseband Filters for IS-95 CDMAReceiver Applications Featuring Digital Automatic Frequency Tuning,” in ISSCC Digest ofTechnical Papers, pp. 172-173, February 1996.

[26] K. Halonen, S. Lindfors, J. Jussila, L. Siren, “A 3V gmC-Filter with On-Chip Tuningfor CDMA,” in Proceedings of the Custom Integrated Circuits Symposium, pp. 83-86, May1997.

229

[27] T. Ojanperä, R. Prasad, ed., Wideband CDMA for Third Generation MobileCommunications. Boston, London: Artech House, 1998.

[28] S. H. Lewis, P. R. Gray, “A Pipeline 5-MSample/s 9-Bit Analog-to-Digital Converter,”IEEE J. Solid-State Circuits, vol. 22, pp. 954-961, December 1987.

[29] L. Sumanen, M. Waltari, K. Halonen, “A Low Power A/D Converter for WCDMATestbed,” in Proceedings of the 16th Norchip Conf., pp. 125-130, November 1998.

[30] T. Yamaji, H. Tanimoto, H. Kokatsu, “An I/Q active balanced harmonic mixer withIM2 cancelers and a 45° phase shifter,” IEEE J. Solid-State Circuits, vol. 33, pp. 2240-2246,December 1998.

[31] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. Kivekäs, K. Halonen, “A Wide-Band Direct Conversion Receiver With On-Chip A/D Converters,” in Symposium on VLSICircuits Digest of Technical Papers, pp. 32-33, June 2000.

230