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MITSUBISHI ELECTRIC CORPORATION

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DIP-CIB EVB DPH－4646e－ Application Note

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DIPCIB evaluation board

DIP-CIB Evaluation Board

APPLICATION NOTE

POWER DEVICE WORKS



DIP-CIB EVB DPH－4646e - Application Note

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Table of Contents

CHAPTER I DIP-CIB Evaluation Board Concept ............................................................................................ 4 1.1 Applications ............................................................................................................................................ 4 1.2 Outline and Features.............................................................................................................................. 4 1.3 Product options ...................................................................................................................................... 4 1.4 Configuration.......................................................................................................................................... 5

1.4.1 Drive system configuration using DIP-CIB and HVIC/LVIC ........................................................... 5 1.4.2 Connections to the DIP-CIB evaluation board............................................................................... 6

CHAPTER II Using DIP-CIB .............................................................................................................................. 8 2.1 Introduction ............................................................................................................................................ 8 2.2 Applications ............................................................................................................................................ 9 2.3 Features................................................................................................................................................. 9 2.4 Line up ................................................................................................................................................... 9 2.5 Package Outline and Pin Description................................................................................................... 10

2.5.1 Package Outline.......................................................................................................................... 10 2.5.2 Pin Description............................................................................................................................ 10

2.6 Isolation Distance..................................................................................................................................11 2.7 Forward Surge Current and its I2t of Rectifier Diode ............................................................................ 12 2.8 R.M.S Current simulation of DIP-CIB modules..................................................................................... 12 2.9 Short Circuit Withstand Capability ........................................................................................................ 13 2.10 Determination of Gate Resistance ..................................................................................................... 14 2.11 Temperature characteristics of NTC Thermistor ................................................................................. 15 2.12 Mounting Guidance ............................................................................................................................ 16

2.12.1 Heat Sink Flatness.................................................................................................................... 16 2.12.2 Mounting torque ........................................................................................................................ 16 2.12.3 Grease Application.................................................................................................................... 16

2.13 Handling Precautions ......................................................................................................................... 17 CHAPTER III Using HVIC / LVIC to drive the DIP-CIB .................................................................................. 18

3.1 Introduction .......................................................................................................................................... 18 3.2 Features of the HVIC (M81019FP / M81721FP) .................................................................................. 18 3.3 Output driver stage and protection functions........................................................................................ 18

3.3.1 Output driver stage...................................................................................................................... 18 3.3.2 Protection circuits........................................................................................................................ 18

3.4 Input circuits of the HVIC...................................................................................................................... 20 3.5 Typical connection................................................................................................................................ 20 3.6 High side power supply（bootstrap circuit）........................................................................................ 20

3.6.1 Initial charging............................................................................................................................. 21 3.6.2 Charging and discharging of the bootstrap capacitor during inverter operation .......................... 21 3.6.3 Bootstrap circuit design............................................................................................................... 23

3.7 Wiring precautions for the protection circuit ......................................................................................... 24 3.8 Further design hints ............................................................................................................................. 25

3.8.1 Avoiding VB, Vs undershoot........................................................................................................ 25 3.8.2 Gate drive loops.......................................................................................................................... 25



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3.9 Using the LVIC (low voltage integrated circuit)..................................................................................... 25 3.9.1 Features of the LVIC (M81716FP) .............................................................................................. 25 3.9.2 Typical connection....................................................................................................................... 26 3.9.3 Paralleling the dual buffer for double output current capability.................................................... 26 3.9.4 Insertion of a pull down resistor .................................................................................................. 26 3.9.5 Noise filter for the control supply................................................................................................. 26 3.9.6 Zener diode for supply ................................................................................................................ 26

CHAPTER IV Printed Circuit Board (PCB) design........................................................................................ 27 4.1 General considerations for the PCB design ......................................................................................... 27 4.2 Top layer design ................................................................................................................................... 27 4.3 Bottom layer design ............................................................................................................................. 28 4.4 Placement diagram .............................................................................................................................. 29 4.4 Schematic ............................................................................................................................................ 30 4.5 Bill of material (BOM) ........................................................................................................................... 31

CHAPTER V ANNEX ....................................................................................................................................... 33

WARNING:

The described DIP-CIB evaluation board is linked to dangerous voltages and can generate EMI / EMC noise. The operation of the DIP-CIB is hazardous and should be performed by experienced persons only.

The DIP-CIB evaluation board is for testing purposes only. The DIP-CIB evaluation board does not comply with any safety, EMI or EMC standards.

Power loss simulation software MELCOSIM available: www.mitsubishichips.com

http://www.mitsubishichips.com/



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CHAPTER I DIP-CIB Evaluation Board Concept 1.1 Applications Industrial motor drives of up to 3.7kW, 200V/220V, 400V/440V AC line 1.2 Outline and Features

The DIP-CIB (Dual-Inline-Package-Converter-Inverter-Brake) evaluation board provides a platform for efficient testing of transfer mold DIP-CIB modules driven by a dedicated HVIC and a driver for the brake chopper IGBT. By simple connection of a 3~ AC mains voltage, a DC-link capacitor, a 15V single supply and control signals a complete power stage is realized. Fig.1 shows a photo of the DIP-CIB evaluation board with populated 3 shunt resistors and gate resistors mounted on a heat sink. The PCB contains all necessary components like half bridge high voltage integrated circuit (HVIC) to drive and to protect the IGBTs, a low voltage integrated circuit (LVIC) for brake IGBT driving, a simple bootstrap circuit to provide a floating supply voltage for the P-side IGBT, space for 3 shunts to allow a detection of the individual N-side emitter current as well as for the short circuit (SC) detection. The printed circuit board (PCB) layout realizes a low inductive interface between the on board DC-link snubber capacitor and the high voltage supply of the IGBT. All power connections for the AC voltage input, the DC-link electrolytic capacitors, the brake circuit and the 3~ motor outputs are established by simple 6.3mm FASTON type connectors. The low voltage (15V) power supply and control signals are applied to a single row 2.54mm pitched pin header. The heat sink in the shown photo has been designed to achieve sufficient creepage and clearance distances. Using the shown configuration including a fan, a continuous output power of 5,5kW was realized during laboratory tests.

1.3 Product options

Table 1: Product Line-ups of DIP-CIB and LVIC / HVIC for different motor ratings LVIC Type

Name HVIC Type

Name DIP-CIB Type

Name IGBT Rating

(IC /VCES) Estimated

Motor Rating Isolation

M81716FP M81019FP CP10TD1-24A 10A / 1200V 1.5kW / 440VAC M81716FP M81019FP CP15TD1-24A 15A / 1200V 2.2kW / 440VAC M81716FP M81019FP CP25TD1-24A 25A / 1200V 3.7kW / 440VAC M81716FP M81721FP CP20TD1-12A 20A / 600V 2.2kW / 220VAC M81716FP M81721FP CP30TD1-12A 30A / 600V 3.7kW / 220VAC

Viso = 2500Vrms(Sinusoidal,

1min)

Note: The motor ratings represent general motor power capacities for general-purpose inverter application. The available motor output power may be different from the above one for different application conditions.

Fig.1 DIP-CIB drive system demo kit



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1.4 Configuration 1.4.1 Drive system configuration using DIP-CIB and HVIC/LVIC



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The block diagram shows a simple evaluation circuit for the DIP-CIB and the HVIC / LVIC. In this diagram the references of the components have been chosen to specify the type of component: D1: Bootstrap fast recovery diode 1A D2: Zener diode for surge voltage suppression R1: Filter capacitor R2: Fault output (FO) pull up resistor R3: LVIC pull down resistor R4: Bootstrap charging resistor Rs: Shunt resistor for short circuit (SC) detection C1: Electrolytic capacitor for bootstrap circuit C2: Ceramic capacitor for bootstrap circuit C3: Ceramic capacitor for HF blocking of the 15V supply C4: Ceramic capacitor for fault output noise suppression Rg(on): Turn on gate resistor Rg(off): Turn off gate resistor The selection criteria for these components are explained in the corresponding chapters. An inrush current limitation circuit is not shown in the diagram. It is recommended to use the evaluation board in an isolated, current limited and well-protected environment only. 1.4.2 Connections to the DIP-CIB evaluation board

Figure 1.4.2.1: Fully populated PCB (incl. Rg(on), Rg(off) and 3 shunt resistors) The DIP-CIB evaluation board is delivered without the gate resistors for turn-on and turn-off. The suitable

INRUSH current limiter

Brake resistor

DC-link capacitor

3~ mains input M 3~ motor

output

MCU / DSP

control signal and 15V

power supply


DIP-CIB EVB DPH-4646e- Application Note

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selection of Rg for each DIP-CIB module rating under specific application conditions is explained in chapter 2.10. On the PCB there is space for a standard chip type SMD resistor of “1206” size or MELF type. The influence of the gate resistor value selection on power loss and dI/dt is shown in chapter II. The SMD shunt for each phase is sized “2817”. The value can be determined by the following equation considering the short circuit (SC) comparator input of the dedicated HVIC of 0.5V (typ.) and a recommended SC detection level of 1.7 time the rated current of the DIP-CIB module:

shuntratedCSC

SC RItypV

IV

≈⋅

=,7.1

.)(5.0

Selecting a shunt resistor under these conditions will ensure low stress on the IGBT under SC- conditions As an example the suitable value for the shunt resistor for the CP25TD1-24A would be selected as 12mΩ following above equation.



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CHAPTER II Using DIP-CIB 2.1 Introduction The DIP-CIB is a cost-effective transfer mold type Converter-Inverter-Brake (CIB) module developed for low power industrial use. By employing the latest Mitsubishi power chips CSTBTTM and the advanced bonding and packaging technologies, the DIP-CIB series achieves excellent electric and thermal dissipation characteristics, offering a highly reliable solution for variable speed motor drive applications. DIP-CIB series have been developed in a dual in-line transfer molded package dedicated for mounting and direct PCB connection (Fig.2-1). Its internal circuitry consists of a three-phase diode rectifier bridge, a three-phase inverter circuit, a brake chopper circuit and a NTC thermistor, providing standard three-phase AC-to-AC conversion together with temperature detection (Fig.2-3). The power rating is ranged from 10A to 25A in 1200V class and 20A to 30A in 600V class. The entire DIP-CIB is a complete lead free product complying with the RoHS directive.

Fig.2-1 DIP-CIB photograph with embedded aluminum heat spreader Figure 2-2 shows a cross section through the DIP-CIB lead frame construction. A significantly improved heat transfer was achieved by utilizing a dedicated “Insulated heat dissipation sheet”. This special material features high thermal conductivity paired with high dielectric withstands capability. All bare chips are soldered directly on the lead frame and bonded with aluminum wire

Fig.2-2 Cross-section of internal structure

Mold resin

Cu frame

IGBTFWDAl wire

Aｌ heat sinkInsulated heat dissipation sheet

CNV-Di



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Fig.2-3 Internal circuit topology

P1 P

R S T

N1 N(B) UN U VN V WN W TH1 TH2

B

GB

GUP

EUP

GUN

Converter Brake Inverter NT

GVP

EVP

GVN

GWP

EWP

GWN

NTC

2.2 Applications General-purpose inverter, servo, and other low power industrial motor drives. 2.3 Features

① Low loss and high short circuit withstand capability by using Mitsubishi advanced CSTBTTM (Carrier Stored Trench-gate Bipolar Transistor) chips.

② Low loss and high surge current withstand capability converter diode. ③ Thin Dual In-line Package with dedicated pin arrangement simplifying the PCB layout. ④ Complete lead free bonding and plating technology complying with RoHS directive. ⑤ Excellent thermal dissipation structure provides lower thermal impedance. ⑥ NTC thermistor provides means for over temperature protection. ⑦ Low side open emitter structure offers means for low cost phase current detecting.

2.4 Line up

Table 2-1. DIP-CIB Product Line-up Device rating Type name Rectifier Inverter Brake

Matching motor rating

Isolation voltage

CP10TD1-24A 10A/1600V 10A/1200V 10A/1200V 1.5 kW / 440VAC CP15TD1-24A 15A/1600V 15A/1200V 10A/1200V 2.2 kW / 440VAC CP25TD1-24A 25A/1600V 25A/1200V 15A/1200V 3.7 kW / 440VAC CP20TD1-12A 20A/800V 20A/600V 10A/600V 1.5 kW / 220VAC CP30TD1-12A 30A/800V 30A/600V 15A/600V 2.2 kW / 220VAC

2500Vrms (Sinusoidal,

1min)

※The motor rating is just a rough matching to the DIP-CIB current rating by considering 150% overload of general purpose inverter drive.



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2.5 Package Outline and Pin Description 2.5.1 Package Outline

Fig.2-4 DIP-CIB package outline

2.5.2 Pin Description

Table 2-2 Pin description Pin No. Pin code Description

1 TH1 NTC thermistor terminal 1 2 TH2 NTC thermistor terminal 2 3 P1 Converter output positive terminal 4 P DC-link positive terminal 5 GUP High side U-phase IGBT gate terminal 6 EUP High side U-phase IGBT emitter terminal 7 GVP High side V-phase IGBT gate terminal 8 EVP High side V-phase IGBT emitter terminal 9 GWP High side W-phase IGBT gate terminal

10 EWP High side W-phase IGBT emitter terminal 11 GB Brake IGBT gate terminal 12 (N)B Brake IGBT emitter terminal 13 B Brake IGBT collector terminal 14 R AC line input terminal 15 S AC line input terminal 16 T AC line input terminal 17 N1 Converter output negative terminal 18 GUN Low side U-phase IGBT gate terminal



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19 EUN Low side U-phase IGBT emitter terminal 20 GVN Low side V-phase IGBT gate terminal 21 EVN Low side V-phase IGBT emitter terminal 22 GWN Low side W-phase IGBT gate terminal 23 EWN Low side W-phase IGBT emitter terminal 24 U U-phase output terminal 25 V V-phase output terminal 26 W W-phase output terminal

2.6 Isolation Distance The minimum clearance between lead pins and heat sink of DIP-CIB is 2.3mm if a flat shaped heat sink is used. A creepage distance of 12.7mm can be reached by optimizing the shape of the heat sink. In order to increase the electric clearance between lead pins and the heat sink, a heat sink with “convex” shape as shown in Fig.2-5a should be used. Fig.2-5b shows the practical heat sink shape used with the evaluation board. The height of the convex depends on the regulation requirement that your inverter set is to be applied. For example, the minimum clearance required by UL840 is 5.5mm; therefore the “convex” height should be at least 3.2mm.

Table 2-3 Minimum Electric Distance (Over voltage category: III, Pollution degree: II, Material CTI group: II, Working voltage: 500Vrms) Standard Clearance distance (mm) Creepage distance (mm)

UL840 5.5 3.6 IEC61800-5-1 5.5 3.6

(DIP-CIB) 2.3 + α (between pin and heat sink) α is shown in Fig 2-5a

12.7 (between pin and heat sink)

DIP-CIB min.2.3mm

min.12.7mm To ensure enough clearance, an additional electric space is necessary here. The length depends on the requirement of the applied standard

Fig.2-5a (left): Insulation distance and “convex” heat sink shape

Fig.2-5b (right): example of a heat sink shape realizing max. clearance distance

The insulation between NTC and main circuit is considered to be only a basic insulation. Therefore, the NTC cannot be treated as a part of a safety / protective extra low voltage (PELV or SELV) circuit of a power drive system (PDS) as defined by IEC61800-5-1, which requires reinforced insulation or a basic insulation plus a supplementary insulation.

α

DIP-CIB



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2.7 Forward Surge Current and its I2t of Rectifier Diode

The Forward Surge Current IFSM and its I2t of Rectifier Diode are shown in Table 2-4, and the Fig.2-6 shows an example of their time characteristics of CP10TD1-24A.

Table 2-4 Rectifier diode IFSM and I2t

(Condition: Peak value of 1/2 cycle at 60Hz sine wave, non-repetitive)

CP10TD1-24A CP15TD1-24A CP25TD1-24A CP20TD1-12A CP30TD1-12A IFSM (A) 200 245 315 245 315 I2t (A2s) 168 252 416 252 416

0

100

200

300

400

500

600

700

0.1 1 10 100Time (ms)

I FSM (A

)

Fig.2-6 Time characteristics of the forward surge current and I2t (typ. of CP10TD1-24A)

2.8 R.M.S Current simulation of DIP-CIB modules Fig.2-7 and 2-8 show the available r.m.s current of 1200V/600V DIP-CIB based on the power loss and temperature rise simulation, respectively. Limiting the peak value of the output current under device rating is recommended. Simulation conditions:

For 1200V CIB: VCC=600V, VGE=±15V, Tj=125, Tc=100, RG=spec. min., Rth(j-c)=spec. max., P.F=0.8, sine PWM, output current 50/60Hz

0

2

4

6

8

10

12

14

16

18

20

0 5 10 15 20 25Carrier frequency fc (kHz)

Out

put c

urre

nt Io

(Arm

s)

CP25TD1-24A

CP15TD1-24A

CP10TD1-24A

Fig.2-7 Current carrying capability of 1200V DIP-CIB

0

20

40

60

80

100

120

140

160

180

200

0.1 1 10 100Time (ms)

I2 t (A

2 s)



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For 600V CIB: VCC=300V, VGE=±15V, Tj=125, Tc=100, RG=spec. min., Rth(j-c)=spec. max., P.F=0.8, sine PWM, output current 50/60Hz

0

5

10

15

20

25

0 5 10 15 20 25Carrier frequency fc (kHz)

Out

put c

urre

nt Io

(Arm

s)

CP20TD1-12A

CP30TD1-12A

Fig.2-8 Current carrying capability of 600V DIP-CIB

The latest data and information are available on the web: www.mitsubishichips.com Please check also the latest power loss simulation tool MELCOSIM for a power loss calculation under specific application conditions

2.9 Short Circuit Withstand Capability The IGBT chips inside the DIP-CIB can withstand a 10μs lasting short circuit condition without damage under normal 15V gate drive. Please shutdown the DIP-CIB within 10μs in case of a short circuit failure. Fig.2-9 shows the dependence of the bearable maximum collector current upon the short circuit time with regarding to the gate-emitter voltage of CP10TD1-24A. ※When using Mitsubishi HVIC M81019FP / M81721FP for DIP-CIB gate drive, the HVIC internal short-circuit (SC) protection circuit can shutdown an SC IGBT within 3usec.

0

20

40

60

80

100

120

0 2 4 6 8 10 12 14 16Input pulse width tw (µs)

Sho

rt ci

rcui

t cur

rent

Isc

(A)

CP10TD1-24AVcc=800VTj=125（start）RG=33Ω-VGE=-10V

+VGE=18.5V

16.5V

15V13.5V

Fig.2-9 Short circuit withstand capability of CP10TD1-24A (typical)

http://www.mitsubishichips.com/



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DIP-CIB Evaluation Board 2.10 Determination of Gate Resistance

The gate resistance greatly affects the inverter switching performance. A small resistance leads to fast switching, low power loss and high dv/dt, and a large resistance results in slow switching, high power loss and low dv/dt. Besides the consideration of the trade-off between power loss and dv/dt, the following items should also be taken into account when determining the gate resistance.

Based on the CSTBT / FwDi electrical properties the minimum gate resistance for the DIP-CIB modules is calculated by the following formula.

deviceclassVforAIAR

deviceclassVforAIAR

ratingCG

ratingCG

1200)()(313

600)()(625

)((min)

)((min)

⋅Ω=

⋅Ω=

The considerations of the lower limit of the gate resistance:

① Does not cause breakdown within RB-SOA ② Does not cause breakdown within guaranteed SC-SOA ③ dI/dt does not cause FWD failure ④ Surge voltage will not exceed device voltage rating ⑤ No distinct shape distortion of the switching waveform (EMI/EMC) ⑥ The gate current does not exceed the maximum rating of the gate driver

The considerations of the upper limit of the gate resistance:

① Does not cause gate voltage oscillation ② Does not cause large tolerance of the turn off switching time ③ The delay of the switching time does not exceed dead time permission and cause arm

shoot-through ④ The increased power loss and temperature rise will not reduce the device current carrying

capability.

According to the switching performance shown in Fig.2-10 and Fig.2-11, it is possible to get a better compromise between the power loss and switching dv/dt and turn off time by selecting different resistances for turn on and turn off operation.

0.0

1.0

2.0

3.0

4.0

0 50 100 150 200 250 300 350RG (Ω)

Sw

itchin

g lo

ss

(mJ/pu

lse)

Eoff

Eon

Err

Tj=125Vcc=600VVGE=±15VIc=10A

Fig.2-10 Dependency of switching loss on gate resistance (typical for CP10TD1-24A)



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-10

-8

-6

-4

-2

0

0 50 100 150 200 250 300 350

RG (Ω)

dv/d

t (k

V/us

)

Tj=25

Tj=125

0

2

4

6

8

10

0 50 100 150 200 250 300 350

RG (Ω)

dv/d

t (k

V/us

) Tj=25

Tj=125

Turn on Turn off dv/dt

Fig.2-11 Dependency of max. dv/dt on gate resistance of CP10TD1-24A (typical)

2.11 Temperature characteristics of NTC Thermistor Fig. 2-12 shows the temperature characteristics of the NTC thermistor, the tolerance of the NTC resistance is ±5% at Tc=100.

0

1

2

3

4

5

6

7

8

9

10

25 50 75 100 125Temperature ()

Res

ista

nce

(kΩ

)

0.5

1.0

1.5

2.0

2.5

75 100 125Temperature ()

Res

ista

nce

(kΩ

)

Min.Nom.Max.

10595

Fig.2-12 Temperature characteristics of the NTC thermistor Thermistor resistance Rx at an arbitrary temperature Tx (K) can be calculated by the formula

)]11(exp[25

)100/25(25 TTBRR

XX −⋅⋅=

Where R25 (=10kΩ) is the resistance at Tc=25°C, T25=298K, B(25/100)=3450K.



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2.12 Mounting Guidance 2.12.1 Heat Sink Flatness

The flatness of DIP-CIB case surface is -50～+100μm. Therefore, the external heat sink should provide the same flatness.

Heat sink contact area

DIP-CIB

＋

＋－

－

Heat sink

Heat sink

Measurement line

Silicone grease applied

DIP-CIB

Heat sink flatness area

＋－

Fig.2-13 Definition of DIP-CIB case flatness Fig2-14 Definition of heat sink flatness

2.12.2 Mounting torque A torque-controllable screwdriver to mount DIP-CIB in two steps is used to mount the DIP-CIB correctly. In the first step, use 20～30% of the recommended torque (1.18N·m · 25% = 0.29N·m) for a temporary mounting, while in the second step, the recommended torque (1.18N·m) is applied for a permanent mounting in the same order as the primary one, as shown in Fig.2-15. A correct mounting will provide better contact with minimum contacting thermal resistance and sufficient ruggedness against mechanical vibration and shock in a long-term operation. Excessive torque or unbalanced mounting will apply unwanted stress to the package structure and its contained power chips possibly leading to a degradation of electric characteristics or package cracks or early failure.

Table 2-5 Mounting torque specifications Item Condition Min. Typ. Max. Unit

Mounting torque Recommended 1.18N・m Mounting screw : M4 0.98 1.18 1.47 N･m

Note： Generally, the temporary fastening torque is 20～30% of the maximum torque rating.

Fig.2-15 DIP-CIB mounting guidance

2.12.3 Grease Application Evenly applying thermally-conductive grease with 100um～200um thickness over the heat sink contact surface of the module will ensure good thermal contact and the a proper thermal dissipation of the module. Thermal grease can also prevent the contact surface from corrosion. High quality thermal grease should be selected ensuring a long-term stable thermal interface within a wide operating temperature range. Abundant grease after the mounting process should be removed.

Mounting order Temporary mount: ① → ② Permanent mount: ① → ②

DIP-CIB



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Silicone grease G-746 made by Shin-Etsu Polymer Co., Ltd. and YG6260 made by GE-Toshiba Silicones are recommended thermal grease types. Having same or better performance any other thermal grease can be used.

2.13 Handling Precautions

Transportation ・Put package boxes in the correct direction. Putting them upside down, leaning them or giving them uneven stress might cause electrode terminals to be deformed or resin case to be damaged.

・Throwing or dropping the packaging boxes might cause the devices to be damaged. ・Wetting the packaging boxes might cause the breakdown of devices when operating. Pay attention not to wet them when transporting on a rainy or a snowy day.

Storage ・We recommend room temperature and humidity in the ranges 5～35 and 45～75％, respectively, for the storage of modules. The quality or reliability of the modules might decline if the storage conditions are much different from the above.

Long storage ・When storing modules for a long time (more than one year), keep them dry. Also, when using them after long storage, make sure that there is no visible flaw, stain or rust, etc. on their exterior.

Surroundings ・Keep modules away from places where water or organic solvent may attach to them directly or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They might cause serious problems.

Disposal ・The epoxy resin and the case materials are made of approved products in the UL standard 94-V0, still they are incombustible.

Static electricity ・Exclusive ICs of MOS gate structure are used for the DIP-IPM power modules. Please keep the following notices to prevent modules from being damaged by static electricity.

（1）Notice of breakdown by static electricity Excessively high voltage (over the Max. rated input terminal voltage) resulting from the static electricity of human bodies and packaging materials might cause the modules to be damaged if applied on the control terminals. For countermeasures against static breakdown, it is important to control the static electricity as much as possible and when it exists, discharge it as soon as possible.

* Do not use containers that are easy to be electro-statically charged during transportation.

* Be sure to short the control terminals with carbon cloth, etc. just before using the module. Also, do not touch between the terminals with bare hands.

* During assembly (after removing the carbon cloth, etc.), earth machines used and human bodies. We suggest putting a conductive mat on the surface of the operating table and the surrounding floor.

* When the terminals on the printed circuit board with mounted modules are open, the modules might be damaged by static electricity on the printed circuit board.

* When using a soldering iron, earth its tip. （2）Notice when the control terminals are open * When the control terminals are open, do not apply voltage between the collector and

emitter. * Short the terminals before taking a module off.



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CHAPTER III Using HVIC / LVIC to drive the DIP-CIB 3.1 Introduction The purpose of this chapter is to explain the highlights of HVIC/LVIC to drive the DIP-CIB efficiently and well protected in motor drive applications. 3.2 Features of the HVIC (M81019FP / M81721FP) Floating supply voltage up to 1200V(M81019FP) / 600V(M81721FP) with low leak current

(less than 1uA) Low quiescent power supply current Separate sink and source output for dedicated RG,on and RG,off (current (±1A)) Active miller clamp NMOS with sink current up to –1A Input signal filter Over-current detection and output shutdown FO input and output Fault signals (bi-directional communication) High side under voltage lockout Designed originally for DIP-CIB

3.3 Output driver stage and protection functions 3.3.1 Output driver stage The structure of the output driver stage is shown in figure 3-3-1. This circuit structure employs a solution for the problem of the Miller current through Cres in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to increase the safety margin, this circuit structure uses a NMOS to establish a low impedance path to prevent the self-turn-on due to the parasitic Miller capacitor in conjunction with dV/dt.

Cres

Cies

VBS/VCC

VS/VNO

VIN=0(from HIN/LIN)

VOUT

Figure 3-3-1 the structure of output driver stage

When HIN/LIN is at low level and the voltage of VOUT (IGBT gate voltage) is below the active Miller effect clamp NMOS input threshold Voltage, the active Miller effect clamp NMOS is being turned on and offers a low resistive path for the Miller current through Cres. Even the voltage of the VOUT is higher than active Miller effect clamp NMOS input threshold but the duration doesn’t exceed active Miller clamp NMOS filter time, active Miller effect clamp NMOS structure in the driver would not turn-off. 3.3.2 Protection circuits The HVIC is designed for the DIP-CIB and provides useful protection features for DIP-CIB modules.

Active Miller Effect Clamp NMOS

dV/dt



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LogicFilter

UV

PulseGenerator Interlock

&Noise Filter

VREG

ProtectionLogic

Vref

VregVCC

－

＋

Vref

Filter

VB

HPOUTHNOUT1HNOUT2

VS

VCC

LPOUT

LNOUT2

VNO

LNOUT1

FO

GND

HIN

LIN

CIN

FO_RST Filter

Figure 3-3-2 the block diagram of HVIC (1). High side VBS supply under voltage lockout When the VBS supply voltage drops below the VBS supply UV trip voltage and the duration of this condition exceeds the VBS supply UV filter time, the output of the high side is locked. As soon as the VBS supply voltage rises above the VBS supply UV reset voltage, the output will respond to the following active HIN signal. (2). Input interlock circuit When the input signals (HIN/LIN) are high level at the same time, the outputs (HOUT, LOUT) keep their previous status. But if signals (HIN/LIN) are going to high level simultaneously, HIN signals will get active and cause output of high side to enter "H" status. If a high-high status of input signals (HIN/LIN) is ended with only one input signal entering low level and another still being in high level, the output will enter high-low status after the delay matching time. (3). Short circuit protection timing diagram When an over-current is detected by exceeding the threshold of the internal comparator at the CIN terminal and LIN is at high level at the same time, the short circuit protection will get active and shutdown the outputs while the fault output FO will issue a low level (indicating a fault signal). The fault output latch is reset by a high level signal at the fault output reset terminal FO_RST. The FO will return to high level while the output of the driver will respond to the following active input signal. (4). FO input timing diagram When FO is pulled down to low level in case the FO of other phases becomes low level (fault happened) or the MCU/DSP sets FO to low level, the outputs (HOUT, LOUT) of the driver will be shut down. As soon as FO goes high again, the output will respond to the following active input signal. The FO pin can be used to communicate with controllers and synchronize the shut down with other phases. (5). Low side VCC supply power reset When the VCC supply voltage is lower than the power reset trip voltage, the power reset gets active and the outputs (HOUT/LOUT) become "L". As soon as the VCC supply voltage rises higher than the power reset trip voltage, the outputs will respond to the next active input signals.



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DIP-CIB Evaluation Board 3.4 Input circuits of the HVIC The HVIC for DIP-CIB adopts high active input logic. A minimum 3kΩ pull-down resistor is built-in into each input circuit of the HVIC as shown in Fig. 3-4-1; hence, an external pull-down resistor is not required.

Figure 3-4-1. Internal structure of control input terminals

3.5 Typical connection

HVIC DC BUSVoltage

Rshunt

Vout

VNO

DC-

VBVCC

Rboot Dboot

Cboot

DC+

VS

HPOUTHNOUT1HNOUT２

LPOUTLNOUT1LNOUT２

GND

CIN

RCIN

CCIN

FO

HINLINFO_RST

MCU/DSPController

OtherPhases

15VHOUT

LOUT

5V~15V

RGON

RGON

RGOFF

RGOFF

RFO

CFO

Figure 3-5-1. Typical connection of HVIC

Note1. If the HVIC is working in a high noise environment, it is recommended to connect a 1nF ceramic capacitor (CFO)

close to the FO pin. Note2. The FO output is an open drain type. This signal line should be pulled up to the positive side of a 5V supply with

an approximate 10kΩ resistor. 3.6 High side power supply（bootstrap circuit） As shown in Figure 3-5-1, the bootstrap circuit is formed by a capacitor (Cboot) between VB terminal and VS

HIN, LIN FO_RST

HVIC

3KΩ(min.)



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terminal and an arrangement of a resistor (Rboot) and a diode (Dboot) between Vcc terminal and VB terminal. 3.6.1 Initial charging

HVIC

High-sideDriver

Low-sideDriver

DC BUSVoltage

Rshunt

VS

Vout

Inductive Load

VNO

GND

VB

VCC

Rboot Dboot

Cboot

VB

HIN

LIN

LOUT

FO

VCC

DC bus voltage

PWM Start

Fig 3-6-1. Charging current loop and timing chart of bootstrap circuit In order to start the DIP-CIB system, an initial bootstrap charging is necessary. By turning on the N-side IGBT, as shown in Fig 3-6-1, the bootstrap capacitor will be charged. The pulse width or pulse number should be large enough to ensure sufficient charging of the bootstrap capacitor before operating the system with load. 3.6.2 Charging and discharging of the bootstrap capacitor during inverter operation

VS

VB

C1R1

M1

Q1

R1

VCC

D1 IGBT1

IGBT2

FWD1

FWD2

P

M

N

ID

HVIC

Fig 3-6-2. Inverter circuit diagram

(1). Charging operation timing chart of bootstrap capacitor (C1) When the N-side is in ON state, e.g. either the IGBT2 is conducting or the current flows through the anti-parallel FwD2 of the IGBT, the charging voltage on C1 (VC1) is calculated by

VC1 = VCC – VF(D1) – V(IGBT2/FWD2) - ID･R1 a. Sequence 1: IGBT2 ON (Figure 3-6-3)



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While IGBT1 is in ON state, the voltage of C1 gradually declines from the potential VC1 due to the current consumed by the drive circuit.

IGBT1

ON

OFF

IGBT2

ON

OFF

Potential of C1

VC1

VS

VC1

Spontaneous discharge of C1

Declining due to currentconsumed by drive circuit

Figure 3-6-3. Timing chart of sequence 1

b. Sequence 2: FWD2 conducting (Figure 3-6-4) The freewheeling current flows continuously through FWD2 and adds a negative voltage in above equation for the charging voltage of C1. Therefore the potential of VS drops to -VEC2, and then C1 is recharged to restore the declined potential.

IGBT1

ON

OFF

IGBT2

ON

OFF

Potential of C1

VC1

VS

VC1 Declining due to currentconsumed by drive circuit

Figure 3-6-4. Timing chart of sequence 2

(2). Guidance for the selection of the bootstrap capacitor (C1) and resistance (R1) The capacitance of bootstrap capacitor can be calculated by:

C1=IBSxT1/ ∆V

where T1 is the maximum ON pulse width of IGBT1 and IBS is the drive current of the HVIC (depends on temperature and frequency characteristics), and ∆V is the allowable discharge voltage. A certain margin should be added to the calculated capacitance. Resistance R1 should be basically selected such that the time constant C1･R1 will enable the discharged voltage (∆V) to be fully charged again within the minimum ON pulse width (T2) of IGBT2.



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However, if only IGBT1 has an ON－OFF－ON control mode (Figure 3-6-5), the time constant should be set so that the consumed energy during the ON period can be charged during the OFF period.

Declining due to current consumed by drive circuit

IGBT1

ON

OFF

IGBT2

ON

OFF

Potential of C1

Vc1

VS

Charging area

Figure 3-6-5. Timing Chart of ON－OFF－ON Control Mode

3.6.3 Bootstrap circuit design (1). Selection of the bootstrap capacitor Condition: VBS drop less than 1.5V, for example, ∆VBS (discharged voltage)=1V, the maximum ON pulse width T1 of P-side IGBT is 5ms, IBS is 1.2mA(Max. Rating), then

C=IBSxT1/∆VBS=6.0x10-6 The calculated bootstrap capacitance is 6.0uF. By taking into consideration the degradation of electrolytic capacitors, the capacitance is generally selected to be not less than 2～3 times of the calculated one. (2). Selection of the bootstrap resistor Condition: The value of bootstrap capacitor is 20uF, VCC=15V, VBS=14V. If the minimum ON pulse width t0 of N-side IGBT or the minimum OFF pulse width t0 of upper-side IGBT is 100us, bootstrap capacitor needs to be charged ∆V BS=1V during this period, then,

R=(VCC - VBS) xt0 / (C x ∆V BS)=5 The proposed bootstrap resistor would be 5Ω. Note 1. In the case of the control for DCBLM (brushless DC motors) or 2-phase modulation for IM (Induction Motor) at startup, there will be a long ON time period on the P-side IGBT, please pay attention to the bootstrap supply voltage drop. Note 2. The above results are only a calculation example. It is recommended that you design a system by taking consideration the actual control strategy and lifetime of components. (3). Selection of the bootstrap diode The bootstrap diode with a withstand voltage more than 600V/1200V is recommended for this circuit. The bootstrap diode should be fast recovery, low Qrr type having a recovery time of less than 100ns. (4). Noise filter for control supply It is recommended to insert a Low ESR ceramic type capacitor 0.22～2uF(paralleling electrolytic and low ESR ceramic may result in a efficient solution) to the control supply terminals. The smaller the supply parasitic impedance is, the smaller a feasible noise filter capacitance can be. The supply circuit should be such designed that the noise fluctuation is less than ±1V/μs, and the ripple voltage is less than ±2V. (5). Zener diode for supply



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To prevent HVIC from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between VB/VCC and VS/GND terminals. 3.7 Wiring precautions for the protection circuit

The proper operation of the protection function is closely related to the parasitic effects of a real PCB layout such as the inductance of a routed track, and the resistive voltage drop due to thickness of the Cu- layer and the width of the track itself. Several influences should be considered:

WN VN UN

C

GND

CIN

A

P

N1

VNO

D

RCIN

Rshunt

DIP-CIB

DC-bus current route

SC protection External Parts

B

CCIN

HVIC for phase U

Figure 3-7-1 Short circuit protection circuit

A. Influence of the part-A wiring pattern

The ground of the Low-side IGBT gate is VNO. If part-A wiring pattern in Figure 3.7 is too long, a large voltage fluctuation occurs due to the wiring inductance, which results in the variation of the IGBT’s emitter potential during switching operation. Please install a shunt resistor as close to the N terminal as possible.

B. Influence of the part-B wiring pattern

The part-B wiring affects the SC (short circuit) protection level. The SC protection works by judging the voltage across the CIN-GND (typ.0.5V) terminals. If part-B wiring is too long, a surge voltage will occur easily due to the wiring inductance. Hence leads to a deterioration of the SC protection level. It is necessary to connect CIN and GND directly to the two ends of shunt resistor and avoid the part-B wiring area.

C. Influence of the part-C wiring pattern

A RCIN / CCIN filter is added to remove noise influence occurring on the shunt resistor. The filter effect will

become small and noise will easily be imposed on the wiring if the part-C wiring is too long. Please install the RCIN / CCIN filter near CIN, GND terminal as close as possible.

D. Influence of the part-D wiring pattern



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The part-D wiring pattern has an influence on all the items described in above item A～C. Therefore the GND wiring should be as short as possible using large Cupper tracks on the PCB.

3.8 Further design hints 3.8.1 Avoiding VB, Vs undershoot

HVIC

High-sideDriver

Low-sideDriver

DC BUSVoltage

Rshunt

VS

Vout

Inductive Load

ParasiticResistor

Inductive Parasitic elements

VNO

GND

Inductive Parasitic elements

VB

VCC

Rboot Dboot

Cboot

Figure 3-8-1 the mechanism of VB and Vs undershoot GND Figure 3-8-1 shows the transition when the high side IGBT is turned off and the low side freewheel diode starts to take over the load current. The occurring dI/dt in conjunction with the parasitic inductances shown in figure 3-8-1 induce a voltage which forces the Vs potential to drop below GND level. Depending on the level of this voltage, VB may also fall below GND. In such a case a current could float from GND to VB through the parasitic diodes between drain and source of the high voltage MOS structure built in as the key element of the level shifting circuit. As soon as VB returns to a positive potential, a recovery current of the parasitic diodes floats from VB to GND. This effect is a potential reason for the malfunction “latching” of a HVIC. Hence a special structure using unique patented logic filters can prevent from a malfunction. Moreover too high VB, Vs undershoot could even destroy the HVIC for high current would float from GND to high side by the parasitic diode between VB and GND. 3.8.2 Gate drive loops Gate drive loops must be reduced as much as possible to reduce EM coupling and improve the turn-on and turn-off performances. Traces between HVIC and the IGBT should be kept as short as possible 3.9 Using the LVIC (low voltage integrated circuit) 3.9.1 Features of the LVIC (M81716FP) OUTPUT CURRENT・・・+0.8A,-0.6A DUAL BUFFER Easy paralleling



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3.9.2 Typical connection

M81716FPINA

INB

OUT A

OUT B

VDD

GND

High voltage

Brake IGBTIn DIP-CIB

From MCURgate

Rpulldown

Figure 3-9-1. Typical connection of LVIC

3.9.3 Paralleling the dual buffer for double output current capability It is recommended to parallel the dual buffer inside the LVIC for full current capability as shown in figure 3-9-1. 3.9.4 Insertion of a pull down resistor The LVIC doesn't have a pull-down resistor. Therefore it is recommended to add a pull-down resistor of approximately 5kΩ at input terminals INA and INB. 3.9.5 Noise filter for the control supply It is recommended to insert a Low ESR ceramic type capacitor 0.22～2uF(paralleling electrolytic and low ESR ceramic may result in an efficient solution) to the control supply terminals. 3.9.6 Zener diode for supply To prevent the LVIC from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between VDD and GND terminals.



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CHAPTER IV Printed Circuit Board (PCB) design

4.1 General considerations for the PCB design The PCB of the DIP-CIB evaluation board is a double layer board with an average cupper thickness of 35µm on each layer. The efficient design of the power stage and the control signal interface - realizing the design targets of low inductive connections and no crossing of signal and high voltage traces - on only two layers became possible by the matching pin terminal layout of the HVIC and the DIP-CIB. Large ground planes were realized on both layers. For wide temperature range and robustness for the soldering process a FR4 epoxy based material has been chosen. All components except the DIP-CIB itself have been placed from the top “component” side for simple manufacturing. Besides the pads for components there are various test pads on the PCB top layer to perform a fully functional (high voltage motor drive) test of the board before shipping. 4.2 Top layer design The design of the top layer (Cu traces in red color) contains the majority of the connections between the surface mounted components and the connections between SMT components and power components. In light blue color the creepage distance extending milling profile is indicated for reference, too. A part of the silk screen for component placement information is shown in this view to ease the orientation.

Bootstrap area and P-sidedriver to IGBT interface

N-bus traces

N-side driver to IGBTinterface and CR filter

Snubber capacitor



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4.3 Bottom layer design The design of the bottom layer (shown as blue traces) establishes the connections between the HVIC’s control inputs and outputs and the pinheader for control signals. A second large ground plane can be observed in this layer, too. In order to improve the conductivity of the ground plane the solder stop layer was removed for this area. Thus this special trace extends to the Emitter of the braking IGBT and can be easily identified by its shiny solder coated surface appearance.

On the bottom layer the connections between the power terminals of the DIP-CIB of the 3~ input, the output, the DC-link connection and the brake IGBT outputs are realized.

Traces of the control signal interface

Ground plane (N-bus)



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4.4 Placement diagram The placement diagram indicates the position of components placed from top and bottom side of the PCB, their reference according to the bill of material (BOM) and their orientation in case of diodes, electrolytic capacitors and integrated circuits, test points (TP) and the holes for the mounting of through hole components. The following resistors (1206 / MELF) are not placed: R4,R10, R14,R15, R16, R17, R18, R19, R20, R21, R22 and R23. The following resistors (2817) are not placed: R1, R2, R3. The DIP CIB is not placed. After determination of the right type / size of module as discussed in chapter II, the DIP-CIB should be placed from the bottom side and should be soldered from the top side respecting the usual handling precautions for ESD sensitive components.

The pin assignment of JP1, the control signal terminal, is printed on the PCB silk screen (placement layer). The placement diagram references to components shown in the schematic (ref: chapter 4.5) and the bill of material (BOM) (ref: chapter 4.6).



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4.4 Schematic



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4.5 Bill of material (BOM) Part Value Package / comment C1 100nF 0805 C2 100nF 0805 C3 100nF 0805 C4 47µF/25V SMD-C-6 C5 47µF/25V SMD-C-6 C6 47µF/25V SMD-C-6 C7 100nF 0805 C8 1nF 0805 C9 1nF 0805 C10 47µF/25V SMD-C-6 C11 1nF 0805 C12 100nF 0805 C13 10nF 0805 C14 100nF 0805 C15 100nF 0805 C20 0,15µF..0,22µF/1250V C27,5B15 D4 Z24/1,3W SMA D8 SF1200/STTH112 DO41-10 D9 SF1200/STTH112 DO41-10 D10 SF1200/STTH112 DO41-10 DIP-CIB CPXXTD1- CIB *** population for 1200V version (default) *** IC1 M81019FP 24P2Q IC2 M81019FP 24P2Q IC3 M81019FP 24P2Q *** population for 600V version *** IC1 M81721FP 24P2Q IC2 M81721FP 24P2Q IC3 M81721FP 24P2Q IC4 M81716FP SO-8 JP1 PINHD-1X12 1X12 JP2 PINHD-1X2 1X02 JP3 N(Br) 6.3mm FASTON type terminal JP4 N1 6.3mm FASTON type terminal JP5 T 6.3mm FASTON type terminal JP6 S 6.3mm FASTON type terminal JP7 R 6.3mm FASTON type terminal JP8 P2 6.3mm FASTON type terminal JP9 P1 6.3mm FASTON type terminal JP10 Br 6.3mm FASTON type terminal JP11 U 6.3mm FASTON type terminal JP12 V 6.3mm FASTON type terminal JP13 W 6.3mm FASTON type terminal R1 2817 not populated R2 2817 not populated R3 2817 not populated R4 1206 not populated R5 10 Ohm 1206



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R6 10 Ohm 1206 R7 10 Ohm 1206 R8 10k 0805 R9 1,5k 0805 R10 1206 not populated R11 1,5k 0805 R12 1,5k 0805 R13 4k7 0805 R14 1206 not populated R15 1206 not populated R16 1206 not populated R17 1206 not populated R18 1206 not populated R19 1206 not populated R20 1206 not populated R21 1206 not populated R22 1206 not populated R23 1206 not populated R30 68R 1206



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CHAPTER V ANNEX

Notes When Using This Specification

• This specification is intended as reference materials when customers use semiconductor products of

Mitsubishi Electric. Thus, we disclaim any warranty for exercise or use of our intellectual property rights and other proprietary rights regarding the product information described in this specification.

• We assume absolutely no liability in the event of any damage and any infringement of third party’s rights arising from the use of product data, diagrams, tables, and application circuit examples described in this specification.

• All data including product data, diagrams, and tables described in this specification are correct as of the day it was issued, and they are subject to change without notice. Always verify the latest information of these products with Mitsubishi Electric and its agents before purchase.

• The products listed in this specification are not designed for using with devices or systems, which would directly endanger human life. Should you intend to use these products for special purposes such as transportation equipment, medical instruments, aerospace machinery, nuclear-reactor controllers, fuel controllers, or submarine repeaters, please contact Mitsubishi Electric and its agents.

• Regarding transmission or reproduction of this specification, prior written approval of Mitsubishi Electric is required.

• Please contact Mitsubishi Electric and its agents if you have any questions about this specification.

Notification for Safe Designs

We are making every effort to improve the quality and reliability of our products. However, there are possibilities that semiconductor products be damaged or malfunctioned. Pay much attention to take safety into consideration and to adopt redundant, fireproof and malfunction-proof designs, so that the breakdown or malfunction of these products would not cause accidents including human life, fire, and social damages.

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