DIGITALLY ASSISTED PIPELINE ADCs

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Digitally Assisted Pipeline ADCs Theory and Implementation

by

Boris Murmann Standford University

and

Bernhard E. Boser University of California, Berkeley

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 1-4020-7840-4 Print ISBN: 1-4020-7839-0

2004 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow

Print 2004 Kluwer Academic Publishers Dordrecht

All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Kluwer Online at: http://kluweronline.com and Kluwer's eBookstore at: http://ebooks.kluweronline.com

Dedication

To our families.

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Contents

List of Figures xi

List of Tables xv

Acknowledgments xvii

Preface xix

1. INTRODUCTION 1

1. Motivation 1

2. Overview 2

3. Chapter Organization 4

2. PERFORMANCE TRENDS 5

1. Introduction 5

2. Digital Performance Trends 6

3. ADC Performance Trends 7

3. SCALING ANALYSIS 15

1. Introduction 15

2. Basic Device Scaling from a Digital Perspective 16

3. Technology Metrics for Analog Circuits 17

4. Scaling Impact on Matching-Limited Circuits 25

5. Scaling Impact on Noise-Limited Circuits 33

4. IMPROVING ANALOG CIRCUIT EFFICIENCY 43

1. Introduction 43

2. Analog Circuit Challenges 43

3. The Cost of Feedback 45

viii Digitally Assisted Pipeline ADCs

4. Two-Stage Feedback Amplifier vs. Open-Loop Gain Stage 46

5. Discussion 52

5. OPEN-LOOP PIPELINED ADCS 53

1. A Brief Review of Pipelined ADCs 53

2. Conventional Stage Implementation 54

3. Open-Loop Pipeline Stages 55

4. Alternative Transconductor Implementations 60

6. DIGITAL NONLINEARITY CORRECTION 63

1. Overview 63

2. Error Model and Digital Correction 65

3. Alternative Error Models 74

7. STATISTICS-BASED PARAMETER ESTIMATION 75

1. Introduction 75

2. Modulation Approach 76

3. Required Sub-ADC and Sub-DAC Redundancy 77

4. Parameter Estimation Based on Residue Differences 79

5. Statistics Based Difference Estimation 84

6. Complete Estimation Block 87

7. Simulation Example 90

8. Discussion 97

8. PROTOTYPE IMPLEMENTATION 101

1. ADC Architecture 101

2. Stage 1 102

3. Stage 2 106

4. Post-Processor 107

9. EXPERIMENTAL RESULTS 109

1. Layout and Packaging 109

2. Test Setup 111

3. Measured Results 112

4. Post-Processor Complexity 121

10. CONCLUSION 123

1. Summary 123

2. Suggestions for Future Work 124

Appendices

A- Open-Loop Charge Redistribution 127

B- Estimator Variance 131

Contents ix

C- LMS Loop Analysis 137

1. Time Constant 137

2. Output Variance 138

3. Maximum Gain Parameters 139

References 143

Index 153

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List of Figures

1-1. System overview. 3

2-1. ADC performance trend. 10

2-2. ADC energy efficiency trend. 11

2-3. Comparison of speed trends: ADCs versus digital. 12

2-4. Comparison of energy efficiency trends: ADCs versus digital. 12

2-5. Modern ADC application: 802.11 base band processor for

wireless networks [21]. 13

2-6. ADC applications in the speed/resolution space. The equi-

power contours assume FOM2=3pJ/conversion. 14

3-1. Supply voltage scaling. 18

3-2. NMOS transit frequency. 19

3-3. Transconductor efficiency versus gate overdrive. The dotted

line shows the case for perfect square law devices. 20

3-4. Product gm/IDfT. 21

3-5. NMOS intrinsic device gain at VOV=200mV. 22

3-6. NMOS intrinsic device gain at VOV=200mV (Zoom into typical

operating region). 22

3-7. Technology scaling trends of AVTH and AE. 24

3-8. Flash ADC block diagram. 26

3-9. Preamp/latch model. 27

3-10. Flash ADC energy as a function of sampling rate (assuming

constant mismatch factors AVTH, and AE). 29

3-11. Flash ADC energy as a function of sampling rate (assuming

improving mismatch factors AVT, and AE with technology). 30

3-12. Estimated flash ADC energy versus feature size (from speed

trajectory in Figure 3-11). 31

xii Digitally Assisted Pipeline ADCs

3-13. Published flash ADC performance vs. technology. 32

3-14. Basic amplifier model. 34

3-15. Noise limited circuit energy versus speed and technology. 36

3-16. Ratio slewing/linear settling time vs. sampling speed. 38

3-17. Noise limited circuit energy with slewing included. 39

3-18. Published 10-bit pipelined ADC performance vs. technology. 40

3-19. Typical 10-bit pipelined ADC power distribution. 41

4-1. Analog circuit challenges and power dissipation. 44

4-2. Comparison: (a) Precision feedback amplifier. (b) Open-loop

45amplifier. 4-3. (a) Two-stage feedback amplifier. (b) Open-loop gain stage. 46

4-4. Two-stage amplifier penalty factor. 49

4-5. Percent power savings with open-loop amplification as a

function of gain (assuming Ka =Kb). 50

4-6. Percent power savings with open-loop amplification as a

function of gain (assuming Vref=1V, Ka=10V-1 and Kb given by (4-13)). 52

5-1. Pipelined ADC block diagram. 53

5-2. Conventional pipeline stage. 55

5-3. Open-loop pipeline stage. 56

5-4. Open-loop stage model. 57

5-5. Differential pair V-I characteristic. 58

5-6. Differential pair nonlinearity as a function of D=Vxmax/VOV. 59

6-1. (a) ADC block diagram. (b) Reduced model for analysis. 64

6-2. Reduced model with stage sub-circuits. 65

6-3. Model for error compensation. 68

6-4. Additive nonlinearity compensation. 69

6-5. (a) Model with shifted variables. (b) Equivalent/compensated

model. 71

6-6. Modification for hardware efficient linear digital weighting. 73

6-7. Complete digital correction hardware. 73

7-1. System model with digital code modulation. 77

7-2. I ntroducing Sub-ADC redundancy: (a) Quantization error of a

2-bit sub-ADC. (b) Error of a (2+1)-bit sub-ADC. (c) Superimposed modulation. 78

7-3. Sub-ADC/DAC interface: (a) Bipolar modulation.

(b) Equivalent unipolar modulation with DAC offset. 79

7-4. System model for transfer function analysis. 80

7-5. Residue plot for both RNG states. 81

7-6. Single transfer function segment without correction and

b3

List of Figures xiii

7-7. Difference measurement with symmetrical ordinates (b3

xiv Digitally Assisted Pipeline ADCs

9-14. Stage 1 power breakdown. 119

9-15. FOM2 performance of the prototype. 120

9-16. Estimated post-processor area for linear and cubic calibration. 122

A-1. Open-loop pipeline stage. 128

A-2. Equivalent stage model. 128

B-1. Simulated estimator variance for Gaussian input. 135

C-1. LMS loop block diagram. 137

List of Tables

2.1. Moores Law: Integration density in lead microprocessors. 6

2.2. Speed in lead microprocessors. 6

2.3. Digital energy/power efficiency. 7

3-1. 6-bit Flash ADC Performance. 32

4-1. Amplifier performance metrics. 47

7-1. Open-loop amplifier parameters. 91

7-2. LMS Loop Parameters (N=30,000). 94

9-1. Pinout. 111

9-2. Test equipment. 112

9-3. Performance summary (25qC). 121

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Acknowledgments

The authors would like to acknowledge Dimitrios Katsis, Mike Scott, Philip Stark and Sotirios Limotyrakis for their help in improving the manuscript. The authors thank Analog Devices for providing their ADC design for re-use as an experimental prototype. The help of Katsu Nakamura, Sudhir Korrapati, Dan Kelly, Larry Singer, Will Yang and other members of the High-Speed Converter group was greatly appreciated.

This research was funded by Analog Devices and UC MICRO 01-006.

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Preface

The continued reduction of integrated circuit feature sizes and commensurate improvements in device performance are fueling the progress to higher functionality and new application areas. For example, over the last 15 years, the performance of microprocessors has increased 1000 times. Analog circuit performance has also improved, albeit at a slower pace. For example, over the same period the speed/resolution figure-of-merit of analog-to-digital converters improved by only a factor 10.

Of the many reasons for this disparity between analog and digital circuit performance advances, accuracy requirements stand out as a critical constraint in most analog circuits while being virtually absent in digital designs. Thermal noise, linearity, and matching are distinctly analog circuit problems and require design tradeoffs that invariably lower achievable performance. For example, linearity requirements are usually met with high-gain feedback loops. Unfortunately, this solution also lowers circuit speed and results in elevated noise, reduced signal range, and increased power dissipation.

Technology scaling, while unquestionably advantageous for digital circuits, further exacerbates analog circuit design challenges. While offering increased speed, scaled devices suffer