digitally-assisted design and calibration for high ...m...2.2 double-tail latch-type comparator...
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Digitally-Assisted Design and Calibration for
High Performance Flash Analog-to-Digital Converters
A Thesis Presented
by
Marina Zlochisti
to
The Department of Electrical and Computer Engineering
in partial fulfillment of the requirement
for the degree of
Master of Science
in
Electrical Engineering
Northeastern University
Boston, Massachusetts
August, 2018
I
Abstract
Digitally-assisted integrated circuit design has gained popularity in recent years due
to challenges associated with analog components in mixed-signal systems-on-a-chip,
which include process variations, mismatches, and increased demand for circuit complex-
ity in sub-micron fabrication process technologies. To optimize efficiency and cost, the
focus during hardware design is increasingly directed on the creation of reliable and robust
circuits that are immune to variations and unpredictable factors out of the designer’s con-
trol. On the other hand, the circuits should be power and area efficient to adapt to the needs
associated with portable devices, wireless communications, and the global energy and cost
saving trends. On-chip calibration techniques can be developed to address these issues by
reducing the sensitivity of analog circuit designs, thereby improving their universal use-
fulness and scalability. Another emerging trend is the rising demand for high-speed low-
power analog-to-digital converters (ADCs) to accommodate the increased use of digital
processing and big data. The research described in this thesis unites these topics in a design
approach for ADCs.
This thesis introduces the design of a 3-bit flash ADC with an offset calibration
scheme, which is integrated into a two-step 8-bit hybrid flash/successive approximation
register (SAR) architecture with time-interleaving. Due to the hybrid architectural struc-
ture, the offset requirement for the flash ADC is more stringent than for a conventional
standalone 3-bit ADC. Two pairs of transistors are employed to adjust the offsets for each
of the seven comparators in the flash ADC by creating a current flow imbalance between
the comparator’s branches. The amount of current injected in each branch is controlled
through the gate voltages of the calibration transistors, which are generated with automatic
on-chip calibration circuitry that was developed as part of this research. The circuits were
designed, simulated, and fabricated using 0.13µm complementary metal-oxide semicon-
ductor (CMOS) technology. The calibration path emulates the ADC’s normal operation to
establish realistic loading and transient effects. Furthermore, the design approach ad-
dresses integration challenges within the hybrid ADC system, such as kickback noise and
common-mode variations. Monte Carlo simulation results show that the offset standard
variation is reduced from 19.2mV to 582µV (worst case) through the calibration. The
power consumption of all digital circuits (not including calibration circuitry) is 1.36mW
II
from a separate 1.2V supply, and the power consumption of the calibration logic with a
10MHz clock is 600µW. The dynamic latched comparator of the flash ADC with kickback
reduction was evaluated with post-layout simulations including process-voltage-tempera-
ture (PVT) variations. It has a 231ps propagation delay, and consumes 160µW. From
simulations of the flash ADC, the worst-case effective number of bits (ENOB) is 2.88 bits,
and the worst-case signal-to-noise-and-distortion ratio (SNDR) is 19.1dB in the slow pro-
cess corner case with a temperature of 85°C, 1.14V supply, and low input frequency
(2.923MHz). The flash ADC consumes 3.6mW. The comparator design incorporates a
kickback reduction technique that reduces the kickback effect from 23.3mV to 1.2mV for
a 500mV input during system-level simulations. Measurements of a prototype chip show
that the ENOB improves from 3.64 to 5.24 bits using a 500MHz clock during automatic
calibration.
III
Acknowledgements
First and foremost, I would like to express my appreciation and thank my thesis ad-
visor, Prof. Marvin Onabajo, for his guidance and support through these years. Without
his encouragement I would not have initiated and completed my Master’s degree.
I would also like to thank Alireza Zahrai for the guidance during all stages of the
hybrid ADC project, and Nicolas Le Dortz from “Analog Devices Lyrics Lab” for the
collaboration and help.
I would also like to thank my committee members, Prof. Yong-Bin Kim, Prof.
Astmesh Shrivastava, and Dr. Hari Chauhan for their participation in the final stages of
my M.S. degree completion.
I would like to thank my husband, Alex, who supported and encouraged me all the
way, my daughter Emily, and my family: my parents, my sister Irina and my grandmother
Raisa (R.I.P) who passed away last April.
Finally, I would like to thank my former managers and co-workers at Intel Jerusalem,
who gave me the opportunity to spend 2.5 productive years and supported my decision to
move to the US and obtain a Master’s degree.
IV
Table of Contents
Abstract ............................................................................................................................... I
Acknowledgements .......................................................................................................... III
1. Introduction ................................................................................................................ 12
1.1 Recent design trends for flash ADCs and hybrid ADCs .................................. 12
1.2 Process variation challenges and digitally-assisted analog design .................. 15
1.3 Contribution of this work ................................................................................. 19
1.4 Thesis outline ................................................................................................... 20
2. High-Speed and Low-Power Comparators for Flash ADCs ...................................... 21
2.1 Dynamic latch-type voltage sense amplifier (StrongARM latch) .................... 21
2.2 Double-tail latch-type comparator ................................................................... 24
2.3 The kickback problem of preamplifier-less comparators, and kickback reduction
methods ............................................................................................................ 25
2.4 The offset problem and foreground offset calibration methods ....................... 29
2.5 Comparator with digitally programmable offset correction and common-gate
transistors for kickback reduction .................................................................... 31
3. Flash ADC Calibration Scheme ................................................................................. 34
3.1 Flash ADC in a hybrid ADC architecture ........................................................ 34
3.2 Offset sources in flash ADCs ........................................................................... 35
3.3 Digital calibration implementation .................................................................. 36
3.4 Memory block .................................................................................................. 41
3.5 Analog circuitry for input generation in the calibration path ........................... 43
3.5.1 Wide-swing operational amplifier design ............................................ 47
3.5.2 Calibration DAC .................................................................................. 50
4. Simulation Results ..................................................................................................... 52
4.1 Comparator simulations ................................................................................... 52
4.2 Flash ADC simulation results .......................................................................... 58
V
4.3 Wide-swing operational amplifier ................................................................... 65
4.4 Behavioral Verilog-A model for the determination of offsets on the hybrid ADC
system level ...................................................................................................... 70
4.5 Digital calibration – Verilog and schematic simulations ................................. 79
4.6 Verification of the external access features for the memory............................ 82
4.7 Kickback of the flash ADC .............................................................................. 83
5. Prototype Chip and Printed Circuit Board (PCB) Design ......................................... 84
5.1 Fabricated chip ................................................................................................. 84
5.2 PCB design ....................................................................................................... 85
5.3 Flash ADC and calibration logic test setup ...................................................... 89
5.3.1 Test setup for external reading from memory ...................................... 90
5.3.2 Test setup for external manual writing to memory .............................. 91
5.4 Measurement results and discussion ................................................................ 92
5.4.1 Verification within the hybrid ADC system ........................................ 93
5.4.2 Calibration logic verification ............................................................... 94
6. Conclusions and Future Work ................................................................................. 101
References ...................................................................................................................... 103
Appendix I - Digitally Programmable Offset Compensation of Comparators in Flash
ADCs using Varactors ............................................................................................. 108
Appendix II - Tables of Coarse and Fine Codes and their Corresponding Voltage Levels
................................................................................................................................. 114
VI
List of Figures
Figure 1. Overview of ADC applications. ....................................................................... 12
Figure 2. Differential 3-bit flash ADC. ........................................................................... 13
Figure 3. Standard deviation vs. technology node from [24]. ......................................... 17
Figure 4. Offsets in flash ADC. ....................................................................................... 18
Figure 5. Monte Carlo simulation of yield versus offset standard deviation (data taken
from [25]). ........................................................................................................................ 19
Figure 6. StrongARM latch comparator. ......................................................................... 21
Figure 7. StrongARM comparator - operation phases : (a) Reset (b) Evaluation sub-phase
1 (c) Evaluation sub-phase 2 (d) Evaluation sub-phase 3 (regeneration). ....................... 23
Figure 8. Transient waveforms of a StrongARM comparator. ........................................ 24
Figure 9. Double-tail comparator. ................................................................................... 25
Figure 10. Kickback effect in a comparator. ................................................................... 26
Figure 11. Kickback reduction method from [30]: (a) reset phase, (b) regeneration phase.
......................................................................................................................................... 27
Figure 12. Kickback reduction as in [29]. ....................................................................... 28
Figure 13. Dynamic latched comparator with kickback reduction and offset compensation
circuitry. ........................................................................................................................... 31
Figure 14. Comparator layout. ......................................................................................... 32
Figure 15. Flash ADC layout with resistors ladder. ........................................................ 33
Figure 16. Hybrid ADC architecture from [10]. .............................................................. 35
Figure 17. Systematic offset versus input common-mode voltage variations. ................ 36
Figure 18. Flash ADC offset calibration system (single-ended equivalent). ................... 37
Figure 19. Offset calibration range of the comparators within the system. ..................... 38
Figure 20. Flow chart of the calibration. ......................................................................... 39
Figure 21. Layout of calibration circuitry. ....................................................................... 41
Figure 22. Memory block and auxiliary digital components of the on-chip calibration
logic. ................................................................................................................................ 42
Figure 23. Circuits at the input of the calibration path. ................................................... 44
Figure 24. Floor plan of the resistor ladder. .................................................................... 44
VII
Figure 25. RON for the complementary switch (transmission gate), nMOS switch, and
pMOS switch. .................................................................................................................. 45
Figure 26. Layout of input signal generation circuits for calibration. ............................. 46
Figure 27. Wide-swing operational amplifier schematic. ................................................ 47
Figure 28. Class-AB control output stage. ....................................................................... 49
Figure 29. Calibration DAC block diagram. ................................................................... 50
Figure 30. Calibration DAC layout. ................................................................................ 51
Figure 31. Comparator transient voltages from schematic-level simulations. ................ 52
Figure 32. Comparator transient voltages from simulations without kickback reduction.
......................................................................................................................................... 53
Figure 33. Offset simulation setup. .................................................................................. 55
Figure 34. Monte Carlo simulation results (with transient noise) for 7 comparators in the
flash ADC. ....................................................................................................................... 56
Figure 35. Offset determination example with the DOTB method. ................................ 57
Figure 36. Simulated SNDR and SFDR of the 3-bit flash ADC vs. input frequency. .... 58
Figure 37. Monte Carlo DNL simulation results with a correlation of 0.9 without
calibration. ....................................................................................................................... 61
Figure 38. DNL and INL before and after calibration with the worst-case statistical corner.
......................................................................................................................................... 62
Figure 39. Output spectra with fin = 6.836 MHz and fin = 487.3 MHz after calibration. 62
Figure 40. Test setup for the wide-swing operational amplifier. ..................................... 65
Figure 41. Frequency response of the unity-gain operational amplifier. ......................... 66
Figure 42. Input common-mode voltage range. ............................................................... 67
Figure 43. Step response of the operational amplifier. .................................................... 68
Figure 44. Simulated PSRR curves of the unity-gain buffer after 100 Monte Carlo runs.
......................................................................................................................................... 68
Figure 45. Configuration for simulation of the CMRR. .................................................. 69
Figure 46. Simulated CMRR curves after 100 Monte Carlo runs. .................................. 70
Figure 47. Offset determination and calibration testbench. ............................................. 71
Figure 48. Timing diagram for the offset determination. ................................................ 71
VIII
Figure 49. Flash ADC input with 5 offset determination phases, 3 cycles of calibration,
and 5 offset determination phases after calibration. ........................................................ 73
Figure 50. Offset determination: binary search example. ................................................ 73
Figure 51. Example of calibration phase for the first comparator with the realistic flash
input. ................................................................................................................................ 74
Figure 52. Histogram of the first comparator offset (for -375mV differential reference)
from 100 Monte Carlo runs in the presence of transient noise, before and after calibration.
......................................................................................................................................... 75
Figure 53. Histogram of the second comparator offset (for -250mV differential reference)
from 100 Monte Carlo runs in the presence of transient noise, before and after calibration.
......................................................................................................................................... 75
Figure 54. Histogram of the third comparator offset (for -125mV differential reference)
from 100 Monte Carlo runs in the presence of transient noise, before and after calibration.
......................................................................................................................................... 76
Figure 55. Histogram of the fourth comparator offset (for 0mV differential reference) from
100 Monte Carlo runs in the presence of transient noise, before and after calibration. .. 76
Figure 56. Histogram of the fifth comparator offset (for +125mV differential reference)
from 100 Monte Carlo runs in the presence of transient noise, before and after calibration.
......................................................................................................................................... 77
Figure 57. Histogram of the sixth comparator offset (for +250mV differential reference)
from 100 Monte Carlo runs in the presence of transient noise, before and after calibration.
......................................................................................................................................... 77
Figure 58. Histogram of the seventh comparator offset (for +375mV differential reference)
from 100 Monte Carlo runs in the presence of transient noise, before and after calibration.
......................................................................................................................................... 78
Figure 59. Waveforms of the controller block. ................................................................ 79
Figure 60. Calibration logic enable signals sequence for one full comparator calibration
cycle. ................................................................................................................................ 80
Figure 61. Coarse calibration sequence waveforms. ....................................................... 80
Figure 62. Fine calibration sequence waveforms. ........................................................... 81
Figure 63. Digital logic schematic simulation results. .................................................... 81
IX
Figure 64. External writing functionality example (schematic-level simulation). .......... 82
Figure 65. Flash ADC input with and without kickback reduction (500mV input). ....... 83
Figure 66. Input voltage amplitude versus kickback. ...................................................... 83
Figure 67. Micrograph of the hybrid ADC chip containing the flash ADC and calibration
logic. ................................................................................................................................ 84
Figure 68. Bias current generation for the calibration buffer input stage. ....................... 85
Figure 69. Generation of bias voltages for the cascode stage of the buffer. .................... 86
Figure 70. Generation of input references for the calibration buffer. .............................. 87
Figure 71. PCB components for the calibration buffer. ................................................... 87
Figure 72. Voltage generation for the flash ADC reference ladder on the PCB. ............ 88
Figure 73. Calibration DAC reference generation. .......................................................... 88
Figure 74. Hybrid ADC PCB........................................................................................... 89
Figure 75. Measurement setup. ........................................................................................ 90
Figure 76. Setup to read from memory. ........................................................................... 90
Figure 77. Example configuration: reading from memory. ............................................. 91
Figure 78. Test setup for external writing to memory. .................................................... 92
Figure 79. Measured output spectra of the 6-bit 1GS/s hybrid ADC output for fin =
10.193MHz before and after manual calibration. ............................................................ 94
Figure 80. Floor plan of the hybrid ADC. ....................................................................... 95
Figure 81. Measured output spectra (4096-point FFT) of the 6-bit 500MS/s hybrid ADC
output for fin = 10.28442383MHz after automatic calibration. ....................................... 97
Figure 82. Measured output spectra (4096-point FFT) of the 6-bit 500MS/s hybrid ADC
output for fin = 10.28442383MHz before automatic calibration. ................................... 98
Figure 83. Measured output spectrum (8192-point FFT) of the 6-bit 1GS/s hybrid ADC
output for fin = 10.193MHz after automatic calibration (with 500MS/s clock). ............. 98
Figure 84. Measured DNL and INL of the hybrid ADC after automatic calibration (6-bit
evaluation). ...................................................................................................................... 99
Figure 85. Measured DNL and INL of the hybrid ADC before calibration (6-bit
evaluation). ...................................................................................................................... 99
Figure 86. Comparator with varactors for offset calibration. ........................................ 108
Figure 87. Calibration logic for a single comparator with varactor-based tuning. ........ 110
X
Figure 88. Varactor capacitance vs. applied gate voltage. ............................................ 110
Figure 89. Input offset vs. gate voltage curves for the Di and OUTn nodes. ................. 111
Figure 90. Monte Carlo simulation results for the input offset voltage of a single
comparator with the varactor tuning method: (a) before calibration, (b) after calibration.
....................................................................................................................................... 111
Figure 91. Simulated DNL/INL of the flash ADC with the varactor-based calibration
method. .......................................................................................................................... 112
Figure 92. Output spectrum at 1GS/s of the flash with varactors for calibration: (a)
479MHz input, (b) 6.84MHz input. ............................................................................... 113
XI
List of Tables
Table 1. Comparator dimensions ..................................................................................... 33
Table 2. External memory decoder .................................................................................. 43
Table 3. Comparison between the comparator with and without kickback reduction
transistors based on schematic-level simulations ............................................................ 54
Table 4. Comparator post-layout specifications with 4mV peak-to-peak differential input
toggling around different reference levels ....................................................................... 54
Table 5. Comparator performance over PVT variations - post layout ............................ 55
Table 6. Flash ADC schematic performance over PVT corners ..................................... 60
Table 7. Calibration voltages for INL/DNL testing of one statistical corner .................. 61
Table 8. Calibration voltage levels extracted with intentional 30mV systematic offset . 63
Table 9. Post-layout SNDR, SFDR and ENOB for low input frequency (6.836 MHz) and
close-to-Nyquist input frequency (487.3 MHz) ............................................................... 64
Table 10. Post-layout power dissipation of the flash ADC core, sets of flash latches, and
calibration latch set .......................................................................................................... 64
Table 11. Post-layout frequency response summary for the operational amplifier (stability
analysis) ........................................................................................................................... 65
Table 12. Simulated opamp post-layout performance with a common-mode input level of
600mV and PVT variations ............................................................................................. 66
Table 13. Interpretation of Figure 64 ............................................................................... 82
Table 14. Manual offset calibration codes ....................................................................... 93
Table 15. Automatic offset calibration codes .................................................................. 97
Table 16. Summary of the hybrid ADC system performance compared to other works
(Data taken from [18]) ................................................................................................... 100
Table 17. Coarse codes and corresponding voltage levels ............................................ 114
Table 18. Fine codes and corresponding voltage levels ................................................ 115
12
1. Introduction
1.1 Recent design trends for flash ADCs and hybrid ADCs
With the advancement of digital signal processing and enormous increase of data sizes,
analog-to-digital converters (ADCs) play an important role in many electronic systems to
convert analog continuous signals into the digital domain with appropriate accuracy and
speed. ADCs have a great variety of applications in wireless communication systems, such
as imaging, test and measurement, ultra-wideband communications (UWB), high speed se-
rial links, digital oscilloscopes, digital TVs, wireless personal area networks (EPAN), serial
link receivers and software-defined radios. Figure 1 visualizes a few application examples.
In many cases, wireless receiver blocks are followed by an ADC prior to the digital signal
processor (DSP) that implements functions such as equalization and forward error correc-
tion [1]; or the output of wired analog front ends for processing of sensed signals, such as in
electroencephalography (EEG) for instance [2], is processed by an ADC.
BPFLNA BPF
LO
ADC DSP
Analog Front End
Digital TV
Oscilloscope
Cell phones
Satallites
Defense (Iron Dome
– detection radar)
Software Defined
radio Receiver
Implantable Cardioverter
Defibrillaror
EEG
Analog
Front EndFilter ADC
Figure 1. Overview of ADC applications.
13
Traditionally, flash ADCs have been widely used for high-speed analog-to-digital
conversion because they are known as the fastest ADCs for their parallel operation, good
bit-error-rate (BER) performance and low latency. However, their input capacitance and
power consumption increase exponentially with the number of bits because the number of
required comparators for a conventional N-bit flash ADC is 2N-1. This makes them less
power and area efficient for high resolutions, increases the kickback noise, and poses dif-
ficulties during routing of signals on the chip [3].
Th
erm
om
ete
r to
bin
ary
en
co
der
B2
VRP
VRN
3Vr/8
7Vr/8
5Vr/8
6Vr/8
4Vr/8
+- +
-+-
+- +
-+-
+- +
-+-
+- +
-+-
+- +
-+-
+- +
-+-
+- +
-+-
VIP
VIN
Vr/8
2Vr/8
2Vr/8
Vr/8
3Vr/8
4Vr/8
5Vr/8
6Vr/8
7Vr/8
CLK
B1
B0
Figure 2. Differential 3-bit flash ADC.
14
Figure 2 displays the structure of the differential 3-bit flash ADC used in this thesis.
This topology is conventionally comprised of seven comparators, a resistor ladder with
eight identical resistors for reference voltages generation, and an encoder that converts
seven thermometer-coded bits to three binary-coded bits.
The fact that a flash ADC yields thermometer code, and the information is taken from
the two transitioning comparators (from 0 to 1 or vice versa), implies that there is a lot of
redundancy in the basic flash architecture. Therefore, recent works have focused on archi-
tectures that alleviate this disadvantage.
Folding architectures as in [4]-[5] reduce the number of comparators by half, where
an N-1 bit flash ADC is followed by a 1-bit folding stage that determines the Nth bit.
Interpolation flash ADCs also reduce the number of comparators by cascading the outputs
of adjacent comparators to another comparator, and using the information obtained from
the 2-stage operation [6].
Other approaches borrow from principles that are similar to successive approximation
register (SAR) ADCs, such as time-interleaving (TI). A time-interleaved ADC architec-
ture effectively increases the conversion rate by using N parallel channels, each operating
with reduced frequency of fs/N, and N phases of the slow clock. This technique is typical
for SAR ADCs because of the inherently limited sampling rate [7]-[12]. For example, [12]
uses four time-interleaved channels for the flash ADC with a frequency of fs/4, and also
presents a partially active flash ADC, using the fact that the redundant comparators during
flash operation should be turned off to save power depending on the voltage level to be
digitized. This is done by dividing the comparators into slices: coarse 2-bit flash ADC
determines which slice to activate, which resembles 2 stage ADC, but does not require
residue generation. Time based flash ADCs that are adopted from sigma-delta ADCs have
also been of interest [13]. Voltage-to-time converters (VTCs) sample the input and convert
it to a time signal, which is subsequently interpreted through on-chip logic.
15
Fully digital flash ADCs are presented in [14] and [15]. Digital circuits are less sen-
sitive to noise and are easily scalable for implementations in CMOS process technologies
with small dimensions. Since the ADC is interfacing analog and digital domains, it would
be desirable to make it fully synthesizable by replacing/digitizing its only two components
in the analog domain, which are the comparator and reference ladder. Reference [14] pro-
poses digital comparators by using two NAND-3 gates that resemble comparator
operation. In [15]-[16], a stochastic analog-to-digital conversion approach eliminates the
resistive reference ladder by exploiting device mismatches inside the comparator as virtual
references.
Recently, new hybrid architectures, such as a sub-ranging flash-SAR ADC [17] or
flash-TI-SAR ADCs [7], were introduced to exploit the benefits of flash and SAR ADCs.
This thesis research is part of the work on a subranging TI architecture [10], [18]. The
flash ADC is used to resolve the most significant bits (MSBs), whereas a TI ADC resolves
the least significant bits (LSBs). The fast MSB conversion by the flash ADC together with
subranging helps to reduce the number of interleaved ADCs, which results in higher input
bandwidth (BW).
1.2 Process variation challenges and digitally-assisted analog design
Fifty-three years ago, Intel co-founder Gordon Moore predicted that the number of
transistors on a chip would double annually as a result of rapid shrinking of transistor sizes
and reduction of costs [19]. Indeed, for the last decades the semiconductor industry has
been following this trend to a good proximity (with correcting it 10 years later to doubling
every 18 months). Device scaling allows to design more complex and advanced systems,
reduces the power and die area, increases the speed, lowers the cost, and overall allows
much more functionality. However, the scaling has been reaching its limits, and recently
the ITRS (Technology Roadmap for Semiconductors) concluded that the transistors will
stop shrinking by 2021, and that further efforts would be boosting density by stacking
layers of circuitry [20]. Intuitively, shrinking the sizing makes the fabrication process dif-
ficult because the sub-micron transistors are reaching the atomic size (which is 0.2nm in
silicon), while the newest technology has 7nm feature dimensions. In addition, various
16
physical effects associated with the short channels of field effect transistors limit function-
ality during circuit design. If initially it was relatively simple to model the transistors with
a few parameters such as threshold voltage VT, current constant KP, and body effect con-
stant γ; nowadays MOSFETS no longer follow the ideal models, and it is difficult to
predict the circuit functionality based on theoretical analysis [21]. In ADC designs, for
example, many challenges are related to low intrinsic gain of the transistors and limited
voltage headroom due to reduced supply voltage. The following effects are responsible
for this [22]:
Threshold voltage variations – Source and drain areas play a more significant role
in forming the inversion layer besides the gate voltage, therefore lowering the
threshold voltage VT. In addition, the drain creates a two-dimensional field, and
contributes to the surface potential and attracts carriers from source, which also
lowers VT. This effect is called drain induced barrier lowering (DIBL). The exact
value of the threshold voltage depends on the actual channel lengths, which vary
during fabrication; hence, the variations can be extensive.
Tunneling and leakage effects – Gate oxide tunneling (i.e., for smaller oxide
thickness tox, it is easier for carriers to “jump” through the gate), band-to-band
tunneling (BTBT), gate-induced drain leakage (GIDL), subthreshold leakage
(transistors conduct for voltages below VT).
Velocity saturation of carriers due to collisions occurs for lower saturation voltages
(VDSAT), which reduces the current.
17
Figure 3. Standard deviation of threshold voltage vs. technology node from [24].
The miniaturization of transistors has significant impact on process variations and in-
tra-die variability, which reduce the yield of systems-on-a-chip [23]. The standard
deviation of variations is increasing with further technology scaling, such that either more
parts fall within “void” category or it is easier for a single part to fail. Moreover, due to
the high volume of integrated circuits, the variation effects are accumulative, making it
extremely difficult to design a circuit that operates for all extreme cases; and usually re-
quires overdesign and more testing. This involves redundancy and increased cost as well
as die area. Figure 3 illustrates the increased standard deviation of threshold voltage versus
technology node [24]. Process variations can be die-to-die (D2D) or within-die
(WID) [23]. The former are assumed to affect all the components on the same chip simi-
larly, and are different from die to die; and the latter is associated with variations within
each chip. The WID variations can be either random or systematic.
18
Figure 4. Offsets in flash ADC.
Figure 4 visualizes the discussed problem for flash ADCs. In an ideal scenario, a com-
parator provides a logic output of “1” if VI > VREF and an output of “0” if VI < VREF. A
more realistic comparator can be modeled as an ideal one with a DC voltage source con-
nected in series with the reference voltage that models the combined effects of all offsets.
The offsets are random variables with normal distribution and have a direct impact on an
ADC’s functionality, worsening its integral and differential nonlinearities (INL and DNL,
respectively) [25].
19
Figure 5. Monte Carlo simulation of yield versus offset standard deviation (data taken from [25]).
Figure 5 (data from [25]) shows the yield of Monte Carlo (MC) MATLAB simulation
of a 6-bit flash ADC versus comparator offset standard deviation. Yield is the fraction of
parts that meet specifications and can be sold to customers over those that do not meet the
specifications. As the offset standard deviation σoffset increases, the yield dramatically de-
creases; and to obtain a yield of 99%, σoffset should be at most 0.15 LSB.
1.3 Contribution of this work
This thesis advances the capabilities of digitally-assisted flash ADC design through
a calibration technique with built-in testability, which was developed to enhance the per-
formance of hybrid ADCs in particular. To improve robustness and immunity of the
system to mismatches and PVT variations, this calibration scheme was designed to com-
pensate the offsets of the flash ADC’s comparators. A conventional standalone 3-bit flash
ADC has relaxed offset requirements due to its low number of bits, such that an offset of
½ LSB would typically suffice. However, when a flash ADC is incorporated as coarse
ADC in a hybrid architecture with higher resolution, then the offset requirement is more
stringent and should comply with the overall system requirements. This research delivers
a solution to the challenge of integrating a flash ADC into a hybrid ADC system. In addi-
tion to addressing the offset problem with calibration, the design approach alleviates
kickback, clock feedthrough and timing constraints. Specifically, a kickback reduction
20
technique is utilized in the comparator architecture. Furthermore, in addition to the four
time-interleaved channels for normal operation, an auxiliary sample-and-hold channel is
utilized in the calibration path to generate the same switching characteristics and loading
effects as in normal operation. A wide-swing operational amplifier with floating current
class-AB output stage for high output swing was designed to pass an artificial input com-
mon-mode level during calibration, as it has been observed that calibration code depends
highly on the input common-mode.
1.4 Thesis outline
The organization of this thesis is as follows: Chapter 2 describes key circuit compo-
nents of the flash ADC, which mainly consist of high-speed, low-power dynamic
comparators; and design techniques to cope with the kickback and offset cancellation.
Chapter 3 focuses on the calibration scheme by initially introducing the flash ADC in the
hybrid ADC architecture, followed by the discussion of offset sources and an overview
for the digital implementation of the calibration scheme and its auxiliary circuits. Chap-
ter 4 includes schematic and post-layout simulation results for the comparator, flash ADC
performance metrics, high-swing operational amplifier, and automatic and manual cali-
bration. Chapter 5 focuses on the design of the fabricated chip and PCB, as well as the
discussion of measurement results. A summary and conclusions are provided in chapter 6.
Appendix I presents the initial version of the comparator and calibration scheme before it
was modified for improved integration. Appendix II includes tables of coarse and fine
calibration codes and their corresponding voltage levels.
21
2. High-Speed and Low-Power Comparators for Flash ADCs
A comparator is the fundamental building block of a flash ADC. Two popular topol-
ogies of latch-type voltage sense amplifier [26] comparators are presented here: A
conventional dynamic latch comparator (StrongARM Latch) [27], and the double-tail volt-
age sense amplifier [28]. These comparators have high input impedance, strong positive
feedback, full rail-to-rail output swing, and no static power consumption. Also, these com-
parators operate synchronously with a clock signal. Therefore, they are well-suited for
high-speed low-power applications. However, they suffer from offsets and kickback noise.
Pre-amplifiers usually alleviate these problems, but they have static power consumption
and offsets of themselves, which is why they are avoided in this work.
2.1 Dynamic latch-type voltage sense amplifier (StrongARM latch)
The differential structure of the dynamic comparator is presented in Figure 6. The
comparator consists of input differential pairs M1-M4, clocked tail transistors M5-M6, re-
generative back-to-back inverters M7-M10, and reset transistors M11-M14. The generated
output is in reversed polarity, therefore an inverter is placed at each output, which also
buffers the comparator from the load.
VIP VINVRNVRP
Clock
Voutn
Clock
Voutp
Clock
M1 M2 M3 M4
M6
M10M11 M12 M9
M7
Clock
M14M13
M5
M8
VDD
Di+ Di-
No+ No-
Figure 6. StrongARM latch comparator.
22
There are two main modes of operation: reset phase and evaluation phase (depicted in
Figure 7).
Reset phase: When the clock signal is low, it turns off M5-M6 and leaves M1-M4 with
floating source terminals. Hence, the conductance paths are pre-charging all the internal
nodes: Di+, Di-, No+, No- to 𝑉DD through M11-M14. .The notation Di corresponds to a drain
(D) of the input (i), and No corresponds to an output node before inversion.
Evaluation phase: This phase consists of three sub-phases [27]. The first one begins as
soon as the clock transitions to high, which causes M11-M14 to turn off, and the internal
nodes Di+ and Di- begin to discharge from VDD towards 0. At this point, the back-to-back
inverters are still off until the voltage on the Di- and Di+ nodes falls, such that VGS is high
enough to turn on M7-M8. M1-M4 turn on in saturation mode (VDS is high enough to allow
such operation). The next sub-phase begins when M7-M8 turn on (by the time Di nodes
fall below VDD - VTH). According to the analysis in [27], the internal Di nodes continue to
fall during this phase because the cross-coupled nMOS transistors M7-M8 do not contrib-
ute much to the regeneration process. Only when the pMOS cross-coupled transistors M9-
M10 turn on (in the third and last sub-phase), one output transitions back to VDD and the
other one to 0V. One could conclude that the second sub-phase is redundant since it does
not contribute to regeneration. However, it should be noted that it creates “dead time”
between the turn-on of the input pairs and the pMOS M9-M10 transistors, otherwise there
would be a direct path from VDD to ground causing static power dissipation.
The comparator’s decision depends on the discharge rate, which is determined by
the current flowing through each branch. If 𝑉𝐼𝑃 − 𝑉𝑅𝑃 > 𝑉𝐼𝑁 − 𝑉𝑅𝑁, then the current through
the positive branch (Di+) is larger, discharging it faster such that the nMOS in this branch
turns on first and the discharge of No+ begins before the discharge of No-, generating a low
voltage at No+. Figure 8 shows the simulated transient waveforms of the comparator for
the Di and output nodes.
23
VIP VINVRNVRP
VoutnVoutp
M1 M2 M3 M4
M6
M10M11 M12 M9
M7
M14M13
M5
M8
VDD
Di+ Di-
No+ No-
0 0VDD VDD
VDD VDD
VIP VINVRNVRP
VoutnVoutp
Clock
M1 M2 M3 M4
M6
M10M11 M12 M9
M7
Clock
M14M13
M5
M8
VDD
Di+ Di-
No+ No-
Vgs
VIP VINVRNVRP
VoutnVoutp
Clock
M1 M2 M3 M4
M6
M10M11 M12 M9
M7
Clock
M14M13
M5
M8
VDD
Di+ Di-
No+ No-
Vgs>Vds-Vth
Vsg
VIP VINVRNVRP
VoutnVoutp
Clock
M1 M2 M3 M4
M6
M10M11 M12 M9
M7
Clock
M14M13
M5
M8
VDD
Di+ Di-
No+ No-
regeneration
(a) (b)
(c) (d)
Figure 7. StrongARM comparator - operation phases: (a) reset, (b) evaluation sub-phase 1, (c) eval-
uation sub-phase 2, (d) evaluation sub-phase 3 (regeneration).
24
Figure 8. Transient waveforms of a StrongARM comparator.
2.2 Double-tail latch-type comparator
The double-tail latch-type voltage sense amplifier was first presented in [28], and is
depicted in Figure 9. This topology has the advantage of a low number of stacked transis-
tors, which is crucial as supply voltages are scaled down. Also, the input differential pair
is isolated from the regenerative stage, which enables more current in the regenerative
stage for faster operation, and less current in the input stage. The principle of operation is
very similar to the conventional dynamic comparator:
Reset phase: When the clock signal is low, Di+ and Di- are pre-charged to VDD. As a
result, M9 and M10 turn on and pre-charge Voutn and Voutp to 0V.
Evaluation phase: When the clock signal transitions to high, the conduction paths
start discharging the Di nodes towards 0V until VGS of M9 and M10 is small enough to turn
them off. In this case, the higher input (bigger VGS of the input transistors) determines
which clamping transistor turns off first (M9 or M10) to dominate the regenerative opera-
tion. Clearly, if for example, 𝑉𝐼𝑃 − 𝑉𝑅𝑃 > 𝑉𝐼𝑁 − 𝑉𝑅𝑁, M9 turns off first, and node Voutp that
is released from being clamped to ground rises first, starting to build a voltage difference
with Voutn. Therefore, no inverters are needed at the output.
25
Figure 9. Double-tail comparator.
2.3 The kickback problem of preamplifier-less comparators, and
kickback reduction methods
The absence of a preamplifier results in high kickback noise at the input of the flash
ADC. The kickback is caused by a large variation of internal voltages within the compar-
ator, which are coupled by the gate-drain capacitance (Cgd) of the input transistors back to
the input nodes (also called “differential kickback” [29]). In addition, a “common-mode
kickback” is caused by the clocked gates of the tail transistors (M5 and M6 in Figure 6) at
the sources of the input pairs. Since in a flash ADC the comparators are connected in
parallel, the accumulative kickback effect becomes more problematic.
The severity of the kickback also depends on the impedance of the preceding circuit,
which is finite and sometimes asymmetric. For example, asymmetry can be naturally
26
caused by the fact that the reference voltages come from resistor reference ladders, while
the input of the comparators come from the switches connecting the flash ADC to the
sample-and-hold circuit. Figure 10 illustrates the kickback effect as the internal voltage at
Vx falls quickly from VDD towards 0V at the clock’s rising edge, and couples to the input.
Figure 10. Kickback effect in a comparator.
Kickback reduction methods have been of an interest in ADC design to alleviate the
effective number of bits (ENOB) degradation caused by incorrect comparator output eval-
uation due to the change in the input voltage. Most of the common techniques use the
same principle - isolating the input from the latching part of the circuit for reduced swings
at the drain and source of the input pairs.
In [30], sampling switches are inserted before the input differential pair, which dis-
connect the comparator from the preceding circuit for part of the time (regeneration
phase), eliminating kickback during this time. An additional circuit detects when the com-
parator has finished the decision, and triggers a reset for the input pair, such that the
27
previous sampled voltage does not disturb the next cycle. This mechanism is depicted in
Figure 11.
VIP
VIN
VDD
VDD
PH1=low
PH1
M1
M2
M3 M4
M5M6M7
M8
VDD0
0
0
VIP
VIN
VDD
VDD
PH1=high
PH1
M1
M2
M3 M4
M5M6M7
M8
0
0
0
(a)
(b)
VDD
Figure 11. Kickback reduction method from [30]: (a) reset phase, (b) regeneration phase.
Reference [29] offers a similar method for decoupling the input pair from the rest of
the comparator by inserting additional nMOS switches between the input pair and the re-
generative phase (instead of external switches as in [30]); and connecting the input pair
sources directly to ground, therefore avoiding the kickback coming from the clocked tail
(Figure 12). The XNOR operation of the comparator outputs controls the gate of the ad-
ditional transistors M5 and M6 in Figure 12: when the outputs are equal to VDD, the input
transistors are connected. After the comparator has made a decision, which implies that
one output is low and the second one is high, the transistors turn off.
28
ClockClock
M1 M2 M3
VDD
Clock
M4
Voutp
Voutn
Voutp
Voutn
M5 M6
VIP VIN
Figure 12. Kickback reduction as in [29].
The work in [31] proposes placing common-gate amplifiers between the input pair
transistors and the regenerative/reset transistors in order to block the kickback noise. The
works in [32], [33], [34] propose similar methods, but with clocked common-gate transis-
tors. When the clock is low, the output and internal nodes are pre-charged to VDD, but the
drain/source input nodes are isolated such that only clock feedthrough is coupled, which
is much lower than the VDD.
Reference [35] uses dummy input pair, where the voltage is reset to 0V and increases
from 0V to VDD, instead of falling from VDD to 0V as in the conventional case. This creates
the opposite coupling effect and cancels a large portion of the kickback. The double-tail
comparator structure, as in [28], naturally provides shielding between the input and output
and therefore produces less kickback. Eventually, we chose the clocked common-gate
structure for its simplicity and effectiveness.
29
2.4 The offset problem and foreground offset calibration methods
Low-power comparators are typically designed with small device dimensions to min-
imize parasitic capacitances, which also benefits the achievable speed [36]. This approach
increases the input offset that is inversely proportional to the dimensions as shown in
equation (2.1), where THV
is the threshold voltage standard deviation, W is the transistor
width, L is the length [17], and AVTH is a process coefficient.
WL
ATH
TH
V
V (2.1)
The random offset of a differential pair can be estimated with equation 2.2 [37]:
R
R
S
SVVVV
THGS
THOS
2,1
2,12,1
2,12
(2.2)
ΔVTH1,2 is the threshold mismatch of the input differential pair, ΔS1,2 is a physical dimen-
sions mismatch of the input pair transistors, and ΔR is the effective load resistance
mismatch of M7-M14 in Figure 6.
Transconductance can be expressed as:
THGSVV
Igm
2,12
(2.3)
From (2.2) and (2.3), the following can be derived in a simplified way as in [38]:
W
W
gm
IV
OS
2,1
2,1 (2.4)
From the above equations, the offset depends on the input voltage. One way to reduce
the offset is to reduce VGS by controlling the tail transistors M5 and M6 in Figure 6. Usu-
ally, reducing the offset by tuning devices mismatches is not enough and requires
compromising other specifications as speed and power.
30
To ensure sufficient linearity in a standalone flash ADC it is required to satisfy the
condition 3∙σ < LSBFlash/2. In a 3-bit case, for instance, LSBFlash = 125mV with 1Vp-p full-
scale swing. However, when the flash ADC is part of a hybrid ADC, its comparators must
satisfy the overall ADC resolution. With a full-scale swing of 1Vp-p in this design, a target
offset specification of 3∙σ < LSBHybrid/2 ≈ 2mV was used since LSBHybrid = 1V / (28) =
3.9mV. Using large input pair transistors to reduce the mismatch offset is not an option to
achieve this goal because they increase the total input capacitance of the flash ADC as well
as the kickback noise. Since digitally-assisted design approaches are effective in increasing
robustness to process variations with system-level design flexibility, this thesis research was
aimed at developing a digital offset calibration for flash ADCs within hybrid ADCs.
Most offset reduction methods involve similar principles: Offsets are caused by mis-
matches that lead to an imbalance between the two main branches of the differential
comparator. Hence, to suppress the offset, an opposing imbalance can be introduced such
as by adding capacitance [38]-[40] or by injecting current [41]. For example, [38] uses
varactors and [7] uses banks of capacitors.
With addition of capacitance, the imbalance is generated through the differences in
the charging and discharging rates at internal nodes. The link between the offset change
and capacitance change is given by the following equation [40]:
C
CVV
C
C
gm
IV THGS
OS2
2,1
2,1 (2.5)
where ΔC is the difference in capacitances of the two branches, and C is the sum of the
capacitances.
A current injection method can be implemented, for example, by connecting parallel
transistors at the input and modifying the effective transconductance of one device in the
differential pair. This approach is used in this thesis, and described in the next subsection.
31
2.5 Comparator with digitally programmable offset correction and
common-gate transistors for kickback reduction
VIP VINVRNVRP
Clock
Voutn
Clock
Voutp
Clock
Mtail1
M1 M2 M3 M4
Mtail2
M5 M6
M10M13 M11 M9
M8M7
VDD
Clock
Clock
Vfp
Vcp
M14
M15
M17
M12
Vfn
VcnM16
M18
Dip Din
Vregenp Vregenn
Dcgp Dcgn
Vtailp Vtailn
Figure 13. Dynamic latched comparator with kickback reduction and offset compensation circuitry.
The comparator design is depicted in Figure 13. Despite of the evident advantages of
the double-tail comparator, a conventional single-stage latch-type sense amplifier was
chosen. The double-tail comparator requires both clock and inverse clock, which compli-
cates the design and adds more non-idealities due to the clock mismatches. Although
several works proposed different variations of double-tail comparators with only one clock
(e.g., [42] [43][44]), we decided to choose a more conventional structure for its on-chip
reliability and widespread use.
The kickback noise is reduced by placing the series nMOS switches (M5–M6 in Figure
13) between the input pairs (M1–M4) and the regenerative back-to-back inverters (M7–
M10). With this kickback reduction technique, the nodes at the drain of the input transistors
are floating during the reset phase instead of pre-charging to VDD. This results in less volt-
age variation at the drains of M1–M4 during the comparator’s operation, thereby reducing
the kickback noise at the input. In this design, the maximum kickback (absolute value) is
reduced from 23.3mV to 1.21 mV during transistor-level flash ADC simulations. Note
32
that simulations revealed that a kickback of 23.3mV would severely degrade the effective
number of bits (ENOB) of the hybrid ADC to 3.16 bits [10].
For offset compensation, two pairs of transistors (M15-M18) have been inserted to adjust
the offset of each comparator by creating a current imbalance between its branches. The
amount of current injected in each branch is controlled through the gate voltage of the cali-
bration transistors. For flash ADC calibration within the hybrid ADC architecture, using the
current injection method rather than the capacitor-based techniques (e.g., Appendix I) leads
to less extra parasitic capacitance as well as reduced kickback noise. Figure 14 displays the
comparator layout. For improved device matching, the input pair was drawn with an in-
terdigitated technique, and the two branches are completely symmetric. Figure 15 shows
the layout of the flash ADC with the seven comparators, resistive ladder with its kickback
reduction capacitors and the output buffers. The layout was optimized to have the shortest
path from the output buffers to the FFs’, decoders and the comparator-based asynchronous
binary search (CABS) of the hybrid structure, and from the switches following the sample-
and-hold circuit to the flash input, while allowing sufficient space to route the 28 calibra-
tion signals from the digital logic. The comparator occupies 28.7µm × 15.6µm (including
the substrate and pwell areas). The flash ADC occupies 213.6µm × 103.7µm. Table 1
summarizes the comparator dimensions.
input
reset
CG kickback
reduction
tail
outputfine
coarse
regenerative
inverters
reset
outputfine
coarse
Figure 14. Comparator layout.
33
7 Comparators
VIP VIN
Clock
flash ladder with kickback reduction
capacitors
28 calibration signals
output
buffers
T0T1T6 T5 T4 T3 T2
Figure 15. Flash ADC layout with resistors ladder.
Table 1. Comparator dimensions
Transistor Role Dimensions W/L
[µm/nm]
Fingers Multiplier
1 Mtail1,Mtail2 tail transistors 1 µm /120 nm 2 1
2 M1,M2,M3,M4 input pairs 2.88 µm /120 nm 3 1
3 M5,M6 kickback reduction 1.2 µm /120 nm 2 1
4 M7,M8 nMOS of regenerative stage 1.92 µm /120 nm 4 1
5 M9,M10 PMOS of regenerative stage 2.4 µm /120 nm 4 1
6 M11,M12,M13,M14 reset 1 µm /120 nm 2 1
7 Inverter pMOS output inverter 2.88 µm /120 nm 4 1
8 Inverter nMOS output inverter 0.72 µm /120 nm 1 1
9 M15,M17 coarse calibration 0.28 µm /120 nm 1 1
10 M16,M18 fine calibration 0.28 µm /1.12 µm 1 1
34
3. Flash ADC Calibration Scheme
The flash ADC calibration scheme is designed to calibrate the comparators while em-
ulating the normal system operation of the hybrid ADC. In section 3.1 the hybrid ADC
architecture is shortly described. Section 3.2 elaborates on offset sources of the flash ADC.
Section 3.3 describes the digital calibration implementation. Section 3.4 presents the
memory block. Section 3.5 is dedicated to input signal generation of the calibration path
and the wide-swing operational amplifier design.
3.1 Flash ADC in a hybrid ADC architecture
The designed 3-bit flash ADC was integrated as coarse ADC in an 8-bit hybrid ADC,
where the remaining 5-bits are resolved by the successive approximation register (SAR)
ADCs in the second stage (Figure 16). The SAR ADCs in this hybrid architecture [10] is
a comparator-based asynchronous binary search (CABS) type. A sample-and-hold and
capacitive digital-to-analog converter (SHDAC) circuit samples the input voltage, and
also shifts it to the optimal voltage range (for linearity performance) of the second stage
based on the flash ADC output bits. A 3-bit high-speed flash ADC helps to reduce the
number of cycles for the SAR (CABS) ADC in the second stage, resulting in a faster
overall conversion rate.
The design details of the hybrid ADC are outside of the scope of this thesis, but it is
worthwhile to examine a key flash ADC design consideration in this application as dis-
cussed in Section 2.4. In a conventional standalone flash ADC, the use of comparators
having an offset of 3∙σ < LSB/2 would suffice, where σ is the statistical standard deviation
of the offset voltage. However, since this flash ADC is utilized as first stage of an 8-bit
hybrid ADC, the offset requirement is significantly more stringent and must comply with
the 8-bit ADC requirement; i.e., 2mV with a 1Vp-p differential full scale range. This offset
requirement helps to prevent nonlinearity errors in the hybrid ADC, but creates the design
challenge of having to ensure low input offset in the flash ADC. Therefore, an offset re-
duction technique is needed to achieve the required accuracy.
35
SHDAC Buffer
CLKSAMPX.1
CLKSAMPX.2
Control.1CLKSAMP.1
5bSHDAC
CABS
ADCBuffer
CLKCABS.1
Control.2CLKSAMP.2
Vin Flash
ADC
On-Chip
Calibration
System
CLKFlash
SHDAC Ctrl
Flash Enc
3b x 4
Co
ntr
ol.
1C
on
tro
l.3
Co
ntr
ol.
4
CLKSAMPX.CAL
7 T
herm
o.
Co
ntr
ol.
2
SHDAC CAL
Control.CALCLKSAMP.CAL
SHDAC Buffer
CLKSAMPX.4
CLKSAMPX.3 CLKCABS.3
Control.4CLKSAMP.4
SHDAC Buffer
CLKCABS.4
Control.3CLKSAMP.3
5bCABS
ADC
CLKCABS.2
CABS
ADC
CABS
ADC
5b
5b
Figure 16. Hybrid ADC architecture from [10].
3.2 Offset sources in flash ADCs
The offsets of the flash ADC comparators have two sources: the main one is random
static offsets from device mismatches, and the second one is small systematic offsets
caused by common-mode voltage (VCM) variations at the flash input. The VCM variations
originate from asymmetric charge injection from the sampling switch after sampling, and
from kickback noise of the flash ADC. Because of the low common-mode rejection ratio
(CMRR) of the comparator architecture, a difference of common-mode level between the
reference voltage and the input voltage also causes an offset. Figure 17 shows the simu-
lated offset as a function of common-mode voltage difference between the input and the
reference of each comparator. The overall systematic offset is higher for higher input am-
plitudes, creating larger gate-source voltage differences for the comparator input
transistors that cause asymmetric characteristics. One technique to overcome the system-
atic offset is changing the common-mode voltage of the reference ladder in the flash ADC
36
to an optimum value. This can suppress the flash input common-mode variation for all
input levels, and can be done by shifting the VRP and VRN of the flash ADC in one direction
by the same amount. However, to ensure the proper operation in the presence of process
variations, the range of the offset calibration system for the flash ADC is designed to be
able to remove this systematic offset in addition to the random (mismatch) offset.
Common-mode Change (mV)
Off
set
(mV
)
Figure 17. Systematic offset versus input common-mode voltage variations.
3.3 Digital calibration implementation
Figure 18 illustrates the block diagram of the closed-loop foreground offset calibra-
tion. The system automatically controls the gate voltages of the coarse tuning transistors
(M15-M16) and fine tuning (M17-M18) transistors for current injection within each compar-
ator (Figure 13) to achieve the required input-referred offset. The coarse transistors have
a larger W/L ratio than the fine transistors, such that a change of their gate voltage leads
to more drain current change and therefore more offset adjustment. During calibration
mode, the flash ADC input is disconnected from the main signal path, and successively
connected to each of the 7 reference voltages via an extra sampling path identical to the
ones in main ADC channels.
37
Flash
ADC
7SHDAC
CAL
CLKSAMP.CAL
CLKSAMPX.CAL
Control
Memory
SHDAC 3
1.2V 500mV
520mV1.18V
SHDAC 4
SHDAC 1
SHDAC 2
VcpVcnVfp Vfn
Decoder
37
Comparator
Calibration
LogicBuffer
1.1 V
0.1 V
counter[6:0]
VCM
reset
calib_done
counter[6:0]
Fin
e.b
in[5
:0]
Co
ars
e.b
in[4
:0]
polarity[6:0]
coarse[17:0]
fine[35:0]
QD
clk
CLKSAMPX.CAL
500mV 500mV
50
50
to emulate the matching
network at the ADC input
counter_ctrl[2:0]
Figure 18. Flash ADC offset calibration system (single-ended equivalent).
The calibration range was selected to cover 3∙σ of the random offset in addition to
the systematic offset. The coarse correction has an offset step size of 23mV, and the fine
correction has a step size slightly smaller than 1.4mV. The coarse correction and fine cor-
rection are controlled by a digital-to-analog converter (DAC) with 36 levels. The DAC
that generates the coarse and fine voltages is implemented with one resistor ladder that
has a voltage range from 500mV to 1.2V with steps of 40mV and 20mV for coarse and
fine tuning, respectively. Figure 19 shows offset coverage for the seven comparators in-
side the system when sweeping the coarse voltage from 500mV to 1.18V for both positive
and negative offset polarities with steps of 40mV, while the fine voltage is set to minimal
and maximal values (500mV and 1.2V). The zigzag characteristic of the plots is due to
overlaps of the offset compensation regions defined by the digital coarse codes. The com-
pensation range is designed to have enough overlaps to ensure that no offset value is
missed by the calibration. Each comparator has a different coverage range for the same
38
control code because the offset shift through current injection depends on the imbalance
of a comparator’s differential reference voltages (VRN, VRP in Figure 13). The top and
bottom comparators (±375mV reference levels) have the widest coverage range, while the
middle comparator (0mV reference level) has the least coverage.
Figure 19. Offset calibration range of the comparators within the system.
The calibration scheme is structured to mimic the hybrid ADC’s normal operation.
During the calibration mode, all switches between the main SHDACs (1-4) and the flash
ADC input in Figure 18 are opened. Instead, the CLKSAMPX.CAL signal activates the sam-
pling in the calibration channel. The calibration is executed serially for each comparator
and fine/coarse tuning transistors inside the comparator. The counter bits from the control
logic set the switches of the resistor ladder DAC to generate the corresponding reference
voltage for each comparator. This DC input voltage is applied through a buffer to be sam-
pled by SHDAC CAL. The unity-gain buffer in Figure 18 is required to drive the SHDAC,
and to isolate the input reference generation DAC from the kickback noise of the flash
ADC. A wide-swing operational amplifier with low output resistance was designed for
this buffer in the calibration path. The amplifier, which is powered down during the ADC’s
normal mode of operation, is discussed further in Section 3.5.1 .
39
YES
Polarity Detection
Coarse calibrationCycling through coarse codes
500mV:40mV:1.2V
Calib. begin
i <=7
Voi is latched
i=1
polarity
flipped
Fine calibrationCycling through fine codes
500mV:20mV:1.2V
polarity
flipped
Calib. DoneNO
YES
NO
NO
YES
YES
NO
YES
coarse code
is 1.2V
fine code is
1.2V
NO
i=i+1
Figure 20. Flow chart of the calibration.
The outputs of the comparators in Figure 18 are latched with DFFs that are
clocked by an inverted version of CLKSAMPX.CAL. Figure 20 illustrates the calibration algo-
rithm flow chart. At the beginning of each cycle, the proper differential input reference level
is set for the comparator under calibration. Next, the polarity of the offset is determined
according to the latched comparator output. Afterwards, the coarse calibration process be-
gins by sweeping the 5-bit coarse code to set the switches for the coarse calibration voltage
with steps of 40mV. The coarse calibration stops when the comparator output flips to a
different state from the initially detected polarity, which triggers the start of the fine calibra-
tion. If the offset reaches the maximum coarse calibration voltage and the output does not
flip, then the coarse calibration stops and fine calibration begins automatically. Otherwise,
the stored code is set to one code before the flipping of the comparator output, such that the
comparator returns to its original polarity. Next, the gates of the coarse tuning transistors in
the comparator are set to voltages corresponding to the code at which the coarse calibration
40
stopped. Then, the fine calibration proceeds in the same manner but with voltage steps of
20mV. At the end of the fine calibration, a “calib_done” signal resets all state machines and
calibration codes, and starts the next comparator calibration. The control block also incre-
ments the counter to activate different switches at the resistor ladder that generates the
differential reference voltage for the next comparator. In each cycle, the calibration codes
are stored in the memory, which directly sets the switches of the coarse and fine calibration
DACs. It was observed from Monte Carlo simulations that a minimum of two consecutive
calibrations are required to obtain correct offset compensation codes because the calibration
converges to smaller residual offset when the systematic offset at the start of the calibration
cycle has already been reduced through a prior cycle. To ensure reliable operation, the cali-
bration was designed to sequentially cycle through the comparators three times.
Figure 21 displays the complete layout of the calibration circuitry, including the in-
terface to the pad frame. The calibration logic occupies 667µm x 661µm. The complete
on-chip digital calibration circuitry occupies 1300µm × 750µm (0.68mm2 after subtracting
the 30% empty space), which includes the digital calibration logic, DACs, low-bandwidth
unity-gain buffers, and one extra SHDAC. The power consumption of all digital circuits is
1.36mW from a separate 1.2V digital supply; which includes the DFF sets, control logic for
the SHDACs, and the thermometer-to-binary output encoders for the flash ADC. The esti-
mated power consumption of the calibration system is 600µW when it is activated with a
10MHz clock. Since the offset calibration is a foreground method, its power consumption
is not affecting the total ADC power during normal operation.
41
Connection of the
calibration DAC to
flash ADC
Comparators 7
outputs for
calibration
Calibration
Logic
Calibration
DAC
Input generation
buffers with bias
current mirrorsInputs to the
calibration SHDAC
Decoupling
capacitors
Figure 21. Layout of calibration circuitry.
3.4 Memory block
The memory block stores all codes (fine, coarse, and polarity) of the calibration logic
for the seven comparators. The block diagram of the memory structure can be seen in
Figure 22. The fine code has 36 levels: 500mV to 1.2V with steps of 20mV (6 bits for
binary representation). The coarse code has 18 levels: 500mV to 1.2V, with steps of
40mV, where the last step from 1.18V to 1.2V is 20mV (5 bits for binary representation).
The polarity code has 1 bit. The memory directly controls the switches, such that the codes
are stored in their thermometer representation. Therefore, the size of the memory
(MEM_CORE block in Figure 22) is 36+18+1 = 55 bits multiplied by 7 for the number of
42
Figure 22. Memory block and auxiliary digital components of the on-chip calibration logic.
comparators. Because the calibration logic yields binary representation of the codes, the
coarse code is converted from 5 bits binary to 19 bits through a decoder, and the fine code
is converted from 6 bits binary to 36 bits. The memory supports external writing of manual
codes, as well as reading of either manual or automatic calibrated codes. To reduce the
number of the chip package pins, the external decoder and encoder were designed to con-
vert data of 6 bits for fine and 6 bits for coarse (5 bits) plus polarity (1 bit). A 3-bit pin
address_ext[2:0] represents the comparator number, where 001 corresponds to the com-
parator with the lowest differential reference (-375mV), and 111 corresponds to the
comparator with the highest differential reference (+375mV). The 1-bit pin ad-
dress_ext[3] determines if the written or read code is coarse and polarity (for
address_ext[3] = 0), or whether it is a fine code (for address_ext[3] = 1). Table 2 lists the
described decoding actions. If mem_ext_en is 1, the MEM_CORE receives external data,
otherwise the data comes from the calibration logic.
43
The bi-directional analog multiplexer (MUX) either writes to memory (when
RW_mux = ‘1’) or reads from memory (RW_mux = ‘0’). In this way, the reading and writ-
ing operations are performed from the same pin, which avoids six additional external pins.
Table 2. External memory decoder
address_ext[3] mem_in_ext[5] mem_in_ext[4] mem_in_ext[3] mem_in_ext[2] mem_in_ext[1] mem_in_ext[0]
0 coarse [4] coarse [3] coarse [2] coarse [1] coarse [0] polarity
1 fine [5] fine [4] fine [3] fine [2] fine [1] fine [0]
3.5 Analog circuitry for input generation in the calibration path
To automatically calibrate the seven comparators of the 3-bit flash ADC, an input that
equals the specific reference of each comparator must pass through the same path as the
regular signal, which ensures similar transient effects such as kickback and feedthrough.
Figure 23 displays the block diagram of the input generation path. The input is generated
from a conventional ladder with polysilicon resistors (oprppres in the GlobalFound-
ries130nm CMOS process design kit). Compared to diffusion resistors, polysilicon
resistors have high precision and therefore are more immune to PVT variations at the ex-
pense of chip area.
For matching purposes, two resistors of 1.057kΩ (with width of 4µm and length
of 18µm) are connected in parallel using a semi-common centroid layout structure (Figure
24). Two sets of seven transmission gate switches are controlled by the calibration logic
for a proper input voltage connection. Each set passes the input signal to the two high-
swing operational amplifiers with unity-gain connection, which act as buffers. Resistors
R9-R12 in Figure 23 emulate the balun termination of the hybrid ADC, which are precision
polysilicon resistor oprppres_inh (best tolerance) with resistance of 49.75Ω, width of
20.17µm, and length of 4µm. Vcm is the common-mode voltage of the hybrid ADC, which
is 600mV. Hence, the generated voltages were shifted accordingly. For example, for
CTRL[6] = ‘1’, the upper buffer receives 975mV, which after voltage division results in
44
VIPSHDAC = 787.5mV. For the same case, the second buffer receives 225mV, which gen-
erates VINSHDAC = 412.5mV after voltage division. Therefore, the differential voltage
becomes VIPSHDAC - VINSHDAC = -375mV.
VRL
VRH
Wide-Swing
OP-AMP
Wide-Swing
OP-AMP
VcmSHDAC
CAL
R9
R10
R11
R12
CTRL[6:0]
CTRL[0]
CTRL[0]
1.1 V
100mV
975 mV
850 mV
725 mV
600 mV
475 mV
350 mV
225 mV
VIPSHDAC
VINSHDAC
R1
R2
R3
R4
R5
R6
R7
R8
Figure 23. Circuits at the input of the calibration path.
R1
R8
R2
R7
R3
R6
R4
R5
R5
R4
R6
R3
R7
R2
R8
R1
Figure 24. Floor plan of the resistor ladder.
45
Figure 25. RON for the complementary switch (transmission gate), nMOS switch, and pMOS switch.
The transmission gate switches in Figure 23 are composed of complementary
nMOS and pMOS transistors with sizes of 2µm/120nm (nMOS) and 8µm/120nm (pMOS).
This topology has two main advantages. First, it allows full scale voltage swing because
the nMOS conducts well for low voltages (for 0 < VIN < VDD-VTHN), and the pMOS con-
ducts well for high voltages (for |VTHP| < VIN < VDD). This feature is critical for this design
because the input voltages are close to the rails. Secondly, the equivalent ON resistance
(RON) is more constant over a wide input range than for a single nMOS or pMOS
switch [45]. Figure 25 shows the simulated ON resistance (RON) for a complementary
switch in comparison to that of switches with only nMOS switch and pMOS transistors.
Note that lower variations of RON reduce the harmonic distortions that are created. Since
the switching frequency is low (can be a few tenths of the long calibration clock cycle),
there are no stringent timing requirements for the complementary control signal alignment,
which is why a simple inverter is used at the pMOS gate.
The layout of the calibration input path occupies 263µm × 166µm excluding ref-
erence current generation, and is shown in Figure 26.
46
wide-swing operational amplifier
switches
resistor ladder
Figure 26. Layout of input signal generation circuits for calibration.
47
3.5.1 Wide-swing operational amplifier design
Figure 27. Wide-swing operational amplifier schematic.
The rail-to-rail operational amplifier [46] with single-ended output depicted in Fig-
ure 27 was designed in unity-gain configuration because this topology enables a wide
input common-mode range (from 225mV to 925mV in this case). This is achieved by two
complementary differential pairs (nMOS and pMOS) connected in parallel. The nMOS
pair (M1-M2) is mostly active for high input common-mode voltages, while the pMOS pair
(M3-M4) is active for low input common-mode voltages. A folded cascode structure is
formed by transistors M13-M14 and M19-M20. The input voltage is converted to current that
flows into the common-gate transistors of the folded cascode stage. M11-M12 and M21-M22
48
are biasing transistors, where M11 and M21 are connected in a diode connection with im-
proved swing, which gives one threshold voltage more headroom compared to a classical
diode connection. Although a folded cascode has lower gain, higher noise and consumes
more power compared to a “telescopic” amplifier (because separate biasing is required for
the input and cascode stages), the latter suffers from limited swings. This is due to stacked
transistors on top of the input pair. A folded cascade, on the other hand, can have common-
mode levels close to one of the rails. In addition, a telescopic amplifier is not suitable for
a unity-gain configuration as used for the calibration buffer in this design. When deriving
the conditions for which the input and load transistors are in saturation, the allowable
voltage range turns out to be too small (less than the threshold voltage of a transistor),
which is described with more details in [22].
Transistors M17-M18 and M23-M24 in Figure 27 form a class-AB output stage to pro-
vide rail-to-rail swing. This is achievable with the complementary common-source
connections in the output stage. Note that transistors M15-M18 form floating current
sources, whose purpose is to maintain a relatively constant voltage difference between the
gates of M23 and M24. Figure 28 depicts a generalization of the floating class-AB control
circuit. The configuration with floating current sources provides constant current inde-
pendent of the input bias current, which occurs as follows: If Vin decreases, then more
current flows from the pMOS input (and less from the nMOS input), which reduces the
current through M11 (and increases the current through M21). As a result, the internal nodes
of the cascode stage VX and VY move up. Thus, the current through M15 increases, and the
current through M16 reduces by the same amount, such that the current across the cascode
branch is kept constant. In reality there are some deviations in the currents because the
transistors in a submicron process do not follow the square rule.
Conventionally, we would expect to have an input pair and a cascade summing circuit
followed by the class AB output stage, but in this design the floating current source of the
class AB control has been shifted to the summing stage. Therefore, no separate bias is
needed for the class AB stage, which would add more noise sources. Note that the current
gain between that stage and the preceding stage is 1, such that the input-referred noise
contribution is significant.
49
Figure 28. Class-AB control output stage.
Since the effective transconductance (gm) of the input stage in Figure 27 is the sum-
mation of gmN (gm of the nMOS pair) and gmP (gm of the pMOS pair), it highly depends on
the instantaneous input common-mode level and is doubled around the middle of the range
when both pairs are active. This variation is problematic because a nearly constant gm is
needed for some applications, as it affects parameters such as harmonic distortion, slew
rate, frequency compensation etc. One approach to overcome this problem is to double the
effective gm at the extremes of the input range to compensate for the inactive pair. This
can be done by using the fact that gm is proportional to square root of the current:
DoxpnmIC
L
Wg
,2 (3.1)
In [47], the current of the active pair is directed to a current mirror, then it is tripled and
added to the current of that pair, yielding 4·ID, which provides 2·gm with one pair as when
both pairs are active [47]. For this work, the amplifier in Figure 27 does not have gm-
control because constant gm is not required for the unity-gain configuration in the calibra-
tion path where it is used to pass DC voltages.
50
3.5.2 Calibration DAC
The calibration digital-to-analog converter (DAC) from Figure 18 (of the calibra-
tion system) that converts the digital code to an applied gate voltages is depicted in Figure
29. A shared resistors ladder consists of 35 P-type doped polysilicon resistors (opppcres)
of 1.055kΩ with width of 4µm and length of 12µm. The ladder generates 36 reference
levels between 500mV and 1.2V with steps of 20mV. A polarity bit determines which
branch receives the voltage level and which one remains at 500mV. Figure 30 displays the
layout of the DAC with the switches and MUXs, which occupies approximately 500µm ×
500µm.
Figure 29. Calibration DAC block diagram.
51
cali
bra
tio
n r
esis
tor
lad
de
r
7 sets of switchescoarse fine
mux
28 calibration outputs to the flash ADC
Figure 30. Calibration DAC layout.
52
4. Simulation Results
4.1 Comparator simulations
The comparator in Figure 13 and the flash ADC were simulated with a mix of tran-
sistor-level circuits having a supply of 1.2V in 0.13μm CMOS technology, and behavioral
Verilog-A components (for offset determination and calibration). The simulation was per-
formed in Cadence Spectre with the analog design environment (ADE-XL). Figure 31
shows schematic-level transient simulation results from the internal nodes of the middle
comparator (0V differential reference). During the simulation, the differential input was
toggled between -2mV and 2mV (2mV peak-to-peak single-ended, which corresponds to
1/2 LSB in this design).
Clock
Vin
Di
Vregenp
Vregenn
VOUT
Dcg
Vdsi
Figure 31. Comparator transient voltages from schematic-level simulations.
The drain of the common-gate transistors and all the nodes above it (Dcgp, Dcgn, Vregenp,
Vregenn in Figure 13) pre-charge to VDD at the reset phase when the clock is low. The Di
nodes (Dip and Din) are pre-charged to 0V through the calibration transistors. Initially,
Vregenp and Vregenn (the comparator output before inversion) start falling together from 1.2V
towards 0V, but as the positive input is higher than the negative input, the positive branch
53
draws more current and discharges faster. Therefore, a positive feedback discharges it fur-
ther towards 0V, and the corresponding Vregenn node charges back to 1.2V. Since a
conducting path to VDD is created at the rising edge of the clock, the Di node voltage rises
up to 260mV as evident from Figure 31, and then it falls back to 0V according to the
discharging rate of the positive feedback of the back-to-back inverters. Without the com-
mon gate, this node would be pre-charged to 1.2V instead of 260mV. Since for kickback
reduction purposes the VDS voltage of the input pair is of interest, and not merely VD, the
swing (Vdsi in Figure 31, which is Dip-Vtailp or Din-Vtailn in Figure 13) at the input pair is
even smaller: 169.35mV.
For comparison, Figure 32 shows the voltages at internal nodes from a schematic-
level simulation without the common-gate transistors for kickback reduction. In this case,
VDS is equal to 931.8mV for the input transistors. Table 3 provides a comparison between
the designed comparator and the same one without kickback reduction transistors. The
propagation delay is the time interval between the instant when the clock crosses VDD/2
and when the comparator output crosses VDD/2. The different comparators in the flash
ADC have different common-mode levels. Typically, the performance deteriorates as the
difference between the inputs grows, which is the worst for the extreme comparators 1
and 7 in the flash ADC. The propagation delay with and without kickback reduction is
similar, while the power dissipation is lower with kickback reduction because the Di nodes
do not reach the supply rails.
Figure 32. Comparator transient voltages from simulations without kickback reduction.
54
Table 3. Comparison between the comparator with and without kickback reduction transistors
based on schematic-level simulations
#
Comparator
Differential
Reference
[mV]
Propagation Delay [ps] Power [µW]
With Kickback
Reduction
Without Kickback
Reduction
With Kickback
Reduction
Without Kickback
Reduction
1 375 122.5 117.4 90.74 123.1
2 250 111.2 113.7 87.23 123.8
3 125 105.3 110.5 84.94 123.5
4 0 103.5 109.5 84.31 123.6
5 -125 105.4 110.5 84.95 123.5
6 -250 111.3 113.7 87.26 123.8
7 -375 122.7 117.5 90.81 123.1
Table 4 summarizes the simulated post-layout comparator specifications for the dif-
ferent differential reference levels when the comparator input toggles 4mV peak-to-peak.
The comparator and the load buffer of the comparator were both simulated with the ex-
tracted layout parasitics. Table 5 shows propagation delay and power from post-layout
simulations with PVT variations: for temperatures of -10°C, 27°C, 85°C; process corners of
SS (slow), FF (fast), TT (typical); and supply voltages of 1.14V, 1.2V, 1.26V. The worst
condition for propagation delay is SS, 1.14V, -10°C; which yields a delay of 231.4ps. The
worst case for power is FF, 1.26V, 85°C with a power consumption of 159.9µW.
Table 4. Comparator post-layout specifications with 4mV peak-to-peak differential input toggling
around different reference levels
Comparator Differential
Reference [mV]
Propagation Delay [ps] Power [µW]
1 375 164 120.2
2 250 156 112.3
3 125 150 109.2
4 0 149 108.3
5 -125 153 109.4
6 -250 163 112.7
7 -375 184 121.2
The simulation technique called “Dynamic Offset Test Bench (DOTB)” [48] was em-
ployed to evaluate the offsets. As depicted in Figure 33, the comparator’s differential
output passes through two flip-flops (FFs) triggered by the falling edge of CLK, after which
it is integrated and fed back to the input. The integrator output voltage accumulates until
it reaches equilibrium, which occurs when it corresponds to the comparator input offset.
55
Table 5. Comparator performance over PVT variations - post layout
Corner Process Voltage [V] Temperature [°C] Propagation delay [ps] Power [µW]
1 FF 1.14 -10 100.5 97.14
2 FF 1.14 27 102.9 111.4
3 FF 1.14 85 106.3 136.7
4 FF 1.2 -10 94.58 106.7
5 FF 1.2 27 97.24 121.3
6 FF 1.2 85 101.1 148.2
7 FF 1.26 -10 90.24 116.5
8 FF 1.26 27 93.08 131.6
9 FF 1.26 85 97.17 159.9
10 SS 1.14 -10 231.4 76.72
11 SS 1.14 27 228 85.31
12 SS 1.14 85 224.5 102.5
13 SS 1.2 -10 219.5 83.95
14 SS 1.2 27 217.1 93.86
15 SS 1.2 85 219.2 110.9
16 SS 1.26 -10 211 91.19
17 SS 1.26 27 210.2 102.3
18 SS 1.26 85 213.2 120.5
19 TT 1.14 -10 154.6 87.02
20 TT 1.14 27 157.4 99.14
21 TT 1.14 85 163.3 121.5
22 TT 1.2 -10 147.4 95.41
23 TT 1.2 27 150.4 108.2
24 TT 1.2 85 156.2 131.6
25 TT 1.26 -10 142.7 104.3
26 TT 1.26 27 145.7 117.7
27 TT 1.26 85 151.5 142.1
Figure 33. Offset simulation setup.
56
Nu
mb
er
of
Occ
urr
en
ces
Offset Voltage (mV)
Comparator 1
Nu
mb
er
of
Occ
urr
en
ces
Offset Voltage (mV)
Comparator 2
Nu
mb
er
of
Occ
urr
en
ces
Offset Voltage (mV)
Comparator 3
Nu
mb
er
of
Occ
urr
en
ces
Offset Voltage (mV)
Comparator 4
Nu
mb
er
of
Occ
urr
en
ces
Offset Voltage (mV)
Comparator 5
Nu
mb
er
of
Occ
urr
en
ces
Offset Voltage (mV)
Comparator 6
Nu
mb
er
of
Occ
urr
en
ces
Offset Voltage (mV)
Comparator 7
Figure 34. Monte Carlo simulation results (with transient noise) for 7 comparators in the flash ADC.
57
Figure 34 displays the histograms of the comparator offsets (with different common-
mode levels) from schematic-level Monte Carlo simulations with 100 runs, using defined
correlations for matched devices [49] of 0.9 and activated transient noise. The offset stand-
ard deviations are (starting from comparator 1 with the lowest differential reference):
17.57mV, 11.52mV, 9.06mV, 8.403mV, 9.027mV, 11.3mV and 16.71mV. For the middle
comparator, the calibration transistors can cover from -104.5mV (for coarsen and finen of
1.2V) to 123.7mV (for coarsep and finep of 1.2V), which was over-designed for 3σ and sys-
tematic offsets. Figure 35 shows one statistical corner example to demonstrate how offset
is determined with the DOTB method. Once the comparator reaches equilibrium and tog-
gles, the integrator output converges around 44mV, which is the estimated offset.
Co
mp
ara
tor
ou
tpu
t (V
)
Inte
gra
tor
ou
tpu
t (m
V)
time (ns)
Figure 35. Offset determination example with the DOTB method.
58
4.2 Flash ADC simulation results
The flash ADC, resistor ladder for generation of reference voltages, DFFs, and ther-
mometer-to-binary encoders were designed on the transistor level; and their extracted
view was used for post-layout simulations. For standalone evaluation of the flash ADC,
an ideal 3-bit DAC was employed to reconstruct the output. The flash ADC has been in-
tegrated into the hybrid ADC structure with four time-interleaved SAR (CABS) ADCs as
described in Section 3.1. In order to relax the propagation delay requirements on the sys-
tem level, there are four sets of DFFs and thermometer-to-binary encoders in the hybrid
ADC architecture. For the standalone flash ADC simulations summarized in this section,
only one set was used and clocked with a high-speed 1GS/s signal instead of a 250MHz
sampling clock. The other four sets of DFFs were connected to establish more realistic
loading as part of the extracted top-level cell, but the clock for them was disabled.
For ENOB (effective number of bits), SNDR (signal-to-noise-and-distortion ratio)
and SFDR (spurious-free dynamic range) evaluations, the inputs of the flash ADC were
fed through a differential balun model with a sinusoidal input of 1V peak-to-peak and 50Ω
termination for impedance matching. Figure 36 shows the SNDR and SFDR versus input
frequency for a number of frequencies over the Nyquist bandwidth (500MHz) from sche-
matic simulations with transient noise. It can be observed that a relatively constant SNDR
and SFDR are maintained over a wide range of frequencies.
Figure 36. Simulated SNDR and SFDR of the 3-bit flash ADC vs. input frequency.
59
The ENOB can be calculated with equation 4.1 below [50]. For an ideal ENOB of 3
bits, the best SNDR that can be achieved is 19.82dB, which is close to the value of 19.45dB
calculated from the worst-case simulation result in Figure 36. The SFDR is above
26.75dBc. A rule of thumb for SFDR is 20·log(2bits/INL), which implies that the SFDR is
lower for ADCs with a small number of bits. Therefore, 27dB may seem small compared
to ADCs reported in the literature with a higher number of bits. However, it is similar
to [51], which has a SFDR of 28.5dB for 4-bits, and 24.6dB and 28dB for other reference
works summarized in Table 1 of [51].
02.6
76.1)(
dBSNDRENOB (4.1)
The test frequencies were chosen based on the coherent sampling principle with a
sampling frequency of fs = 1GS/s, M = 1024 number of samples, and varying number of
cycles contained in the data record from N = 3 to N = 503 (prime numbers). The input
frequency is selected according to equation 4.2 below from [52]. In this way, there are no
repeating data patterns because there are no common factors between the number of input
periods and the number of samples in the data.
sin
fM
Nf (4.2)
Table 6 summarizes the simulated flash ADC performance with PVT variations for
a low input frequency (fin = 2.923MHz and N = 3 from equation 4.2) and a close-to-
Nyquist input frequency (fin = 491.21MHz and N = 503 from equation 4.2). The variations
include temperatures of -10°C, 27°C, 85°C; slow (SS), fast (FF), typical (TT) process
corner cases; and supply voltages of 1.14V, 1.2V, 1.26V. The worst case ENOB (2.88
bits) and SNDR (19.1dB) occurs with the SS process corner, 85°C, and 1.14V.
60
Table 6. Flash ADC schematic performance over PVT corners
Corner (Process, Voltage[V]
and Temperature [°C])
fin = 2.923MHz fin=491.21MHz
SNDR SFDR ENOB SNDR SFDR ENOB
1 FF 1.14 -10 19.45 26.95 2.938 19.49 27.15 2.945
2 FF 1.14 27 19.44 27.12 2.936 19.4 27.07 2.93
3 FF 1.14 85 19.31 27.33 2.916 19.28 27.06 2.91
4 FF 1.2 -10 19.44 26.97 2.938 19.48 27.07 2.944
5 FF 1.2 27 19.45 27.21 2.938 19.41 26.97 2.932
6 FF 1.2 85 19.34 27.37 2.921 19.29 27.12 2.913
7 FF 1.26 -10 19.44 26.96 2.938 19.5 27.16 2.947
8 FF 1.26 27 19.42 26.99 2.934 19.47 27.12 2.941
9 FF 1.26 85 19.35 27.17 2.922 19.33 27.08 2.918
10 SS 1.14 -10 19.45 26.63 2.938 19.52 27.1 2.95
11 SS 1.14 27 19.47 26.76 2.941 19.55 27.27 2.955
12 SS 1.14 85 19.11 26.81 2.881 19.53 27.25 2.951
13 SS 1.2 -10 19.45 26.63 2.938 19.52 27.16 2.95
14 SS 1.2 27 19.47 26.76 2.941 19.54 27.26 2.953
15 SS 1.2 85 19.44 26.83 2.938 19.54 27.37 2.954
16 SS 1.26 -10 19.46 26.73 2.94 19.52 27.12 2.951
17 SS 1.26 27 19.47 26.76 2.942 19.52 27.13 2.95
18 SS 1.26 85 19.47 26.95 2.943 19.54 27.34 2.954
19 TT 1.14 -10 19.47 26.76 2.941 19.5 26.9 2.947
20 TT 1.14 27 19.43 26.71 2.935 19.55 27.34 2.955
21 TT 1.14 85 19.44 27.01 2.938 19.49 27.23 2.945
22 TT 1.2 -10 19.46 26.71 2.94 19.53 27.18 2.951
23 TT 1.2 27 19.46 26.75 2.94 19.52 27.04 2.95
24 TT 1.2 85 19.44 26.96 2.938 19.53 27.56 2.952
25 TT 1.26 -10 19.46 26.71 2.94 19.51 27.06 2.948
26 TT 1.26 27 19.48 26.8 2.943 19.52 27.11 2.951
27 TT 1.26 85 19.44 26.9 2.937 19.54 27.52 2.953
For differential nonlinearity (DNL) and integral nonlinearity (INL) evaluation before and
after calibration, a slow sawtooth (ramp) signal was applied to the input with predefined
10 samples for each code (for resolution of 0.1 LSB). The duration of each code, normal-
ized by the number of the samples gives the DNL. This method is analogous to histogram
testing. The INL and DNL are limited by comparator mismatches and resistor ladder mis-
matches [53], but here the evaluation takes only the comparator mismatches into
consideration to assess the effectiveness of the calibration. Monte Carlo schematic simu-
lations with 50 samples were completed with a correlation of 0.9 for transistors matched
in the layout, yielding a DNL of up to 0.4 LSB. Figure 37 displays the histogram of the
DNL with standard deviation of 0.148 LSB. For the worst-case statistical corner from the
Monte Carlo samples, each of the seven comparators was calibrated with a Verilog-A
calibration module, and afterwards the corresponding voltage levels of the codes were
61
applied as ideal DC voltage sources connected to the calibration transistors gates. With
this setting, a new INL/DNL simulation was repeated.
Table 7 summarizes the applied voltage levels at the gates of the calibration transistors
in the comparators. Figure 38 shows the corresponding INL and DNL before and after
calibration. The DNL after calibration improved from 0.4LSB to 0.1LSB, while the INL
improved from 0.3LSB to 0.1LSB. To save simulation time, the ideal Verilog-A calibra-
tion module operates at 1GS/s instead of 10MHz as the real calibration block. One set of
DFFs was clocked at 1GS/s accordingly (instead of 250MHz as in the hybrid ADC under
normal operation).
Figure 37. Monte Carlo DNL simulation results with a correlation of 0.9 without calibration.
Table 7. Calibration voltages for INL/DNL testing of one statistical corner
comparator coarsep [mV] coarsen [mV] finep [mV] finen [mV]
1 500 580 500 600
2 620 500 580 500
3 500 580 500 560
4 500 580 500 520
5 500 700 500 660
6 580 500 540 500
7 500 620 500 680
62
DN
L (
LS
B)
INL
(L
SB
)CODE
CODE
Figure 38. DNL and INL before and after calibration with the worst-case statistical corner.
Ma
gn
itu
de
(d
B)
Frequency (Hz)
Spectrum after calibration for f in = 6.836 MHz
Spectrum after calibration for f in = 487.3 MHz
Frequency (Hz)
Ma
gn
itu
de
(d
B)
Figure 39. Output spectra with fin = 6.836MHz and fin = 487.3MHz after calibration (post-layout).
63
Figure 39 displays the output spectra of the flash ADC from simulations with transient
noise and a 6.836MHz 0.5Vpeak differential input as well as a 487.3MHz input close to
Nyquist frequency after calibration. The top cell with all the flash ADC circuitry and ex-
tracted layout parasitics was used for these simulations, which includes the comparators,
resistor ladder, five sets of DFFs, and four sets of thermometer-to-binary encoders.
A systematic offset of 30mV was intentionally introduced at the flash input (with
ideal voltage sources of 15mV and -15mV at the positive and negative inputs, respec-
tively). The codes for each comparator were extracted with the Verilog-A calibration
module, and afterwards applied as ideal DC voltage sources connected to the gates of the
calibration transistors in the comparators. Table 8 lists the corresponding voltages of the
extracted codes. Even though the systematic offset is the same for all comparators and
there is no kickback for the standalone flash ADC (because the inputs are ideal), the codes
for each comparator are different because of the different common-mode levels. Since the
introduced offset is positive in this simulation case, the N side (coarsen) is calibrated while
the P side (coarsep) is kept at 500mV by the control logic. This characteristic occurs be-
cause the positive offset indicates that the positive branch is discharging faster, such that
the negative side is calibrated to drive more current and catch up with the positive side.
Table 9 summarizes SNDR, SFDR and ENOB from post-layout simulations for low and
close-to-Nyquist frequencies. Here, the improvement is small because the offsets are ac-
ceptable for a standalone 3-bit flash ADC (less than 0.5LSB, which is 62.5mV). On the
other hand, the system-level measurements in Section 5.4 demonstrate the significant per-
formance improvement for the hybrid ADC. The flash ADC consumes 3.61mW of power
based on simulations, excluding the calibration logic. Table 10 summarizes the power
consumption of the flash ADC core (including the resistor ladder and the comparators),
the power of the latches, and the total power.
Table 8. Calibration voltage levels extracted with intentional 30mV systematic offset
comparator coarsep [mV] coarsen [mV] finep [mV] finen [mV]
1 500 620 500 640
2 500 660 500 680
3 500 700 500 640
4 500 740 500 560
5 500 700 500 620
6 500 660 500 700
7 500 660 500 520
64
Table 9. Post-layout SNDR, SFDR and ENOB for low input frequency (6.836 MHz) and close-to-
Nyquist input frequency (487.3 MHz)
fin [MHz] SNDR [dB] SFDR [dB] ENOB [Bits]
Before calibration 6.836 18.83 26.55 2.807 487.3 18.885 26.89 2.845
After calibration 6.836 19.505 26.99 2.948 487.3 19.515 26.96 2.949
Table 10. Post-layout power dissipation of the flash ADC core, sets of flash latches, and calibration
latch set
fin [MHz]
Power of flash
ADC core
[mW]
Power of flash
latches [mW]
Power of flash
calibration
latches [mW]
Total Power
[mW]
Before calibration 6.836 1.553 1.504 0.3385 3.346 487.3 1.536 1.928 0.3356 3.720
After calibration 6.836 1.507 1.449 0.3241 3.231 487.3 1.491 1.874 0.3216 3.608
65
4.3 Wide-swing operational amplifier
In this section, the post-layout standalone performance of the wide-swing opera-
tional amplifier (opamp) in Section 3.5.1 for the test input generation of the calibration
path is evaluated. The opamp is connected in unity-gain configuration, and is loaded with
its realistic load of 50Ω resistors as well as the post-layout view of the calibration SHDAC
as depicted in Figure 40. The interconnections between the blocks (including the bias cir-
cuitry of the input differential pairs) were made on the schematic level. When excluding
the bias current mirrors, the opamp consumes up to 6.3mW of power from a 1.2V supply.
The frequency response was simulated with the stability analysis (stb) tool while placing
a probe in the negative feedback of the amplifier to simulate the loop gain, bandwidth and
phase margin for different common-mode voltage levels and bias reference currents of
100µA and 150µA for the nMOS input pair and pMOS input pair, respectively. The results
are summarized in Table 11. The worst phase margin is 42.37° and the worst loop gain is
44.06dB. Figure 41 shows the simulated frequency response with a common-mode input
voltage of 600mV.
Vcm
SHDAC
CAL
LoadVin
Figure 40. Test setup for the wide-swing operational amplifier.
Table 11. Post-layout frequency response summary for the operational amplifier (stability analysis)
Common-Mode Input [mV] Loop Gain [dB] Bandwidth [MHz] Phase Margin [°]
225 50.29 2.025 43.43
350 51.31 1.922 42.37
475 50.14 2.068 44.18
600 48.89 2.205 46.08
725 48.3 2.203 47.3
850 48.37 2.042 48.24
975 44.06 2.255 52.96
66
Frequency (Hz)
Lo
op
Gain
(d
B)
Ph
as
e (
de
g)
Figure 41. Frequency response of the unity-gain operational amplifier.
Table 12. Simulated opamp post-layout performance with a common-mode input level of 600mV
and PVT variations
Corner (Process, Voltage[V]
and Temperature [°C]) Loop Gain [dB] Bandwidth [MHz] Phase Margin [°]
1 FF 1.14 -10 44.15 3.455 64.54
2 FF 1.14 27 44.86 3.338 62.82
3 FF 1.14 85 44.17 3.786 58.6
4 FF 1.2 -10 46.37 3.203 59.53
5 FF 1.2 27 46.42 3.278 55.25
6 FF 1.2 85 44.31 4.229 50.27
7 FF 1.26 -10 47.18 3.385 48.1
8 FF 1.26 27 46.16 3.778 46.17
9 FF 1.26 85 43.72 4.92 44.03
10 SS 1.14 -10 44.03 1.557 60.48
11 SS 1.14 27 46.97 1.527 53.57
12 SS 1.14 85 48.15 1.638 48.28
13 SS 1.2 -10 45.55 1.767 48.15
14 SS 1.2 27 47.36 1.851 43.33
15 SS 1.2 85 47.43 2.088 40.09
16 SS 1.26 -10 44.51 2.584 36.9
17 SS 1.26 27 46.21 2.534 34.22
18 SS 1.26 85 46.14 2.714 46.08
19 TT 1.14 -10 45.24 2.349 60.55
20 TT 1.14 27 47.71 2.083 56.04
21 TT 1.14 85 47.92 2.184 51.38
22 TT 1.2 -10 48.38 2.173 48.89
23 TT 1.2 27 48.89 2.205 46.08
24 TT 1.2 85 47.49 2.592 43.47
25 TT 1.26 -10 48.31 2.622 39.02
26 TT 1.26 27 48.16 2.718 38.46
27 TT 1.26 85 46.37 3.197 38.02
67
Table 12 lists the post-layout simulation results for a common-mode input level of
600mV over PVT variations for temperatures of -10°C, 27°C, 85°C; slow (SS), fast (FF),
typical (TT) processes; and voltages of 1.14V, 1.2V, 1.26V. The worst-case gain is 43.7dB
for the FF, 85°C, 1.26V conditions. The worst-case phase margin is 34.2° with SS, 85°C,
and 1.26V. The buffer output is within 598.9mV and 603mV.
The input common-mode range (ICMR) is the range of common-mode voltages
for which the amplifier exhibits the same desired differential gain. Figure 42 shows the
simulated transfer characteristic curve of the output versus input in unity- gain configura-
tion. The ICMR is approximately 1.07V, covering the desired range of 225mV – 975mV
for the application in the on-chip calibration.
VIN (V)
VO
UT (
V)
Figure 42. Input common-mode voltage range.
The simulated slew rate ranges from 149.8V/µs (for a transition from 850mV to
975mV) to 241V/µs (for a transition from 225mV to 350mV). For a settling error tolerance
of 1mV (up to 0.3%), the simulated settling time is up to 9.2 ns, which is sufficient with a
10MHz calibration clock. Figure 43 shows the simulated step response for the worst case
transition.
68
VO
UT (
V)
VIN
(V
)
Figure 43. Step response of the operational amplifier.
The output impedance was evaluated with an AC source connected to the output in
unity-gain configuration using the layout with extracted parasitics. The worst-case re-
sistance (real part of the impedance) looking into the output with feedback connection is
325.7mΩ, which is sufficiently low compared to the 50Ω resistors at the output.
PS
RR
(d
B)
Frequency (Hz)
Figure 44. Simulated PSRR curves of the unity-gain buffer after 100 Monte Carlo runs.
69
The power supply rejection ratio (PSRR), which represents the change of the out-
put voltage caused by a change in supply voltage, was evaluated with transfer function
(xf) analysis in Spectre. Figure 44 shows the PSRR vs. frequency plots obtained with 100
Monte Carlo runs (schematic level with unity-gain configuration and 600mV DC input
voltage) using defined correlation of 0.9 for transistors matched in the layout. The mini-
mum PSRR is 32.3dB at 10MHz and 38.86dB at 1MHz. For extreme common-mode
voltage levels (225mV as the worst case), the minimum PSRR is 28.35dB at 10MHz and
35.62dB at 1MHz.
The common-mode rejection ratio (CMRR) is the ratio of the differential gain to
the common-mode gain. Ideally the common-mode gain is 0, therefore leading to infinite
CMRR. The CMRR was simulated with AC analysis using the configuration depicted in
Figure 45, as presented in [54]. According to [54], CMRR = VC/VO (V/V) in this config-
uration. Figure 46 shows the simulated CMRR (in decibels) vs. frequency from 100 Monte
Carlo runs for an input common-mode level of 600mV. The worst-case CMRR at 10MHz
is 54.34dB (61.26dB at 1MHz), and the lowest CMRR for an extreme common-mode level
is 35.48dB.
Vcm
SHDAC
CAL
LoadVC
VC
Vo
Figure 45. Configuration for simulation of the CMRR.
70
CM
RR
(d
B)
Frequency (Hz)
Figure 46. Simulated CMRR curves after 100 Monte Carlo runs.
4.4 Behavioral Verilog-A model for the determination of offsets on the
hybrid ADC system level
The complete testbench for offset determination and calibration is presented in Figure
47. Since the calibration involves settling times and the calibration logic operates with a
clock frequency of 10MHz that is much lower than the ADC sampling clock, the simulations
with the AMS simulator in Cadence require an excessive time. For this reason, the DAC and
calibration logic were implemented with Verilog-A modules for Monte Carlo simulations,
while the other circuits and components are simulated on the transistor level. To further
reduce the simulation time, a binary search was used for offset determination instead of the
DOTB method described in Section 4.1. The testbench determines the offsets of all the seven
comparators numerically before calibration, then performs the calibration procedure seri-
ally, and determines the offsets again after calibration. Because the calibration code modifies
the comparator operation, which is coupled to the flash input as kickback, the calibration
codes of other comparators can be modified or affected. For this reason, the calibration pro-
cedure is executed for three cycles, where the most significant expected change is from cycle
1 to cycle 2. Since the simulation with transient noise impacts the offset determination, the
71
offset was evaluated five times to obtain an average. Each comparator is connected to the
Verilog-A module for the calibration as portrayed in Figure 47.
Figure 47. Offset determination and calibration testbench.
0ns 60ns 120ns 180ns 240ns 300ns 360ns 420ns
comp_cont
ref_diff
bin_en
clk_meas_bin
calib_meas_sel
Offset determination
cycle 2
Offset determination
cycle 1
Offset calibration
comparator #1
calib_en
(decimal representation)
-750mV
750mV
0mV
-500mV
500mV
-250mV
250mV
1
2
3
4
56
7
1
2.14us 2.34us
2
Offset calibration
comparator #2
Figure 48. Timing diagram for the offset determination.
72
The conceptual timing diagram for the system testbench is shown in Figure 48. Ini-
tially, all the control signals activate the path of the first comparator for its offset
determination:
1. The calibration is disabled (calib_en<i> is set to 0 for i = 1 to 7).
2. The controller of the digital MUX at the flash output (MUX 1 in Figure 47) takes
the output of the first comparator to be delivered to the binary search block.
3. Differential signal ref_diff = refn-refp is set to its corresponding reference, which
is -750mV (= 975mV – 225mV) for the first comparator and -500mV, -250mV,
0V, 250mV, 500mV and 750mV for the other comparators (2 - 7), respectively.
4. Digital MUX 2 and MUX 3 select the binary search input to be delivered to the
SHDAC.
5. bin_en transitions to high, activating the binary search procedure.
Figure 49 shows the simulated flash ADC input (differentially) for the 5 binary search
phases for offset determination, 3 cycles of constant input for each comparator calibration,
and 5 additional binary search phases for numerical post-calibration offset estimation. The
binary search block starts from 180mV (chosen to cover the complete offset range with
margin for variations). If the sampled signal is a logic “1”, then the binary search reduces
the input amplitude by half, otherwise it increases the amplitude by half. Eventually, the
binary search output converges to the estimated offset value. At the end, the bin_en signal
transitions to low and the controller activate the paths for the second comparator before
repeating the process. The clk_meas_bin signal is synchronized to the sampling clock of
the calibration (SCLK_CAL_2) and the inverse of the high-speed clock (CLK_BAR) to
sample the comparator output at the correct time. Figure 50 shows the binary search pro-
cedure of the nominal case before calibration of comparator number 7. The more steps
are allowed, the more accurate the binary search output becomes. In this design, we allow
11 steps (the number of clk_meas_bin pulses), which is more than sufficient.
73
Fla
sh
in
pu
t
Offset determination 5
times before calibration
Offset determination 5
times after calibration3 cycles of calibration
Figure 49. Flash ADC input with 5 offset determination phases, 3 cycles of calibration, and 5 offset
determination phases after calibration.
Fla
sh
in
pu
tB
inary
se
arc
h
ou
tpu
t
Co
mp
ara
tor
ou
tpu
t
Figure 50. Offset determination: binary search example.
74
Fla
sh
in
pu
tC
oars
e a
nd
fin
e v
olt
ag
es
Co
mp
ara
tor
ou
tpu
t
Figure 51. Example of calibration phase for the first comparator with the realistic flash input.
The controller Verilog-A block in Figure 47 enables calib_en<1> of the first com-
parator and disables all others such that only one comparator is calibrated at a time. The
Verilog-A based calibration is executed every high-speed clock cycle (1GS/s) instead of
the slow clock rate of 10MHz, which allows to reduce the simulation time by a factor of
100. The controller provides two complementary output signals that enable the corre-
sponding calibration block (Calib Logic in Figure 47) attached to each comparator and to
activate the corresponding switches of the resistor DAC at the input buffer (shown in Fig-
ure 18). Next, MUX 2 and MUX 3 disconnect the binary search input, connect it to the
buffer (controlled by calib_meas_sel in Figure 47 and Figure 48), and the binary search
path is disabled. A time of 200ns is dedicated for each comparator calibration. This in-
cludes 2ns for initial settling, 55ns for cycling through all codes (19 for coarse, and 36 for
fine), and a few cycles for transitions (initial polarity determination etc.).
75
Figure 52. Histogram of the first comparator offset (for -375mV differential reference) from 100
Monte Carlo runs in the presence of transient noise, before and after calibration.
Figure 53. Histogram of the second comparator offset (for -250mV differential reference) from 100
Monte Carlo runs in the presence of transient noise, before and after calibration.
76
Figure 54. Histogram of the third comparator offset (for -125mV differential reference) from 100
Monte Carlo runs in the presence of transient noise, before and after calibration.
Figure 55. Histogram of the fourth comparator offset (for 0mV differential reference) from 100
Monte Carlo runs in the presence of transient noise, before and after calibration.
77
Figure 56. Histogram of the fifth comparator offset (for +125mV differential reference) from 100
Monte Carlo runs in the presence of transient noise, before and after calibration.
Figure 57. Histogram of the sixth comparator offset (for +250mV differential reference) from 100
Monte Carlo runs in the presence of transient noise, before and after calibration.
78
Figure 58. Histogram of the seventh comparator offset (for +375mV differential reference) from 100
Monte Carlo runs in the presence of transient noise, before and after calibration.
Figure 52 - Figure 58 display the histograms of the offset values before and after cali-
bration for the seven comparators, which were obtained with 100 Monte Carlo simulation
runs of the calibration system with transient noise enabled. The offset standard deviations
before calibration were 18.01mV, 10.98mV, 8.61mV, 8.11mV, 9.29mV, 11.09mV, and
19.19mV. After calibration, these offsets reduced to 1.05mV, 741µV, 527µV, 447µV,
363µV, 593µV, and 582µV, respectively. The results are different than those reported
in [10] because the final design version of the fabricated flash ADC has been characterized
here, whereas the design in [10] is an earlier version. Note that the standard deviations within
the systems are different than that of a single comparator (presented in Section 4.1). This is
because the inputs for the single comparator were ideal, but in the system simulation the
loading effects of the other six comparators are taken into consideration together with the
preceding switches and SHDAC, and with realistic input generation path that modifies the
common-mode level.
79
4.5 Digital calibration – Verilog and schematic simulations
Analog and mixed-signal (AMS) simulations with Verilog view of the calibration
logic and transistor-level schematic of the remaining circuits were performed to test the
functionality of the complete calibration system. DC voltage sources with random offsets
up to ±72mV were introduced at each comparator input to artificially insert mismatches.
Figure 59 shows the digital waveforms of the controller block. During calibration (until
Flash_calib_done becomes ‘1’), the controller is in state 2 most of the time, which corre-
sponds to the CALIB state (including states INIT, CALIB_BEGIN, CALIB,
CALIB_DONE, and FLASH_CALIB_DONE). When Comparator_calib_done transitions
to high, the new calibration cycle of a single comparator begins, starting with reset_pulse.
Figure 60 displays one full calibration cycle for a single comparator: Reset_pulse
Polarity_detect_en Polarity_detect_done Coarse_calib_en Coarse_calib_done
Fine_calib_en Fine_calib_done Reset_pulse. Figure 61 and Figure 62 show the
waveforms of the coarse and fine calibration respectively, as well as other signals related
to writing codes to memory and to the applied voltage levels for the calibration transistors.
A code is written to memory at the end of state 3 (MEM_WRITE state), and then an eval-
uation is performed in state 1 (WAIT state), after which the new voltage level has settled
such that a new code can be determined in state 2 (COARSE_CALIB/ FINE_CALIB state)
for its release at the beginning of the next state 3. The results from a complete transistor-
level schematic simulation of the calibration logic are displayed in Figure 63, showing the
same calibration voltages obtained from the AMS simulation (700mV for coarse, and
620mV for fine).
State
Comparator_calib_done
Comparator_count
Cycle_count
Flash_calib_done
Reset
Reset_pulse
Figure 59. Waveforms of the controller block.
80
Clock
Reset
Polarity_detect_en
Polarity_detect_done
Coarse_calib_en
Coarse_calib_done
Fine_calib_en
Fine_calib_done
Figure 60. Calibration logic enable signals sequence for one full comparator calibration cycle.
Coarse
Voltage
[mV]
Clock
Comparator output
coarse_calib_en
coarse_calib_done
State
Coarse code
Coarse code after decoder
Coarse code written to memory
Figure 61. Coarse calibration sequence waveforms.
81
Fine Voltage
[mV]
Clock
Comparator output
coarse_calib_done
fine_calib_done
State
Fine code
Fine code after decoder
Fine code written to memory
fine_calib_en
Figure 62. Fine calibration sequence waveforms.
Fla
sh
inp
ut
Co
mp
ara
tor
ou
tpu
tC
oars
e
vo
lta
ge
Fin
e
vo
lta
ge
Figure 63. Digital logic schematic simulation results.
82
4.6 Verification of the external access features for the memory
Figure 64 displays an example from simulating the functionality of the external writ-
ing capability introduced in Figure 22. The code is written once write_en_ext transitions
to high. Table 13 provides an interpretation of Figure 64.
Calibration
voltages
(V)
Time (ns)
write_en_ext
mem_in_ext [5:0]
address_ext [3:0]
Figure 64. External writing functionality example (schematic-level simulation).
Table 13. Interpretation of Figure 64
mem_in_ext [5:0] address_ext[3:0] Command interpretation
0011 Set coarse code for comparator number 3
011100 The code is with polarity 0 (coarsep) and binary code 1110,
which corresponds to 1.06mV (according to Table 17)
1011 Set fine code for comparator number 3
010010 The code is with the previous polarity 0 (finep) and binary code
010010, which corresponds to 860mV (according to Table 18)
0011 Set coarse code for comparator number 3
000000 Write 500mV to coarsep
1011 Write 500mV to finep
83
4.7 Kickback of the flash ADC
Figure 65 displays the differential input waveform of the flash ADC within the hy-
brid ADC system, which was simulated with and without kickback reduction transistors
for the worst case (when the input voltage is equal to the peak value of 500mV). It can be
observed that the kickback reduces from 23.3mV to 1.21mV. Figure 66 shows the kick-
back voltage from a sweeping of the input voltage amplitude with and without kickback
reduction transistors, which further confirms the effectiveness of the design technique.
Figure 65. Flash ADC input with and without kickback reduction (500mV input).
Kic
kb
ac
k (
mV
)
No kickback reduction
With kickback reduction
Figure 66. Input voltage amplitude versus kickback.
84
5. Prototype Chip and Printed Circuit Board (PCB) Design
5.1 Fabricated chip
Figure 67 displays the micrograph of the chip from the hybrid ADC project, which
was fabricated in 130nm CMOS technology. The annotated parts of the die contain the
flash ADC and calibration circuitry that were integrated into the hybrid ADC system. The
die was assembled in a TQFP128 package for measurements on a custom-designed board.
flash ADC
Calibration
DAC
Calibration
Logic
Input Signal
GenerationCalibration Channel
Figure 67. Micrograph of the hybrid ADC chip containing the flash ADC and calibration logic.
85
5.2 PCB design
A printed circuit board (PCB) was designed to generate off-chip bias voltages and
currents for the calibration buffer, flash ADC and calibration DAC, as well as regulated
supply voltages for the on-chip components. Figure 68 displays the bias current generation
for the buffer input stage. A potentiometer of 10kΩ with a series resistor of 1.8kΩ can
generate a current in the range of 84-472µA for the pMOS pair and 88-499µA for the
nMOS pair, with a nominal desired values of 150µA and 100µA, respectively. For noise
bypassing, a through-hole capacitor of 10µF and an SMD capacitor of 47pF are connected
at the pins.
Figure 68. Bias current generation for the calibration buffer input stage.
Figure 69 visualizes the PCB configuration of the bias voltages for the cascode
stage in the buffer amplifier. The voltages are generated from dividers with resistors of
1kΩ and 1kΩ carbon film resistor potentiometers. The voltage MZ_VB3 can be tuned
from 0V to 600mV with nominal desired value of 400mV, and the voltage MZ_VB2 can
be tuned from 600mV to 1.2V with nominal desired value of 800mV. Figure 70 displays
the PCB components for the reference voltage generation at the calibration buffer input.
Since the on-chip interface is a resistor ladder, an off-chip buffer is needed to provide the
86
reference voltage with low output resistance. The TI OPA2626 is used for this purpose.
Figure 71 provides an overview of the complete custom PCB components for the voltages
and current of the calibration buffer. Figure 72 displays the configuration to obtain the
reference voltages for the flash ADC resistor ladder. MZ_FLASH_VRP is in range of
600mV to 1.2V with a nominal value of 850mV, and MZ_FLASH_VRN is in range of 0-
600mV with a nominal value of 350mV. The reference voltage for the calibration DAC
are generated using a similar approach, as depicted in Figure 73, where the possible range
is 0-800mV with a nominal value of 500mV. Figure 74 displays a photo of the assembled
PCB for the test chip measurements.
Figure 69. Generation of bias voltages for the cascode stage of the buffer.
87
Figure 70. Generation of input references for the calibration buffer.
Figure 71. PCB components for the calibration buffer.
88
Figure 72. Voltage generation for the flash ADC reference ladder on the PCB.
Figure 73. Calibration DAC reference generation.
89
Control
switches
Calibration
clock
AddressData to
read/write Control
switches
Calibration references generation
Supply
Supply
Hybrid ADC
references generation
Inputs
Switching between calibration/
normal operation mode
Calibration Reset
ADC Clock
Figure 74. Hybrid ADC PCB.
5.3 Flash ADC and calibration logic test setup
For automatic calibration, CAL_EN connects the calibration path and disconnects
all the other four channels, and RESET starts the calibration. The measurement setup is
depicted in Figure 75. The test setup for manual reading and writing from memory is de-
scribed next.
90
Logic
analyzer
Calib.
clock
Clock
generator
Signal
generator
Vcm for clock
bias T and
board supply
Regulator
power
Power for
the
differential
amplifier
Figure 75. Measurement setup.
5.3.1 Test setup for external reading from memory
Figure 76. Setup to read from memory.
91
Figure 76 displays the setup for reading from memory. At first, the jumpers of the
MEM_EXT[5:0] code (used for both reading and writing) are disconnected, and the output
can be read with a multimeter. To enter to reading mode, DIP switch MEM_EN_EXT is
set to OFF (enable) and DIP switches RW_SEL, WRITE_EN_EXT are set to ON (disable).
To read a proper address, ADDRESS_EXT[2:0] is set with DIP switches for choosing a
comparator number; while ADDRESS_EXT[3] is ON for coarse and polarity reading, and
OFF for fine code reading (according to the decoder in Figure 22). Figure 77 shows an
example setup for external reading, which sets the fine code for address 100.
Figure 77. Example configuration: reading from memory.
5.3.2 Test setup for external manual writing to memory
Figure 78 displays the external writing configuration. MEM_EN_EXT routes all
MUXs (coarse, fine, polarity, counter) to external values if it is connected to VDD (when
the switch is OFF). WRITE_EN_EXT with activated (OFF) MEM_EN_EXT enable the
memory core, triggering a single writing of the codes for setting the address. Otherwise,
the clock triggers the writing for internal calibration. The logic clock is not necessarily
92
needed for writing. When the address and data are set by the DIP switches, then
WRITE_EN_EXT first changed to OFF before setting it to ON again.
Figure 78. Test setup for external writing to memory.
5.4 Measurement results and discussion
After adjusting the reference voltages and currents, as described in section 5.2, the
flash ADC and calibration system performance were evaluated by recording the digital
data of the four channels via low-voltage differential signaling (LVDS) outputs and a logic
analyzer before and after calibration. The data was processed in MATLAB to obtain the
linearity (INL and DNL) and spectral (ENOB, SNDR, SFDR) evaluations. As described
in section 3.4, the coarse tuning has 19 voltage levels that are represented by 5-bits from
00000 to 10010; and the fine tuning has 36 voltage levels that are represented by 6-bits
from 000000 to 100011. Tables with the codes and their corresponding voltage represen-
tations are provided in Appendix II (Table 17 and Table 18). Section 5.4.1 presents the
93
system-level verification by adjusting the codes for coarse/fine and polarity manually,
while section 5.4.2 describes automatic calibration performance evaluations.
Larger than expected offsets of the fabricated CABS ADCs due to random mis-
matches have degraded the measured linearity performance. Therefore, the evaluations of
ENOB, INL, DNL, SNDR and SFDR are for 6-bit instead of 8-bit resolution, which was
done by dropping the last two LSBs as in [18].
5.4.1 Verification within the hybrid ADC system
The optimum coarse and fine calibration codes as well as the offset polarity bit for
each comparator in the flash ADC are listed in Table 14. The total measured power of the
flash ADC is 1.05mW and the total digital power is 0.86mW, including the D flip-flops
and thermometer-to-binary encoders at the flash ADC output. A histogram testing
method [56] was employed to evaluate DNL and INL errors of the hybrid ADC while
applying a low-frequency sinusoidal input signal of 3.235MHz. As shown in [18], the
DNL and INL values after calibration are within -0.41/+0.50 LSB and -0.77/+0.52 LSB,
respectively. Figure 79 displays the measured output spectra of the hybrid ADC with 6-
bit evaluation at a sampling rate of 1GS/s with a 10.19287109MHz sinusoidal input signal.
The measured ENOB after calibration is 5.57 bits in this test case, as opposed to 3.34 bits
before calibration. The 6-bit ADC achieves an SNDR of 35.29dB and an SFDR of
47.31dB. According to [18], the calibration is also effective near Nyquist frequencies,
when for 493.958MHz the measured ENOB is 5.26 bits.
Table 14. Manual offset calibration codes
Differential reference [mV] Coarse code Fine code Polarity bit
1 -375 00011 000100 1
2 -250 00000 000010 1
3 -125 00010 001011 0
4 0 00010 010000 0
5 125 00110 100000 0
6 250 00011 010100 0
7 375 00101 011000 0
94
Figure 79. Measured output spectra of the 6-bit 1GS/s hybrid ADC output for fin = 10.193MHz be-
fore and after manual calibration.
5.4.2 Calibration logic verification
For automatic calibration, a clock signal of 500MHz was applied with a calibration
clock of 1MHz. A clock frequency reduction to 500MHz was used because of a loss of
calibration effectiveness with a 1GS/s clock, where the comparators connected to the larg-
est differential reference voltages experienced discrepancies. In such cases, both the fine
and coarse codes reached their maximum values, which resulted in clipping of the recon-
structed output due to insufficient comparator offset tuning range. Observing the hybrid
ADC floorplan in Figure 80 can shed some light on the timing bottleneck. The problem
occurs at the interface between the flash output and the logic, or the flash input and
SHDAC. The DFFs in the calibration path are located at least 38µm further from the flash
output compared to the DFFs in the main hybrid ADC for normal operation. Their outputs
are routed all the way up to the logic (553.5µm horizontally, and 387µm vertically), while
the other four sets are routed to the decoders with straight connections. The routing to the
logic is unlikely to cause a problem, otherwise we would have observed it during the
95
500MS/s testing as well. The flash ADC functionality with 1GS/s clock has been proven
by the results in section 5.4.1 and in [18], and any calibration logic timing fault can be
resolved with the use of a slower calibration clock. However, the fast clock is routed
577µm further down to the clock generation of the four normal operation channels than to
the clock generation of the calibration channel, as annotated in Figure 80. Since the clock
generation delay blocks were optimized for the hybrid ADC core, the timing difference
between the flash clock, which is the same for both cases, and the generated sampling
clock for the SHDAC causes a problem. As a consequence, the SHDAC for calibration
path is sampled too early, which was alleviated by reducing the clock frequency. For future
implementations it is advisable to use equal distance for the layout of the clock generation
paths of the ADC core and for the calibration circuitry, or to insert a capacitance in the
faster path to achieve equal delays.
Calib. Clock generation
SHDAC cal.
Clock generation
SHDAC
SHDAC
SHDAC
SHDAC
FlashCABS CABS
DFFs cal
Clock signal
577µm
Figure 80. Floor plan of the hybrid ADC.
The calibration path was activated by turning on a DIP switch that determines
whether the ADC is in normal operation (OFF) or calibration mode (ON). To initiate the
automatic calibration, the reset DIP switch, which is labeled in Figure 74, was turned OFF
(providing VDD to the calibration logic) and then ON (manual reset pulse). The codes after
calibration were read as described in section 5.3.1, and are listed in Table 15. Figure 81
and Figure 82 display the output spectra of the 500MS/s 6-bit hybrid ADC testing from
96
captured data with fin = 10.28442383MHz after and before calibration, respectively. Full
scale sinusoidal input signals were used during testing. The calibration improved the
ENOB from 3.64 bits to 5.24 bits. Figure 83 displays the output spectrum with a higher
sampling rate of 1GS/s using the same codes (calibration performed with 500MS/s), where
the ENOB is 4.93 bits. As expected, the result with 1GS/s is worse because the calibration
was performed for 500MS/s, which is associated with different transient and memory ef-
fects determined by clock frequency. The result with 500MS/s after automatic calibration
is 0.33 bits lower than that with manual calibration discussed in section 5.4.1. This is be-
cause the quality of the automatic calibration has strong dependence on the input provided
to the flash ADC during calibration. If the references of the resistor ladder for input gen-
eration are not optimized correctly, an error that translates to offset in the system would
cause the logic to yield a non-optimal code. For manual calibration on the other hand, no
flash input is required, and the codes can be cycled and optimized manually by the de-
signer.
Figure 84 and Figure 85 display the measured INL and DNL after and before au-
tomatic calibration. After calibration, the DNL and INL values are within -0.653/+1.175
LSB and -0.854/+1.141 LSB, respectively. Prior to calibration, the DNL and INL values
are within -1/+3.175 LSB and -2.65/+2.374 LSB, respectively.
Table 16 (from data in [18]) summarizes the performance of hybrid ADC after
manual calibration with a sinusoidal input near the Nyquist frequency compared to other
6-bit ADC works. The comparison shows a good Figure of Merit (FoM) performance due
to the low power consumption and high ENOB, which proves the efficiency of the hybrid
ADC system compared to state-of-the-art. The work in [60] has significantly better FoM
than others, which is due to its significantly lower power consumption, as it was designed
in technology (65nm) with better transition frequency (fT). Generally, more advanced
technologies are associated with smaller devices, higher speeds, and lower parasitics (at
cost of more process variations, as elaborated in section 1.2).
97
Table 15. Automatic offset calibration codes
Differential reference [mV] Coarse code Fine code Polarity bit
1 -375 00100 000011 1
2 -250 00000 001001 0
3 -125 00100 000001 0
4 0 00010 000111 0
5 125 00110 000001 0
6 250 00000 000010 0
7 375 00011 000001 0
Figure 81. Measured output spectra (4096-point FFT) of the 6-bit 500MS/s hybrid ADC output for
fin = 10.28442383MHz after automatic calibration.
98
Figure 82. Measured output spectra (4096-point FFT) of the 6-bit 500MS/s hybrid ADC output for
fin = 10.28442383MHz before automatic calibration.
Figure 83. Measured output spectrum (8192-point FFT) of the 6-bit 1GS/s hybrid ADC output for fin
= 10.193MHz after automatic calibration (with 500MS/s clock).
99
Figure 84. Measured DNL and INL of the hybrid ADC after automatic calibration (6-bit evalua-
tion).
Figure 85. Measured DNL and INL of the hybrid ADC before calibration (6-bit evaluation).
100
Table 16. Summary of the hybrid ADC system performance compared to other works (data taken
from [18])
Specification This work [57]
JSSC,09
[58]
JSSC,13
[59]
JSSC,06
[60]
TCASI,17
Sampling Rate (GS/s) 1 1.25 1.6 0.6 0.8
Resolution (bit) 6 6 6 6 6
CMOS Technology (nm) 130 130 90 130 65
ENOB @ NQ 5.26 5.0 4.44 5.02 4.8
SNDR @ NQ (dB) 33.42 32 28.5 32 30.6
SFDR @ NQ (dB) 45.71 35 35.5 46 36.2
Supply Voltage (V) 1.2 1.2 1.3 1.2 1
Power Consumption (mW) 10.5 32 20.1 5.3 3.62
FoM @ NQ(fJ/conv. step)
(=Power/(2ENOB@NQ × fs)) 274 800 579 272 162
101
6. Conclusions and Future Work
The design of a 3-bit flash ADC with a foreground offset calibration scheme was
described in this thesis, which enhances the effectiveness of flash ADCs within emerging
hybrid architectures. The flash ADC was integrated as a coarse ADC into a 1GS/s sub-
ranging two-step hybrid ADC architecture with four TI (time-interleaved) channels oper-
ating at one fourth of the frequency (250MS/s). The digitally-assisted calibration was
primarily developed for improving the performance of flash ADCs within hybrid ADC
architectures. It involves the connection of two transistors in parallel with input pairs of
the flash comparators; one for coarse tuning, and one for fine tuning. Based on the flash
ADC output, the calibration logic provides DC voltages from a calibration DAC to adjust
the strength of the current injection from the auxiliary transistors for offset compensation.
Common-gate cascode transistors were added to the comparators to alleviate kickback
perturbation at the flash ADC input caused by the finite impedance of preceding channels
and switching operation. Measurement results demonstrate the calibration effectiveness
within the hybrid ADC for a 6-bit output, revealing an ENOB improvement from 3.64 to
5.24 bits with a 10.284MHz input signal (500MS/s flash clock), and to 5.57 bits with
manual calibration. The DNL and INL improved from within -1/+3.175 LSB and -
2.65/+2.374 LSB to within 0.653/+1.175 LSB and -0.854/+1.141 LSB, respectively. De-
signed in 130nm CMOS technology, the flash ADC and calibration circuits consume a
total power of 1.05mW and 0.86mW respectively, while the flash is operating with a
1GS/s clock and the calibration logic is operating with a 1MHz clock.
With regards to future work, more area-efficient and power-efficient design tech-
niques can be explored. For example, future research endeavors could aim at
simplification of the logic and reduction of the number of calibration bits. This would
decrease the area for on-chip memory and for the calibration DAC reference ladder with
its interconnections. Furthermore, different comparator architectures can be explored in
the future, such as the double-tail comparator. Similarly, the calibration method could be
applied to different flash architectures. This may enable the use of a flash ADC with more
bits within the hybrid ADC architecture, and thereby alleviate the parasitics of the CABS
while maintaining the same or even better performance because the number of CABS
comparators or time-interleaved channels would be reduced.
102
To improve the automatic calibration effectiveness, observability of the calibration
buffer output can be added, which could enable proper tuning of the input provided to the
flash ADC during calibration. The clock generation for calibration should be optimized to
enable calibration with a 1GS/s clock.
103
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108
Appendix I - Digitally Programmable Offset Compensation of
Comparators in Flash ADCs using Varactors
This appendix introduces an offset calibration approach that exploits the dynamic
characteristics of a comparator to achieve a wide linear tuning range by placing voltage-
controlled capacitors (varactors) at two different internal nodes: drain of the input pairs
(𝐷𝑖 nodes) for linearity, and output nodes for wider compensation range [55]. The com-
parator with varactors is displayed in Figure 86. This was the initial version of the
calibration scheme, but was changed prior to the prototype chip fabrication due to the
system requirements for low kickback and small loading capacitance. When the compar-
ator topology was changed to include the kickback reduction technique, the current
injection method (Section 2.5) became more suitable to meet the system requirements.
VREFPVIP
CLK
VOP
CLK
Di_p
OUTn_p
Vcalc+
Vcalf+
VREFN VIN
CLK
VON
Di_n
OUTn_n
Vcalc-
Vcalf-
CLKM1 M2
M3 M4 M5 M6
M7 M8
M10M9M11 M12M13 M14
1.92µm/
0.12µm
1.92µm/
0.12µm
8*1.44µm
/0.24µm
0.72µm/
0.12µm0.72µm/
0.12µm
0.96µm/
0.12µm
0.96µm/
0.12µm
0.72µm/
0.72µm
0.72µm/
0.72µm0.72µm/
0.48µm
0.72µm/
0.48µm
coarse coarse
fine fine
Figure 86. Comparator with varactors for offset calibration.
Previous works utilizing varactors for offset compensation have nonlinear relations
between the tuning voltage and the offset, which complicates the calibration. Here, a dig-
ital calibration scheme controls the gate voltages of the varactors and detects the minimum
offset condition. The proposed configuration was simulated with a transistor-level flash
ADC design in 0.13µm CMOS technology and a Verilog-A behavioral implementation of
109
the calibration circuitry. The ADC consumes 1.48mW of power (excluding the calibration
circuitry, flip-flops, and encoder) from a 1.2V voltage supply. Monte Carlo simulation
results indicate that the method reduces the 3-sigma input offset of the comparator from
36.9mV to 1.6mV. The simulated effective number of bits (ENOB) of the flash ADC is
2.96 bits.
Referring to Figure 86, there are three possible pairs of nodes in the comparator at
which the varactors can be placed: the drains of tail transistors M1 and M2, the drains of
the differential pairs M3-M6 (𝐷𝑖 nodes), and the output nodes of the regenerative latch
transistors (OUTn nodes). The first option is not effective because adding capacitance at
the tail current source nodes affects both branches equally. Calibration at OUTn_n and
OUTn_p has two main advantages. First, the nodes can tolerate extra loading without caus-
ing significant memory effects in the latch. Second, the current at the output node is
approximately twice the current at the Di node in this design, allowing to cover a wider
compensation range without increasing the device sizes. However, the Di node has the
advantage of a wider linear tuning range, which aids the calibration and significantly re-
duces the number of required resistors in the ladder of the DAC (in Figure 87) that
generates the varactor control voltages. Another important aspect is that the varactor’s
effective capacitance depends not only on its gate control voltage, but also on the
drain/source/bulk-to-substrate potential, which is changing over time during each clock
cycle depending on the node of the comparator to which the varactor is connected. Figure
88 displays the capacitance versus gate voltage for varactors at the Di and OUTn nodes
(referred to as “fine” and “coarse”, respectively) for two extreme drain/source/bulk-to-
substrate voltage cases: 1.2V and 0V. The instantaneous capacitance on the two curves
changes during the dynamic operation of the comparator as a result of the
drain/source/bulk-to-substrate voltage variation. The voltages at the Di nodes behave more
symmetric over time. Both Di nodes fall from 1.2V to 0V at the rising edge of the clock
but with a small voltage difference, implying that the extra differential compensation ca-
pacitance has a more linear relationship to the offset voltage. In contrast, the voltages at
the OUTn nodes diverge more during the operation, which leads to more time-varying
differential capacitance between the nodes due to their drain/source/bulk-to-substrate volt-
age differences. For this reason, the less linear output nodes are used for coarse tuning to
110
achieve a wider overall range, while the Di nodes are used for fine tuning to exploit the
good linearity characteristics.
2R
5R
4R
R
R
R
R
2R
R
R
R
R
R
R
Fine
Calibration
Coarse
Calibration
Coarse
Calib.
Fine
Calib.
Offset
Polarity
Detector
Digital Calibration Logic+-
+-
VREFP
VREFN
VIP
VIN+-
0
1
0
1
0
1
0
1
Vcalc+
Vcalc-
Vcalf+
Vcalf-
OU
Tn
_n
OU
Tn
_p
Di_
p
Di_
n
DAC
1.1V
0.85V
0.65V
0.55V
0.5V
0.45V
0.4V
0.35V
0.3V
0.25V
0.1V
0V
0.6V
0.15V
0.2V
R
VOP
VON
CLK
Figure 87. Calibration logic for a single comparator with varactor-based tuning.
Figure 88. Varactor capacitance vs. applied gate voltage.
111
Figure 89 displays the simulated comparator input offset versus the gate voltages of
the fine and coarse varactors. Since the Di nodes are naturally more sensitive to memory
effects during reset phase, the fine varactors were selected to be smaller. It can be observed
that the linear range of the fine varactor is approximately 0.8V, while the linear range of
the coarse varactor is approximately 0.3V.
Figure 89. Input offset vs. gate voltage curves for the Di and OUTn nodes.
(a) (b)
Figure 90. Monte Carlo simulation results for the input offset voltage of a single comparator with
the varactor tuning method: (a) before calibration, (b) after calibration.
112
Figure 91. Simulated DNL/INL of the flash ADC with the varactor-based calibration method.
Figure 90 presents the results from 500 Monte Carlo simulation runs, revealing
that the standard deviation of the comparator input offset voltage decreases from 12.3mV
(without calibration) to 534µV (with calibration). Figure 91 shows the differential nonlin-
earity (DNL) and integral nonlinearity (INL) improvements of the flash ADC with the
calibrated comparator in the presence of random offsets (-30mV to 25mV) that were in-
tentionally introduced by varying the values of DC voltage sources in series with one of
the inputs of each comparator. Figure 92 displays the output spectrum of the flash ADC
with a 6.836MHz 0.5Vpeak differential input and with a 487.3MHz input close to Nyquist
frequency.
113
(a)
(b)
Figure 92. Output spectrum at 1GS/s of the flash with varactors for calibration: (a) 479MHz input,
(b) 6.84MHz input.
114
Appendix II - Tables of Coarse and Fine Codes and their
Corresponding Voltage Levels
Table 17. Coarse codes and corresponding voltage levels
Voltage [V] [5] [4] [3] [2] [1]
0.50 0 0 0 0 0
0.54 0 0 0 0 1
0.58 0 0 0 1 0
0.62 0 0 0 1 1
0.66 0 0 1 0 0
0.70 0 0 1 0 1
0.74 0 0 1 1 0
0.78 0 0 1 1 1
0.82 0 1 0 0 0
0.86 0 1 0 0 1
0.90 0 1 0 1 0
0.94 0 1 0 1 1
0.98 0 1 1 0 0
1.02 0 1 1 0 1
1.06 0 1 1 1 0
1.10 0 1 1 1 1
1.14 1 0 0 0 0
1.18 1 0 0 0 1
1.20 1 0 0 1 0
115
Table 18. Fine codes and corresponding voltage levels
Voltage [V] [5] [4] [3] [2] [1] [0]
0.50 0 0 0 0 0 0
0.52 0 0 0 0 0 1
0.54 0 0 0 0 1 0
0.56 0 0 0 0 1 1
0.58 0 0 0 1 0 0
0.60 0 0 0 1 0 1
0.62 0 0 0 1 1 0
0.64 0 0 0 1 1 1
0.66 0 0 1 0 0 0
0.68 0 0 1 0 0 1
0.70 0 0 1 0 1 0
0.72 0 0 1 0 1 1
0.74 0 0 1 1 0 0
0.76 0 0 1 1 0 1
0.78 0 0 1 1 1 0
0.80 0 0 1 1 1 1
0.82 0 1 0 0 0 0
0.84 0 1 0 0 0 1
0.86 0 1 0 0 1 0
0.88 0 1 0 0 1 1
0.90 0 1 0 1 0 0
0.92 0 1 0 1 0 1
0.94 0 1 0 1 1 0
0.96 0 1 0 1 1 1
0.98 0 1 1 0 0 0
1.00 0 1 1 0 0 1
1.02 0 1 1 0 1 0
1.04 0 1 1 0 1 1
1.06 0 1 1 1 0 0
1.08 0 1 1 1 0 1
1.10 0 1 1 1 1 0
1.12 0 1 1 1 1 1
1.14 1 0 0 0 0 0
1.16 1 0 0 0 0 1
1.18 1 0 0 0 1 0
1.20 1 0 0 0 1 1