1. Digital FundamentalsTenth EditionFloydChapter 7 2009 Pearson Education, Upper PearsonRiver, NJ 07458. All Rights Reserved 2008 Saddle EducationFloyd, Digital Fundamentals, 10th ed

2. Logic circuits Combinational Circuits Sequential CircuitsBasic BlockFlip-FlopsFloyd, Digital Fundamentals, 10th ed 2 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 3. Flip-Flop 1 ( 0 1 ) ( 1 0 ) BistableMonostable AstableFloyd, Digital Fundamentals, 10th ed 3 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 4. CHAPTER OVERVIEW Bistable devices have two stable states, called SET andRESET. They are used as storage devices. Monostable devices (monostable trigger, one-shot) haveone stable state. They are used as timers. Astable devices (multivibrator) do not have stable state.They are used as waveform generators.Floyd, Digital Fundamentals, 10th ed 4 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 5. 8-1 LATCHES( ) A latch is a type of bistable logic device. There are two types of latches: S-R latch ( SET-RESET latch) D latch (Delay latch)Floyd, Digital Fundamentals, 10th ed 5 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 6. The S-R Latch An active-HIGH input S-R latch is formed with two cross-coupled NOR gates. An active-LOW input S-R latch is formed with two cross-coupled NAND gates.Floyd, Digital Fundamentals, 10th ed 6 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 7. Negative-OR Equivalent of the NAND gate S-R LatchFloyd, Digital Fundamentals, 10th ed 7 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 8. S-R QQ RS ! Active-LOW inputFloyd, Digital Fundamentals, 10th ed 8 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 9. R=0, S=1 0 Reset Q = 0 Q =1 Q = 1 Q = 0 Q10 Q Q01 Q1010 0R0 1 S10R11 S1 Q=0 Q=1Q=0 Q=1Floyd, Digital Fundamentals, 10th ed 9 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 10. R=1, S=0 1Set Q = 0 Q = 1 Q = 1 Q = 0 Q 1 0 QQ 01Q 0 101 1R 10S0 1R 1 0S 0 Q=1 Q=0Q=1 Q= 0Floyd, Digital Fundamentals, 10th ed 10 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 11. R=1, S=1 = 1 Q = 0Q Q = 0 Q = 1 Q01 QQ 1 0 Q0110 1R 10S1 1R 01 S 1 Q=1 Q=0 Q=0 Q=1Floyd, Digital Fundamentals, 10th ed 11 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 12. R=0, S=0 Q1 1 Q R 00SQ1 0R S 0Q 1 1 RD SD 0 1 0 Floyd, Digital Fundamentals, 10th ed 12 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 13. S-R ( ) R S Qn Qn+11 1Qn QnSSQ0 1Qn 0 R RQ1 0Qn 1 0 00 1* 0 01 1*Qn+1 S R Qn0 011n+ 1 Q = S + RQn0 0 111 1 000*S + R = 1 01 1 1 1 0*Floyd, Digital Fundamentals, 10 edth 13 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 14. QQRSQn Qn+1 00Qn QnSSQ 01Qn 1RRQ 10Qn 0 110 0*111 0*R SActive-HIGH input Qn+1 S R n+ 1Qn0 01 1Q= S + RQn 0 0 0 1 010 01 SR= 0 * 110 0 1 *Floyd, Digital Fundamentals, 10th ed 14 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 15. S RQFloyd, Digital Fundamentals, 10th ed 15 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 16. 74LS279 S-R Floyd, Digital Fundamentals, 10th ed 16 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 17. Example 8 - 1Floyd, Digital Fundamentals, 10th ed 17 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 18. The Gated SR LatchFloyd, Digital Fundamentals, 10th ed 18 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 19. S =1R=0 Q Q S=00S = 1R=0 R= S=0 R=1 R1 S1 S-R S-R EN R S Qn+1 0 QnR S 100 Qn EN101 1 10 Q n+ 1 = S + RQ n 110 0 SR = 0 111 1*Floyd, Digital Fundamentals, 10th ed19 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 20. S-R Q 0 SetKeep Reset Keep 1 EN R01001 EN S100 0 1 Q 1 0 1QFloyd, Digital Fundamentals, 10th ed20 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 21. The Gated D Latch D Q QDENQn+1 0 Qn 1 11 0 10 D Q END EN Q Q n+ 1 = D + RQ nS DQ n SR = 0 Floyd, Digital Fundamentals, 10th ed 21 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 22. Example 8 - 3Floyd, Digital Fundamentals, 10th ed 22 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 23. 74LS75 Quad Gated D LatchesFloyd, Digital Fundamentals, 10th ed 23 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 24. Latch vs. Flip-Flop Bistable devices Latch: change output at any time Flip-Flop: Synchronous CLK TriggerFloyd, Digital Fundamentals, 10th ed 24 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 25. 8-2 EDGE-TRIGGERED FLIP-FLOPS Edge-triggered flip-flops are synchronous bistabledevices. Their outputs change states only at a specifiedpoint on a signal called clock (CLK).Floyd, Digital Fundamentals, 10th ed 25 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 26. The Edge-Triggered S-R Flip-FlopFloyd, Digital Fundamentals, 10th ed 26 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 27. The Edge-Triggered S-R Flip-FlopFloyd, Digital Fundamentals, 10th ed 27 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 28. Example 8 - 4Floyd, Digital Fundamentals, 10th ed 28 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 29. Example 8 - 4Floyd, Digital Fundamentals, 10th ed 29 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 30. A method of Edge-Triggering SQCLK QR CLK Floyd, Digital Fundamentals, 10th ed 30 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 31. The Edge-Triggered D Flip-FlopFloyd, Digital Fundamentals, 10th ed 31 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 32. Timing diagramCPDQ Truth Table CP DQQ D DDFloyd, Digital Fundamentals, 10th ed 32 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 33. Example 8 - 5Floyd, Digital Fundamentals, 10th ed 33 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 34. Edge-Triggered J-K FFS JQ CLK QK RS = JQ n Q n + 1 = S + RQ n SR = = JQ +K + Q )Qn n n R = KQ n0 ( = JQ + KQ nnFloyd, Digital Fundamentals, 10th ed 34 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 35. IF J=1,K=0,Q0=0;THEN G1 enabled, Q=1 (SET)IF J=0,K=1,Q0=1;THEN G2 enabled, Q=0 (RESET)IF J=0,K=0; THEN no changeIF J=1,K=1; THEN change to oppositestate(Toggle)Floyd, Digital Fundamentals, 10th ed 35 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 36. J =1 K=J K CLKQn+1J=0 J0 Q 1J =K= K=0 0 0 Qn C J = K K = 1Q 0 1 0 JK 1 0 1Qn+1= JQ + KQ nnn1 1 QCPJ1 00 1K0 10 1QFloyd, Digital Fundamentals, 10th ed 36 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 37. Example 8-6Floyd, Digital Fundamentals, 10th ed 37 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 38. Example 8-7Floyd, Digital Fundamentals, 10th ed 38 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 39. Asynchronous Preset and Clear Inputs Before operation, a flip-flop must have a knownstate. This is done by preset ( direct set) and clear(direct reset) inputs. These are inputs that affect thestate of the flip-flop independent of the clock.Floyd, Digital Fundamentals, 10th ed 39 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 40. J-K Flip-Flop with Preset and Clear Inputs PRE 0 J1QCLK 10K 0 1 Q CLR 1 J S QC K R Q J K 1 Floyd, Digital Fundamentals, 10th ed 40 2009 Education, Upper Saddle River, NJ 07458. All Rights Reserved 0Pearson 41. Example 8-8Floyd, Digital Fundamentals, 10th ed 41 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 42. IC Flip-Flops--74HC74 (dual D FF)Floyd, Digital Fundamentals, 10th ed 42 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 43. IC Flip-Flops--74HC112 (dual JK FF)Floyd, Digital Fundamentals, 10th ed 43 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 44. Example 8-9Floyd, Digital Fundamentals, 10th ed 44 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 45. Comparison of edge-triggered and level-triggeredE/CPD Q(LEVEL)Q(EDGE)Floyd, Digital Fundamentals, 10th ed 45 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 46. ENQQ Qn=0 =1Q 0 1 =0 Qn+1=1 RDSD 0 1 1 0 EN 110 1 EN Qn+1 0RS Qn ENQ !Floyd, Digital Fundamentals, 10th ed 46 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 47. 1Q n + 1 = JQ n + KQ n J SQ = 1 Q + 0 Qn nC K RQ =Q n 1 Q QFloyd, Digital Fundamentals, 10th ed 47 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 48. 8-3 MASTER-SLAVE FLIP-FLOPSMaster-slave flip-flops are pulse- triggered. A master-slave flip-fop consists of two gated latches. Data are entered into it at the leading edge of the clock, but the output does not reflect the input state until the trailing edge. Master-slave flip-flops have largely been replaced by the 48 edge-triggered devices.Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 49. The Master-Slave J-K Flip-FlopFloyd, Digital Fundamentals, 10th ed 49 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 50. The Master-Slave J-K Flip-FlopFloyd, Digital Fundamentals, 10th ed 50 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 51. JK Q QJ=K=0 Q QFR2 C S2 CP FR1 C S1=0 K CP J =0Floyd, Digital Fundamentals, 10th ed 51 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 52. J=K=1 1 QQ Qn=1 0 Qn+1=0 Q QF R2C S2 1 CP 0F R1C S11 0 =1 K CP J=1Floyd, Digital Fundamentals, 10th ed52 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 53. J=K=1 0 QQQn=0 1 Qn+1=1QQF R2 C S2 0 CP1 FR1 C S1 01 =1 K CP J=1Floyd, Digital Fundamentals, 10th ed 53 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 54. J=1 K=0 Q QQn=0 1 Qn+1=1QQFR2 C S2CP1FR1 C S1 01 =0 K CP J=1Floyd, Digital Fundamentals, 10th ed 54 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 55. Q Q Qn=1 J=1 K=0 Qn+1 =1 Q QF F R2 S2 C CPF 0R1 C S1 0 10 =0K CP J =1Floyd, Digital Fundamentals, 10th ed 55 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 56. J=0 K=1 Q Q Qn+1=0 Q QFR2 C S2 CPFR1 C S1=1 K CP J =0Floyd, Digital Fundamentals, 10th ed 56 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 57. Example 8-10Floyd, Digital Fundamentals, 10th ed 57 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 58. 8-4 Flip-Flops Operation Characteristics Propagation delay times Set-up time Hold Time Maxim Clock Frequency Pulse Widths Power DissipationFloyd, Digital Fundamentals, 10th ed 58 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 59. Propagation delay timesFloyd, Digital Fundamentals, 10th ed 59 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 60. Floyd, Digital Fundamentals, 10th ed 60 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 61. Set-up timeFloyd, Digital Fundamentals, 10th ed 61 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 62. Hold TimeFloyd, Digital Fundamentals, 10th ed 62 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 63. Other parameters Maxim Clock Frequency Pulse Widths Power DissipationFloyd, Digital Fundamentals, 10th ed 63 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 64. Comparison of typical FFsFloyd, Digital Fundamentals, 10th ed 64 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 65. 8-5 FLIP-FLOP APPLICATIONS Flip-flops are building blocks for sequentiallogic. There are many applications of flip-flops. For example, by using n flip-flops,we can achieve An n-bit parallel data storage A frequency divider of 2n A modulo 2n counterFloyd, Digital Fundamentals, 10th ed 65 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 66. 4-bit Register Used for Data Storage The data on the D inputs are stored simultaneously bythe flip-flops on the positive edge of the clock.Floyd, Digital Fundamentals, 10th ed 66 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 67. Divide-by-2 Device When a pulse waveform is applied to the clock input, the Q output is a square wave with one-half the frequency of the clock input.Floyd, Digital Fundamentals, 10th ed 67 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 68. Divide-by-4 Device When a pulse waveform is applied to the clock input, the Q output is a square wave with one-half the frequency of the clock input.Floyd, Digital Fundamentals, 10th ed 68 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 69. Modulo 4 Counter If we take QA as the LSB and QB as the MSB, a 2-bitsequence is produced as the flip-flops are clocked.Floyd, Digital Fundamentals, 10th ed 69 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 70. Q0Q11J01J1 CLK Qn+1=JQn+KQn=Qn K0 K1CLK fQ0 0 1 010 10 10 Q1 0 1 100 11 00 Q1 Q0n 2n10 00 11 01Modulo 4 Counter 2n 2 nFloyd, Digital Fundamentals, 10th ed70 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 71. Schmitt-Trigger AB UI1.5V UO=UOL BC 0.6VVI-, then VO=HIGH If VI+ VA>VB 1 0 VB+S VB 0 0 2 C1> VA Vbias, Vc=LOW Base BIf VBE 2 VCC vC1 = 0, vC 2 = 1 Q = 0 vO = 0 3Floyd, Digital Fundamentals, 10th ed128 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 129. UT+uI2vO13VCC VCC UT 3 1 VCC 3O t UT- uO O 12vIOVCCVCCt33 Note: if control voltage VCO (PIN 5) is given, then UT+ = VCO UT- = 1/2VCO UT- = 1/2VCOFloyd, Digital Fundamentals, 10th ed129 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 130. Voltage Transfer Characteristic VT = 1 VCC3 VT + = 2 VCC3 VT + VT = 1 VCC 3Floyd, Digital Fundamentals, 10th ed 130 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 131. Homework P407 6,8,12,18,26,28,30Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 132. Summary Bistable Latch Trigger One-shot 555 Timer One-shot Astable Schmitt-TriggerFloyd, Digital Fundamentals, 10th ed 132 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 133. Selected Key TermsLatchA bistable digital circuit used for storing a bit.Bistable Having two stable states. Latches and flip-flops are bistable multivibrators. Clock A triggering input of a flip-flop. D flip-flop A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse. J-K flip-flop A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 134. Selected Key Terms Propagation The interval of time required after an input signaldelay time has been applied for the resulting output signal tochange.Set-up time The time interval required for the input levels to beon a digital circuit.Hold time The time interval required for the input levels toremain steady to a flip-flop after the triggeringedge in order to reliably activate the device.Timer A circuit that can be used as a one-shot or as anoscillator.Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 135. 1. The output of a D latch will not change if a. the output is LOW b. Enable is not active c. D is LOW d. all of the aboveFloyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 136. 2. The D flip-flop shown willQ a. set on the next clock pulseD b. reset on the next clock pulse CLK CLK c. latch on the next clock pulseQ d. toggle on the next clock pulseFloyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 137. 3. For the J-K flip-flop shown, the number of inputs thatare asynchronous isPRE a. 1 b. 2 J Q c. 3 CLK Q d. 4 KCLRFloyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 138. 4. Assume the output is initially HIGH on a leading edgetriggered J-K flip flop. For the inputs shown, the outputwill go from HIGH to LOW on which clock pulse? a. 1 CLK b. 2 J c. 3 K 1 2 34 d. 4Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 139. 5. The time interval illustrated is called a. tPHL 50% point on triggering edge b. tPLHCLK c. set-up time Q 50% point on LOW-to- d. hold timeHIGH transition of Q?Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 140. 6. The time interval illustrated is called a. tPHL b. tPLHDCLK c. set-up time d. hold time ?Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 141. 7. The application illustrated is a a. astable multivibrator HIGH HIGH b. data storage devicefout JQAJQB c. frequency multiplierfinCLKCLK d. frequency divider KKFloyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 142. OutputlinesQ08. The application illustrated is aDC a. astable multivibrator RDQ1 b. data storage device CR c. frequency multiplierDQ2 d. frequency dividerCParallel datainput lines RDQ3Clock CRClearFloyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 143. 9. A retriggerable one-shot with an active HIGH output hasa pulse width of 20 ms and is triggered from a 60 Hz line.The output will be a a. series of 16.7 ms pulses b. series of 20 ms pulses c. constant LOW d. constant HIGHFloyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 144. 10. The circuit illustrated is a +VCC a. astable multivibrator (4) (8) R1 b. monostable multivibrator (7) RESET VCC DISCH c. frequency multiplier R2(6) THRES OUT (3) (2) (5) d. frequency dividerC1 TRIG CONTGND (1)Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 2008 Pearson Education 145. Answers: 1. b 6. d 2. d 7. d 3. b 8. b 4. c 9. d 5. b 10. aFloyd, Digital Fundamentals, 10th ed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved