Digital Systems IEEC 180A

Lecture 4

Bevan M. Baas

• This circuit schematic shows all 8 minterms “present” for a 3-input combinational logic function

• In practice, all possible minterms would never all be present in a circuit (do you see why?)

• There is one possible minterm for each row in the truth table

m1

m0

m2

m3

m4

m5

m6

m7

Z

MintermExample

MintermExample

• By construction, one and only one minterm is active (equals 1) at any point in time

m1

m0

m2

m3

m4

m5

m6

m7

0

0

0

0

0

0

0

1

00

1

Z1

MintermExample

• By construction, one and only one minterm is active (equals 1) at any point in time

m1

m0

m2

m3

m4

m5

m6

m7

0

0

1

0

0

0

0

0

01

1

Z1

MintermExample

• Z = m0 + m1 + m7

• To implement an expression, a circuit is built with only the present minterm(s)

• The output can be 1 only when one of the present minterms forces the output to 1

m1

m0

m2

m7

01

1

Z

0

0

0

0

MintermExample

• Z = m0 + m1 + m7

• To implement an expression, a circuit is built with only the present minterm(s)

• The output can be 1 only when one of the present minterms forces the output to 1

m1

m0

m2

m7

11

1

Z

0

1

0

1

MintermExample

• Z = m0 + m1 + m7

• Of course gate inputs can not be left unconnected (unspecified). There are two solutions:– Tie unused inputs to a

value that disables those inputs. For an OR gate, inputs would be tied to 0 (or False or Gnd)

– The best solution is to simplify the gate. In this example, the 8-input OR gate is simplified to a 3-input OR gate

m1

m0

m2

m7

11

1

Z

0

1

0

1