Answers to Final Exam. of Digital System Design 2004/06/14 (Mon.) 1. Design a gated D latch using only NAND gates and one inverter. (10%)

11.4 (p. 311)

2. A rest-dominant flip-flop behaves like an S-R flip-flop, except that the inputs S = R = 1 is allowed,

and the flip-flop is reset when S = R = 1. (a) Derive the characteristic equation for a reset-dominant flip-flop. (5%) (b) Show how a reset-dominant flip-flop can be constructed by adding gates(s) to an S-R flip-flop.

(5%) 11.6 (p.311)

(a) Q+ = SR’ + R’Q (b)

3. (a) Complete the following timing diagram for a J-K flip-flop with a falling-edge trigger and

asynchronous ClrN and PreN inputs. (5%) 11.9 (p.312)

(b) Complete the timing diagram for the following circuit. Note that the Ck inputs on the two flip-flops are different. (5%)

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4. Design a 3-bit counter which counts in the sequence: 001, 011, 010, 110, 111, 101, 100, (repeat) 001,… (a) Use D flip-flops (8%) (b) Use T flip-flops (8%) (c) In each case, what will happen if the counter is started in state 000? (4%)

12.7 (p.350)

5. Construct a state graph for the shift

register shown below. (X is the input, and Z is the output.) Is this a Mealy or Moore machine? (10%) 13.2 (p.382)

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6. Explain how parity can be used for error detection? (5%) p. 356, p.362

7. Consider a 6-bit adder with an accumulator in the following figure. Suppose the X register contains a number from a previous calculation. We do not want this number. Instead, we want X to equal 4 * Y. (X = x5 x4 x3 x2 x1 x0 and Y = y5 y4 y3 y2 y1 y0.) On the timing diagram, give values for Ad and ClrN so that we will have X = 4 * Y held in the accumulator. (10%)

12.1 (p.349)

8. A sequential circuit has the form shown in the following figure, with

D1 = Q2Q3’ D3 = Q2’ + X D2 = Q3 Z = XQ2’ + X’Q2 (a) Construct a state table and state graph for the circuit. Is this a Mealy or Moore machine? (10%) (b) Draw a timing diagram for the circuit

showing the clock, X, Q1, Q2, Q3, and Z. Use the input sequence X = 01011. Change X between clock edges so that we can see false outputs, and indicate any false outputs on the diagram. (10%)

(c) Compare the output sequence obtained from the timing diagram with that from the state graph. (3%)

(d) At what time with respect to the clock should the input be changed in order to eliminate the false output(s)? (2%)

13.4 (p.383) , see p. 653 - 654 3