Digital Phase-Shift Modulation for an IsolationBuffer in Silicon-on-Sapphire CMOS

Eugenio Culurciello P. Pouliquen, A. G. AndreouElectrical Engineering Electrical & Computer Engineering

Yale University Johns Hopkins UniversityNew Haven CT 06520 Baltimore MD 21218

eugenio.culurciello@yale.edu

Abstract- We designed and fabricated a 4-channels digital By taking advantage of the isolation properties of theisolation amplifier in a 0.5,um Silicon-on-Sapphire technology. Silicon-on-Sapphire (SOS) substrate [8], we previously de-The isolation device was fabricated on a single die, taking signed and fabricated a monolithic single chip isolation deviceadvantage of the isolative properties of the sapphire substrate.The individual isolation channels can operate in excess of 40Mbps [9], [10]. In ths paper we Improve on this design by employingusing digital phase-shift-keying modulation. Modulation of the a digital phase-shift-keying modulation of the input signalsinput signal is used to increase immunity to errors at low input and reducing the silicon area and the number coupling capac-data rates. The device can tolerate ground bounces of IV/,us and itors per channel (Figure 1). Modulation is used to increaseisolate more than 800V. The device uses N+1 capacitors for N immunity to errors at low input data rates. The device useschannels as opposed to 2N of previous implementations, thus N+1 coupling capacitors for N channels, in contrast to theminimizing the coupling silicon area and increasing reliability. N capaci nrevior N mchan tations. to theTypical applications are in harsh industrial environments, trans- 2N capacitors used in previous implementations. Thus theportation, medical and life-critical systems. coupling area and number of capacitors is minimized to obtain

higher reliability. The following sections report on the design,I. INTRODUCTION modeling and test results of the SOS digital isolation amplifier.

A digital isolation amplifier is an electrical circuit thatcommunicates an input digital signal from one region to an Vdd i Vddooutput digital signal in a second region that are electrically --isolated from the first one. The isolation of communication lcircuits is desirable in environments where ground loops are Ipresent, or where it is not possible to ensure a common ground In 1 F Outireference between output and input nodes. Typical applications Iare in harsh industrial environments, where ground currents are Ipresent due to leakage from the machinery's power supply. ,Isolation is also used to prevent human personnel injuriesor equipment damage and in the medical field, where it is I n4 Out4necessary to isolate human subjects from data-acquisition andlife-critical systems. Applications are also found in the military I 'field, for high reliability systems and transportation. OscAn integrated version of an isolation circuit is convention- I

ally an assembly of two separate dies packaged together, as in I _ IJthe case of optocouplers [1], bulk capacitive coupling [2], and Gndi o Gndooptical interconnections [3]. The cost of the isolator can behigh because of the expenses and the difficulties in packagingtwo dies with the desired isolation properties. In addition, the Fig. 1. System architecture: the four channels digital isolation amplifier. Thepower consumption is higher due to the parasitic capacitances digital modulating clock is powered by the receiver side (right) and transmitted

and inductances of multi-chip modules. In a conventional capacitively to the transmitter (left).bulk process, the isolation of two circuits on the same dieis not achievable because of the presence of a common II. SYSTEM OVERVIEWgalvanic substrate. Capacitive coupling has been employed Figure 2 is a detailed schematic of one of the four isolationin bulk CMOS multi-chip modules to transfer data signals channels named isoCap3sc. The specification for each channelbetween multiple dies [4], [5], [6]. On-chip isolation using required a data rate of 40Mbps, military range temperatures,a Silicon-On-Insulator (SOI) substrate has been demonstrated and input signal rise/fall time between 1Ons and l.5ns. Thefor modem lines and for data only [7]. required isolation was at least 100V in continuous mode. The

0-7803-9390-2/06/$20.00 ©C2006 IEEE 3710 ISCAS 2006

device is designed to withstand ground bouncing of more All channels share the same input and output power supplies.than IV/us using a circuit topology able to reject spurious For each channel the input pads are protected against surgestransitions. This feature is obtained by using digital modula- by using protection clamp diodes connected to their powertion of the input signal before transmission to the receiver supply. Output pads are buffered with digital inverters to bethrough the capacitive isolation interface of Figure 2. The able to drive a 25pF capacitive load.use of modulation increases the switching frequency acrossthe coupling capacitor. Spurious transitions are eliminated if I CAPACITIVE COUPLED ISOLATION CIRCUIT MODELthe switching frequency is higher than the maximum allowed In an effort to model the performance of the isolation circuit,ground-bouncing. The input signal is buffered and modulated we compute here two important design parameters:at the transmitter (input) side and communicated to the re- (A) the minimum isolation capacitance for signal couplingceiver (output) circuit using capacitive coupling. Each stage's (B) the minimum input slew-rate necessary to detect acoupling capacitor Cf has a capacitance of 150f and has transitionbeen designed using metal-I and metal-3 plates. The siliconarea used by the capacitor is 175 x 60um2. A. Minimum Capacitance.

Notice that our first isolation device [9], [10] used two Figure 3 is a model of the capacitive-coupling circuit:capacitors per channels, while isoCap3sc only uses one capac- C is the isolation capacitor, Ca and Cb are the parasiticitor, thus saving precious silicon area. In addition the previous capacitances at the two terminals of the isolation capacitor.device provided non-zero bit-error-rates (BER) at low inputrates. We measured BER of 6 10-7 for a 10KHz input. The Icdevice reported in this article, thanks to the digital modulation .

of the input signal, did not suffer from bit-errors at low Vin a Vb Voutfrequencies.

VddoCa b

Vddi

Cf I ~~~~~~~~~~~~~gnd gnd' ibIn > D Q Vgg

Dff DQDff Out Fig. 3. Model of operation of a capacitively coupled isolation circuit.

isolationIGndi barrier GdConsider now an AC model of the capacitive coupling. Vi,

is a digital signal whose value is always between Vdd and 0CLKi CLKo volts. Equivalently Va, is the inverted voltage of Vi, and its

is always between 0 and Vdd volts. The voltage Vb can becalculated by using equation 1.

Fig. 2. The isoCap3sc isolation channel C

Vb = Va (1) CA 180 degrees phase-shift-keying modulation is performed C + Cbby XOR-ing the input signal with the transmitter clock CLKi. As can be seen from the capacitive divider in equation 1, theThe transmitter clock is obtained through capacitive coupling capacitance C must be much larger than the parasitic Cb forfrom the receiver side, where the global clock is generated. We proper operation. If equation 1 is not satisfied, the transmitteduse a 13-stage ring oscillator at the output side to produce an signal amplitude is going to be smaller than Vdd and errorsapproximately 200MHz digital clock signal that modulates the will occur at the receiver.input signal. A D-Type Flip-Flop synchronizes the modulation Let us consider the charge at nodes Vb and across theand demodulation to avoid spurious transitions of the output isolation capacitance C: Qb = CbVb and Q, = C(Va - Vb).due to transmission delay. The input Flip-Flop operates on the The maximum charge at Vb is CbVdd and the minimum isrising clock edge. The demodulator is a Flip-Flop synchro- 0V. The maximum charge across C is C(Vdd + 2Vth) and thenized to the falling edge of the clock CLKo. The output of the minimum is OV. This assumes that the node Vb is protected byisoCap3sc isolation channel is the terminal Out in Figure 2. two diodes connected to the power supplies and with thresholdAt the receiver side, protection diodes located at the receiver Vth.input node enforce that the voltage at the floating nodes always To assess whether the capacitive link is functional, we needdrifts to one of the supplies, to prevent damage in case the to see if a swing of Va can change the state of Vb (charge it byground-bouncing rate is much faster than the modulation rate. ±Vdd). As an example, consider the case when Vb =-VLh and

The final prototype of the capacitive isolation buffer in Va switching from 0V to Vdd. We obtain that the initial chargeFigure 1 (named isoCap3) is organized as an array of 4 Qbi =-CbVLh and the initial charge across C is: Qci CVLh.independent isolation channels isoCap3sc in one single chip. The final value of the charge across the isolation capacitance

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* th f -CV V A lt th fi 1 h 1V11~~~~~~~~~~~JL P6 7006 ACQUIRE lis therefore Qf C(Vdd + Vth). As a result, the final charge .k...... ....

at node Vb is Qbf = -CbVth + C(Vdd + Vth). If we chooseC> Cb then the voltage Vb > Vdd, limited by the protectiondiodes. Thus operation requires that C»> Cb.

B. Minimum Slew-Rate:When employing capacitive isolation, the input voltage

swings is the desired signal to be detected, while groundbounce swings have to be rejected. Let us consider the currents AiT X 1e Iacross the isolation capacitor C. The current ic Pis expressedby equation 2.

dVa dVbtc =C - C (2) Hl1 2,00Y CH2 ZOO g2Ur C2 lv1l6dt dt I

Using the results in [10], we can write equation 3.

C dVgb dVggi Fig. 4. Isolation channel input (top trace) and output (bottom) operating atCb dt Cb dt (3) 40MHz.

With Vgb being the voltage between node b and the inputground (iGnd). The first term on the right hand side of of up to 25pF. A plot of the measured power consumptionequation 3 is due to Va or the input signal. The second term is using 4 channels in parallel is given in Figure 5.the interference or noise due to ground bounce. We conclude No crosstalk between channels was observed. All thesethat, for correct device operation, equation 4 has to be satisfied. measurement were conducted with the isolation chip driving

dVa dVggi 2ft of coaxial cable and a 25pF load (oscilloscope load). Figuredt dt-(4) 4 shows the output of one isolation channel (bottom trace)dt dt when driven with a 40MHz input (top trace).

This imposes a constraint on the minimum signal slewrate. The prototype in this paper satisfies this condition using 60digital modulation of the input signal. Since the modulatingsignal is much faster than the input signal, the input slew-rate is effectively masked. As an example consider the case of 50(dVa/dt)min . This value must be bigger than (dVgg/Idt)max,With a power supply of 3V and a 200MHz modulating clock, 40the value of (dVa/dt)min is approximately 3 x 108V/s. While Ethe expected grounds slew rate (dVgg'/dt) max is about 1 x ao30.

106V/s. These values satisfy equation 4. 0

IV. RESULTS AND MEASUREMENTS 20

We simulated the isolation buffer isoCap3 at the designcorners for temperature, and transistors characteristics. We 10simulated with a temperature range of [-55C, +125C] for typi-cal, fast and slow transistors. We conducted the measurements 0°2 18at 25Mbps. The circuit performed correctly in all settings. We Frequency [Hz]also tested the circuits with a power supply of 3.3V ±10%of the nominal value at 40Mbps. In both cases the circuit

Fig. 5. Power consumption of the isolation amplifier versus input frequency.was operational. All simulations have been conducted with The device was operated with four channels in parallel driven by the sameall 4 inputs tied together and the output connected to a 25pF input.capacitance, corresponding to a worse case scenario for thepower consumption. Operation while providing isolation was verified experimen-

The measured supply current of 4 channels in parallel tally, with the circuit operating with an input square wavewas 1.5mA at low data rates and 3.3V power supply. This of 30MHz, Vddo = 3.3V and VGndo-Gndi = 25V. Figureconsumption is attributed to the ring oscillator operating at 6 illustrates the isolation property of two SOS metal layers.the receiver's side and generating the global modulation clock. Specifications for the device described in this chapter wereThe consumption rose to 4mA with a 10MHz input and 16mA a ground to ground isolation of up to 100V. We measuredwith a 40MHz input. The majority of the power consumption the isolation of the amplifier up to 110V with a Keithleywas due to the output drivers, designed to drive capacitances unit 236 and measured no significant current (Figure 6), as

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evidence that the isolation in the SOS die is conforming to the isolation capacitorspecifications. The actual measured breakdown of the deviceoccurred in the proximity of 820V between the grounds ofinput and output circuits. This isolation is guaranteed by the3.6pum of separation from the metal-I and metal-3 capacitanceplates. The breakdown measurements were conducted using anelectrophoresis equipment FisherBiotech FB400.A picture of the fabricated SOS isolator amplifier is given in

Figure 7. The die has 12 bonding pads: the left six are to tobottom) the input supply, four data inputs and the transmitter'sground; the right six are the output supply, four data outputsand the receiver's ground.

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02r .1. 1 A 2 1 [1] S.Waabnu ir i output circuits-0.5mOI silicon area as opposea to tne tou x l4 ' 'oscillator

0 20 40 60 80 100 120 Fig. 7. Micrograph of the fabricated SOS isolation amplifier.Voltage Difference [V]

Fig.n6e Isoatione performap3sces b een metaandsmetth lal3 c kteS.E20723,NASA Mars Advanced Technology Development grantFig.es6.Ied1243213, point of contact Steve Jaskulek.

REFERENCESFinally we report that each channel isoCap3sc uses 230 x

60n m2 of silicon area, as opposed to the 230 x140si m used [1] 5. Waaben, "High performance optocoupler circuits," in IEEE Inter-national Solid-State Circuits Conference, vol. XVIII, San Francisco,in our first implementation [9], [10]. Taking into account that California, 1975, pp. 30-3 1.one channel isoCap3sc is used to transmit the global clock [2] S. E. Mick, J. M. Wilson, and P. Franzon, "Packaging technology forfrom receiver to transmitter, the four channel device presented AC coupled interconnection," in IEEE Flip- Chip Conference, July 2002.

[3] A. Pappu and A. Apsel, "Electrical isolation and fanout in intra-chipin this paper uses approximately 1/2 of the silicon area of our optical interconnects," in IEEE International Symposium on Circuits andprevious devices. Systems ISCAS 2004, vol. 2, May 2004, pp.1I - 533-6.

[4] 5. E. Mick, J. M. Wilson, and P. Franzon, "4 Gbps AC coupledV. SUMMARY interconnection," in IEEE Custom Integrated Circuits Conference, May

signal desiged and fabreaseimmunited to4 errs diitalo inp datn 192002, pp. 133-140.45] T. J. Gabara and W. C. Fischer, "Capacitive coupling and quantizedamplifier in a 0.5um silicon-on-sapphire technology. The feedback applied to conventional CMOS technology," IEEE Journal ofisolation properties of the sapphire substrate allow to integrate Solid-State Circuits, vol. 32, no. 3, pp. 419-427, March 1997.lV/,usandisolation amp erenthasinge80 . Modlardtion or thevinput [6] D. Saltzman and T. Knight Jr., "Capacitive coupling solves the known

this isolation amplifier in asingleadie.nModulatigood die problem," in IEEE Multi-Chip Module Conference, Marchsignal is used to increase immunity to errors at low input data 1994, pp. 95 -100.rates. The individual isolation channels operate in excess of [7] N. Kanekawa, Y Kojima, S. Yukutake, M. Nemoto, T. Iwasaki,

sK. Takamiand, Y Tekeuchi, and Y Y Y.Shima, "An analog front-end40Mbpsusing a differential transmission scheme. We have LSI with on-chip isolator for V90 56 kbps modems," in IEEE Custom

shown the ability of the device to tolerate ground bounces of Integrated Circuits Conference, May 2000, pp. 327-330.IV/,us and isolate more than 800V. Compared to our previous [8] Peregrine, 0OSum FC Design Manual, 52nd ed., Peregrine Semiconductor

Inc., San Diego, CA, March 2005, http://www.peregrine-semi.com/.desigyn we reduced the silicon area by half and eliminated BER [l]PE.Clucelo P.Pliqn,- A. Andreou, K. Stroh n,a3n S