0000.PPT 5/9/2008 1

Bradford S. WatsonBradford S. WatsonStaff EngineerStaff EngineerAdvanced Algorithm Development GroupAdvanced Algorithm Development Group

Digital Payload Modeling for Space Applications

Copyright 2008. Lockheed Martin Corporation. All rights reserved.

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OverviewOverview

• In recent years in the commercial or government space businesses, there has been a movement away from RF analog payloads for pure “bent-pipe,” or “transponder” applications.

• Up until even the recent past, these payloads have been fixed band plan, implemented with all analog electronics.

• Today’s customers are looking towards all digital payloads that utilize digital signal processing (DSP) to accomplish the same goals while providing enhanced mission capability and flexibility.

Location A Location B

“Bent Pipe” transponder satellite at Geostationary Orbit (35,786 km)

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The ChallengeThe Challenge• Design a Modular Agile digital Payload (MAP) to take the place of the traditional analog communications satellite payload.• The payload must have the following characteristics:

• Be spaceworthy; i.e., highly reliable, and highly tolerant of radiation effects.• Be reconfigurable; that is, able to be altered on-orbit for different functions as business conditions change. • Be highly flexible and agile with respect to bandplan and channelization, so that bandwidth for users can be assigned “on-demand,” and spectrum can be arbitrarily allocated anywhere within the full bandwidth of a beam.• Be modular, and re-useable for many different programs, all with different requirements.

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The Early DaysThe Early Days

• Early on in the program, it was a complete unknown what this system would look like.• Requirements from numerous programs were flying around, and they were often incompatible with each other, particular their bandplans:

• AMC: 4, 8, 36, and 72 MHz wide channels.• MMSI: 24 and 32 MHz wide channels.• JSAT: 27 MHz wide channels.• AsiaSAT: 8 and 36 MHZ wide channels.• and many others…

• These unknown requirements not only made it very difficult to design the hardware, but put a tremendous amount of work on the DSPengineer designing algorithms.

• As the lead DSP engineer, I found myself re-writing the algorithms almost daily, in order to demonstrate the various bandplans.

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The Hardware SolutionThe Hardware Solution

Digital Channelizer Unit (DCU):• A modular, space-worthy payload composed of the following building blocks:• CIO – Channelizer I/O Module

• Composed of 5 Field Programmable Gate Arrays (FPGAs), three of which are voted for extremely high reliability.• Handles all of the signal processing, real-time.

• DRM – Data Routing Module• Multi-gigabit, non-blocking data routing in rad tolerant FPGAs.

• RIO – RF Input/Output Modules• Power Converters

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System Level DCU ArchitectureSystem Level DCU Architecture

Beam 4Beam 3

Beam 2

SPARE

Beam 1Beam 2Beam 3Beam 4

RF

SPARE

RF ADC Dig

SPARE

Dig

SPARE

Dig Dig DAC

Beam 1

RF

SPARE SPARE

ControllerSCB

Frequency Generation

EPC & Intermediate Power

Spacecraft TT&C Bus MIL

-STD

155

3 B

Spacecraft RIU

RIO – RF Input/Output Module

CIO – Channelizer Input/Output Module

DRM – Data Routing Module

Serial Command Bus

Each input port (RIO):

125 MHz anti alias filter

RF power optimized for ADC

CIO modules:

Digitize Spectrum

Divide Channels

DRM module:

Multi-Gigabit

Routing

CIO modules:

Reconstruct Spectrum

Dig. to RF conversion

RIO modules:

Reconstruction

Filtering

BCA Control

5 for 4 Processing Modules

2 For 1 Router/Controllers

RF RF

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DCU on MAP SpacecraftDCU on MAP Spacecraft

MAP MAP –– type type SpacecraftSpacecraft

Digital Channelizer Unit Digital Channelizer Unit ((DCUDCU)) CIOCIO DRMDRM

Channelization in CIOChannelization in CIO

Active Arrays

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DCU AlgorithmDCU AlgorithmAlgorithm Overview

•• The The DCU algorithm DCU algorithm is defined as the mathematical manipulation (via fixed point is defined as the mathematical manipulation (via fixed point arithmetic implemented in the DCU FPGAs) of data samples to perfarithmetic implemented in the DCU FPGAs) of data samples to perform the following orm the following tasks:tasks:

–– Process a total digitized analog frequency bandwidth of 500 MHz Process a total digitized analog frequency bandwidth of 500 MHz (which may or (which may or may not be contiguous).may not be contiguous).

–– Break up this bandwidth into narrowband Break up this bandwidth into narrowband ““subchannelssubchannels”” (i.e., (i.e., ““channelizechannelize””))–– Have the ability to reHave the ability to re--arrange the subchannels in any arbitrary order.arrange the subchannels in any arbitrary order.–– Have the ability to alter the subchannel gains arbitrarily, in mHave the ability to alter the subchannel gains arbitrarily, in multiple modes.ultiple modes.–– Have the ability to measure and report the average and peak signHave the ability to measure and report the average and peak signal power level at al power level at

the input and output of the DCU, as well as at the subchannel lethe input and output of the DCU, as well as at the subchannel level.vel.–– Recombine the subchannels (i.e., "reconstruct" them) into a compRecombine the subchannels (i.e., "reconstruct" them) into a composite bandwidth of osite bandwidth of

the same size as the input.the same size as the input.–– Transform the recombined spectrum so that it can be converted baTransform the recombined spectrum so that it can be converted back into the ck into the

analog domain for further processing.analog domain for further processing.–– Be arbitrarily reconfigurable in signal processing function.Be arbitrarily reconfigurable in signal processing function.

•• The functional data flow for a 4 port DCU is depicted here:The functional data flow for a 4 port DCU is depicted here:

DACDAC

DACDAC

ReconstuctReconstuct

ReconstuctReconstuctRoute

ChannelizeChannelize

ChannelizeChannelize

ADCADC

ADCADC

Port 0Port 1

Port 2Port 3

Port 0Port 1

Port 2Port 3

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Matlab Algorithmic Model

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Input Signal Spectrum After Quarter Band Filtering

Frequency (MHz)

Am

plitu

de (d

B)

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Reconstructed Function Output

Frequency (MHz)

Am

plitu

de (d

B)

-2 0 2-100

-50

0subch 0, port 0

MHz

dB

-2 0 2-100

-50

0subch 1, port 0

MHz

dB

-2 0 2-100

-50

0subch 2, port 0

MHz

dB

-2 0 2-100

-50

0subch 3, port 0

MHz

dB

-2 0 2-100

-50

0subch 4, port 0

MHz

dB

-2 0 2-100

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0subch 5, port 0

MHz

dB

-2 0 2-100

-50

0subch 6, port 0

MHz

dB

-2 0 2-100

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0subch 7, port 0

MHz

dB

-2 0 2-100

-50

0subch 8, port 0

MHz

dB

-2 0 2-100

-50

0subch 9, port 0

MHz

dB

-2 0 2-100

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0subch 10, port 0

MHz

dB

-2 0 2-100

-50

0subch 11, port 0

MHz

dB

-2 0 2-100

-50

0subch 12, port 0

MHz

dB

-2 0 2-100

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0subch 13, port 0

MHz

dB

-2 0 2-100

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0subch 14, port 0

MHz

dB

-2 0 2-100

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0subch 15, port 0

MHz

dB

-2 0 2-100

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0subch 16, port 0

MHz

dB

-2 0 2-100

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0subch 17, port 0

MHz

dB

-2 0 2-100

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0subch 18, port 0

MHz

dB

-2 0 2-100

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0subch 19, port 0

MHz

dB

-2 0 2-100

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0subch 20, port 0

MHz

dB

-2 0 2-100

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0subch 21, port 0

MHz

dB

-2 0 2-100

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0subch 22, port 0

MHz

dB

-2 0 2-100

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0subch 23, port 0

MHz

dB

-2 0 2-100

-50

0subch 24, port 0

MHz

dB

-2 0 2-100

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0subch 25, port 0

MHz

dB

-2 0 2-100

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0subch 26, port 0

MHz

dB

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Two - Sided Input Signal Spectrum After Sampling (Possibly Aliased Spectrum)

Frequency (MHz)

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Passband Output Spectrum

Frequency (MHz)

Am

plitu

de (d

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Input IF Preprocess

Channelize

Reconstruct Output IF

• A floating point model of the DCU algorithm has been developed in the Matlab environment.

• This model is designed to be veryflexible, allowing the user to specify a wide range of arguments.

• This makes the Matlab model useful for functionally verifying various channelization schemes quickly and efficiently. The user simply needs to pick the right parameters (filter coefficients, FFT length, decimation/interpolation factors), etc.

• The DCU algorithm function can be called from the Matlab command line, or as part of a script file.

• This function is composed of lower level functions that do arbitrary channelization and reconstruction.

routing_table, gain_table

Route,

GainRoute,

Gain

DCU AlgorithmDCU Algorithm

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Simulink Structural Model

Simulink Model

FPGA SynDSP Blockset Model

Simulink to Hardware Development

HDL Synthesis

The next step in the development was to build a structural model of the DCU algorithm in the Simulink environment.

• This model is designed to test implementation assumptions about the DCU Algorithm and provide a model that is very similar to what the real gateware will look like.

Once the Simulink model works properly, another Simulink model is developed by replacing the blocks with components from another vendor’s blockset in order to generate VHDL.

Simulink Block Diagram

DCU AlgorithmDCU Algorithm

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DCU AlgorithmDCU AlgorithmModel VerificationOnce VHDL for the various pieces of the DCU algorithm have been developed, tested in the Simulink environment, and stitched together in the Mentor HDL environment, the next step is functional simulation and verification.

For this task, we choose the EDA Simulator Link MQ tool (formerly known as “Link for Modelsim”).

• This tool allows us to make use of all of the signal generation and visualization tools available to us in the Simulink environment, while still simulating the VHDL at the bit level.

• In fact, we can use the exact same test-benches for VHDL test and verification that we used during the development phase.

• This tool was immensely helpful in finding bugs in the code that were not apparent in the Simulink environment alone.

Pull the generated code together with HDL Designer

Bring into Simulink Environment Simulate with ModelSim

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ConclusionConclusion• Using advanced tools and methods, we took a program from concept through functional, space-worthy hardware in about 1½ years.

• Estimated reduction in development time 8 months over traditional (hand coding) methods.

• Process flow and tools:• Concept – Matlab (Signal Processing Toolbox)• Structural Model – Simulink (Signal Processing and Communications Blockset)• VHDL Model – SynDSP Blockset in Simulink Environment• VHDL Code Integration – HDL Designer• Functional Verification and Degugging - EDA Simulator Link MQ tool in Simulink Environment