IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 38, NO. I , FEBRUARY 1989 59

Digital Measurement of the Polar and Rectangular Forms of Impedances

SALEEM M. R. TAHA

Aktruct-A digital method for the measurement of the real and imaginary parts of the impedance (rectangular-form), as well as its magnitude and phase (polar-form) is described. It depends on using a new hybrid processor that gives digital numbers that are proportional to the imaginary and real parts of the impedance, besides the magni- tude and phase. A circuit for indicating whether the impedance is ca- pacitive or inductive is also given. This method could also be used for admittance measurement and for the determination of the inductance or capacitance of any circuit. The basic accuracy of the system is about 0.2 percent.

I. INTRODUCTION HE impedance measurement bridges, such as the T Schering bridge and Maxwell bridge [l], provide

methods used for impedance measurement. However, these methods have difficulty in obtaining the balanced condition [2].

The vector impedance method is one of many electronic methods for impedance measurement [3]. This method re- quires the flow of a constant current through the unknown impedance and that is difficult to obtain for capacitive and high value impedances. There is another electronic method for impedance measurement using two quadrature sinusoidal waves [4]. But this method is sensitive to the change in the amplitude of the two input waves.

This paper introduces a new method for impedance measurement. It depends on generating four analog sig- nals that are proportional to the voltage ( V z ) across the unknown impedance, the current ( Zz ) through it, and the sine and cosine of the phase angle between them. Both forms of the impedance (polar and rectangular) are cal- culated. In this method the current through the unknown impedance is not necessarily constant. Also, this method can be modified easily to obtain the admittance measure- ment.

11. THEORY OF OPERATION Fig. 1 shows the block diagram used for impedance

measurement. The unknown impedance (2 ) is connected in series with a known resistance ( R ) to a sinusoidal os- cillator of frequency f = u /2x . Since the voltage V3 across the resistance ( R ) is equal to V, - VI, and the

Manuscript received December 23, 1987; revised August 5, 1988. The author is with the Electrical Engineering Department, College of

IEEE Log Number 8824663. Engineering, University of Baghdad, Baghdad, Iraq.

current Zz that passes through ( 2 ) is equal to the current ZR passing through (R ), then

V3 = ZzR sin ( u t ) . (1)

Let the voltage V , across the unknown impedance (2 ) be Vz sin (ut + +), where + is the impedance argument. These two voltages VI and V3 are then applied to the hy- brid processing unit (HPU) to get four digital words. The first corresponds to +, the second is equal to the imped- ance magnitude 12 1, the third and fourth are equal to the imaginary and real parts of the impedance, respectively.

111. THE HPU CIRCUIT DESCRIPTION As explained above, the HPU circuit performs the mea-

surements of the polar and rectangular forms of the un- known impedance. Fig. 2 shows the schematic diagram of the HPU circuit.

A. Evaluation of + The two waves V, sin ( u t + +) and ZzR sin (ut) are

applied to comparators C1 and C2 (Fig. 2). The output square waves ( a and b ) are then exclusively ORed. The EX-OR gate output is then Armed with wave a and clock pulses. The output of the AND gate (wave c) is then ap- plied to a counter to obtain a digital word that represents the angle +. Fig. 3 shows the waveforms timing diagram that illustrates the evaluation of + process.

B. Evaluation of 12 1 In order to evaluate the magnitude of the unknown

impedance, two dc signals are generated. The first is pro- portional to the voltage Vz across the unknown imped- ance, the second is proportional to the current Zz through it. Then these two signals are applied to the well-known dual-slope analog-to-digital converter (ADC). The first is applied as the analog input of the ADC and the second as the reference input, to obtain a digital word that is pro- portional to 12 1, where 12 I = Vz/Zz. Let us first consider the generating of a dc signal that is proportional to V,. The signal Vz sin ( u t + +) is applied to a 90" phase-shift circuit to obtain the signal Vz cos (ut + +), (see Fig. 2). Fig. 4 shows the active RC realization of the 90" phase shift. In this active phase shifter, monolithic operational amplifier and RC discrete elements were used in the re-

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 38. NO. I , FEBRUARY 1989

Fig. 1 . The complete block diagram for impedance measurement.

Polar-torm Of i

Rectan(pllar - form of t

sin (wt ~

COUNTER

Fig. 2. Schematic diagram of the HPU circuit.

I t

aL time

time

bb time

C

11111 -time

Fig. 3 . Waveforms at different points of the HPU circuit.

- Fig. 4. Active RC realization of the 90' phase shift.

alization of this quadrature amplifier. Its voltage transfer function is

(2) v o

Vi T = - = l / n - 2 tan-' WCR.

The output voltage remains equal to the input voltage, when the phase shift is varied from about 0" to 180". Quadrature voltage is obtained when wCR = 1 [ 5 ] . The circuit was fabricated with a 74 1-pA operational ampli-

TAHA: DIGITAL MEASUREMENT OF IMPEDANCES 61

Fig. 5 . Diagram of the DVG.

fier, a polyester capacitor, and metal film resistors, each of 1-percent tolerance. The values of circuit components, for 1-kHz operation, are shown in Fig. 4. For the resistor R, a variable pot was used. It was adjusted until the de- sired phase shift of 90" was obtained.

Two digital vector generators (DVG), DVG1 and DVG2, are used to generate two signals, the first is Vz cos ( u t + 4 ) sin 4 and the second is Vz sin ( u t + 4) cos 4. When these two signals are subtracted from each other, a signal Vz sin ut is obtained. The DTM 1717 type DVG is used in the circuit implementations of both DVG1 and DVG2. Fig. 5 shows this type of the DVG. The Vz sin ut signal is then applied to the rectifier and averager (B ) circuit to obtain a dc signal K2 Vz( K2 is constant and will be defined later).

The signal Iz R sin (u t ) is applied to the rectifier and averager ( A ) , which consists of an op-amp that works as a full-wave rectifier of gain ( R , / R 2 ) . Thus the average output that follows it is equal to ( IzRR1/R2?r) = K I Iz (where K , = RR, /R2?r ) . This dc signal, after being in- verted, is applied to the ADC as the reference input.

Since the rectifier and averager (B ) circuit is the same as (A ), then K2 = RI / R 2 T. The dc signal K2 Vz is applied to the ADC, via the multiplexer, as the analog input of the ADC. Then the ADC output is a digital word repre- senting 12 I = V z / l z .

C. Evaluation of the Real and Imaginary Parts of 2 Let us define the real and imaginary parts of 2 as

Re ( 2 ) = Vzcos 4/Zz

Im ( 2 ) = Vz sin + / I z .

( 3 )

(4) In order to obtain two dc signals representing Vz cos 4 and Vz sin 4, two sample-and-hold ( S / H ) circuits (S /Hl and S/H2) are used to hold the instantaneous values of Vz cos ( u t + 4) and Vz sin ( u t + 4 ) at the instant that ut = 0 (Fig. 2). This is accomplished, using a monostable that gives the hold signal to both ( S / H ) circuits at the low-to-high transition state of waveform b, which oc- cured at ut = 0.

The outputs of the S/H circuits are then applied to the ADC (via the multiplexer) to obtain two digital words representing Re (Z ) and Im (2 ).

D. Capacitive/Inductive Indicator The capacitive-inductive indication circuit is shown in

Fig. 6. An SR flip-flop is used here. The wave (a) is used to control the set of the flip-flop. The reset is controlled

clk I I I I

capacitive inductive

Fig. 6. The capacitive/inductive indication circuit and its waveforms.

RING COUNTER L

I

qLATc?, I ?yLic;2] q L k 3 J

I Z I t m ( Z ) Re ( Z )

Fig. 7. The implementation of the multiplexer, ADC, and latches circuits of the HPU circuit.

by the inverted ( a ) signal. The wave (b) is differentiated, and used to clock the input of the SR flip-flop. This circuit determines whether wave (a) leads or lags wave (b), hence, the output Q represents the sign of angle 4. If Q is low, the unknown impedance is inductive; and if it is high, the unknown impedance is capacitive.

E. The Multiplexer, ADC and Latches Circuits Fig. 7 shows the multiplexer, ADC, and latches circuits

of the HPU. Four dc signals, (K2 Vz, VZ sin 4, VZ cos 4, and - K1 I z ) , are applied to these circuits to evaluate the quantities I 2 1, Re (2 ), and Im (2 ) as digital words.

The well-known dual-slope ADC is used here as a di- vider (as explained above). To avoid using three ADC's for each quantity measurement, a single ADC is imple- mented with a multiplexer in front of it to time-share the same ADC for these three measurements cycles.

A ring counter is used to control the multiplexer. At first, the LSB of this counter is high, while the other bits are low. Thus switch S1 is closed, applying the K2 Vz volt- age to the integrator. The output of the integrator ramps

62 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT. VOL. 38, NO. I . FEBRUARY 1989

down due to its positive input. Consequently, the com- parator's output is high and the counter starts counting the clock pulses until the counter reaches its full-scale state (i.e., all its output bits are high). Then the output of the AND (1) gate becomes high, this is used to trigger the D flip-flop and the ring counter. Hence, switch S1 is open and S4 is closed, applying the ( - K 1 Zz ) voltage to the integrator. Thus the integrator's output ramps down, and when it reaches to zero the comparator's output becomes low. Hence, the counter stops counting and let its count- ing value at this instant be (N 1 ), where [6]

N1 = K(Vz/Zz) = K ( Z ( (5) where

K = (2" - 1) (K*/KI), n number of bits of the counter.

The high-to-low change in the comparator output is used to trigger a monostable whose pulse output will trigger the ring counter, hence, its 2' bit changes state from high- to-low. This change of the state of the 2' bit is used to latch the digital word N1 in the LATCH1 circuit. The monostable output pulse is also used to reset the integrator by closing switch S5, while its high-to-low transition is used to clear the counter and the D flip-flop. Hence, the circuit is now ready to repeat the above described process with the Vz sin 4 as the analog input to the ADC and ( -K, Zz) as the reference input. Let the final digital word of the counter at the end of the second conversion cycle be N2, then

N2 = K ' ( V z sin + / I z )

= K' Im (2) (6) where

K' = (2" - l ) /KI.

A third cycle of measurement is done with the V, cos 4 as the analog input and ( - K1 Zz) as the reference' input. Now, let the final digital word be N3, then

N3 = K'( Vz COS +/Zz)

= K' Re ( Z ) . (7)

IV. EXPERIMENTAL RESULTS AND DISCUSSION The system for the digital impedance measurement has

been constructed experimentally with ( 2 1 /2 ) SN7493 as the counter and (2 1/2) SN74175 as the latches. Also, AM460 is used as the comparators and pA741 as the op- amps.

Impedance magnitude between 1 Q and 1 MQ over 5 decade ranges of measurement can be easily changed by changing the value of the known resistance R . Increasing the impedance magnitude above 1 Mil will reduce the ac- curacy, since this impedance will be comparable with the value of the input impedance of the components that fol- low it. This will cause the currents Z, and Zz to be unequal.

It should be noted that this method gives the value of impedance (magnitude, phase, real, and imaginary parts) at the source frequency f (for this frequency, the fre- quency of the clockfc that is used for the dual-slope ADC divider is made equal to ( 3 X 2" + ' ) f ) . Moderate accu- racy (better than 0.5 percent) has been obtained for fre- quencies less than 1 kHz using a 10-bit ADC output. For this range of frequency, the influence of parasitic capac- itors can be ignored [7]. The upper limit of frequency is mainly determined by the slew rate of the comparator and op-amps.

For the phase detection scheme (Fig. 2), the finite slew rate of the comparators C1 and C2 will cause its square output to be delayed by a phase (A4). Thus the S/Hl and S/H2 circuits output will be Vz sin ( 4 + A+) and

This will cause errors in the Re ( Z ) and Im (2 ) mea- surements. From (6) , one may evaluate the change (AN2) in the number N2 due to change in 4 by A4:

N2 + AN2 = K'(Vz/Zz) sin (4 + A+).

Vz COS ( 4 + A+).

Simplifying this equation one may obtain [8]

AN2 = KIA4 Re (2).

AN3 = K' A 4 Im (2).

(8 )

(9)

Similarly from (7), one may obtain

One of the reasons for the phase error A4 is due to the assumption that the EX-OR gate gives a two precision volt- age at low and high states. If AI, and A2 are the change in the level of voltage at low and high states, respectively, then A+ will be proportional to ( n / 2 - 4) AI, and 4A2, respectively.

It should be noted that the error due to the 90" phase shift module could be considered as a phase error which is mainly due to the finite slew rate of the op-amp used, and due to the distortion of the input sinusoidal wave. Also, the finite sample time ( T ~ ) of the S / H circuits will cause their outputs to be Vz sin ( 4 + 2 ~ f . r ~ ) and Vz cos

The output of the difference amplifier V3 (Fig. 1) is ( 4 + 2nf7s).

given by

Now, if R I = R, = R3 = R4, then V3 = V, - VI. However, due to the 'error in the value of these resis- tances, one may write R2 as ( R I + 6 R 2 ) , R3 as ( R I + 6R3) , and R4 as ( R I + 6R4) , where 6R2, 6R3, and SR4 are the difference between the value R , and R2, R3 and R4, respectively. Thus (lo)% can be written (after simplifica- tion and approximation) as [7]

6R2 + 6R3 - SR4 6R2 v, + - VI. 2R1 R2

V3 = ( V , - VI) +

TAHA: DIGITAL MEASUREMENT OF IMPEDANCES 63

TABLE 1

Parameter Measuring Range* Maximum Resolution*

2, R , X 1 0-1 MQ 0.1 mQ Y, G , B 10 $3-10 s 0.001 ps ,$ - 180” to + 180” 0.01” L 100 nH-1000 H 0.01 nH C 1 pF-l F 0.1 pF

*Depends on measuring frequency.

The second and third terms of (1 1) will cause the dif- ference amplifier output (V , ) to differ from the voltage across the resistance R both in phase and magnitude. This will cause errors in the measurements.

Four common sources of noise present problems in an- alog switch technology. These are: popcorn noise, l/f noise, thermal noise, and shot noise [9]. The hybrid JFET analog switches (for example, DG 181 and DG 281) can offer the discerning user certain advantages over MOS- FET and CMOS analog switches (DG508 as an example) in terms of noise, thermal offsets, and charge injection. Therefore, JFET analog switches are used in circuit de- sign.

It should be noted that this method can be used for ad- mittance measurement ( Y ) by interchanging the two waves V, sin (ut + 4) and ZzR sin ( u t ) .

This method could also be used for determining the in- ductance or capacitance of any circuit. The quality or dis- sipation factor (that is equal to the ratio of the imaginary to real part) could be measured by this method.

The system’s specifications are summarized as follows (Table I). Measured parameters: Z(impedance), Y(ad- mittance), 4 (phase angle), R (resistance), X(reac-

tance), G(conductance), B(susceptance), L(induc- tance), C(capacitance).

Z, R, X 1 Q-1 MQ Y, G, B: 1 nS-10 S L: 1 nH-1 kH C: 1 pF-1 F 4: -180” to +180” Test signal frequency: 5 Hz-1 MHz Basic accuracy: 0.2 percent

ACKNOWLEDGMENT The author wishes to thank A. Estephan for his kind

help in preparing the original figures for this paper.

REFERENCES [ 11 C. Oliver, Electronic Measurement and Instrumentation. New York:

McGraw-Hill, 1971. [2] D. Tait, “Inductance measurement-A new bridge configuration,”

Electron. Ind., vol. 6, no. 1 1 , pp. 22-23, 25, Nov. 1980. [3] C. J . Alonto et a l . , “Direct reading fully automatic vector impedance

meters,” Hewlett-Packard J . , pp. 12-20, Jan. 1967. [4] R. J. Reis, “Measurement of an unknown impedance in an automatic

tester,” IBM Tech. Disclosure Bull., vol. 24, no. 7A, pp. 3147-3148, Dec. 1981.

[5] M. Rahman, M. T. Ahmed, and V. G. K. Murti, “A TRA bridge technique for in-circuit impedance measurement,” IEEE Trans. In- strum. Meas., vol. IM-33, pp. 252-256, Dec. 1984.

[6] S. M. R. Taha and M. A. H. Abdul-Kanm, “New analogue processor using digital circuits,” Int. J. Electron., vol. 52, no. 5, pp. 455-461, 1982.

[7] K. M. Ibrahim and M. A. H. Abdul-Karim, “Digital impedance mea- surement by generating two waves,” IEEE Trans. Instrum. Meas., vol. IM-34, pp. 2-5, Mar. 1985.

[SI -, “Digital impedance measurement based on inverse sine function module,’’ IEEE Trans. Insrrum. Meas., vol. IM-35, pp. 87-88, Mar. 1986.

[9] E. Davies, “Errors associated with analogue switches,” Electron. Eng., pp. 149-152, Nov. 1979.