PRESENTED BY-NEERAJ KUMAR

VISHWAJEET KUMARYOGENDRA KUMAR

RAJU KUMARMRINMOY MANDAL

ABHISHEK GUPTA

Design of an Electronic Lock System

Project Guide-Mr. Tarun Kumar Das(Assistant Professor,ECE Department)

1) Objective 2) What is an Electronic lock?3) Types of Electronic lock4) Our approach to the Design5) Finite State Machines(FSM)6) Field Programmable Gate Array (FPGA)7) VHDL Overview & Architecture8) Xilinx Spartan3 Interfacing8) Results and Analysis9) Future Scope10) Conclusion 11) References & Bibliography

Contents

Objective

The objective of this project is to implement a electronic-lock system where the user will be granted access to his locked room simply through a password. With such a system, the advantages of keyless access will be accomplished with only passive involvement from the client.

An electronic lock is a simple type of a keyless door lock System which can

be accessed by any person knowing its

unlock code.

What is an Electronic Lock?

Types of Electronic Lock

Electronic locks can be of different types:-Numerical, Password or Code lockCard LockBiometrics, etc

Our Approach to the Design

Our approach was to design an electronic lock which requires password for authentication. This password is in the form of numerical code.

We have written the code in VHDL and simulation is done on ALDEC software. Later on it was to be burn on spartan-3 kit.

Before going into the detail a brief description of Finite State Machines, VHDL, FPGA and Spartan-3 kit was required as we have used all these during our Project.

System Design

For the design of an electronic lock we have utilized an 8-bit PISO shift register & FSM (Mealy Machine). The following block diagram represents our design:

Design Description

Our approach to design an electronic lock begin with the design of an 8-bit FSM. Initially an 8-bit sequence is fed to a 8-bit PISO shift register, the output of the PISO is connected to the FSM. Both the PISO and the FSM are synchronized by a single clock.

We choose a 8-bit sequence for the PISO and then draw the state diagram of 8-bit manually, from it we have derive the state table and from state table we design a Logic Diagram. We also have written the code for FSM in VHDL and obtained a state diagram which is similar to the manual drawn state diagram.

Logic Diagram

Finite State Machines

A sequential system is also known as Finite State Machine (FSM). The FSM approach to sequential design is a straight forward generic approach that allows any sequential system to be designed. In theory, a sequential system of any complexity can be designed as a single FSM. In practice, complex systems are decomposed into components, where one or more are FSMs.

FSM can be classified into two types:- 1) Mealy Machine 2) Moore Machine

Mealy Machine

In a Mealy machine, the outputs are a function of the present state and the value of the inputs as shown in Figure.

Accordingly, the outputs may change asynchronously in response to any change in the inputs.

Moore Machine

In a Moore machine the outputs depend only on the present state as shown in Figure.

A combinational logic block maps the inputs and the current state into the necessary flip-flop inputs to store the appropriate next state.

However, the outputs are computed by a combinational logic block whose inputs are only the flip-flops state outputs.

The outputs change synchronously with the state transition triggered by the active clock edge

State Diagram of Our Design

Field Programmable Gate Array (FPGA)

FPGA usually refers to a VLSI module that can be programmed to implement large digital systems containing thousands of gates. These multilevel gate networks may include random gates to state machines. FPGA contains many identical logic cells where each logic cells can be individually programmed.

The advantages of FPGA are- It has very short turn-around time, Since no physical manufacturing step is necessary a

functional sample can be obtained almost as soon as the design is mapped into a specified technology,

Though FPGA chips are very costly but for small volume production of ASIC chips and for fast prototyping FPGA offers a very valuable option

Cell Based Approach of FPGA

FPGA (Spartan 3) Kit Interfacing

VHDL Overview

VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level.

The VHDL language can be regarded as an integrated amalgamation of the following languages:

Sequential language + Concurrent language + Net-list language + Timing specifications + Waveform generation language => VHDL

VHDL Architectural Styles

Data Flow Modeling: Describes paths and operations on signals as a circuit is

traversed Uses signal assignmentsBehavioral Modeling: No details about the circuit implementation are implied by the

description (i.e., uses a higher level of abstraction) Describes the circuit responses(behavior) to input conditions Relies on the sequential nature of the processStructural Modeling: Breaks up the implementation into a hierarchy of subsystems

(“components”) Describes more complex entities in terms of combinations of

simpler component

Results and Analysis(State Diagram drawn manually)

Results and Analysis(State Diagram obtained from Software)

Entity : f sm_8bitArchitecture: f sm_8bit

zd[7:0] clkreset

c reg[7:0]

c x

process(clk)begin

if (clk'event and clk='1') then i f(reset='1')then reg<=d;else reg<=reg(6 downto 0)& '0';end i f;end i f;

end process;x<=reg(7);

process(clk)begin

if (clk'event and clk='1') then i f(reset='1')then reg<=d;else reg<=reg(6 downto 0)& '0';end i f;end i f;

end process;x<=reg(7);

present_state

clk

No clock enablece

s0

z<='0';z<='0';

s1

z<='0';z<='0';

s2

z<='0';z<='0';

s3z<='0';z<='0';

s4 z<='0';z<='0';

s5 z<='0';z<='0';

s6

s7z <='1';z <='1';

z<='0';z<='0';

x='0'@ELSE

x='1'

@ELSE

x='1'

@ELSE

x='0'

@ELSE

x='1'

@ELSE

x='0'

z<='0';z<='0';

@ELSE

x='1'

@ELSE

x='1'

z<='1';z<='1';

@ELSE

reset='1'

Results and Analysis(Output Waveform)

When reset is high (reset=1) the input data is loaded into the register.

Results and Analysis(Output Waveform)

After making reset low from previous high state we get output high (z=1) when the FSM detects the correct 8-bit input sequence “01101011” and all the registers are reset.

Future Scope

The overall work done by us led to a particular point from where we can move our project to multiple directions:-

We can design a hardware using the logic diagram implemented in our project

We can directly burn the VHDL code on a memory chip using FPGA kit

The level of security can also be enhanced by increasing the number of bits in the code

The system can be made more secure by connecting the output end of a lock to an online monitoring system

Conclusions

Our whole concept of the project was to design a lock system with an 8-bit code using the Mealy Finite State Machine that we have successfully implemented on software.

We have satisfactorily completed most sections of our aimed project. We could not achieve 100 percent because of some unavoidable constraints.

In spite of the constraints we were able to complete most of the portions and we are very satisfied with our work.

References & Bibliography

www.wikipedia.orgwww.google.co.inwww.ieee.comwww.electriclock.nethttp://electrosofts.com