digital integrated circuits a design perspective
DESCRIPTION
Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, 2002. Goal of this chapter. Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis - PowerPoint PPT PresentationTRANSCRIPT
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Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
The DevicesThe Devices
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
July 30, 2002
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Goal of this chapterGoal of this chapter
Present intuitive understanding of device operation
Introduction of basic device equations Introduction of models for manual
analysis Introduction of models for SPICE
simulation Analysis of secondary and deep-sub-
micron effects Future trends
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The DiodeThe Diode
n
p
p
n
B A SiO2Al
A
B
Al
A
B
Cross-section of pn-junction in an IC process
One-dimensionalrepresentation diode symbol
Mostly occurring as parasitic element in Digital ICs
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Depletion RegionDepletion Regionhole diffusion
electron diffusion
p n
hole driftelectron drift
ChargeDensity
Distancex+
-
ElectricalxField
x
PotentialV
W2-W1
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostaticpotential.
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Diode CurrentDiode Current
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Forward BiasForward Bias
x
pn0
np0
-W1 W20p n
(W2)
n-regionp-region
Lp
diffusion
Typically avoided in Digital ICs
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Reverse BiasReverse Bias
x
pn0
np0
-W1 W20n-regionp-region
diffusion
The Dominant Operation Mode
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Models for Manual AnalysisModels for Manual Analysis
VD
ID = IS(eVD/T – 1)+
–
VD
+
–
+
–VDon
ID
(a) Ideal diode model (b) First-order diode model
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Junction CapacitanceJunction Capacitance
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Diffusion CapacitanceDiffusion Capacitance
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Secondary EffectsSecondary Effects
–25.0 –15.0 –5.0 5.0
VD (V)
–0.1
I D (A
)
0.1
0
0
Avalanche Breakdown
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Diode ModelDiode Model
ID
RS
CD
+
-
VD
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SPICE ParametersSPICE Parameters
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What is a Transistor?What is a Transistor?
VGS VT
RonS D
A Switch!
|VGS|
An MOS Transistor
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The MOS TransistorThe MOS Transistor
Polysilicon Aluminum
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MOS Transistors -MOS Transistors -Types and SymbolsTypes and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS withBulk Contact
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Threshold Voltage: ConceptThreshold Voltage: Concept
n+n+
p-substrate
DSG
B
VGS
+
-
Depletion
Region
n-channel
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The Threshold VoltageThe Threshold Voltage
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The Body EffectThe Body Effect
-2.5 -2 -1.5 -1 -0.5 00.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
VBS
(V)
VT (
V)
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Current-Voltage RelationsCurrent-Voltage RelationsA good ol’ transistorA good ol’ transistor
QuadraticRelationship
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS (V)
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
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Transistor in LinearTransistor in Linear
n+n+
p-substrate
D
SG
B
VGS
xL
V(x) +–
VDS
ID
MOS transistor and its bias conditions
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Transistor in SaturationTransistor in Saturation
n+n+
S
G
VGS
D
VDS > VGS - VT
VGS - VT+-
Pinch-off
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Current-Voltage RelationsCurrent-Voltage RelationsLong-Channel DeviceLong-Channel Device
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A model for manual analysisA model for manual analysis
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Current-Voltage RelationsCurrent-Voltage RelationsThe Deep-Submicron EraThe Deep-Submicron Era
LinearRelationship
-4
VDS (V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
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Velocity SaturationVelocity Saturation
(V/µm)c = 1.5
n
(m/s
)
sat = 105
Constant mobility (slope = µ)
Constant velocity
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PerspectivePerspective
IDLong-channel device
Short-channel device
VDSVDSAT VGS - VT
VGS = VDD
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IIDD versus V versus VGSGS
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VGS (V)
I D (
A)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VGS (V)
I D (
A)
quadratic
quadratic
linear
Long Channel Short Channel
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IIDD versus V versus VDSDS
-4
VDS (V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS (V)
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
ResistiveSaturation
VDS = VGS - VT
Long Channel Short Channel
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A unified modelA unified modelfor manual analysisfor manual analysis
S D
G
B
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Simple Model versus SPICE Simple Model versus SPICE
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VDS
(V)
I D (
A)
VelocitySaturated
Linear
Saturated
VDSAT=VGT
VDS=VDSAT
VDS=VGT
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A PMOS TransistorA PMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0-1
-0.8
-0.6
-0.4
-0.2
0x 10
-4
VDS (V)
I D (
A)
Assume all variablesnegative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
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Transistor Model Transistor Model for Manual Analysisfor Manual Analysis
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The Transistor as a SwitchThe Transistor as a Switch
VGS VT
RonS D
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
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The Transistor as a SwitchThe Transistor as a Switch
0.5 1 1.5 2 2.50
1
2
3
4
5
6
7x 10
5
VDD
(V)
Req
(O
hm)
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The Transistor as a SwitchThe Transistor as a Switch
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The Sub-Micron MOS TransistorThe Sub-Micron MOS Transistor
Threshold Variations Subthreshold Conduction Parasitic Resistances
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Threshold VariationsThreshold Variations
VT
L
Long-channel threshold Low VDS threshold
Threshold as a function of the length (for low VDS)
Drain-induced barrier lowering (for low L)
VDS
VT
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Sub-Threshold ConductionSub-Threshold Conduction
0 0.5 1 1.5 2 2.510
-12
10-10
10-8
10-6
10-4
10-2
VGS (V)
I D (
A)
VT
Linear
Exponential
Quadratic
Typical values for S:60 .. 100 mV/decade
The Slope Factor
ox
DnkT
qV
D C
CneII
GS
1 ,~ 0
S is VGS for ID2/ID1 =10
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Sub-Threshold Sub-Threshold IIDD vs vs VVGSGS
VDS from 0 to 0.5V
kT
qV
nkT
qV
D
DSGS
eeII 10
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Sub-Threshold Sub-Threshold IIDD vs vs VVDSDS
DSkT
qV
nkT
qV
D VeeIIDSGS
110
VGS from 0 to 0.3V
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Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions
Strong Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS VDSAT
Weak Inversion (Sub-Threshold) VGS VT
Exponential in VGS with linear VDS dependence
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Parasitic ResistancesParasitic Resistances
W
LD
Drain
Draincontact
Polysilicon gate
DS
G
RS RD
VGS,eff
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Latch-upLatch-up
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Future PerspectivesFuture Perspectives
25 nm FINFET MOS transistor