digital evaluation of tfets in scaled nodes€¦ · voltage-transfer characteristics. low-leakage...

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Digital evaluation of TFETs in scaled nodes

D. Yakimets, M. Garcia Bardon, Y. Xiang,

imec DETEx team

Final Workshop – 10 November 2017

Energy Efficient Tunnel FET Switches and Circuits

imec

Ground Rules Scaling

2Final Workshop – 10 November 2017Energy Efficient Tunnel FET Switches and Circuits

Contacted gate pitch reduction necessary for continuing

density scaling, but Lgate scaling is limited by device

electrostatics out of space for contact and gate

Vertical Device to Continue Area Scaling


FinFET Vertical FET

MOSFETs Face Power Limit


[ Economist.com ]

𝑃 = 𝐶𝑉𝐷𝐷2 𝑓 + 𝑃𝑙𝑒𝑎𝑘

𝑓 = 𝐼/𝐶𝑉𝐷𝐷

Power

Frequency

Solutions:

• Multi core architecture

• Dynamic voltage-frequency scaling

• Sleep transistors

• ...

IoT Is Growing → Leakage Control Is Crucial


[ Cisco VNI Global IP Traffic Forecast, 2016–2021 ]

* M2M – Machine to Machine (IoT)

Tunnel FETs to Overcome Power Limit


Log(IDS)

VGS

VT

MOSFET

Ideal deviceTFET

MOSFET’s SSmin = 60 mV/dec

Because of steep slope, TFET allow:

• Smaller VT at same leakage

• VDD reduction

But TFETs do not provide much current

Can TFET be a next generation transistor?

Outline

• Introduction

• TFET Peculiarities

• V(T)FET Parasitics

• Benchmarking with MOSFET:

– Experimental TFET

– TCAD-based TFET

• Conclusion


Outline

• Introduction





– TCAD-based TFET

• Conclusion


Source ≠ Drain (1)

• Tricky serial connection: area penalty for lateral devices


S D/S DG G

S D SG

Du

mm

y

DG

Conventional MOSFET

TFET: additional contact

region is needed

Source ≠ Drain (2)

• Tricky serial connection: complex routing for vertical devices


DA

DB

SB

Bo

tto

m t

o t

op

via

Out

GB

SA

GA

nTFETA

nTFETB

Bottom to top via is not

needed for conventional

MOSFETs, as SB = DB.

The output for a MOSFET

would be on the top

Ambipolarity

• Low leakage may become not achievable

• Solutions to suppress ambipolarity are not so easy:

– Heterostructures

– Drain underlap


imec TFETs

(A. Verhulst)

Super-linear Onset (1)

• Id-Vg and Id-Vd should be co-optimized (doping / geometry)


|Vds| [V]

Vgs

-0.6V-0.5V-0.4V-0.3V-0.2V

TF

ET

BT

BT

cu

rre

nt I d

s

[10

-3A

/μm

]

imec TFETs

(A. Verhulst)

TF

ET

BT

BT

cu

rre

nt

I ds

[A/μ

m]

Vgs [V]

|Vds

|0.5V0.3V0.2V0.1V0.05V

Optimized

Original

Optimized

Original

Super-linear Onset (2)


• Undesired leakage current during

switching operations

• Loss of signal integrity, with Vdd

and ground never attained

• Long settling times and settling

time-propagation delay

Based on early, non-optimized Jülich Si TFET

data from the e2switch project

Outline

• Introduction





– TCAD-based TFET

• Conclusion


Overview of Parasitic Capacitances


Core device-related parasitics

• A lot of parasitic capacitances are defined through layouts

3D Parasitic Capacitances


Tsp = 4nm .. 14nm

Channel

Top view on gate

Gate oxide

Electrode

extension

length

• Analytical modeling is mostly based on elliptic integrals

Impact of Drain Underlap in TFETs


a = electrode

extension length

• Parasitic capacitance to the undoped part is not computed

Resistance of Bottom Electrode


pc = 1e-9, 5e-9,

1e-8, 2e-8 Ωcm2

Current flow

Bottom electrode

Channel

Contact resistance analytical formula accounts for:

• resistivity of bottom electrode metal (calibrated to measurements);

• semiconductor resistivity (doping-dependent, literature based);

• interface (user-defined);

Outline

• Introduction





– TCAD-based TFET

• Conclusion


Lund Vertical III-V TFET – best in class


ETHZ TCAD well

calibrated to

experimental data

• DNW = 20 nm

• SSmin = 48 mV/dec @ VDS = 0.3 V

• Sub-60 mV/dec operation over two orders

of magnitude (VDS = 0.1 – 0.5 V)

• IDS = 92 uA/um at VDD = 0.5 V

• pTFET = nTFET (fabricated)

16 nm FinFET – Fair Competitor


16 nm ground rules

Fin pitch [nm] 48

Metal pitch [nm] 64

Gate pitch [nm] 90

Cell height 9 tracks

Number of fins 4

VTFET-based standard cells may

be extended up to 15 tracks,

which implies 6 NWs per device

Layered view of NAND2 layout

Test Bench – Ring Oscillator

• Ring oscillator made of INV with FO=3

with BEOL load

• BEOL wire length is equivalent of mobile

SoC critical paths: 50 CGP

• Simulations are run in SPICE with

calibrated compact models accounting for

FEOL parasitics


BEOL properties:

• R = 25 Ω/µm;

• C = 195 aF/µm.

• RC of the 50 CGP long wire 98.7 fs.

High-performance Flavour (IOFF = 10 nA)


0.20

0.25

0.30

0.35

0.40

0

2

4

6

8

10

12

14

16

0 20 40 60

Pow

er

[uW

]

Frequency [GHz]

FinFET

Experimental TFET

VTFET are much slower than FinFETs

VTFET consume quite a lot of power:

direct short circuit current due to poor noise margins

0.00

0.10

0.20

0.30

0.40

0.00 0.20 0.40

Vout

[V]

Vin [V]

Voltage-transfer

characteristics

Low-leakage Flavour (IOFF = 10 pA)


0.20

0.25

0.30

0.35

0.40

0.30

0.35

0.40

0

0.2

0.4

0.6

0.8

1

1.2

0 2 4 6

Pow

er

[uW

]

Frequency [GHz]

FinFET

Ideal TFET

Ideal TFET (without traps) is required to

reach this low leakage

At VDD less than 0.30 V, TFET becomes

competitive

Low-activity Applications (α = 0.1%)


0.01

0.1

1

0.01 0.1 1 10 100

Energ

y [

aJ]

Frequency [GHz]

No traps (ideal)Bulk traps onlyAll traps (experimental)16nm-like FinFET

𝐸 = 𝛼𝑃𝑎𝑐𝑡𝑖𝑣𝑒 + 𝑃𝑙𝑒𝑎𝑘 ∙ 𝜏

Analysis across various

leakage targets and VDD values

For each frequency,

the minimum energy was selected

To account for poor NMs, (IOFF, VDD) pairs,

where NM is less than 25% of VDD are

filtered out

Outline

• Introduction





– TCAD-based TFET

• Conclusion


imec vertical TFETs

• 10 x 49 nm channels

• 5 nm like ground rules


imec TFETs

(A. Verhulst) Ten tracks tall layout

compatible with the SAQP flow

Noise Margins Balancing


Equal IOFF = 10pA Equally steep SS

Equally poor SSShifted pTFET

Inverter VTC

VDD=0.4V

109 mV shift

Low VT case

High VT case

normalized by W = 49 nm

Ideal TFET Is Competitive with MOSFET


Two BEOL loads are considered:

50CGP-long and 300CGP-long wire

VDD range is 0.15V to 0.6V

IOFF range is 1 pA to 10 nA

NM > 30% of VDD

𝐸 = 𝛼𝑃𝑎𝑐𝑡𝑖𝑣𝑒 + 𝑃𝑙𝑒𝑎𝑘 ∙ 𝜏

Outline

• Introduction





– TCAD-based TFET

• Conclusion


Conclusion

• Good TFET device is rather complex:

– SS should be steep

– Ambipolarity should be suppressed

– Super-linear onset should be minimized

• Source ≠ Drain:

– Area penalty for lateral device

– Increased interconnects complexity for vertical device

• VTFET competes with MOSFET at not actively switching, low-speed

applications requiring low power consumption if traps are suppressed


III-V heterostructures

with complex geometry

Vertical epi-grown

structures enabling

area scaling

• Cost of introduction?

• Variability

digital evaluation of tfets in scaled nodes€¦ · voltage-transfer characteristics. low-leakage...

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