Digital Controller for High-Frequency Rectifierswith Power Factor Correction Suitable for

On-Chip ImplementationAleksandar Prodic

Laboratory for Low-Power Management and Integrated SMPSECE Department- University of Toronto

Toronto, ON, CANADA

Abstract-- This paper describes a digital controller for high-frequency single-phase power factor correction rectifiers(PFC) that is suitable for on-chip implementation. To achievehigh switching frequency, fast dynamic response, andimplementation with a small number of logic gates, thedesigns of basic functional blocks are optimized. In the outervoltage loop a windowed based analog-to-digital converter(ADC) with adjustable quantization steps is used, to achievefast dynamic response. The complexity of the current looprealization is significantly reduced through the utilization of afloating reference created by a EA modulator and anotherwindowed based ADC. In addition, a segmented ring-oscillatorbased digital pulse-width modulator (DPWM) is used toeliminate the need for a high frequency external clock andreduce the overall size of the system. The effectiveness of thisdigital architecture is demonstrated on a 200 kHz, 300 Wboost-based PFC experimental prototype.

Index Terms-PFC, digital control, IC implementation.

I. INTRODUCTION

Digital control of switch-mode power supplies (SMPS)offers attractive features, such as superior flexibility,implementation of advanced control and powermanagement techniques, simple transfer of designs fromone implementation technology to another (designportability), and realization with a small number ofexternal passive components [1]. Even though theseadvantages are generally recognized, application specificanalog controller integrated circuits (IC) are stillpredominant in single-phase rectifiers with power factorcorrection (PFC). This is mostly due to the highcomplexity of general-purpose functional blocks thathave been used in prototypes presented in recent researchliterature [1]-[6].A block diagram of a digitally controlled PFC is shown inFig.l. It consists of a power stage controlled by twofeedback loops. The inner, current loop, forces the inputcurrent ig(t) to follow the wave shape of the input voltage.The task of the outer loop is to regulate the output voltageby changing emulated resistance Re, which is the ratio ofthe input voltage and current Vg(t)lig(t).It can be seen that a general implementation of thiscontroller requires three ADCs, a processing unit forcontrol laws implementation, and a digital-pulse widthmodulator (DPWM). An attempt to integrate thisarchitecture using conventional general-purposecomponents would result in an overly complex IC, whose

85-260 Vrms converlvter) t

H2ll(t) Rjl.(l) |c(t) Hivo.t(t)

AiDSi DPWM| i

dJn] Current loopregulator

u[n] Voltage loop |ev[n] Ve [i]Digital controller regulator

Fig. 1. Digitally controlled PFC.

silicon area would be significantly larger than that ofless-expensive integrated analog controllers [7] are stillpreferred choice in PFC applications.For example, to regulate a PFC at switching frequenciesbeyond 200 kHz, the ADC for input current measurementis required to sample the current during each switchingcycle [5],[6] and produce a digital equivalent of its analoginput in several microseconds or less. A general purposeADC with such characteristics is usually more complexthan a complete analog controller consisting of a fewoperational amplifiers, a pulse generator, and amultiplier]. The ADCs for the output and input voltagemeasurements are usually over-designed as well.Information about slow-varying input voltage can beacquired less frequently than that about the input currentand a full range ADC for the output voltagemeasurements is usually not necessary. For a properlydesigned voltage loop, most of the time, the outputvoltage is around a desired reference and the ADCoperates in a very narrow range. Additional problem isthe limited frequency of counter-based DPWM [9] thatare commonly used in such systems. The DPWMresolution decreases with frequency, and often does notprovide satisfactory voltage regulation [10].The main goal of this paper is to introduce a new digitalcontroller that has optimized architectures of ADCs andDPWM that allow efficient on-chip implementation. Toachieve these results basic functional blocks of digitalcontrollers developed for low-power high frequencydc-dc converters are modified [11]-[13]. Namely,windowed-based ADC for output voltage measurements,

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floating reference ADC for input current errormeasurements, a low range compensator and a segmentedring-oscillator based DPWM are combined.In the following section an explanation of the controlleroperation is given. Section III gives a description of basicfunctional blocks. Experimental results verifying properoperation of this system are given in Section IV.

II. CONTROLLER OPERATION

The controller of Fig.2 operates in a similar way as theconventional average-current controller of Fig. 1. TheADC of the outer loop creates a digital equivalent of thevoltage error ej[n] that is passed to the voltage loopcompensator. The compensator, then, produces a controlsignal u [n] that effectively changes emulated resistance.It is multiplied by the value proportional to theinstantaneous rectified line voltage vg(t), to create thereference for the input current. The difference betweenthis product and a scaled input current, i.e. current errorei[n], is processed by the current loop compensator. Itcreates a command d[n] for the DPWM.However, the main difference between architecturesshown in Figs. 1 and 2 is that the two ADCs for inputcurrent and voltage measurements and the multiplier ofthe conventional architecture are replaced with a muchsimpler structure. In addition, the conventional full-rangeADC for output voltage measurement is replaced withanother windowed-based ADC with non-uniform andprogrammable quantization steps. Finally, a segmentedring high-resolution DPWM [12], which unlikeconventional counter-based structures does not require ahigh frequency external clock is used. This DPWM canoperate at programmable switching frequenciesexceeding 10 MHz and requires very simple hardware forimplementation.

III. ARCHITECTURES OF BASIC FUNCTIONAL BLOCKS

This section gives a description of the architectures of thekey functional blocks that make this controller structuresuitable for on-chip implementation.

A. Voltage loop and the ADC with non-uniform andprogrammable quantization steps

The voltage loop is designed having two main goals onthe mind, simple implementation and fast response to theoutput load transients.It consists of look-up table based PI compensator and awindowed based ADC whose input-to-outputcharacteristic around the reference Vref is shown in Fig.3.Its quantization step around reference AVqle=1, i.e. zeroerror bin, is larger than the other bins. This non-uniformstructure allows direct implementation of a regulationband, i.e. dead-zone, voltage loop controller [14] - [17]that results in very good dynamic response. In thismethod, the zero error bin of the ADC is set to be largerthan the output capacitor ripple at the twice linefrequency. In this way, the ripple, which limits themaximum bandwidth of the conventional voltage loop[18] is eliminated, allowing for much faster control. Inaddition, to eliminate output voltage oscillations at lightloads, characteristic for dead-zone controllers [17], thesize of the quantization step is made adjustable inaccordance with the output load. At light loads it isreduced to accommodate smaller ripple amplitude andprevent low-frequency oscillations inside the zero errorbin.The block diagram of Fig.4.a shows the architecture ofthe programmable non-uniform ADC.The ADC of isbased on the architecture presented in [13]. It consists oftwo delay lines, a snapshot register, and an error decoder.

' e[n]

2--------AVQle 1< AVQIe 01- Vout(t)

- 1--2--3--4-

Yr4ll

Fig.3. Input-output characteristic of a windowed-based ADCwith non-uniform quantization steps.

Vref

Fig.2. Hardware-efficient digitally controlled PFC.ring architecture

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Fig.4. a: (left) Winowed ADC with non-uniform and programmable quantization steps; b: (right) digitally programmable delay cell.

The propagation times of the delay cells, formed of logicgates (D flip-flops), is controlled through the change oftheir supply voltage. The first line, has N+1 cells whosepropagation time is controlled by the reference voltageVrej(t). The other one comprises of N + M cells and itspropagation time is inversely proportional to theattenuated output voltage of the PFC (Fig.2). The firstN-1 cells of both delay lines are constructed as shown inFig.4.b, they consist of 4 D flip-flops and a 4-to-Imultiplexer. The number of D flip-flops signal goesthrough, and hence, the propagation time of this delaycell depends on control signal Zb[n] which regulates thesize of the zero error bin.The conversion process is initiated by the clock signalclk, whose frequency is a 1/10 of the switchingfrequency. This signal triggers both lines and sends twopulses through them. When the pulse propagating throughthe reference line reaches the Nth cell, a strobe signal iscreated and the state of the measurement line is capturedby the snapshot register. Based on the number of cellsthe signal has propagated through, the output voltageerror is determined. If the number of cells the signal haspropagated is smaller than N the output voltage is lowerthan Vrej(t) and positive error e[n], proportional to thedifference in the number of cells is created by the errordecoder. Similarly, the propagation through a largernumber of cells indicates higher output voltage resultingin a negative error. The (N+l)h cell of the reference lineis used to reset all the cells before the next clk pulsearrives.It can be shown that for this structure the size of error binis:

Zb [n](N -)ref AVqie 0 (i)

Hence by changing Zb[n] the zero error bin can be changeas well.The voltage loop compensator implements the followingPI control low:

u[n] = u[n -1] + aev [n] (2)

where the coefficient a is selected in accordance with theguidelines for fast voltage loop design, given in [19].

B. Current LoopTo allow the use of the obtain the reference value for thesimple windowed ADC of Fig.2 for the input currentmeasurements its structure is slightly modified and afloating reference is provided. In this case, the ADC isclocked at the switching frequency and all the delay cellsof the same type are used. The floating reference isformed with a single-bit L-A modulator a transistor and afiltering capacitor. This simple structure eliminates theneed for the ADC for input voltage measurement anddigital multiplier, which are significantly more complexdevices. It should be noted that, since the filteringcapacitor is supplied from the input line, its voltage isproportional to uVg(t), where u(t) is the control valuefrom the voltage loop.Since this structure operates in closed loop it behavessimilar to a successive approximation ADC. The currentloop forces the voltage across the filtering capacitor to beclose to the value proportional to the input current and theneed for a full range fast ADC for input currentmeasurement is eliminated as well.Furthermore, since the range of the current error signalsei[n] is limited, the use of small look-up table based PIDcompensator [15] is enabled. Consequently, the need fora high-speed processor for digital control lawimplementation is also eliminated.C. Segmented-Ring Digital Pulse Width Modulator

To implement an 8-bit digital-pulse width modulator thea segmented-ring architecture [12] is used. It is amodification of the conventional based ring-oscillator-based structure presented in [9]. Compared to the originalarchitecture, the segmented ring requires much smallermultiplexer, which results in order of magnitude smallersilicon area.The DPWM is used both to create control waveforms forthe power stage and to provide the clock signal for theentire system.

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vil

IV. EXPERIMENTAL RESULTS

Based on the block diagram shown in Fig.2 a digitalcontroller combining an FPGA system and custom-madeintegrated circuits was designed and tested with a 300 Wboost-based PFC. To accommodate limitations of theexisting switching components the switching frequencywas limited to 200 kHz, even though the controller cansupport operation at frequencies exceeding 2 MHz.

A. Steady-state operationFig.5 shows steady-state operation of the experimentalsystem. It can be seen that the input current accuratelyfollows the input voltage waveform. Results ofmeasurement of the power factor measurements showedthat a power factor above 0.98 can be achieved for theoutput loads ranging from 20 % to 100% of the ratedpower. The results also showed a very small totalharmonic distortion of less than 5% over the abovementioned range.

B. Load-transient performanceExperimental results demonstrating load transientresponse are shown in Fig.6. It can be seen that thiscontroller has very fast dynamic response. Compared toconventional solutions, having slow output voltage loop,this implementation has several very importantadvantages. It allows for a significant reduction of thesize of the output filter capacitor of the power stage. Inaddition it minimizes the current and voltage stress onthe power stage components as well as on a downstreamdc-dc converter, which is the most common PFC's loads.

V. CONCLUSIONSA digital controller for high-frequency PFCs isintroduced. It is shown that by utilizing a floatingreference ADC for input current measurement andwindowed ADC with non-uniform quantization steps foroutput voltage measurement overall structure of thecontroller can be significantly simplified. An effectiveoperation of this digital controller is verified throughexperiments.

Fig.5. Steady-state operation of the experimental system forV,ii 110 Vrn,, Ch- 1: rectified line voltage vg(t) 50 V/div; Ch-2: i1j,,(t)0.5 A/div

Fig.6. Load transient response of the fast dead-zone controller for loadchange between 100 W and 175 W. The input line voltage is: (a) Vli,,1 10 Vr,mS Ch- 1: vout(t) 10 V/div -ac; Ch-2: ili,,(t) A/div

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