digital comparator design for high speed binary comparison · here we extended our project 128 bit...
TRANSCRIPT
ISSN 2322-0929
Vol.04, Issue.10,
October-2016,
Pages:0975-0978
www.ijvdcs.org
Copyright @ 2016 IJVDCS. All rights reserved.
Digital Comparator Design for High Speed Binary Comparison D. JOHARI KISHAN
1, K.KEERTHAN
2, G.RAJAIAH
3
1PG Scholar, Abdulkalam Institute of Technological Sciences, Kothagudem, Telangana, India.
2Assistant Professor, Abdulkalam Institute of Technological Sciences, Kothagudem, Telangana, India.
3Professor, Abdulkalam Institute of Technological Sciences, Kothagudem, Telangana, India.
Abstract: This paper proposes the design of digital comparator with two different parallel architectures. These comparators are first
realized in Verilog and simulated with Xilinx ISE 14.6 platform and then compared with the traditional design. Simulation results
show that the first proposed architecture reduces combinational delay (logic + interconnect) and the second proposed architecture is
even much faster and has a combinational delay very less compared to the traditional design. Here we extended our project 128 bit
architecture by using 4bit comparator.
Keywords: Binary Comparison, Comparator Design, Verilog.
I. INTRODUCTION
Comparator is usually a simple arithmetic model in which
compares your degree involving a couple binary volumes, state
Any along with N, along with yields result chunks: A>B or even
A<B or even A=B. It is an important data-path component for
any basic intent structures in addition to a vital gadget for
application-specific along with transmission control
architectures. Comparators may also be found in working
communities which perform an important part with parts such as
parallel research, multi-access recollections along with
multiprocessing Comparator kinds significant part of processors
along with digital camera devices. With regard to processors, to
experience excessive throughput together with fast clock
charges, it is necessary in which these kinds of units include
fewer wait. Consequently, your planning involving excessive
pace comparator structures becomes another along with vital
analysis matter. Formerly printed comparator implementations
getting serial along with parallel structures could both equally
end up being obtained in literature. The serial structures would
work for limited advices (i. elizabeth. while the advices include
less amount of bits). With regard to more time advices (say, 33
tad, sixty four tad inputs), your enterprise complexness and the
combinational wait boost greatly. Therefore, parallel tactic is
often chosen for comparators together with more time advices.
The comparator types shown on this document provide parallel
tactic.
II. TRADITIONAL ARCHITECTURE
Traditional magnitude comparator is shown in Fig.1. The
design is a parallel architecture. The circuit has three output
bits: A>B, A<B, A=B. In many applications, only two output
signals A>B, A<B are sufficient. The output bit (A=B) goes
high if all the bits of A are equal to the corresponding bits of B.
The two output signals A>B and A<B, are determined based on
the following two conditions.
If MSBs of the two numbers are unequal, i.e when Ai=1, Bi
=0 then A>B or Ai=0, Bi =1 for A<B.
OR if the pair of bits in the significant bit positions are
equal, and LSBs are different i.e. Ai=Bi and Ai-1 = 1, Bi-1
=0 then A>B or Ai=Bi and Ai-1=0, Bi-1=1 then A<B.
Fig1.Traditional Binary Comparator.
III. PROPOSED ARCHITECTUR ES
A. Proposed Architecture-I
The 1st recommended structure offered i d this particular
papers will depend on parallel approach possesses a pair of
available fit portions: H( i. age. A>B), S( i. age. A<B). This
circuit for the 4-bi t pattern with this comparator can be
viewable with Fig. only two and is also a little any altered
edition on the conventional comparator (which is effective upon
bit-weight contrast regarding a pair of figures from
LSBtoMSB). To understand the logic for the proposed
architecture, let us consider an example for the comparison of
A=10112 and B =11002. In the first stage, we identify and
extract the 1s of first number which have a 0 in the
D. JOHARI KISHAN, K.KEERTHAN, G.RAJAIAH
International Journal of VLSI System Design and Communication Systems
Volume.04, IssueNo.10, October-2016, Pages: 0975-0978
corresponding position of the second number and are allowed to
remain. The basic idea behind this is that only such 1s of a
number make it greater than the other number. All other b it
positions which have a 1 in the corresponding position of the
other number, are made 0. This is done for both the num bers in
parallel, that is, A with respect to B (i.e. ) and B with
respect to A (i.e. ) , thereby forming two numbers A’ and
B’ as shown below.
A = 1 0 1 1 B = 1 1 0 0
B = 1 1 0 0 A = 1 0 1 1
A’= 0 0 1 1 B’= 0 1 0 0
In the second stage, only the most significant 1s of A’ and B’
are extracted by giving it higher priority. Other 1s are made 0.
This stage incorporates logic similar to the priority logic of a
priority encoder. This way two new numbers, A’’ and B’’ are
formed as shown below. Due to the priority logic incorporated,
the number of 1s in A’’ and B’’ is either one or zero
A’= 0 0 1 1 B’ = 0 1 0 0
A’’= 0 0 1 0 B’’=0 1 0 0
In the final stage, from A’’ and B’’ two new signals are
extracted. These are H (i.e. A>B) and S (i.e. A<B), both are of
single bit, obtained by extracting the most significant bit
(1) from A’’ and B’’. If the 1 of A’’ is in a more significant
position than that of B’’ or if B’’ has all 0s but A’’ has a 1, then
this 1 is used to form output bit H. Similarly, if the 1 of B’’ is in
a more significant position than that of A’’ or if A’’ has all 0s
but B’’ has a 1, then this 1 is used to form output bit S as
follows.
A’’= 0 0 1 0 B’’= 0 1 0 0
B’’= 0 1 0 0 A’’= 0 0 1 0
H = 0 S = 1
Fig.2. Proposed Architecture-I.
B. Proposed Architecture-II
The second structures proposed in this report might be named
any look-ahead comparator and it has any parallel approach. It's
two end result portions: A>B and A<B. The world in the 4-bit
design with this comparator will be viewable with Amount 3.
The initial period with this structures uses any evaluate look-
ahead judgement as demonstrated with Fig. several. This look-
ahead section generates evaluate signals CMPi for every little
bit situation, i’ (i= 0, 1, 2, 3). The CMPi indication is going high
in case:
The ith items of A new and W are usually sloping or maybe
The MSBs are usually equal plus more major jobs of a and
W are usually sloping.
For just a granted two of numbers, solely one of the evaluate
signals is going to be high. A higher CMPi will initialize Gi and
Cu and o entrances. When Ai =1 and Bi = 0, end result
regarding Gi and hence, (A>B) is going high. Alternatively, in
case Ai =0 and Bi =1, end result regarding Cuando and hence,
(A<B) is going high.
Fig3. Proposed Architecture II.
Fig4.
C. Modified comparator module for 32-bit tree Structure
Fig.5. 32-Bit Tree Structure Comparator.
Digital Comparator Design for High Speed Binary Comparison
International Journal of VLSI System Design and Communication Systems
Volume.04, IssueNo.10, October-2016, Pages: 0975-0978
The schematic for 32-bit level implementation of the
traditional and proposed comparators is shown in Figure 5. The
blocks of the first stage compute the comparison result for every
4 bits of the input numbers. The blocks in the second stage take
the result of four sets of 4-bit numbers and compute the result
for the two 16-bit numbers which are obtained when the four
sets of 4-bit numbers are concatenated. This logic is repeated in
the third stage where the 2-bit block takes the resultsof two sets
of 16-bit numbers and computes the result for the tw o 32-bit
numbers. In the 32-bit level implementation of both the
proposed comparators, a modified 2-bit comparator module has
been utilized. Since the numbers input to the 2-bit comparator
module are the outputs of 4-bit comparators, certain pairs of
numbers can never be the input combinations: (10,10), (10,11),
(11,10), (11,01), (01,11), (01,01). This is because the (A>B) and
(A<B) output bits of the 4- bit comparator module can never be
1 at the same time. As a result, the Boolean expression for the
(A>B) output of 2-bit comparator module becomes:
The logic-level circuit diagram of the modified 2-bit
comparator module is shown in Fig. 6.
Fig.6. Modified 2-bit comparator.
IV. SIMULATION AND RESULTS
All the simulations of the 32-bit level implementation of the
traditional and proposed comparators have been carried out
using Verilog HDL programming in Xilinx ISE 14.6 platform.
Adequate testing of each design was done to verify correct
operation. Xilinx chip series details used for simulation and
comprehensive analysis are mentioned as under:
Fig7. 32-Bit Comparator Simulation Waveform.
Fig8. 32-Bit RTL Schematic.
Fig9. Proposed 128 Bit Comparator Waveform.
Fig10. 128-Bit Comparator RTL Schematic.
D. JOHARI KISHAN, K.KEERTHAN, G.RAJAIAH
International Journal of VLSI System Design and Communication Systems
Volume.04, IssueNo.10, October-2016, Pages: 0975-0978
V. CONCLUSION
The proposed comparators have been discussed, simulated
and compared with the traditional one. Simulation results show
in section IV, decrease in path delay in case of the proposed
architecture-I and also we designed 128 bit comparator for large
amont data comparison. Those deigns are simulated and
synthesized by Xilinx ISE 14.6 tool.
VI. REFERENCES
[1]Verilog hdl by padmanabam
[2] www.asicworld.com
[3]J. L. Hennessy and D. A. Patterson, Computer Architecture:
A Quantitative Approach. Morgan KaufmannPublishers, 2002.
[4].J. Eyre and J. Bier, “DSP processors hit the mainstream,”
IEEE Computer, pp. 51–59, 1999.
[5]Shun-Wen Cheng, “Arbitrary Long Digit Sorter HWISW Co-
Design,” in Proc. Asia and South Pacific Design Automation
Conj, ASPDAC„ 03, pp. 538-543, Jan. 2003.
[6]D.E.Knuth, Sorting and Searching. Reading: Addison-
Wesley, 1973.
[7]D. Norris, “Comparator circuit,” U.S. Patent 5,534,844, April
3, 1995.
[8] Shun-Wen Cheng, “A high-speed magnitude comparator
with small transistor count” in Proceedings of the 2003 10th
IEEE International Conference on Electronics, Circuits and
Systems (ICECS), pp. 1168- 1171, 2003.
[9] M. Morris Mano, Digital Logic and Computer Design.
Author’s Profile:
D.Johari Kishan received B.Tech in
E.C.E From Abdulkalam Institute of
Technological Sciences (AKIT), Affiliated
To J.N.T.U. Hyderabad. He Is Pursuing
M.Tech In The Stream of ES&VLSID In
Abdulkalam Institute of Technological
Sciences. His Research Interests Include
Embedded Systems And VLSI Design.
Mr.K.Keerthan received B.Tech In E.C.E
from Abdulkalam Institute of Technological
Sciences (AKIT), Affiliated To J.N.T.U
Hyderabad. He Received M.Tech In Vlsi
System Design From Paul Raj Engineering
College, Bhadrachalam. And Sciences
Affiliated To J.N.T.U. Hyderabad. Now He
Is Working As A Assistant Professor In Ece Department in
Abdulkalam Institute of Technological Sciences.
G.rajaiah has received his b.tech degree in
electronics and instrumentation from
kakatiya university in 1997 and m.tech
degree in instrumentation and control
systems from jntu kakinada in 2005.he has
been working as professor& head of
department. He has contributed more than 20
reviewed publications in journals.