COURSE No. & Title : SEWPZC261 DIGITAL ELECTRONICS & MICROPROCESSORS (QUESTION BANK)

Objective Questions. Topic: Number System and Codes (Ch 2)

1. The number of digits in octal system isa.8b.7c.10d. none

2..The number of digits in Hexadecimal system isa.15b.17c.16d. 8

3.The number of bits in a nibble isa.16b.5c.4d.8

4.The digit F in Hexadecimal system is equivalent to ------ in decimal systema.16b.15c.17d. 8

5.Which of the following binary numbers is equivalent to decimal 10a.1000b.1100c.1010d.1001

6.The number FF in Hexadecimal system is equivalent to ------ in decimal systema.256b.255c.240d.239

7. Numbers are stored and transmitted inside a computer ina. binary formb. ASCII code formc. decimal formd. alphanumeric form

8.The decimal number 127 may be represented bya. 1111 1111Bb. 1000 0000Bc. EEH

d. 0111 1111

9.. A byte corresponds toa. 4 bitsb. 8 bitsc. 16 bitsd. 32 bits

10.A gigabyte representsa.1 billion bytesb. 1000 kilobytesc. 230 bytesd. 1024 bytes

11. A megabyte representsa. 1 million bytesb. 1000 kilobytesc. 220 bytesd. 1024 bytes

12.. A Kb corresponds toa. 1024 bitsb. 1000 bytesc.210 bytesd. 210 bits

13.A parity bit isa. used to indicate uppercase lettersb. used to detect errorsc. is the first bit in a byted. is the last bit in a byte14.In hexadecimal number system,A is equal to decimal numbera.10b.11c.17d.18

15.Hexadecimal number F is equal to octal numbera.15b.16c.17d.18

16.Hexadecimal number E is equal to binary numbera.1110b.1101c.1001d.1111

17.Binary number 1101 is equal to octal numbera.15b.16c.17d.14

18.Octal number 12 is equal to decimal numbera.8b.11c.9d. none

19.Decimal number 10 is equal to binary numbera.1110b.1000c.1001d.1010

20.Binary number 110011011001 is equal to decimal numbera.3289b.2289c.1289d.289

21.1111+11111=a.101111b.101110c.111111d.011111

22.Binary multiplication 1*0=a.1b.0c.10d.11

23.4 bits is equal toa. 1 nibbleb.1 bytec. 2 byted. none of above

24.The parity bit isa. always 1b. always 0c.1 or 0d.none of above

25.In 2 out of 5 code,decimal number 8 isa.11000b.10100c.1100d.1010

26. (23.6) 10=……….2a.11111.10011

b.10111.10011c.00111.101d.10111.1

27.BCD number 0110011=…….10a.66b.67c.68d.6928.. Which numbering system employs only ten digits? 

  binary

  hexadecimal

  arabic

  octal

29 .       The digits that may be used in the unit column of the decimal numbering system are: 

  0 through 15

  0 through 9

  1 through 10

  1 through 16

30 . To distinguish between numbering systems, one may refer to the:   reset and carry action

  radix

  positional weight

  significant digits

31 .       A numbering system is sometimes identified by a:    radix superscript

  significant digit

  positional weight

  base subscript

32.       In the decimal system, what may the unit value be called? 

  LSD

  MSB

  LSB

  MSD

33 . Which figure indicates the decimal numbering system is in use?   72

  78

  710

  716

34 . Within the decimal number 3456, the 4 has a value of 400 due to its:   digit value

  insignificance

  radix

  positional weight

35 . With decimal notation, by which factor does each position to the left of the decimal point increase? a. a positive power of ten

b. the LSB value

c. the MSD value

d. a negative power of ten

36.       Reset and carry occurs after any decimal column reaches what value? 

a. 5

b. 7

c. 9

d. 10

37 .       With a 4-digit decimal number, how many resets and carries are possible? 

a. 1

b. 2

c. 3

d. 4

38 .       With the decimal system, after 999 is reset, what is the value of each carry? 

a. 1

b. 10

c. 100

d. 1000

39 .       What is the radix for the binary numbering system? 

a. 16

b. 10

c. 8

d. 2

40 .       The positional weight of the binary one in the binary number 001000 is represented by: 

a. 21

b. 22

c. 23

d. 24

41 .       What reference is used for the left-most position within a given binary? 

a. LSD

b. MSB

c. LSB

d. MSD

42 .       In a binary number, the column for the LSB is represented by 20, which has a value of: 

a. 8

b. 4

c. 2

d. 1

43 .       If decimal numbers 28 and 3 are converted to the binary system and then added, which position would receive the last carry? 

a. the second column

b. each column

c. no column

d. the sixth column

44 .       A decimal number may be converted to binary by continually subtracting the: 

a. largest possible power of two

b. smallest possible power of ten

c. largest possible power of eight

d. largest possible power of sixteen

45 .       What is 3110 converted to binary? a. 110001

b. 011111

c. 101011

d. 111110

50 .       What is the decimal value of the binary number 111110? 

a. 31

b. 62

c. 64

d. 126

51 .       The sum of a binary 10101010 plus a binary 01111 is: 

a. 128

b. 170

c. 185

d. 252

52 .       What is the resultant in binary of the decimal problem 49 + 01 = ? 

a. 01010101

b. 00110101

c. 00110010

d. 00110001

53 .       After conversion, what would a 4-digit binary display show when a reset and carry from a decimal 15 has occurred? 

a. 0000

b. 0001

c. 1110

d. 1111

54 .       What is a base 16 numbering system called? 

a. binary

b. octal

c. coded decimal

d. hexadecimal

55 .       One system that might be used as a short hand for large binary strings would have:  a. high value decimal numbers

b. a radix of 16

c. equal decimal equivalents

d. random octal values

56 .       Hexadecimal letters A through F are used for decimal equivalent values of: 

a. 1 through 6

b. 9 through 14

c. 10 through 15

d. 11 through 17

57 .       With the number 8BF16, what is the positional weight of the 8? a. 16

b. 256

c. 4096

d. 8192

58 .       A decimal number may be converted to HEX by continually subtracting the largest possible power of: 

a. 16

b. 10

c. 08

d. 02

59 .       What is the binary value of 12316? a. 100100011

b. 001100011

c. 111011111

d. 110011100

60 .       What is the result when a decimal 5238 is converted to base 16?  a. 327.375

b. 12.166

c. 1388

d. 1476

61 .       What is the HEX value of a binary 1111111111? 

a. 3FF

b. 400

c. 200

d. FFF

62 . What would be the binary result if a HEX value of F9 is added to a HEX 1? a. 011111001

b. 011111101

c. 011111010

d. 100000000

63 .       Hexadecimal and octal numbering systems are similar for the first:  a.9 digits

b.8 digits

c.7 digits

d.6 digits

64 .       What is the positional weight of the MSB for octal number 7726?  a. 84

b. 83

c. 82

d. 8

65 .       What is the binary equivalent of octal number 1126? 

a.10110011000

b.010 101 110

c.1001010110

d.10010101110

66 .       What is the difference between binary coding and binary coded decimal? 

a. BCD is pure binary.

b. Binary coding has a decimal format.

c. BCD has no decimal format.

d. Binary coding is pure binary.

67 .       Which type of error was eliminated through the use of the gray code? 

a. timing

b.decoding

c.encoding

d.conversion

69 . What is the decimal value of 0011 1001 0111BCD? 

a.7927

b.919

c.1627

d.397

68 .       Unlike most binary codes, the excess-3 code uses: 

a. octal notation

b. an extra three digits

c. an offset

d. decimals through 15

69 .       The ASCII code allows encoding for how many keyboard characters? 

a.64

b.128

c.256

d.512

70.What is the binary equivalent of the decimal number 368(A) 101110000 (B) 110110000(C) 111010000 (D) 111100000

71.The decimal equivalent of hex number 1A53 is(A) 6793 (B) 6739(C) 6973 (D) 6379

72.The Gray code for decimal number 6 is equivalent to(A) 1100 (B) 1001(C) 0101 (D) 0110

73.The 2’s complement of the number 1101101 is(A) 0101110 (B) 0111110(C) 0110010 (D) 0010011

74.The code where all successive numbers differ from their preceding number by single bit is(A) Binary code. (B) BCD.(C) Excess – 3. (D) Gray.Ans: D

75.The hexadecimal number for (95.5)10 is(A) ( 5F.8 )16 (B) ( 9A.B) 16(C) ( 2E.F) 16 (D) ( )5A.4 16

76.The octal equivalent of ( )247 10 is(A) ( )252 8 (B) ( )350 8(C) ( )367 8 (D) ( )400 8

77. Convert decimal 153 to octal. Equivalent in octal will be(A) (231)8 . (B) ( )331 8 .(C) ( )431 8 . (D) none of these.Ans: A78. The decimal equivalent of ( )1100 2 is(A) 12 (B) 16(C) 18 (D) 20Ans: A79. The binary equivalent of ( )FA 16 is(A) 1010 1111 (B) 1111 1010(C) 10110011 (D) none of theseAns: B

80.The result of adding hexadecimal number A6 to 3A is(A) DD. (B) E0.(C) F0. (D) EF.

Objective Questions. Topic: Boolean algebra and logic Gates.

(Ch 2, 3)

1.IC s are:a. analogb. digitalc. both analog and digitald. mostly analog

2.The rate of change of digital signals between High and Low Level isa. very fastb. fastc. slowd. very slow

3. Digital circuits mostly usea. Diodesb. Bipolar transistorsc. Diode and Bipolar transistorsd. Bipolar transistors and FETs

4.Logic pulsera. generates short duration pulsesb. generate long duration pulsesc. generates long and short durationd. none of above

5.What is the output state of an OR gate if the inputs are 0 and 1?a.0b.1c.3

d.2

6.What is the output state of an AND gate if the inputs are 0 and 1?a.0b.1c.3d.2

7.A NOT gate has...a. Two inputs and one outputb. One input and one outputc. One input and two outputsd. none of above

8.An OR gate has...a. Two inputs and one outputb. One input and one outputc. One input and two outputsd. none of above

9.The output of a logic gate can be one of two _____?a. Inputsb. Gatesc.Statesd. none

10.Logic states can only be ___ or 0.a. 3b. 2c.1d.0

11.The output of a ____ gate is only 1 when all of its inputs are 1a. NORb. XORc. ANDd. NOT

12.A NAND gate is equivalent to an AND gate plus a .... gate put together.a. NORb. NOTc. XORd. none

13.Half adder circuit is ______?a. Half of an AND gateb. A circuit to add two bits togetherc. Half of a NAND gated. none of above14.An output of combinational ckt depends ona. present inputsb. previous inputsc. both present and previousd .none of above

15.Which are universal combinational gatesa. NAND & NORb. NOT & ANDc. X-OR & X-NORd. none of above16. Which is correct:a. A.A=0b. A+1=Ac. A+A=A'd. A.A'=0

17.The total number of input states for 4 input or gate isa.20b.16c.12d.8

18.In a 4 input OR gate,the total number of High outputs for the 16 input states area.16b.15c.13d. none of above

19.In a 4 input AND gate,the total number of High outputs for the 16 input states area.16b.8c.4d.1

20.A buffer isa. always non-invertingb.always invertingc. inverting or non-invertingd.none of above

21.An AND gate has two inputs A and B and one inhibits input S.Output is 1 ifa.A=1,B=1,S=1b. A=1,B=1,S=0c. A=1,B=0,S=1d. A=1,B=0,S=0

22. An AND gate has two inputs A and B and one inhibits input S.Out of total 8 input states,Output is 1 ina. 1 statesb. 2 statesc. 3 statesd. 4 states

23.In a 3 input NOR gate,the number of states in which output is 1 equalsa. 1b. 2

c. 3d. 4

24.Which of these are universal gatesa. only NORb. only NANDc. both NOR and NANDd. NOT,AND,OR

25. In a 3 input NAND gate, the number of gates in which output in 1equalsa.8b.7c.6d.5

26. A XOR gate has inputs A and B and output Y.Then the output equation isa.Y=A+Bb.Y=A B’+A’Bc.AB+ AB’d.AB’+A’B’

27.A 14 pin NOT gate IC has………..NOT gatesa.8b.6c.5d.4

28.A 14 pin AND gate IC has………..AND gatesa.8b.6c.4d.2

29.The first contribution to logic was made bya. George Booleb. Copernicusc. Aristotled. Shannon

30.Boolean Algebra obeysa. commutative lawb. associative lawc. distributive lawd. commutative, associative, distributive law

31. A+(B.C)=a. A.B+Cb. A.B+A.Cc. Ad.(A+B).(A+C)

32.A.0=a. 1b. Ac. 0

d. A or 1

33.A+A.B=a. Bb. A.Bc. Ad. A or B

34.Demorgan’s first theorem isa. A.A’=0b. A’’=Ac. (A+B)’=A’.B’d. (AB)’=A’+B’35. Demorgan’s second theorem isa. A.A’=0b. A’’=Ac. (A+B)’=A’.B’d. (AB)’=A’+B’

36. Which of the following is truea. SOP is a two level logicb. POS is a two level logicc. both SOP and POS are two level logicd. Hybrid function is two level logic

37.The problem of logic race occurs ina. SOP functionsb. Hybrid functionsc. POS functionsd. SOP and POS functions

38. In which function is each term known as min terma. SOPb. POSc. Hybridd. both SOP and POS

39. In which function is each term known as max terma. SOPb. POSc. Hybridd. both SOP and Hybrid

40. In the expression A+BC, the total number of min terms will bea.2b. 3c.4d. 5

41.The min term designation for ABCD isa.m0b. m10c. m14d. m15

42. The function Y=AC+BD+EF isa. POSb. SOPc. Hybridd. none of above

43. The expression Y=∏M(0,1,3,4) isa. POSb. SOPc. Hybridd. none of above

44. AB+AB’=a. Bb. Ac.1d. 0

45. In a four variable Karnaugh map eight adjacent cells give aa. Two variable termb. single variable termc. Three variable termd. four variable term

46.A karnaugh map with 4 variables hasa. 2 cellsb. 4 cellsc. 8 cellsd.16 cells

47.In a karnaugh map for an expression having ‘don’t care terms’ the don’t carescan be treated asa. 0b. 1c. 1 or 0d. none of above

48. The term VLSI generally refers to a digital IC havinga. more than 1000 gatesb. more than 100 gatesc. more than 1000 but less than 9999 gatesd. more than 100 but less than 999 gates

49.Typical size of an IC is abouta.1”*1”b. 2”*2”c. 0.1”*0.1”d. 0.0001”*0.0001”

50.A digital clock uses…………..chipa. SSIb. LSIc. VLSId. MSI

51. Digital technologies being used now-a-days area. DTL and EMOSb. TTL, ECL, CMOS and RTLc. TTL, ECL and CMOSd. TTL, ECL, CMOS and DTL

52. A half adder can be used only for addinga. 1sb. 2sc. 4sd. 8s

53. A 3 bit binary adder should bea. 3 full addersb. 2 full adders and 1 half adderc. 1 full adder and 2 half adderd. 3 half adders

54. when two 4 bit parallel adders are cascaded we geta. 4 bit parallel adderb. 8 bit parallel adderc. 16 bit parallel adderd. none of above

55. The widely used binary multiplication method isa. repeated additionb. add and shiftc. shift and addd. any of above

56.When microprocessor processes both positive and negative numbers, the representation used isa. 1’s complementb. 2’s complementc. signed binaryd. any of above

57.      The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.) a. AND/OR

b. NAND

c.NOR

d.OR/AND

58 .

     Each "1" entry in a K-map square represents:   a. a HIGH for each input Truth Table condition that produces a HIGH output.

  b. a HIGH output on the Truth Table for all LOW input combinations.

  c. a LOW output for all possible HIGH input conditions.

  d. a DON'T CARE condition for all possible input Truth Table combinations.

     

59 .

     Looping on a K-map always results in the elimination of:   variables within the loop that appear only in their complemented form.

  variables that remain unchanged within the loop.

  variables within the loop that appear in both complemented and uncomplemented form.

  variables within the loop that appear only in their uncomplemented form.

     

60 .

     Which of the following expressions is in the sum-of-products form?   (A + B)(C + D)

  (AB)(CD)

  AB(CD)

  AB + CD

61 .

     Which of the following is an important feature of the sum-of-products form of expressions?   All logic circuits are reduced to nothing more than simple AND and OR gates.

  The delay times are greatly reduced over other forms.

  No signal must pass through more than two gates, not including inverters.

  The maximum number of gates that any signal must pass through is reduced by a factor of two.

62 .

     Which of the following expressions is in the product-of-sums form?   (A + B)(C + D)

  (AB)(CD)

  AB(CD)

  AB + CD

63.      Solve the network in Figure 4-1 for X.

  A + BC + D

  ((A + B)C) + D

  D(A + B + C)

  (AC + BC)D

64 .

     A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?

  The output of the gate appears to be open.

  The dim indication on the logic probe indicates that the supply voltage is probably low.

  The dim indication is a result of a bad ground connection on the logic probe.

  The gate may be a tri-state device.

65 .

     For a two-input XNOR gate, with the input waveforms as shown in Figure 4-2, which output waveform is correct?

  a

  b

  c

  d

66 .

     Which of the figures shown in Figure 4-3 represents the exclusive-NOR gate?

  a

  b

  c

  d

67 .

     Which statement below best describes a Karnaugh map?   A Karnaugh map can be used to replace Boolean rules.

  The Karnaugh map eliminates the need for using NAND and NOR gates.

  Variable complements can be eliminated by using Karnaugh maps.

  Karnaugh maps provide a cookbook approach to simplifying Boolean expressions.

68 .

     Which of the circuits in Figure 4-4 (a-d) is equivalent to Figure 4-4 (e)?

  a

  b

  c

  d

69 .

     Which of the K-maps in Figure 4-5 represents the expression X = AC + BC + B?

  a

  b

  c

  d

70 .

     The simplest equation which implements the K-map in Figure 4-6 is:

 

 

 

 

70 .

     Which of the figures in Figure 4-7 (a-d) is equivalent to Figure 4-7 (e)?

  a

  b

  c

  d

71 .

     Which of the following logic expressions represent the logic diagram shown?

   

 

 

 

72 .

     What type of logic circuit is represented by the figure shown in Question 18?   XOR

  XNOR

  XAND

  XNAND

73 .

     Which of the following combinations cannot be combined into K-map groups?   Corners in the same row

  Corners in the same column

  Diagonal corners

  Overlapping combinations

74 .

     Which of the circuits in Figure 4-9 (a-d) is the sum-of-products implementation of Figure 4-9(e)?

  a

  b

  c

  d

75.How many two-input AND and OR gates are required to realize Y=CD+EF+G(A) 2,2. (B) 2,3.(C) 3,3. (D) none of these.Ans: A

76.Which of following are known as universal gates(A) NAND & NOR. (B) AND & OR.(C) XOR & OR. (D) None.Ans: A

77.How many AND gates are required to realize Y = CD+EF+G(A) 4 (B) 5(C) 3 (D) 2Ans: D78.DeMorgan’s first theorem shows the equivalence of(A) OR gate and Exclusive OR gate.

(B) NOR gate and Bubbled AND gate.(C) NOR gate and NAND gate.(D) NAND gat When simplified with Boolean Algebra (x + y)(x + z) simplifies to(A) x (B) x + x(y + z)(C) x(1 + yz) (D) x + yzAns: D

79.The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either(A) a NAND or an EX-OR (B) an OR or an EX-NOR(C) an AND or an EX-OR (D) a NOR or an EX-NORAns: D

80.The Boolean expression A.B+ A.B+ A.B is equivalent to(A) A + B (B) A.B(C) A + B (D) A.B

81.The simplification of the Boolean expression (ABC)+ (ABC) is(A) 0 (B) 1(C) A (D) BCAns: B

Objective Questions. Topic: Combinational Logic, Digital Arithmetic (Ch 4, Ch 6& Ch 9)

1. A 3 bit binary adder should bea. 3 full addersb. 2 full adders and 1 half adderc. 1 full adder and 2 half adderd. 3 half adders

2. when two 4 bit parallel adders are cascaded we geta. 4 bit parallel adderb. 8 bit parallel adderc. 16 bit parallel adderd. none of above

2.

3. In 2’s complement addition, the carry generated in the last stage isa. added to LSBb. neglectedc. added to bit next to MSBd. added to the bit next to LSB

4. The number of inputs and outputs in a full adder area. 2 and 1b. 2 and 2c. 3 and 3d. 3 and 2

5.In a 7 segment display the segments a,b,c,d,f,g are lit. The decimal numberdisplayed will bea. 9b. 5c. 4d. 2

6. In a 7 segment display the segments b and c are lit up. The decimal numberdisplayed will bea. 9b. 7c. 3d. 1

7 .A device which converts BCD to seven segments is calleda. encoderb. decoderc. multiplexer

d. none of these

8.Which device changes parallel data to serial dataa. decoderb. multiplexerc. demultiplexerd. flip flop

9.A 1 of 4 multiplexer requires…… data select linea. 1b. 2c. 3d. 4

10. It is desired to route data from many registers to one register. The device needed isa. decoderb. multiplexerc. demultiplexerd. counter

11.Which device has one input and many outputsa. flip flopb. multiplexerc. demultiplexerd. counter

12.Two 16:1 and one 2:1 multiplexers can be connected to form aa. 16:1 multiplexerb. 32:1 multiplexerc. 64:1 multiplexerd. 8:1 multiplexer

13. Parallel adder isa. sequential circuitsb. combinational circuitsc. either sequential or combinational circuitsd. none of above

14. A half adder can be used only for addinga. 1 bitb. 2 bitsc. 4 bitsd. 8 bits

15. Which statement below best describes the function of a decoder?

a. A decoder will convert a decimal number into the proper binary equivalent.

b. A decoder will convert a binary number into a specific output representing a particular character or digit.

c. Decoders are used to prevent improper operation of digital systems.

d.Decoders are special ICs that are used to make it possible for one brand of computer to talk to another.

16 One can safely state that the output lines for a demultiplexer are under the direct control of the:

a.input data select lines.

b. the internal AND gates.c. the internal OR gate.d. Input data line.

17.Refer to the figure given below. The logic function generator being implemented with the multiplexer in this circuit produces a constant LOW on the output. The ABC inputs are checked and appear to be pulsing; also, the 0–7 and EN inputs are checked with the scope and all appear to be at 0 V. A check with the DMM confirms that power is on. What is the problem, and what should be done to correct it?

a. The output is shorted to Vcc; replace the IC.

b. The scope's vertical input is in the AC mode and the common connection for the 0,2,3 and 5 inputs is bad. Set the scope's vertical input mode to DC, and repair the bad solder connection.

c. Power has not been applied to the circuit; apply power.d. The output is shorted to ground; replace the IC.

18. Refer to the keyboard encoder in figure (a). Sometimes when the 5 key is pressed, the system attached to the keypad does not respond. The 5 input on the 74147 is monitored with a digital storage scope while repeatedly pressing the 5 key, and the waveform in figure (b) is obtained; the P above the trace indicates the points at which the technician pressed the key. What is most likely wrong with the circuit?

a. The switches on the 5 key are intermittent; the contacts need to be cleaned or the switch replaced.

b. The pull-up resistor connected to the 5 key is bad and should be replaced.

c.The common ground connection at the bottom of the 0 key has a bad solder connection; repair the connection.

d. The 74147 is intermittent, possibly due to high temperature, and should be replaced.

19.The BCD/DEC decoder shown in figure (a) is examined with a logic analyzer and the results are shown in the waveforms in figure (b). What, if anything, is wrong with the circuit?

a. The "2" output is shorted to Vcc.b. The A1 input is internally open.

c.The A1 input node is internally stuck LOW.

d. Nothing is wrong with the circuit.

20. A 16-input multiplexer is to be used to perform parallel-to-serial data conversion. Which of the following counters would be required to provide the data select inputs?

a. MOD 8

b.MOD 16

c. MOD 4d. MOD 2

21. A breadboard-circuit design using a BCD-to-decimal decoder has a problem wherein the operation of the system is erratic. The technician uses his scope to examine the waveforms throughout the system and doesn't really see any problems. While he's scratching his head, what helpful advice can you offer him as to what might be wrong and what to do to correct the problem?

a. The decoder is thermally intermittent; replace it.b. There is probably a bad connection on the wire wrap protoboard; recheck the wiring.

c.Glitches are probably the culprit; strobe the decoder.

d.The decoder is thermally intermittent and must be replaced; or there is probably a bad connection on the wire wrap protoboard, and the wiring must be rechecked.

22.  Output 5 of a 74138 octal decoder is selected when it is enabled by a data input of:

a.

b.

c.

d.

23. How is the number one (1) indicated on the outputs of a 7447 BCD-to-seven-segment code converter?

a. Segment a is active.b. Segment b is active.c. Segments a and b are active.

d.Segments b and c are active.

24. For the input values (A0–A3, B0–B3, Data Select = 1) given for the circuit given below, what will be indicated on the displays?

a. A = 0, B = 5b. A = 5, B = 0c. A = 6, B = 0

d.A = 0, B = 6

25. It is suspected that the comparator in the figure given below has a problem. The inputs are activated in the table shown below and the corresponding outputs noted. What is most likely wrong with the circuit?For P0 – P3 = 1 and Q0 – Q3 = 0, P > Q = 1, P = Q = 1, P < Q = 0For P0 – P3 = 0 and Q0 – Q3 = 1, P > Q = 0, P = Q = 1, P < Q = 1For P0 – P3 = 1 and Q0 – Q3 = 1, P > Q = 0, P = Q = 1, P < Q = 0

a. The P0–P3 inputs are defective.b. One or more of the Q inputs is bad.

c.The P = Q output is shorted to Vcc.

d. Nothing is wrong; the circuit is functioning properly.

26. Which statement best describes the given figure, and what is the function of the terminal labeled EN?

a. Quad two-input multiplexer. EN is the enable input, which requires an active LOW for the device to work.

b. Quad two-bit multiplier, EN is the active HIGH trigger.

c.Dual quad-input multiplexer, which requires an active LOW on the EN terminal for the device to work.

d.Quad two-input AND gate, which requires an active LOW on the EN input to enable all the gates.

27. The data transmission system shown in below has a problem; the parity error output is always high. A logic analyzer is used to examine the system and shows that the DATA IN on the left matches the DATA OUT on right. What might be causing the problem?

a. The error gate could be defective.b. The storage circuit could be defective.c The parity checker could be bad.

d..Any of the above.

28. What is the purpose of a decoder's inputs?

a. To allow the decoder to respond to the inputs to activate the correct output gate.b. To disable the decoder outputs so that all outputs will be inactive.c. To disable the inputs and activate all outputs.

d To allow the decoder to respond to the inputs to activate the correct output gate, and to disable the inputs and activate all outputs.

29. Multiplexing of digital signals is usually required when:

a. moving data internally within a microprocessor.b. moving data between memory and storage registers in a microprocessor.

c.moving data over long distance transmission lines.

d.moving data internally within a microprocessor or between memory and storage registers.

30. Referring to the figure given below, what output code will appear on the output (A3,A2,A1,A0) when the 5 key is pressed?

a.1010

b. 0101

c. 1101 d. 1011

31. What type of device is shown in the given figure, and what inputs (A3,A2,A1,A0) are required to produce the output levels as shown?

a. A binary-to-decimal encoder; 0,1,1,1b. A decimal-to-binary decoder; 1,1,1,0

c.A BCD-to-decimal decoder; 0,1,1,1

d. A decimal-to-BCD encoder; 1,1,1,0

32. What are the outputs of a 7485 four-bit magnitude comparator when the inputs are A = 1001 and B = 1010?

a.

A < B is 1A = B is 0A > B is 1

b.

A < B is 0A = B is 1A > B is 0

c.

A < B is 0A = B is 0A > B is 1

d.A < B is 1A = B is 0

A > B is 0

33. Determine the correct output for the multiplexer and its associated timing diagram given below.

a. Ya b. Yb

c. Yc d.Yd

34. What must be done in the given figure in order to use two 7485 4-bit comparators to compare two 8-bit numbers?

a.The P < Q, P = Q, and P > Q outputs of COMP A must be connected to the same outputs of COMP B.

b.The P < Q, P = Q, and P > Q outputs of COMP A must be connected to the <, =, and > inputs of COMP B.

c.The = input of COMP A must be connected to Vcc, and the < and > inputs must be connected to ground.

d. The P < Q, P = Q, and P > Q outputs of COMP A must be connected to the <, =, and > inputs of COMP B, the = input of COMP A must be connected to Vcc, and the < and > inputs must be connected to ground.

35.The number of control lines for a 8 – to – 1 multiplexer is(A) 2 (B) 3(C) 4 (D) 5Ans: B

36.The gates required to build a half adder are(A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate(C) EX-OR gate and AND gate (D) Four NAND gates

37.The device which changes from serial data to parallel data is(A) COUNTER (B) MULTIPLEXER

(C) DEMULTIPLEXER (D) FLIP-FLOPAns: C

38.A device which converts BCD to Seven Segment is called(A) Encoder (B) Decoder(C) Multiplexer (D) Demultiplexer

39. How many select lines will a 16 to 1 multiplexer will have(A) 4 (B) 3(C) 5 (D) 1Ans: A

Objective questions: Topic: Sequential logic circuits

(Ch 5, Ch 7)

(Latches&Flipflops, Counters&Registers)1. A flip flop is aa. combinational circuitb. memory elementc. arithmetic elementd. memory or arithmetic

2. In a D latcha. data bit D is fed to S input and D’ to R inputb. data bit D is fed to R input and D’ to S inputc. data bit D is fed to both R and S inputsd. data bit D’ is not fed to any input

3. In a D latcha. a high D sets the latch and low D resets itb. a low D sets the latch and high D resets itc. race can occurd. none of above

4.In a positive edge triggered JK flip flopa. High J and High K produce inactive stateb. Low J and High K produce inactive statec. High J and Low K produce inactive stated. Low J and Low K produce inactive state

5.In a positive edge triggered D flip flopa. D input is called direct setb. Preset is called direct resetc. preset and clear are called direct set and reset respectivelyd. D input overrides other inputs

6. In a positive edge triggered JK flip flopJ=1,K=0 and clock pulse is rising.Q willa. be 0b. be 1c. show no changed. toggle

7. For edge triggering in flip flops manufacturers usea. RC circuitb. direct coupled designc. either RC circuit or direct coupled designd. none of these

8. In a JK flip flop toggle meansa. set Q=1 and Q’=0b. set Q=0 and Q’=1c. change the output to the opposite stated. no change in input

9. A mod 4 counter will counta. from 0 to 4b. from 0 to 3c. from any number n to n+4d. none of above

10.A ring counter has N flip flops. The total number of states area. Nb. 2Nc. 3Nd. 4N

11.A counter has modulus of 10. The number of flip flops area. 10b. 5c. 4d. 3

12.In a ripple countera. whenever a flip flop sets to 1,the next higher FF togglesb. whenever a flip flop sets to 0,the next higher FF remains unchangedc. whenever a flip flop sets to 1,the next higher FF faces race conditiond. whenever a flip flop sets to 0,the next higher FF faces race cond

13.A counter has 4 flip flops. It divides the input frequency bya.4b. 2c. 8d. 16

14. A decade counter skipsa. binary states 1000 to 1111b. binary states 0000 to 0011c. binary states 1010 to 1111d. binary states 1111 and higher

15.The number of flip flops needed for Mod 7 counter area. 7b. 5c. 3d. 1

16.A presettable counter with 4 flip flops start counting froma. 0000b. 1000c. any number from 0000 to 1111d. any number from 0000 to 100017.A 4 bit down counter can count froma. 0000 to 1111b. 1111 to 0000c. 000 to 111d. 111 to 000

18. A 3 bit up-down counter can count froma. 000 to 111b. 111 to 000c. 000 to 111 and also from 111 to 000d. none of above

19.IC counters area. synchronous onlyb. asynchronous onlyc. both synchronous and asynchronousd. none of above

20. Shifting digits from left to right and vice versa is needed ina. storing numbersb. arithmetic operationsc. countingd. storing and counting

21. The basic storage element in a digital system isa. flip flopb. counterc. multiplexerd. encoder

22. The simplest register isa. buffer registerb. shift registerc. controlled buffer registerd. bidirectional register

23. The basic shift register operations area. serial in serial outb. serial in parallel outc. parallel in serial outd. all of above

24. A universal shift register can shifta. from right to left

b. from left to rightc. both from right to left and left to rightd. none of above

25. In a shift register, shifting a bit by one bit meansa. division by 2b. Multiplication by 2c. subtraction by 2d. any of above

26. An 8 bit binary number is to be entered into an 8 bit serial shift register. The number of clock pulses required isa. 1b. 2c. 4d. 8

27. Which of the following is not a form of multivibrator?

a. Tristable.b. Monostablec. Bistabled. Astable

 

28. The S-R latch shown here has active high inputs.

29. A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously?

  a. The Q output is reset to 0.  b. The Q output is set to 1.  c. The Q output toggles to the other state.  d. The Q output remains unchanged.

30. What is the function of the following circuit?

  a. A four-bit memory register.  b. A four-bit shift register.  c. A four-bit ripple counter.

d. A four-bit synchronous counter.

31. What is the frequency of the output of the following circuit?

a. 4 Hz b. 16 Hz C.  8 Hz d. 1 Hz.

32. What is the function of the following circuit?

 a. A modulo-6 counter b. A modulo-8 counter c.  A modulo-10 counter d. A modulo-12 counter

33. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________.

a. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0b. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0

c.Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1

d. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1

34. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?

a. 0000 b. 0010

c.1000

d. 1111

35. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?

a. tristateb. end around

c.universal

d. conversion

36. On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.

a.Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1

b. Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0c. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0d. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0

37. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.

a. 1101 b.0111

c. 0001 d. 1110

38.  How can parallel data be taken out of a shift register simultaneously?

a. Use the Q output of the first FF.b. Use the Q output of the last FF.c. Tie all of the Q outputs together.

d.Use the Q output of each FF.

39.  What does the output enable do on the 74395A chip?

a. It determines when data can be loaded.b. It forces all outputs to go HIGH.c. It forces all outputs to go LOW.

d.It activates the three-state buffer

40.  To operate correctly, starting a ring shift counter requires:

a. clearing all the flip-flops

b.presetting one flip-flop and clearing all others

c. clearing one flip-flop and presetting all othersd. presetting all the flip-flops

41.  In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns?

a. 2 b. 6

c.12

d. 24

42.  A modulus-12 ring counter requires a minimum of ________.

a. 10 flip-flops

b.12 flip-flops

c. 6 flip-flopsd. 2 flip-flops

43. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.

a. 01110 b. 00001

c.00101

d. 00110

44.  What is meant by parallel loading the register?

a. shifting the data in all flip-flops simultaneouslyb. loading data in two of the flip-flops

c.loading data in all flip-flops at the same time

d. momentarily disabling the synchronous SET and RESET inputs

45. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

a. 1100 b. 0011

c.0000

d. 1111

46. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.

a. 0000 b. 1111

c.0111

d. 1000

47. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.

a. 4 s

b.40 s

c. 400 sd. 40 ms

48. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.

a. 16 sb. 8 s

c.4 s

d. 2 s

49. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

a.ring shift

b. clockc Johnsond. binary

50. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

a. 10011100 b.11000000

c. 00001100 d. 11110000

51. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

a. 11101011 b. 00010111

c. 11110000 d.00000000

52. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

a.right, one

b. right, twoc. left, oned. left, three

53.  How many clock pulses will be required to completely load serially a 5-bit shift register?

a. 2 b. 3

c. 4 d.5

54.  What is the difference between a ring shift counter and a Johnson shift counter?

a. There is no difference.b. A ring is faster.

c.The feedback is reversed.

d. The Johnson is faster.

55. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.

a. 1110 b. 0111

c. 1000 d.1001

56. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.

a. 1110 b.0001

c. 1100 d. 1000

57. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?

a. parallel-in, parallel-outb. parallel-in, serial-out

c.serial-in, parallel-out

d. serial-in, serial-out

58. When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.

a. 40 kHzb. 50 kHz

c.400 kHz

d. 500 kHz

59.  Ring shift and Johnson counters are:

a.synchronous counters

b. aynchronous countersc. true binary countersd. synchronous and true binary counters

60.  In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?

a. 1 b 2

c. 4 d.8

61. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

a. 1101000000 b.0011010000

c. 1100000000 d. 0000000000

62.  How many flip-flops are required to make a MOD-32 binary counter?

a. 3 b. 45

c.5

d. 6

63. Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?

a. 50,000 b. 65,536

c. 25,536 d.15,536

64. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?

a.10002

b. 10102

c. 10112 d. 11012

65.  The terminal count of a modulus-11 binary counter is ________.

a.1010

b. 1000

c. 1001 d. 1100

66.  List which pins need to be connected together on a 7493 to make a MOD-12 counter.

a. 12 to 1, 11 to 3, 9 to 2b. 12 to 1, 11 to 3, 12 to 2

c.12 to 1, 11 to 3, 8 to 2

d. 12 to 1, 11 to 3, 1 to 2

67.  Synchronous construction reduces the delay time of a counter to the delay of:

a. all flip-flops and gatesb. all flip-flops and gates after a 3 countc. a single gate

d.a single flip-flop and a gate

68. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:

a. input clock pulses are applied only to the first and last stagesb. input clock pulses are applied only to the last stagec. input clock pulses are not used to activate any of the counter stages

d.input clock pulses are applied simultaneously to each stage

69.  What is the difference between a 7490 and a 7492?

a. 7490 is a MOD-12, 7492 is a MOD-10b. 7490 is a MOD-12, 7492 is a MOD-16c. 7490 is a MOD-16, 7492 is a MOD-10

d.7490 is a MOD-10, 7492 is a MOD-12

70. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.

a.product

b. sum

c. log d. reciprocal

71. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

a.500 kHz

b. 1,500 kHzc. 6 MHzd. 5 MHz

72.  What decimal value is required to produce an output at "X" ?

a. 1b. 1 or 4c. 2

d.5

73.  A BCD counter is a ________.

a. binary counterb. full-modulus counter

c.decade counter

d. divide-by-10 counter

74.  How many flip-flops are required to construct a decade counter?

a. 10 b 8

c. 5 d.4

75.  A seven-segment, common-anode LED display is designed for:

a. all cathodes to be wired together

b. one common LED

c.a HIGH to turn off each segment

d. disorientation of segment modules

76.  To operate correctly, starting a ring counter requires:

a. clearing one flip-flop and presetting all the others.b. clearing all the flip-flops.

c.presetting one flip-flop and clearing all the others.

d. presetting all the flip-flops.

77. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.

a.When MR1 and MR2 are both HIGH, all Qs will be reset to zero.

b. When MR1 and MR2 are both HIGH, all Qs will be reset to one.c. MR1 and MR2 are provided to synchronously reset all four flip-flops.d. To enable the count mode, MR1 and MR2 must be held LOW.

78.  Which of the following is an invalid output state for an 8421 BCD counter?

a.1110

b. 0000

c. 0010 d. 0001

79.  How many different states does a 3-bit asynchronous counter have?

a. 2 b. 4

c.8

d. 16

80. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.

a. 12 msb. 24 nsc. 48 ns

d.60 ns

81.  Three cascaded modulus-5 counters have an overall modulus of ________.

a. 5 b. 25

c.125

d. 500

82. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

a. None b. One

c. Two d.Fifteen

83.  The final output of a modulus-8 counter occurs one time for every ________.

a.8 clock pulses

b. 16 clock pulsesc. 24 clock pulsesd. 32 clock pulses

84. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

a. 1101 b.1011

c. 1111 d. 0000

85. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from

clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.

a. 15 nsb. 30 nsc. 45 ns

d.60 ns

86.  Three cascaded decade counters will divide the input frequency by ________.

a. 10 b 20

c. 100 d.1,000

87.  A counter with a modulus of 16 acts as a ________.

a. divide-by-8 counter

b.divide-by-16 counter

c. divide-by-32 counterd. divide-by-64 counter

88.  What is the difference between a 7490 and a 7493?

a.7490 is a MOD-10, 7493 is a MOD-16

b. 7490 is a MOD-16, 7493 is a MOD-10c. 7490 is a MOD-12, 7493 is a MOD-16d. 7490 is a MOD-10, 7493 is a MOD-12

89.  A ripple counter's speed is limited by the propagation delay of:

a.each flip-flop

b. all flip-flops and gatesc. the flip-flops only with gatesd. only circuit gates

90.  A 4-bit counter has a maximum modulus of ________.

a. 3 b. 6

c. 8 d.16

91.  How many natural states will there be in a 4-bit ripple counter?

a. 4 b. 8

c.16

d. 32

92. Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?

a. Five flip-flops, three AND gatesb. Seven flip-flops, five AND gatesc. Four flip-flops, ten AND gates

d.Six flip-flops, four AND gates

93. The circuit given below fails to produce data output. The individual flip-flops are checked with a logic probe and pulser, and each checks OK. What could be causing the problem?

a. The data output line may be grounded.

b.One of the clock input lines may be open.

c. One of the interconnect lines between two stages may have a solder bridge to ground.d. One of the flip-flops may have a solder bridge between its input and Vcc.

94. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q

output of each stage of the counter?

a. Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz

b.Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz

c. Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHzd. Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz

95. The designation means that the ________.

a. up count is active-HIGH, the down count is active-LOW

b.up count is active-LOW, the down count is active-HIGH

c.up and down counts are both active-LOW

d.up and down counts are both active-HIGH

96.  Why can a synchronous counter operate at a higher frequency than a ripple counter?

a. The flip-flops change one after the other.

b.The flip-flops change at the same time.

c.A synchronous counter cannot operate at higher frequencies.

d. A ripple counter is faster.

97.A ring counter consisting of five Flip-Flops will have(A) 5 states (B) 10 states(C) 32 states (D) Infinite states

98.If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is(A) 1000 Hz (B) 500 Hz(C) 333 Hz (D) 12.5 Hz.Ans: D

99.In a JK Flip-Flop, toggle means(A) Set Q = 1 and Q = 0.(B) Set Q = 0 and Q = 1.(C) Change the output to the opposite state.

(D) No change in output.

100. How many flip flops are required to construct a decade counter(A) 10 (B) 3(C) 4 (D) 2Ans: C

101.For JK flip flop with J=1, K=0, the output after clock pulse will be(A) 0. (B) 1.(C) high impedance. (D) no change.Ans: B

102. The output of SR flip flop when S=1, R=0 is(A) 1 (B) 0(C) No change (D) High impedance