dft course ieee p1687 (ijtag) draft standard for...
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Slide 1© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
DFT Course
A Presentation Based on Slides Created by Members of the IEEE P1687 (IJTAG) Working Group and presented by
Ben Bennetts, DFT Consultant Tel: +44 1489 581276 E-mail: [email protected]
http://www.dft.co.uk/
IEEE P1687 (IJTAG) Draft Standard for Access and Control of Instrumentation
Embedded Within a Semiconductor Device
IEEE P1687 (IJTAG) Draft Standard for Access and Control of Instrumentation
Embedded Within a Semiconductor Device
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Slide 2© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Outline
Background: use of 1149.1 Test Access Port to access embedded instrumentsIEEE P1687 (IJTAG) evolution, scope, motivation, problem statementEvolution of embedded instrumentation – revisitedDescribing embedded instrument features: documentation, BSDL, access protocolsP1687 Application Program InterfaceSecondary interfaces: the HUB conceptConclusions, status, issues, getting involved
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Slide 3© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Disclaimer
This presentation is a personal view of what is happening within the IJTAG initiative. It is not necessarily an IJTAG-endorsed presentation. Other members of IJTAG may have slightly different views of the objectives and status of IJTAG. This is the nature of formative activities.
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Slide 4© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
P1687 EvolutionBegan as separate and independent discussions between ASSET and Inovys, and Agilent and Cisco.First meeting at ITC04 BTTAC (BTAG) meeting.Working group formed shortly after VTS05.IEEE Project Authorization Request approved on 16 March 2006. Allocated P1687 project number *
* Isaac Newton, Principia Mathematica published
Now regular face-to-face meetings at conferences and workshops and weekly telephone conference calls.
8 core members.Over 80 “extended” WG members.
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Slide 5© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
June 2006 – Who’s Involved?Agilent TechnologiesATI ResearchCadenceCISCODAFCAIBMInovysLucent Technologies NovasSiliconAid ST MicroSynopsys Plus a number of independent consultants
Core Group:
Ben Bennetts, Bennetts AssociatesAl Crouch, InovysJason Doege, DA-TestBill Eklow, Cisco SystemsMike Laisné, QualcommMike Ricchetti, ATIKen Posse, Consultant, ChairmanJeff Rearick, Agilent Technologies
Core Group:
Ben Bennetts, Bennetts AssociatesAl Crouch, InovysJason Doege, DA-TestBill Eklow, Cisco SystemsMike Laisné, QualcommMike Ricchetti, ATIKen Posse, Consultant, ChairmanJeff Rearick, Agilent Technologies
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Slide 6© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
IEEE P1687 PAR
Draft Standard for Access and Control of Instrumentation Embedded Within a Semiconductor Device:Scope: “This Standard will develop a methodology for access to embedded test and debug features, (but not the design of the features themselves) via the IEEE 1149.1 Test Access Port (TAP) and additional signals that may be required. The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features”
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Slide 7© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Defining Test, Debug and Instruments
Test, usually taken to be structural (manufacturing) test
Debug, usually taken to mean functional (validation) checkout.
Instrument, very broadly:Any on-chip circuit for test, debug, diagnosis, monitoring, characterization, configuration, or functional use that can be accessed by, configured from, or communicated with an IEEE 1149.1 TAP and TAP controller.Note: an instrument is often called an Intellectual Property, IP.
Examples of instruments: next slide …
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Slide 8© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
TAP Access to Embedded InstrumentsInternal scan chains, LBIST and MBISTI/O BIST (PRBS, Jitter Test, crosstalk test)Process Monitors (used to identify systemic problems)
Systemic: affecting the body generally
RAM
Mem BIST
Interface BIST
Interface BIST
Logic BIST
Scan Chain
Scan Chain
SerDes
SerDes
SerDes
SerDes
JTAGTAP
1500Wrapped
Core
Core Logic
BSR
BSR
BSR
BSR
Voltage Monitors (used to identify IR-drop problems)State DumpBuilt in Logic Analyzer or O-scope embedded instrumentationIEEE 1500 Wrapped CoresBUT – no standard directions on how to access these features
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Slide 9© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Board/System: Facilitate test and debug developmentInteroperability of tests across multiple test-prep-and-apply vendors and across multiple test processes (prototype board validation, volume manufacturing)
Chip instrument designers/providers:Require a standard way of defining the use of an embedded instrument
Chip ATE:Facilitate test and debug developmentPromote low-cost chip ATE
Motivation for P1687
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Slide 10© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Example: Creating a Board/System Test
Complex componentsMultiple SOC and High-End ASICsMicroprocessorsEmbedded and standalone memoriesProgrammable logic devices
Complex design featuresHigh-speed I/OBackplane connectionsMultiple configurations
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Slide 11© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
… at board and system level:
Re-run device embedded memory testsRe-run device logic BISTRun ASIC-based external memory testsRun chip-to-chip High-Speed IO Pseudo-Random Binary Sequences testsMonitor internal signal waveformsCapture internal chip states (scan dump)Use chip test features to assist board test
… and even at chip level
Goal: Re-use Component Instruments …
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Slide 12© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Daunting Task: Assembling IC Info
BSDL (Boundary Scan Description Language) files
Initialization sequence(s) and clock control
Logic BIST and MBIST recipesSetup, launch, checking proceduresDiagnostic routines
List of other test and debug instruments and access methods.
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Slide 13© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
For each high-speed linkMethod to setup, launch, and check Bit-Error RatesAbility to apply different crosstalk, jitter, noise, data content conditions
For each parallel busMethod to setup, launch, and check signal integrity properties.Patterns for crosstalk, glitches, etc.
For each backplane configuration…
Assembling Board/System Info
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Slide 14© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Accessing Instruments: Cisco’s Experience
Accessing Test Features is PainfulMultiple ASIC vendorsMultiple memory vendorsMultiple test methodologies: structural and functional.Multiple ATE platformsMultiple test languages
Bottom line: chip test re-use at board/system?It’s tough!
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Slide 15© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
We need a standard!
There is currently no standard method to describe or interact with chip design, test and debug instrumentation.
It is currently very difficult to re-use chip-level DFTest and DFDebug instruments at the single-board and multi-board (system) levels
There is a growing supply of test and debug instruments and a growing need to re-use it at higher levels….
So, what is a design, test and debug instrument?
P1687 Problem Statement
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Slide 16© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
1149.1Test Access
Port
Boundary-Scan Logic (IR, DRs, Controller, etc.
Memory BIST EnginesMemory BIST
EnginesMemory BIST Engines
Internal Scan Chains
HSIO BIST Engines
Current Control
Configure Clock Domains
IOBIST
IOWRAPPLL and Clock Configuration
O-Scope
Configure Internal Memory BISTs
Configure Scan Wrappers
Selection of Output Compactor
Performance Monitors
Configure External Memory BISTs
Assertion Checking
Crosstalk Generation
Configuration of Compactor Units
Configure Functional Units
Logic Analyzer
Configuration of Decomp Units
Current Meter
Signal Tapping
Control LFSR Re-Seeding
BERT
Alternate IDCode Register
Configuration of Memory BISR
Configure Input Pin Isolators
Core Instrument Interface
Analog MUX Networks
Configuration of Polynomials
Configuration of MISRs
Configuration of Functional Units
Current Measurement
Configuration of Decomp Units
Selection of Incremental and Final Signatures
Configure Pullupand Pulldown
Resistors
Configure 1500 Wrappers
Configure Input Isolators
Configure Clock Chop Ratios
Configure Access to Test Bus
Enabling/Disabling Memory Lock
Configure Tristate Bus Controllers
Configure Scan-In/Scan-Out Ports
Configure Scan Dump Modes
Configure Reduced Pin Count Modes
The Evolution of Embedded Instruments
Anything you like!!
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Slide 17© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Types of Embedded Instruments
IO – Parametric AdjustmentIO – SSO/CrosstalkIO - JitterIO - BERTIO - PRBSLogic BISTExternal Memory BISTInternal Memory BISTFunctional ConfigurationIn-Circuit EmulationI/O configurationTemperature MeasurementVoltage MeasurementPower control/MeasurementClock control1500 wrapper structures
Analog MuxingChip/Die ID
Internal Counters/Status Registers
Packet Generation
Waveform Generation/Analysis
Internal Test ManagementInter-domain SynchronizersIBISTX-Mask control, for TDCScan Dump ControlPower ControlPLL and Clock configurationPerformance MonitorsExternal Trigger selectionO-ScopeLogic Analyzer
More Details ..
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Slide 18© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
uP/ASIC/ASSP/FPGA
IEEE 1149.1
TAPRegister access
Internal test instruments
(BIST, LAs, O-scope, clock
controllers, etc)
TAP-based Access to Instruments
Standard Protocol
ATE, system, remote
Test Data
DescLang
High band width
Internal interface
Latest Protocol
handshake
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Slide 19© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Fully-Embedded Instruments
Fully embedded instruments simply require a mechanism for initialising the instrument, running the instrument, and collecting the final result e.g. memory BIST in Pass/Fail mode.
1149.1TAP
Memory BISTController
Standard Protocol
Master JTAG Controller
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Slide 20© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Partially-Embedded Instruments
Partially embedded instruments require a real-time connection to monitor the progress of the instrument and, possibly, cause a mode change e.g. analysis and display of Logic Analyser signals.
1149.1TAP
LA Signal Conditioner
Standard Protocol
Master JTAG Controller
External Instrument
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Slide 21© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Documentation: architectural descriptions Identify accessible embedded instrumentsSpecify characteristics of the instrument
Access protocols: procedure descriptionsDescribe how to communicate with an instrumentFacilitate re-use through portability
“Enhanced”, secondary access/interface:Service instruments not easily handled solely by the TAP (i.e. use high bandwidth I/O)Simplify hierarchical test architectures
Key Focuses of P1687
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Slide 22© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Communication between provider and consumer is ad-hocThere is no mechanism to specify which instruments are included in the chip
In many cases available test instruments are not used due to lack of knowledge
Details often included in long specs (no common format)Many times specs are communicated “word of mouth”
Documentation - Current Approach
You wanna know a secret?
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Slide 23© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Survey of Cisco BIST Documentation
Cisco study found ….Supplier MBIST and IOBIST
Brief description of logicBoundary scan tester macros
Cisco Internal Logic BISTNo HW documentationVerilog test bench
Supplier High-Speed IO Pseudo-Random Binary SequencesNo documentation (application engineer)
Cisco Internal Scan DumpMacros provided by ASIC DFT group
Cisco External Memory BIST50+ page specificationFull HW and access protocol definition
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Slide 24© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Documentation – Intent
End user can easily identify and program embedded instrumentsFacilitate automated tests based on machine readable descriptions Minimize “Time to Understanding” and “Time to Bring Up”
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Slide 25© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
P1687 HW Documentation Requirements
Describe the architecture of internal instruments i.e. how to use, but not what they do.
Instrument name, type and instance.Register definition: location, length, serial or parallel access, clocks, type.Control action details: initialize, execute, wait time, results collection.Data and instruction formats.Internal and external dependencies.
Provide an inventory of all instrument content on a chip: basically, to identify the number and location of each instrument.Provide enough information for a programmer to determine how to perform low level instrumentation functions.
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Slide 26© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Today’s “common” interfaces for embedded instruments:TAP-basedI2C, or some other bus.Custom CPU interface e.g. ARM CoreSightInternal core-based e.g. 1500 wrapperCustom protocol
Each with theirown language!
Common Access Protocol – Current Approach
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Slide 27© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Facilitate re-usable code across boundary-scan platforms and different test processes.Simplify program development by building on several lower level procedures e.g. IR-Scan, DR-Scan, etc.Application Programming Interface versus a Language such as CTL (IEEE 1450.6), STAPL, SVF, …
Instruction and data protocols..Action sequencing.Pass/Fail and error reporting.Be EDA/ATE vendor independent.
Common Access Protocol - Intent
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Slide 28© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
IEEE P1687 API ProposalP1687 procedures can be thought of as an API:
Can be called from a variety of higher-level environments.Delivered as a package by the IP provider (instrument designer): initiate actions, set up parameters, collect responses.Expose only those features that IP provider chooses.Hide low-level details from user.Instrument actions embedded in a set of standard P1687 function calls based on BSDL/HSDL analysis.
Layers:End user
IP provider
Compiler
1. test / measurement process
2. exported instrument procedures
3. register writes and reads
4. TAP commands
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Slide 29© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
P1687 Static Test Assembly Flow
1149.1 TAP-basedtest assembler
Test program calling IP procedures(your favorite language)
IP procedures(reg read/writes)
Scanpathconfiguration
Stream of TAP instructions/data
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Slide 30© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Interactive programcalling IP procedures
in terms of 1149.1 TAPinterface box API
IP procedures(register
read/writes)
Chip/Board/Sysscanpath
configuration
Chip/Board/System JTAG connection
(stream of TAP instructions/data)
TAP interfaceDLL / API
P1687 Interactive Test/Debug Env
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Slide 31© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Allow hand-off to an interface with higher bandwidth than the 1149.1 TAP for data-intensive operationsAllow interoperation between individual instruments that may require asynchronous signalingAllow an avenue for support of legacy (non-TAP) instrument interfaces
Secondary Interfaces/HUB* - Intent
* Still deciding on a name: router, gateway, nub, kernel, cynosure (guide), nukulus, …
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Slide 32© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Phase 1: simple instrument-to-TAP interfaceNeed: spec for standard interface to instrumentsSolution: scan-based: TAP Test Data Registers (TDRs)
Phase 2: higher bandwidth I/ONeed: hand off data transfer to another interface with higher bandwidth than TAPSolution: mux controls to configure I/Os
Phase 3: instrument intercommunicationNeed: instrument-to-{instrument/ATE} communicationSolution: hierarchical “HUB” with asynchronous signals
Evolving Interface Requirements
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Slide 33© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Phase 1: Test DR-Based Access
TAP1TDITDOTCKTMS Instrument A
Registers for ASO_A1SI_A1
Instrument BRegisters for B
SI_B1 SO_ B1
chip
Phase 1: simple instrument-to-TAP interface
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Slide 34© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Instrument A
Instrument B
TAP1 chipTDITDOTCKTMS Registers for A
Registers for B
SO_A1SI_A1
SI_B1 SO_ B1
some interface
REQ
ACKNote: REQ = startACK = done
Phase 2: TDR + I/O + Polling signals
Phase 2: higher bandwidth I/O
TDITDOTCKTMS
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Slide 35© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Phase 3: HUB Approach
TAP1TDITDOTCKTMS
Instrument ARegisters for A
Instrument BRegisters for B
some interface
HUB
Sync
Status
Sync
Int
chip
Phase 3: instrument intercommunication
TDITDOTCKTMS
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Slide 36© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
HUB-less P1687 Interface (Phase 1)
JTAG SDRJTAG SDR
JTAG TAP
Config Reg Status Reg Data Reg
Instrument
Simplest1687
InterfaceJTAG SDR
JTAG SDR
Config Reg
From TDI
To TDOSerial-In/Out
Transfer to parallel hold
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Slide 37© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
HUB-less P1687 IF w/ Phy + Async Sigs (Phase 2)
Other Phy
JTAG SDRJTAG SDR
JTAG TAP
Hand-
Shake
SyncInt
iClk
Config Reg Status Reg Data Reg
Instrument
JTAGSDR
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Slide 38© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
HUB: One Instrument, One Phy
HUBInterface side
Instrument side
Config Reg IF Status Reg IF Data Reg IF
Config Reg Status Reg Data Reg
Hand-
Sh ake
S yncIn t
iClk
Other Phy
JTAG SDRJTAG SDR
JTAG TAP
Hand-
Sh ake
SyncIn t
iCl k
Config Reg Status Reg Data Reg
Instrument
1687Host -side interface
JTAG SDR
1687 Client-side interface
Note: the HUB can re-use the registers in the instrument.
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Slide 39© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
HUB with Two Instruments (Phase 3)
Config Reg IF Status Reg IF Data Reg IF
Config Reg Status Reg Data Reg
Hand-
Shake
SyncInt
iClk
Other Phy
JTAG SDRJTAG SDR
JTAG TAP
Hand-
Shake
SyncInt
iClk
Config Reg Status Reg Data Reg
Instrument
JTAGSDR
Config Reg IF Status Reg IF Data Reg IF
Hand-
Shake
SyncInt
iClk
Config Reg Status Reg Data Reg
Instrument
Could be synchronous Could be asynchronous
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Slide 40© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
P1687 Interface Hierarchy
1687-client
1687-client
1687-host
1687-client
1687-client
1687-host
1687-client
1500 WSP
1687-hostTAP
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Slide 41© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
SoC
Goal: Make the HUB just simple enoughEnable TAP-based interaction with instrumentsEnable high-bandwidth data transfer (optional)Enable instrument interaction (optional)Enable cascading hierarchically (optional)
Status: Closing in on an architecture but …
Hub Summary & Issues
Primary 1149.1 TAP
Main Core “JTAG” Port
LogicVision’s Wrapper TAP
Custom Port
Sub Core 1500 WSP
Oh dear!!Oh dear!!
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Slide 42© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Summary: The Three Pillars of P1687
Architectural Descriptions[BSDL/HSDL]
Interface Handoff[HUB]
Procedure Descriptions [API or CTL/SVF/STAPL/…]
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Slide 43© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Exact architecture of the HUB1149.1 TAP to lower level ports(1500, WTAP, JTAG, custom)Do we need to handle hierarchy?
BSDL/HSDL for architectural description: syntax, specs
Patterns and protocol procedural language choice:Application Program Interface, or …Full-featured programming language?
Compliance checking
Looking for help Staff subcommittees;
Provide real world examples
Open Issues
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Slide 44© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
To Get Involved …
To get involved/learn more/register your interest, contact Ken Posse (IJTAG Chairman) at [email protected]
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Slide 45© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
To Probe Further …
Jeff Rearick et al., “IJTAG: a Step on the Evolutionary Path”ITC 2005, P32.4Ken Posse et al., “P1687 – Toward a Standard Protocol for Embedded Instrumentation”, to be presented at ITC 2006
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Slide 46© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Any Questions?
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Slide 47© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
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Slide 48© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Appendix 1. In More Detail ….
Selecting Functional Units on the chip to be disabled/enabled Capture of alternate chip IDCode register (chip or mask version)
Chip configuration
Select chop-clock ratios and dividers for functional operationSelect chop-clock ratios for transition and path delay testing
Clock control
Turn on/off entire clock domainsTurn on/off pullup/pulldown resistorsTurn on/off input isolators (pass gates)
Power management
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Slide 49© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
… Continued
Enabling-Disabling memory lock for test and debug (OE and R/!W)
DMA (connecting BIST muxes to chip-level busses with access to pins)
Data collection from a memory BIST operating in diagnostic mode
Selection of Memory BISTs to be run in diagnostic modeSelection of memory BIST background (e.g., 3-C, 5-A, 0-F, 9-6)Selection of memory BIST algorithm
Selection of Memory BISTs to be run in parallel (1-hot bit per BIST)
Memory test
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Slide 50© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
… Continued
Scanning in of signature to be compared
Selection of 'final signature compare' vs. 'incremental signature extraction'
Scanning in of seeds for re-seeding or debugSelection of polynomial of PRPG LFSRsSelection of STUMPs Logic BIST units
Logic BIST
Subsuming AC scan operation completely within JTAGConfiguration of pins used as scan-ins and scan-outsSelection of pins to be used as scan-ins and scan-outsReconfiguration of scan wrappers around coresReconfiguration of scan chainsEnabling-disabling-configuring internal tristate busses
Selection of chip-level scan mode or individual partition scan mode
Scan test
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Slide 51© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
… Continued
Control of internal scan chain configurations (detect versus locate)
Control PLL bypass for clock controlAccess to low-frequency IOs
Reduced pin count test
Access to control registers for gating Scan-Enable and Scan-Clock PLL outputsPLL control
Selection of scan dump mode (lock memory, enables scan-out)Replacing data in key registers (with and UPDATE-like function)
Masking or overwriting key registers (with an EXTEST-like function)
Shadow capturing key registers (with a SAMPLE-like function)Loading an internal counter used as a breakpoint
Debug & Diagnosis
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Slide 52© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
… Continued (End)
Access for embedded instrument outputsControl of use of embedded instrumentsControl of
embedded instrumentation
Drive internal faultsDrive IO faults
Fault insertion
Back
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Slide 53© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Appendix 2: Memory BIST Procedure
Function declaratione.g. : int run_mbist_ram256x32sp(int repair_enable, int background);
Function bodyint run_mbist_ram256x32sp(int repair_enable, int background);
{start_clock(MCK);done_reg = 0;pass_reg = 0;repair_enable_reg = repair_enable;background_reg = background;start_BIST = 1;
}
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Slide 54© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Appendix 3: Four Technical Challenges
BandwidthBus sizing and data rates for instruments
SequencingTemporal staging of instrument actions
SynchronizationCoordination of chip resources and instruments
InteroperationConnectivity with external resources (e.g. ATE)
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Slide 55© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Bandwidth
Communication bottlenecks:Inside chip to outside world: state dumpOutside world to inside chip: memory preloadInside chip to inside chip: BIST
Control vs. Data bandwidthControl precedence? The ability to interrupt data?
Scalability across instrumentsGo/NoGo vs. massive data dump
Real estate vs. throughput
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Slide 56© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
SequencingSimplistic approach to instrument staging:
Initialize, launch, check
ComplicationsMultiple launchesInterruptionsDestructive checking DiagnosticsPower limitations
Language requirements
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Slide 57© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Synchronization
Coordination of chip activity with instrumentsCoordination of board/sys activity with instrumentsCoordination across multiple instrumentsPossible need for real-time interactionTime stamping with IEEE 1588Cross-clock domain data transfersSynchronization to TAP clock domain
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Slide 58© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Interoperation
Connection to external resources (ATE, controllers, measurement devices, etc.)Control and data exchange protocol and languageAccess to instruments during mission modeMaster/Slave relationships with multiple instrumentsSecurity
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Slide 59© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Slides Still Under Development
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Slide 60© 2006, IEEE P1687 Working GroupLast revised: 14 June 2006
Instrument definition
Chain definition
Register access
attribute INSTRUMENT_DEF of <device name>:entity is"Core1 IP1," &"Core2 IP1";
attribute CHAIN_DEF of <device name> entity is:// first register in chain is R1 of Core 1 and it is 4 bits
"Chain1 (Core1.R1,4)," & "Chain1 (Core1.R2,4)," &
// first two elements of Chain2 are R1 and R2 of Core2"Chain2 (Core2.R1,4 Core2.R2,4)";
attribute REGISTER_ACCESS of <device name> entity is:"Chain1 (MEMTST1)," &"Chain2 (MEMTST2)";
P1687 BSDL Attribute Proposals