Dissertation Presentation

On

LOW-VOLTAGE LOW-DROPOUT REGULATOR

DEPARTMENT OF ELECTRONICS ENGINEERING

Prof Sampat KV DEVYANIHOD ECE 1309136702MrsSangeeta Mangesh MTechECE Dept Adv ECEJSSATE ndash Noida JSSATE - Noida

OUTLINEbull Objective of Power Managementbull Basic Idea of Linear Regulatorbull Issues of Concern in LDOsbull Existing Techniques Used Pros and Cons based on

Literature survey in Detailbull Problem Statementbull Project Objectivebull Parametric Objectivebull Tool Usedbull Block Diagrambull Progress Till datebull Proposed Workbull Conclusion bull Future Scope References

POWER MANAGEMENT

bull Batteries discharge ldquoalmostrdquo linearly with time

bull Circuits with reduced power supply that are time dependent operate poorly Optimal circuit performance can not be obtained

bull Objective of a power converter is to provide a regulated output voltage

COVENTIONAL POWER CONVERTERS

bull Low drop‐out linear regulator (LDO)bull Switch‐inductor regulator (switching regulators)bull Switch‐capacitor regulator (charge pump)

TYPES

bull Different applicationsbull Desired efficiency and output ripple

LINEAR REGULATOR BASIC IDEA

LOW VOLTAGE LOW DROPOUT REGULATOR

The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load

bull Compared to DC‐DC switching regulators LDOs are

ndash Of continuous operation

ndash Easier to use

ndash Cheaper solution

ndash But of Lower efficiency

ISSUES OF CONCERN WITH LDO DESIGN

bull Pass transistor

1048782 load current will determine its size and thus layout

bull Error amplifier

1048782 The accuracy required by the LDO determines the magnitude of the open loop gain

1048782 Single pole architectures are recommended for better and easier stability

1048782 The amp transient requirement is dependent on the stability ie gain and phase margins There is a trade‐off in making the PM high and speed of amp This is also true for the Gain

1048782 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

OUTLINEbull Objective of Power Managementbull Basic Idea of Linear Regulatorbull Issues of Concern in LDOsbull Existing Techniques Used Pros and Cons based on

Literature survey in Detailbull Problem Statementbull Project Objectivebull Parametric Objectivebull Tool Usedbull Block Diagrambull Progress Till datebull Proposed Workbull Conclusion bull Future Scope References

POWER MANAGEMENT

bull Batteries discharge ldquoalmostrdquo linearly with time

bull Circuits with reduced power supply that are time dependent operate poorly Optimal circuit performance can not be obtained

bull Objective of a power converter is to provide a regulated output voltage

COVENTIONAL POWER CONVERTERS

bull Low drop‐out linear regulator (LDO)bull Switch‐inductor regulator (switching regulators)bull Switch‐capacitor regulator (charge pump)

TYPES

bull Different applicationsbull Desired efficiency and output ripple

LINEAR REGULATOR BASIC IDEA

LOW VOLTAGE LOW DROPOUT REGULATOR

The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load

bull Compared to DC‐DC switching regulators LDOs are

ndash Of continuous operation

ndash Easier to use

ndash Cheaper solution

ndash But of Lower efficiency

ISSUES OF CONCERN WITH LDO DESIGN

bull Pass transistor

1048782 load current will determine its size and thus layout

bull Error amplifier

1048782 The accuracy required by the LDO determines the magnitude of the open loop gain

1048782 Single pole architectures are recommended for better and easier stability

1048782 The amp transient requirement is dependent on the stability ie gain and phase margins There is a trade‐off in making the PM high and speed of amp This is also true for the Gain

1048782 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

POWER MANAGEMENT

bull Batteries discharge ldquoalmostrdquo linearly with time

bull Circuits with reduced power supply that are time dependent operate poorly Optimal circuit performance can not be obtained

bull Objective of a power converter is to provide a regulated output voltage

COVENTIONAL POWER CONVERTERS

bull Low drop‐out linear regulator (LDO)bull Switch‐inductor regulator (switching regulators)bull Switch‐capacitor regulator (charge pump)

TYPES

bull Different applicationsbull Desired efficiency and output ripple

LINEAR REGULATOR BASIC IDEA

LOW VOLTAGE LOW DROPOUT REGULATOR

The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load

bull Compared to DC‐DC switching regulators LDOs are

ndash Of continuous operation

ndash Easier to use

ndash Cheaper solution

ndash But of Lower efficiency

ISSUES OF CONCERN WITH LDO DESIGN

bull Pass transistor

1048782 load current will determine its size and thus layout

bull Error amplifier

1048782 The accuracy required by the LDO determines the magnitude of the open loop gain

1048782 Single pole architectures are recommended for better and easier stability

1048782 The amp transient requirement is dependent on the stability ie gain and phase margins There is a trade‐off in making the PM high and speed of amp This is also true for the Gain

1048782 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

COVENTIONAL POWER CONVERTERS

bull Low drop‐out linear regulator (LDO)bull Switch‐inductor regulator (switching regulators)bull Switch‐capacitor regulator (charge pump)

TYPES

bull Different applicationsbull Desired efficiency and output ripple

LINEAR REGULATOR BASIC IDEA

LOW VOLTAGE LOW DROPOUT REGULATOR

The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load

bull Compared to DC‐DC switching regulators LDOs are

ndash Of continuous operation

ndash Easier to use

ndash Cheaper solution

ndash But of Lower efficiency

ISSUES OF CONCERN WITH LDO DESIGN

bull Pass transistor

1048782 load current will determine its size and thus layout

bull Error amplifier

1048782 The accuracy required by the LDO determines the magnitude of the open loop gain

1048782 Single pole architectures are recommended for better and easier stability

1048782 The amp transient requirement is dependent on the stability ie gain and phase margins There is a trade‐off in making the PM high and speed of amp This is also true for the Gain

1048782 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

LINEAR REGULATOR BASIC IDEA

LOW VOLTAGE LOW DROPOUT REGULATOR

The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load

bull Compared to DC‐DC switching regulators LDOs are

ndash Of continuous operation

ndash Easier to use

ndash Cheaper solution

ndash But of Lower efficiency

ISSUES OF CONCERN WITH LDO DESIGN

bull Pass transistor

1048782 load current will determine its size and thus layout

bull Error amplifier

1048782 The accuracy required by the LDO determines the magnitude of the open loop gain

1048782 Single pole architectures are recommended for better and easier stability

1048782 The amp transient requirement is dependent on the stability ie gain and phase margins There is a trade‐off in making the PM high and speed of amp This is also true for the Gain

1048782 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

LOW VOLTAGE LOW DROPOUT REGULATOR

The LDO act as a variable resistor that is placed between input power source and the load in order to drop and control the voltage applied to the load

bull Compared to DC‐DC switching regulators LDOs are

ndash Of continuous operation

ndash Easier to use

ndash Cheaper solution

ndash But of Lower efficiency

ISSUES OF CONCERN WITH LDO DESIGN

bull Pass transistor

1048782 load current will determine its size and thus layout

bull Error amplifier

1048782 The accuracy required by the LDO determines the magnitude of the open loop gain

1048782 Single pole architectures are recommended for better and easier stability

1048782 The amp transient requirement is dependent on the stability ie gain and phase margins There is a trade‐off in making the PM high and speed of amp This is also true for the Gain

1048782 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

ISSUES OF CONCERN WITH LDO DESIGN

bull Pass transistor

1048782 load current will determine its size and thus layout

bull Error amplifier

1048782 The accuracy required by the LDO determines the magnitude of the open loop gain

1048782 Single pole architectures are recommended for better and easier stability

1048782 The amp transient requirement is dependent on the stability ie gain and phase margins There is a trade‐off in making the PM high and speed of amp This is also true for the Gain

1048782 Should have high PSRR

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)

bull Bandgap voltage reference

1048782 Should have high PSR

bull Stability and speed of the feedback loop

1048782 Should be assured under all load conditions

bull Choice of the capacitors and feedback resistors (Rf1 and Rf2)

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

1st HIGH PSR USING FEED FORWARD RIPPLE

CANCELLATION TECHNIQUE

MOTIVATION

Problem

ndash Supply ripples affect AnalogRF blocks

ndash Switching converter ripple frequencies are increasing

bull Solution LDO with good PSR at higher operating frequencies

bull Challenges Low drop‐out voltage low quiescent current small

area high PSR across a wide frequency range

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PSR DEGRADTION

PSR degrades at higher frequencies due tobull Finite GBW of feed‐forward amplifier (cancellation path)bull Finite closed loop bandwidthbull Finite self inductance (ESL) of off‐chip capacitor

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PROPOSED ARCHITECTUREFEED FORWARD RIPPLE CANCELLATION (FFRC) LDO

bull Main Ideandash Cancellation path replicates the ripples at gate of pass transistorndash Gate‐source overdrive voltage is free of ripple

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR

Conventional LDOs are typically implemented with at least one feedback loop which is stabilized using a huge external capacitor

LDOs is focused on removing this external capacitor while maintaining stability good transient response and high power supply rejection performance

Dominant pole

Conventional LDO Capacitor-Less LDO

Dominant pole

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO

bull Stability (light loads)bull Load Transient Responsebull Power Supply Rejection

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

CAPACITOR LESS LDO TOPOLOGIES

bull Capacitor‐less LDOs can be roughly divided into two main groups based on the number of active loops

bull Single Loop LDOs

Have at least three gain stages to increase the loop gain

bull Multiple Active Loop LDOs

Have two or more loops to enhance slew rate at the gate of the pass transistor

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

A SINGLE LOOP LDO ARCHITECTURE

Miller Compensation Architecture [Leung03]

Q‐Reduction Architecture [Lau07]

ωp1 ltlt ωp2 ωp3

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

MULTI LOOP ARCHITECTURES

1st Differentiator Architecture [Milliken07]

This topology enhances the load transient response by reducing the undershoots and overshoots

The on‐chip Miller Capacitor is reduced a lot because of the amplifier in the Differentiator path and thus saving area without sacrificing chip area

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

MULTI LOOP ARCHITECTURES (contrsquod)

2nd Minimized‐Q amp Adaptive Zero Compensation (MQampAZC)[HC Yang08 ]This topology has the advantage of being stable at very light loads (50μA)and phase margin of 60deg maintained over entiire range

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

MULTI LOOP ARCHITECTURES (contrsquod)

3rd Transimpedance LDO [JJ Chen07]This topology has the advantage of very fast response to load amp line transients

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES

PARAMETERS SPECIFICATIONS

Vref 14 V

Vin 30 V

Vout 28 V

Pass Transistor Dimensions M=2000 W=18μm and L=06μm

GBW (open loop) 500 kHz

RF1 RF2 100KΩ100KΩ

Technology 05μm

All the previously discussed capacitor‐less LDO architectures have been designed using different technology processes or with different design specificationsbull As a result it is very difficult to compare thembull To fairly compare them the following common design specifications

are used

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PERFORMANCE SUMMARY ON COMPARISION BASIS

PSR results are for IL = 50mAValue extremely low to be measured

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

OTHER TECHNIQUES

bull Other Existing Techniques

ndash RC filtering

ndash Cascading LDOs

ndash Combined RC and cascading

ndash Increasing Loop Bandwidth

bull Drawbacks

ndash Large area consumption

ndash Large dropout voltage

ndash High power consumption

All these techniques do not provide sufficient PSR at frequencies up to required ripple frequencies

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PROBLEM STATEMENT

ldquoDesign Of Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique And 90nm CMOS Technologyrdquo

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

WHY CURRENT SPLITTING TECHNIQUE

On Literature Survey Basisbull Primary switching regulators

Converts high dc voltage to low dc voltage with gt90 conversion efficiency

Generate voltage ripples to minimize switching power loss

Provide good PSR to suppress noise

The drawback of these regulators are low power efficiency highly loaded circuitshigh power consumption depends upon load

Inorder to overcome these drawbacks Current Splitting Technique with OTA-EA and Low Iq is introduce which not only provide high efficiency and low load but also minimum area and low cost

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PROJECT OBJECTIVE

To Design a Low-Voltage Low-Dropout Regulator Using Current

Splitting Technique and 90nm CMOS Technology to achieve

bull An input of 1 V and An output of 085ndash05 V

bull An Error Amplifier Current Splitting Techniquebull Load Capacitor 1μFbull Quiscent Current upto 60 μAbull Minimum Area of 00041 mm Square

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PARAMETRIC OBJECTIVE

bull Design essential operating conditions and prameters are

Technology (CMOS) 90 nm

VddVout (V) 1085 105

Load Capacitor CL (μF) 1

RESR (ohm) 1

Max IQ (μA) 60

Max IOUT (mA) 100

Current Efficiency () 9994

Load Regulation (mVmA) 028 024

Output Variation in (mA) (IOUT1 ndash IOUT2 in mA)

28(0-100)

24(0-100)

Response Time TR (μs) 028 024

PSR 100 kHz (dB) 481 gt50

Area (mm Square) 00041

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

TOOL USED

bull Cadence PSPICEbull Tanner 131

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

BLOCK DIAGRAM

Conceptual block diagram of proposed LDO regulator

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PROGRESS

Literature survey CompletedSurvey Paper writing in Progress

Simulation of an Inverter Circuit Using Tanner V 130 Tool

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

PROPOSED WORK

In this architecture not only minimize area (As Per Base Paper)

but also compact layout and calculation of power dissipation

and delay of the circuit inorder to get an efficient and stable

regulation with better performance is proposed

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

CONCLUSION

bull LDO regulator using an EA for low IQ with high PSR of ~50

dB freq range 100kHz 28-mV max output variation for a 0 ndash

100 mA load transient and a 9994 current efficiency should

be achieved

bull The feasibility of LDO regulator should be verified using

Current Splitting Technique which is also helpful in compact

area of 00041 mm square

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

FUTURE SCOPE

bull Further this can be used as compact architechture for minimum area and low Iq current applications

bull Minimum noise and Delay make this architecture a better performer

bull This minimization not only increase system efficiency and stability but also reduce the overall cost of the system

bull It can be use as best alternative for adaptive filtering

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

REFRENCES

BASE PAPER Chung-Hsun Huang Member IEEE Ying-Ting Ma and Wei-Chen Liao ldquoDeaign of a Low ndash Voltage Low ndash Dropout Regulatorrdquo IEEE J TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL 22 NO 6 JUNE 2014[1] Y-H Lee Y-Y Yang K-H Chen Y-H Lin S-J Wang K- L Zheng P-F Chen C-Y Hsieh Y-Z Ke Y-K Chen and

C-C Huang ldquoA DVS embedded system power management for high efficiency integrated SoC in UWB systemrdquo IEEE J Solid-State Circuits vol 45 no 11 pp 2227ndash2238 Nov

2010[2] M El-Nozahi A Amer J Torres K Entesari and E Sanchez-Sinencio ldquoHigh PSR low drop-out regulator with feed-forward ripple cancellation techniquerdquo IEEE J Solid- State Circuits vol 45 no 3 pp 565ndash577 Mar 2010

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

REFRENCES[3] P Hazucha T Karnik B A Bloechel C Parsons D Finan

and S Borkar ldquoArea-efficient linear regulator with ultra-fast load regulationrdquo IEEE J Solid-State Circuits vol 40 no 4 pp 993ndash940 Apr 2005

[4] M Al-Shyoukh H Lee and R Perez ldquoA transient-enhanced low- quiescent current low-dropout regulator with buffer

impedance attenuationrdquo IEEE J Solid-State Circuits vol 42 no 8 pp 1732ndash1742 Aug 2007[5] Y-H Lam and W-H Ki ldquoA 09 V 035 μm adaptively biased CMOS LDO regulator with fast transient responserdquo in Proc IEEE Int Solid- State Circuits Conf Feb 2008 pp 442ndash443 626[6] H-C Lin H-H Wu and T-Y Chang ldquoAn active- frequency

compensation scheme for CMOS low-dropout regulators with transient-response improvementrdquo IEEE Trans

Circuits Syst II Exp Briefs vol 55 no 9 pp 853ndash857 Sep 2008

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34

[7] A Garimella M W Rashid and P M Furth ldquoReverse nested miller compensation using current Buffers in a three-stage

LDOrdquo IEEE Trans Circuits Syst II Exp Briefs vol 57 no 4 pp 250ndash254 Apr 2010[8] C Chen J H Wu and Z X Wang ldquo150 mA LDO with self

adjusting frequency compensation schemerdquo Electron Lett vol 47 no 13 pp 767ndash768 Jun 2011

[9] J Hu B Hu Y Fan and M Ismail ldquoA 500 nA quiescent 100 mA maximum load CMOS low-dropout regulatorrdquo in Proc IEEE Int Conf Electron Circuits Syst Dec 2011 pp 386ndash389

[10] C Zhan and W-H Ki ldquoAn adaptively biased low-dropout regulator with transient enhancementrdquo in Proc Asia South Pacific Design Autom Conf 2011 pp 117ndash118[11] Edgar Saacutenchez-Sinencio ldquoLow Drop-Out (LDO) Linear Regulators Design Considerations and Trends for High Power Supply Rejection (PSR)rdquo IEEE Santa Clara Valley (SCV) Solid State Circuits Society February 2011

• Slide 1
• Slide 2
• POWER MANAGEMENT
• COVENTIONAL POWER CONVERTERS
• LINEAR REGULATOR BASIC IDEA
• LOW VOLTAGE LOW DROPOUT REGULATOR
• ISSUES OF CONCERN WITH LDO DESIGN
• ISSUES OF CONCERN WITH LDO DESIGN (CONTrsquoD)
• 1st HIGH PSR USING FEED FORWARD RIPPLE CANCELLATION TECHNIQUE
• PSR DEGRADTION
• PROPOSED ARCHITECTURE FEED FORWARD RIPPLE CANCELLATION (FFRC)
• 2nd CAPACITOR LESS LOW DROPOUT VOLTAGE REGULATOR
• DESIGN CONSIDERATIONS IN CAPACITOR LESS LDO
• CAPACITOR LESS LDO TOPOLOGIES
• A SINGLE LOOP LDO ARCHITECTURE
• MULTI LOOP ARCHITECTURES
• MULTI LOOP ARCHITECTURES (contrsquod)
• MULTI LOOP ARCHITECTURES (contrsquod) (2)
• COMMON DESIGN SPECIFICATIONS WITH COMPARATIVE STUDIES
• PERFORMANCE SUMMARY ON COMPARISION BASIS
• Slide 21
• Slide 22
• WHY CURRENT SPLITTING TECHNIQUE
• Slide 24
• Slide 25
• Slide 26
• Slide 27
• PROGRESS
• Slide 29
• Slide 30
• Slide 31
• Slide 32
• Slide 33
• Slide 34