development status of soi asic / fpga · the 20th microelectronics workshop @ tsukuba the design...

Development status ofSOI ASIC / FPGA

Oct. 30th 2007Oct. 30th 2007Electronic, Mechanical Components andElectronic, Mechanical Components and

Materials Engineering Group, JAXAMaterials Engineering Group, JAXAH.H.ShindouShindou

The 20th Microelectronics WorkshopThe 20th Microelectronics Workshop

1

Background

The 20th Microelectronics Workshop @ TsukubaThe 20th Microelectronics Workshop @ Tsukuba

In 2003, critical EEE parts for space use wereIn 2003, critical EEE parts for space use wereselected at the Japan space EEE parts committeeselected at the Japan space EEE parts committeein order to develop advanced space systems.in order to develop advanced space systems.

Programmable device (FPGA) was selected asProgrammable device (FPGA) was selected asone of the first phase items of critical components.one of the first phase items of critical components.

We started the feasibility study about FPGAWe started the feasibility study about FPGA

based on 0.15based on 0.15m FDm FD--SOI technology.SOI technology.

We also started the development of SEU / SETWe also started the development of SEU / SEThardened cell library for SOI ASIC.hardened cell library for SOI ASIC.

SEU: Single Event Upset SET: Single Event TransientFD-DOI: Fully depleted Silicon on Insulator FPGA: Field Programmable Gate Array

ASIC: Application Specific Integrated Circuit

2

Why we choose FD-SOI


JAXA has developed LSIswith the latest technology forcommercial market.

For <0.18m technology,SEEs are main concern forLSIs for space applications.

FD-SOI is attractive forspace because of its SEEhardness as compared withbulk technology.(also suitable for Low powerapplication.)

Now we plan to utilize the FDNow we plan to utilize the FD--SOI as a mainstream technology.SOI as a mainstream technology.SEE: Single Event Effect

Design rule trend andDesign rule trend and JAXAJAXA’’ss

LSI roadmapLSI roadmap

YearD

esig

nR

ule

(1/2

pitch)

[m

]0.01

0.1

1

1990 1995 2000 2005 2010 2015 20201990 1995 2000 2005 2010 2015 2020

0.15m, FDSOI(1.5V)

0.35m, 33MHz 64bitMPU(3.3V)

0.18m, 200MHz 64bitMPU(1.8V)

3

(Courtesy of OKI, quoted from 19MEWS material)(Courtesy of OKI, quoted from 19MEWS material)


PD-SOI vs FD-SOI

4The 20th Microelectronics Workshop @ TsukubaThe 20th Microelectronics Workshop @ Tsukuba

Oki FD-SOI Device Structure & Process

(Courtesy of OKI, quoted from 19MEWS material)(Courtesy of OKI, quoted from 19MEWS material)

- 0.15um SOI (Production line)LOCOS ⇒ STIMetal 0.52 ⇒ 0.39(1M)/0.48(<2M)BOX 200nm ⇒ 145nmLow Leakage (LL) Ioff<2E-12A/um

5

Development schedule (SOI process)


Design & Chip production/

Qualification Test

Test Element Group Chips #2

(3 & 6 Metal Layers)

ASIC Cell library / Memorygenerator


(3 Metal Layers)

Process Development for 6Metal Layers

Process Module Developmentfor 6 Metal Layers

Basic Process Development(3 Metal Layers)

Apr May JunJan Feb MarOct Nov DecJul Aug SepApr May Jun

20082007

Finalizing WLR

WLR

WP

WP

Final SPICE/PDK

WLR: Wafer LevelReliability Evaluation

WP: Wafer Processing

Evaluation

Design Cell library & evaluation chip

Design Memory generatorWP

-- Process development with 6 metal layers is in progress.Process development with 6 metal layers is in progress.-- Final SPICE/PDK is scheduled to be released at the end ofFinal SPICE/PDK is scheduled to be released at the end of

fiscal year.fiscal year.

6

700700k ASIC gatesk ASIC gates

SRAM based reSRAM based re--configurable FPGA.configurable FPGA.(Based on ATMEL architecture)(Based on ATMEL architecture)

FPGAFPGA


Target Specification for ASIC / FPGA

0.150.15μμmm commercial FDcommercial FD--SOI foundry withSOI foundry with

patented SEU/SET free primitive circuits.patented SEU/SET free primitive circuits.

(RHBD techniques used)(RHBD techniques used)

1.51.5V for core and 3.3V for I/Os.V for core and 3.3V for I/Os.

SEU/SET free up to LET of 64MeV/(mg/cmSEU/SET free up to LET of 64MeV/(mg/cm22))

TID: 1kGy(Si) (100krad(Si))TID: 1kGy(Si) (100krad(Si)) ASIC & FPGAASIC & FPGA

TID: Total Ionizing Dose LET: Liner Energy TransferRHBD: Radiation Hardened By Design

Joint development with CNES / ATMELJoint development with CNES / ATMEL


Single Event Transient signal generation

GND

Input VDDoutput

p-Substraten-Well

p+

Input VDDoutput

p-Substraten-Well

p+

GND

OutputInput

VDD

“0”

““11””

SETSET SignalSignal

CMOS/Bulk InverterCMOS/Bulk InverterCMOS/Bulk Inverter

-- ee--hh pair generation by an Ionpair generation by an Ionstrike to the OFFstrike to the OFF--state transistorstate transistor

-- Reversed biased junctionsReversed biased junctionscollect chargecollect charge

-- Voltage transients propagateVoltage transients propagateappreciable distancesappreciable distances


Advantage of SOI structure

CMOS/SOI InverterCMOS/SOI InverterCMOS/SOI Inverter

p+

Input

p-Substrate

VDD

GND

output

n+BOX(SiO2)

GND

OutputInput

VDD

GND

OutputInput

VDD -- Sensitive volume for charge collectionSensitive volume for charge collection

CMOS/Bulk > CMOS/SOICMOS/Bulk > CMOS/SOI

-- All the transistors areAll the transistors are electricallyelectricallyisolated by dielectric materialisolated by dielectric material

It is possible to eliminate the SETIt is possible to eliminate the SETsignal generation by implementingsignal generation by implementingRHBD !RHBD !


Basic concept of RHBD

A YRedundantTr Pairs

RHBD InverterRHBD Inverter(SET free)(SET free)

The redundant transistor pairs completely prevent theThe redundant transistor pairs completely prevent theSET pulse generations on the output terminal.ThisSET pulse generations on the output terminal.Thisconcept can be easily extended for any logic gates andconcept can be easily extended for any logic gates andthe logic circuits. However the optimization of area, power,the logic circuits. However the optimization of area, power,speed penalties is an important issue.speed penalties is an important issue.

10-3

10-2

0.1

1.0

0 20 40 60 80LET [MeV/(mg/cm2)]

Err

or

X-S

ection

[m

2/b

it]

対策なし(リファレンス)

対策あり(エラーなし、上限値)

10-3

10-2

0.1

1.0

10-3

10-2

0.1

1.0

0 20 40 60 800 20 40 60 80LET [MeV/(mg/cm2)]

Err

or

X-S

ection

[m

2/b

it]

対策なし(リファレンス)

対策あり(エラーなし、上限値)Ar

Kr

XeRHBD Inverter

Conventional

10

TEG evaluation


The design and evaluation (Irradiation test) of the TestThe design and evaluation (Irradiation test) of the TestElement Group are in progress.Test results will be applied toElement Group are in progress.Test results will be applied tothe design of FPGA and Cell library.the design of FPGA and Cell library.

Irradiation test system (HeavyIrradiation test system (Heavy--ion accelerator at Japan Atomic Energy Agency)ion accelerator at Japan Atomic Energy Agency)

11

Development schedule (ASIC & FPGA)


Design & Chip production/

Qualification Test


(3 & 6 Metal Layers)

ASIC Cell library / Memorygenerator


(3 Metal Layers)

Process Development for 6Metal Layers

Process Module Developmentfor 6 Metal Layers

Basic Process Development(3 Metal Layers)

Apr May JunJan Feb MarOct Nov DecJul Aug SepApr May Jun

20082007

Finalizing WLR

WLR

WP

WP

Final SPICE/PDK

WLR: Wafer LevelReliability Evaluation

WP: Wafer Processing

Test Element Group Chips #1Configuration bits / Free RAMs for FPGARAM cells, Shift registers for SET testing

Test Element Group Chips #2Core cells for FPGA

Evaluation

Design Cell library & evaluation chip

Design Memory generatorWP

development status of soi asic / fpga · the 20th microelectronics workshop @ tsukuba the design...

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