development of production pvd-aln buffer layer system and

Development of Production PVD-AlN Buffer Layer System and Processes to Reduce Epitaxy Costs and Increase

LED Efficiency

SSL MFG R&D Workshop, Boston, MA

Jun 5-6, 2013

Copyright ©2013 Veeco Instruments Inc. 2

EE0005064 - Development of Production PVD-AlN Buffer Layer System and Processes to Reduce Epitaxy Costs and Increase LED Efficiency

Organization Team Members Facilities

Veeco Instruments Frank Cerio (PI) Veeco Advanced Process Development Team Veeco Hardware/Software Engineering Team

Plainview, NY

Veeco MOCVD Systems Veeco Process Engineering Team Somerset, NJ

Technology Focus: Manufacturing Relevant Subtask Priority Area: Epitaxy and Wafer Processing Cost Reduction Substrate Cost Reduction


Background • Motivation

‒ Si can provide cost advantage and scalability for LED and power device

applications

• Issue ‒ Si reacts with Ga under

typical growth conditions Buffer layer necessary

• Solution ‒ Leverage prior experience

with PVD AlN buffer on sapphire for GaN-on Si

Si scalability

Si “meltback”

PVD AlN on sapphire

http://www.google.com/url?sa=i&source=images&cd=&cad=rja&docid=YQvPmSmlDNaK4M&tbnid=7sXqAIbrpGQnSM:&ved=0CAgQjRwwAA&url=http://www.wafercare.com/page.aspx?id=1012&ei=uh5_UbyhLq3K0gHbkIHwBg&psig=AFQjCNEuEJ8b7z4GlCTmnpn-ME4ZKG3KVQ&ust=1367371834800713


Project Objectives

• Reduction in epitaxy manufacturing costs ‒ Cost of Ownership reduction using higher throughput

PVD AlN buffer ‒ Enablement of GaN/Si processing with PVD buffer

• Three Phase, Two Year Program ‒ Phase I – Process Development – GaN on Si (Year One) ‒ Phase II - High Volume PVD AlN Buffer Tool ‒ Phase III – Manufacturability and Process Improvement


Veeco PVD AlN Buffer System • High productivity reactive sputtering system for the deposition of

aluminum nitride (AlN) buffer layer designed and developed under DOE contract

• Technique for preparation and deposition of epitaxial quality PVD AlN developed under DOE contract

• Batch PVD system • Substrate sizes from 2” to 8” • High temperature capable, >500C • Optional in-situ pre-clean capabilities

• Moiré fringe pattern and SADP confirm epitaxial growth of AlN on Si


GaN on PVD AlN Buffer Layer

AFM: 20µmx20µm RMS = 1nm

PVD AlN Buffer GaN on PVD Buffer

AFM: 5µmx5µm

RMS = 0.3nm


MOCVD GaN on PVD AlN Buffer

• Threading dislocation density from TEM images was calculated to be 7 x108/cm2

PVD AlN Buffer

Si substrate

GaN


Conclusions

• Phases I and II of two year program completed ‒ Met all tasks and major milestones

• Developed high temperature batch platform ‒ High quality epitaxial growth of PVD AlN

• Phase III tasks ongoing and on schedule ‒ Throughput improvement up to 25%

‒ Process improvement and repeatability

‒ Additional hardware evaluation for further improvements

development of production pvd-aln buffer layer system and

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