12th International Conference on DEVELOPMENT AND APPLICATION SYSTEMS, Suceava, Romania, May 15-17, 2014

978-1-4799-5094-2/14/$31.00 ©2014 IEEE

Real-Time Reconfiguration of Distributed Control System Based on Hard Petri Nets

Victor Ababii, Viorica Sudacevschi, Marin Podubnii, Irina Cojuhari Technical University of Moldova Chisinau, Republic of Moldova

ababii@mail.utm.md, svm700@mail.ru, marinpodubnii@mail.ru, irina.cojuhari@ati.utm.md

Abstract—This paper presents the design of a distributed control system based on Hardware Petri nets with real time reconfigurable architecture. The system consists of a main computer unit and a lot of homogeneous reconfigurable controllers connected to a Wireless Local Area Network (WLAN). The control algorithm is implemented into an Field Programmable Gate Array (FPGA) circuit which is configured via a microcontroller. Specialized design tools on a computer unit are responsible for the following steps: Petri net model elaboration, its analysis and validation, translation of the Petri net model into a hardware description, generation of the FPGA configuration bitstream and its transmission to reconfigurable controllers. The configured FPGA device represents a control unit, the working algorithm of which can be changed each time when it is necessary.

Keywords— control system; distributed control; reconfigurable controller; flexible process; FPGA; LAN

I. INTRODUCTION Control systems development is one of the most important

tasks in flexible manufacturing process automation. The main challenge is the use of such computer systems that allow changing of the control algorithm without major efforts, keeping the hardware structure and ensuring a satisfactory quality of the control process. In general, the control algorithm provides the generation of a sequence of control signals, defined in space and time, according to the state of the controlled process and the mathematical model that describe the process [1]. However, modern manufacturing processes, in addition to the flexibility, also presents a very high complexity and are composed of a large number of interacting devices [2].

Flexible production processes are characterized by the following basic criteria: parallelism (concurrent operation of equipment / devices) mutual synchronization of equipment / devices; periodicity of operations; conflict or competition situations [2]. These factors determine performance and quality of final products.

All mentioned criteria make the hardware and software co-design of the manufacturing control system very difficult and complex. Software implementations based on the use of Programmable Logic Controller (PLC) provide very high flexibility for control system, but their performance is not very good because of the sequential calculation of control signals

[3, 4]. Hardware implementations based on wired logic provides a very high speed data processing based on parallel computation of each control signal, but does not offer enough flexibility to the changing conditions of the controlled production process [5, 10]. A solution can be the use of reconfigurable FPGA devices for hardware implementation of control systems [6]. The control application for an FPGA device represents a highly optimized implementation that provides parallel processing with the performance and reliability benefits of dedicated hardware circuitry.

Complexity and competition of the control algorithms for flexible processes requires a preventive testing and validation to exclude all exceptional situations that may occur in the operation. Various techniques and methods were developed for modeling and validation. The use of Petri nets for these purposes has proved very worthwhile [7].

Petri nets are mathematically well founded and can be used to capture causality relations, concurrency of actions and conflicting conditions from digital systems in a natural and convenient way. It is possible to translate Petri nets to Hardware Description Language (HDL), and vice versa, that allows the integration of Petri nets tools into existing design environments.

Implementation methods of Petri nets can be classified into two types: software and hardware. Software implementation represents the emulation of Petri nets using computer software, which usually takes long time. It is widely used in modeling and performance evaluation problems. Hardware implementation of Petri nets is done especially into FPGA circuits. The advantage of FPGA technology is that the interconnection patterns inherent in the Petri net structural description can be very flexibly mapped to the FPGA structure. The possibility of a run-time reconfiguration allows the use of adoptive algorithms that can reduce the time that is necessary for Petri Net simulation. Hardware implementation methods of Petri nets can be divided into direct translation methods and logic synthesis methods. Logic synthesis methods often suffer from the state explosion problem because most modern systems are typically modeled as concurrent systems. Direct translation methods guarantee an implementation by construction. The size of the obtained circuits is linear on the size of the specification.

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The main advantages of a wireless solution are the following: greater mobility and possibility to move devices, bypassing long distances and areas where cables cannot physically fit, fast and easy installation, easy integration of devices into the network, etc.

In this work we have developed a method which allows the design of a distributed control system which consists of a set of reconfigurable controllers implemented into FPGA circuits. The configuration of each FPGA circuit is done wireless in accordance with the Hardware Petri Net (HPN) model which is converted to a bitstream using a direct translation approach. The proposed method allows the real time reconfiguration of the controllers just by changing the HPN. The proposed method can be used for flexible manufacturing control systems design.

The organization of this paper is as follows; in Section II, we describe the control system architecture; in Section III the sequence diagram of a control system design is presented; section IV describes the design example. Finally, in section V, we present the main conclusions and future directions of research.

II. CONTROL SYSTEM STRUCTURE The structure of the real-time reconfigurable distributed

control system based on Hardware Petri Nets is shown in Figure 1.

1p Np

VPNP,PC HPNC,

QuartusII

Fig. 1. Control system structure.

The control system represents a distributed architecture and includes the following components: the computer PC and a set of reconfigurable controllers RC , 1,iRC i N , connected

to WLAN. Reconfigurable controllers RC are homogeneous devices distributed in controlled process space. The manufacturing process consists of a set of sub-processes

1P

N

ii

P

. Each sub-process Pi has an attached controller RCi..

The reconfigurable controller is connected to the network through Ethernet Network Controller (ENC) interface device (model ENC28J60). It also contains a microcontroller MCU (ATmega328), EEPROM memory (model AT25F4096) and FPGA device (Altera Cyclone IV, EP4CE22F17C6N circuit).

The Petri net model synthesis, analyzing and simulation are done in Visual Petri Net + environment (VPNP) [8]. The behavioral analysis determines the main properties of the model such as its reachability, liveness and reversibility. In the result, an XML code of the Petri net model is obtained. According to this code HPN model is generated. This model is translated to an AHDL code (HPNC software tool, [6, 9, 10]). This code is executed and simulated using Quartus II design tool. Finally, the FPGA configuration bitstream is generated.

Reconfigurable controllers RC , 1,iRC i N are

homogeneous devices with the following electrical schematic diagram (Figure 2):

Fig. 2. Electrical schematic diagram of a reconfigurable controller.

Reconfigurable controller RCi consists of an FPGA circuit that controls sub-processes

iP i N, 1, ; EEPROM memory (U1) that stores the FPGA configuration bitstream; microcontroller (U2) that manages the FPGA configuration and the interface circuit (U3) that connects reconfigurable controller to network.

The FPGA circuit configuration is managed by the computer which sends to each reconfigurable controller the generated binary code with all commands and data that are necessary to start the FPGA design. The reconfigurable controller selection is made by ENC interface according to IP address of the target FPGA device.

The interface circuit which is connected to LAN, receives data from the computer using TCP/IP protocol. Data packets are sent to the microcontroller MCU which selects FPGA

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configuration information and saves it in EEPROM memory. Finally, each FPGA circuit is configured according to its own bitstream.

The communication between the reconfigurable controller components, namely FPGA, ENC, MCU and EEPROM is done via Serial Peripheral Interface (SPI) protocol.

The reverse data send, from the reconfigurable controller to the computer, is done in the following way: the microcontroller receives data from the selected FPGA circuit, packs them according to TCP/IP protocol and sends to the computer via interface circuit ENC.

III. SEQUENCE DIAGRAM Sequence diagram (Figure 3) shows the interaction between

the main components and the sequence of operations for real-time reconfigurable control system design.

Fig. 3. Sequence diagram.

The control unit design starts with Petri net model (PNM) synthesis, simulation and performance analysis in VPNP tool. As a result of these operations, a set of XML files ( iFile XML i NFile.XML . , 1, ) are generated. These files

contain the control algorithms descriptions.

The next step is XML to AHDL conversion, using HPNC software tool. The resulted files

iFile AHDL i NFile.AHDL . , 1, are edited and compiled

in Quartus II design software tool. The FPGA configuration bitstreams are contained in iFile sof i NFile.sof . , 1, files.

They are sent to reconfigurable controllers iRC . Finally, FPGA

circuits are configured via Programmer .

Process Control and New Algorithm for Process Control execute the old control algorithm and the new one, respectively.

The eventual changes to the control algorithm can be done by generating new Petri net models and repeating the above operations.

IV. DESIGN EXAMPLE A Petri net model for distributed control system design is

presented in Figure 4. The Petri net model includes three basic building units: the unit for flexible process modeling (Process Continuous Model) defined by the set of sub-processes

iP i, 1,4 , unit for behavioral modeling of the control algorithm (Control System Model), defined by the set of reconfigurable controllers

iRC , shown in Figure 4 as FPGA circuits, unit for process synchronization (Synchronization Model).

Fig. 4. Example of Petri Net Model for synthesis of distributed control system based on HPN.

Petri net model was analyzed in VPNP tool and an AHDL code was generated in HPNC tool. A part of the resulted AHDL code is shown below. This code is used for FPGA 1 device configuration.

include "p_obj.inc"; include "t_obj.inc"; \ subdesign das_2014_xml( clock, set, reset : input; P9_In : Input; P1_Out : Output;) Variable P1 : P_Obj; P9 : P_Obj; P10 : P_Obj; P11 : P_Obj; T5 : T_Obj; T6 : T_Obj; T8 : T_Obj; Begin P1.Set = Set; P9.Reset = Reset; P10.Set = Set; P11.Set = Set; T5.Reset = Reset; T6.Reset = Reset; T8.Reset = Reset; P1.Clk = Clock; P9.Clk = Clock; P10.Clk = Clock; P11.Clk = Clock; T5.Clk = !Clock; T6.Clk = !Clock; T8.Clk = !Clock; P9.Pinc0=P9_In; P1_Out=P1.Pout; P1.Pinc1=T8.Tout;

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P9.Pinc1=T5.Tout; P10.Pinc1=T6.Tout; T5.Tin0=P1.Pout; T6.Tin0=P9.Pout; T8.Tin0=P10.Pout; T8.Tin1=P11.Pout; P1.Pdec0=T5.Tout; P9.Pdec0=T6.Tout; P10.Pdec0=T8.Tout; P11.Pdec0=T8.Tout; end; The AHDL code, obtained in HPNC tool after Petri net

model compilation, contains two types of objects for behavioral description of the main components of a Petri net: position P (p_obj.inc) and transition T (t_obj.inc). Actually, the code represents the interconnection of these objects according to the initial Petri net model. Position P9_In is the input of the control circuit; its value depends on the current state of the manufacturing sub-process. Position P1_Out is the output of the control circuit and represents the control signal that will be sent to the process.

The simulation results presented in Figure 5 confirm that the control circuit works properly.

Fig. 5. Simulation results.

V. CONCLUSIONS FPGA-based control systems are widely used in industry

because they provide parallel processing, high performance and reliability. Real-time reconfiguration of FPGA circuits offers a possibility of their use in flexible manufacturing control systems.

In this paper a method for distributed control system design based on Hardware Petri Nets that is implemented into FPGA devices is proposed. The control system consists of a main computer and reconfigurable controllers connected to a WLAN. The control algorithm is implemented into an FPGA circuit which is configured using a microcontroller. The control algorithm is obtained after a direct translation of a Petri net model into a hardware description.

The proposed method was verified using a simple design example, for which data transmission, EEPROM loading and FPGA configuration were tested.

The next stage in our research provides the analyzing of reliability and performance parameters of control systems depending on their complexity.

ACKNOWLEDGMENTS The researchers conducted in this paper are part of the

11.817.08.55A project "Advanced methods and technologies for design and development of reconfigurable computing applications", Department of Scientific Investigation and Technologic Development, Technical University of Moldova.

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