Designing a Broadband Cherry Hooper BJT amplifier for the 30-50 GHz range

Pragoti Pran Bora, Paola Vega-Castillo, and Wolfgang Krautschneider

Institute of Nanoelectronics and Medical Electronics, Technische Universität Hamburg-Harburg Email: pragoti.bora@emft.fraunhofer.de, pvega@ietec.org, krautschneider@tuhh.de

Abstract —We present the design of a broadband amplifier to be integrated in a cell impedance measurement system for carrying out impedance measurements in the frequency range of 30-50 GHz. The amplifier is designed in a 130 nm SiGe:C HBT with a maximum transit frequency of 250 GHz and a maximum oscillation frequency of 300 GHz. To attain the wide frequency range of operation, the proposed design features two Cherry-Hooper gain stages, followed by two pairs of cascaded emitter followers as output buffer. Simulations show that the amplifier provides a gain of 20 dB in 30-44 GHz range with a band pass upper cut frequency of 50 GHz, and consumes a DC power of 125.1 mW operating at a supply voltage of 3.3 V.

Index Terms – Broadband amplifier, Cherry Hopper Amplifier.

I. INTRODUCTION

Broadband amplifiers need to provide a relatively constant gain and a linear phase response in the frequency range of interest. However, to keep their power consumption at low levels, while achieving all these requirements, is a challenge. One alternative for implementing broadband amplification in a compact circuit is the use of a Cherry Hooper configuration [1]. This configuration circumvents the limitations of the conventional common emitter stages by attaining negligible interaction between the building blocks of the amplifier. This is achieved by grouping two stages, namely a transconductance stage and a transadmittance stage, which have large impedance mismatch between them. We present a broadband amplifier based on Cherry-Hopper gain stages intended for high frequency impedance spectroscopy.

II. PROPOSED AMPLIFIER

The proposed broadband amplifier design is fully differential with three stages: two gain stages followed by an output buffer. Each of these stages is AC-coupled with each other using coupling capacitors at their inputs to maintain good dynamic range at the input and the output without affecting the gain in the frequency range of interest. The gain stages are essentially two cascaded modified Cherry-Hooper amplifiers [2] which provide the required gain and bandwidth, followed by an output buffer. Both stages are presented in Fig. 1. The output buffer consists of a pair of cascaded emitter followers to achieve impedance transformation and a large current gain. This also reduces the interaction between the gain stages from the output loads, which are Gilbert mixers for the intended application of this amplifier. This allows the frequency dependent gain and output impedance of the modified Cherry-Hooper amplifier to remain unaffected by the loads in the frequency range of 30-50 GHz.

Fig. 1: a) Cherry-Hopper gain stage, b) Output buffer stage. Resistor values in Ohms, emitter count is specified when different from 1 or 2.

The DC gain of the gain stage is directly proportional to the transconductance of transistor Q1, the feedback resistance Rf and the ratio between the resistances R2 and R1. The peaking introduced to increase the gain of the gain stage in the 30-50GHz frequency range is expressed in terms of the quality factor Q, which is directly proportional to R1 and inversely proportional to Rf and the base-emitter capacitance Cπ2 of transistor Q2. The peaking frequency ωn is directly proportional to the transconductance of transistor Q2, which can be controlled by the bias current IEE2. The gain, ωn and Q can be controlled by the values of Rf, R2/R1, IEE1 and IEE2. The pole frequency and the quality factor could be increased by increasing IEE2, by decreasing Rf or by decreasing R2/R1. The first option was ruled out because that would require an increase in the number of emitters for each of the transistors and wider interconnects to accommodate the increased amount of current. If Rf is decreased, the gain would be significantly affected. Therefore, R2/R1 was decreased by increasing the value of R1 without affecting the output swing.

III. POSTLAYOUT SIMULATION RESULTS

The post-layout simulation results of Fig. 2 show that the performance of the designed broadband amplifier is close to the target specifications. It provides a relatively constant gain of 20 dB from 30 GHz to 44 GHz and the pass band upper cut frequency is 52 GHz. Power consumption is 125.1 mW. The group delay distortion of the amplifier is 0.37 ns. Since the intended application of this amplifier involves only monotone signals, group delay is not one of main design criteria. The complete amplifier core area is 138.26 µm x 140.44 µm. Table I presents a comparison between the proposed design and similar reported broadband amplifiers. For bandwidth calculation, we have considered the frequency range starting at 30GHz, which yields 20dB gain, and ending when this gain drops 3dB (50GHz). Table I shows that the proposed design can achieve a good amount of gain and fair bandwidth with relatively low power and area consumption. Although the bandwidth is lower than that of the other designs, it is important to remind that the amplifier presented in this work is intended for operation in the 30-50 GHz range and fulfils the requirements of the impedance measurement application.

Fig. 2: Postlayout simulation results of the broadband amplifier a) from 1Hz to 100GHz, b) zoomed from 3 to 50GHz

TABLE I. COMPARISON OF BROADBAND AMPLIFIERS

Design Technology Bandwidth (GHz) Gain (dB) Power (mW) Cherry-Hooper with inductive load [3] 130nm SiGe HBT 62 5 125 Differential [4] 350nm SiGe HBT 32.5 32 120 Single-ended distributed [5] 120nm SOI CMOS 90 11 210 Differential [6] 120nm SiGe BiCMOS 102 10 125 Differential buffered cascade [7] 180nm SiGe HBT >80 20 990 This work 130nm SiGe HBT 20 20 125.1

REFERENCES

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