Design TWGDesign TWG

2000 Update2000 Update

Plans for 2001Plans for 2001

Hsinchu, TaiwanHsinchu, Taiwan

December 2000December 2000

Role of Design in ITRSRole of Design in ITRS Before 1999

– Focused on hardware design and test: tool issues and technologies– Detached from rest of Roadmap

1999– Highlighted SOC trends and requirements– Better integration, interaction with other ITWGs

2001 and beyond– Much more involvement in crosscut issues with other ITWGs

E.g., panel on interconnect systems and optimization; chip size; cost; ... Bidirectional interactions with other ITWGs

– Consideration of new and important areas: Applications Architectures Optimized uses of process technology Analog/mixed signal and other technologies

– More quantitative data/metrics/cost issues

Functionality + Testability

Functionality + Testability + Wire Delay

Functionality + Testability + Wire Delay + Power Mgmt

Functionality + Testability + Wire Delay + Power Mgmt +Embedded software

Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity

Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips

Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF

Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF + Packaging

Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF + Packaging + Mgmt of Physical Limits

1 K

1 Billion

# T

ran

sist

ors

Exponentially growing number of devices

Design complexity is exponential function of device count

Superexponential Design ComplexitySuperexponential Design Complexity

* @ $150K / Staff Yr. (In 1997 Dollars)

Potential Design Complexity and Designer Productivity

1

10

100

1,000

10,000

100,000

1,000,000

198

1

198

3

198

5

198

7

198

9

199

1

199

3

199

5

199

7

199

9

200

1

200

3

200

5

200

7

200

9 10

100

10,000

100,000

100,000,000

Logic Tr./ChipTr./S.M.

Year Technology Chip Complexity Frequency Staff Staff Cost*

1997

1998

1999

2002

250 nm

250 nm

180 nm

130 nm

13 M Tr.

20 M Tr.

32 M Tr.

130 M Tr.

400

500

600

800

90 M

120 M

160 M

360 M

210

270

360

800

3 Yr. Design

xxx

xxx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Equivalent Added Complexity

Design Productivity CrisisDesign Productivity Crisis

Issues in IC Design

New Figure 4 (Draft Rev. B, 3-12-99)

SYSTEM DESIGN

SUBSYSTEM DESIGN

CIRCUIT DESIGN

PHYSICAL DESIGN

MANUFACTURE INTERFACE

Design

Test

SW designPartitioningFunctional mapping

Test architecture

Logic optimizationTechnology mapping

Test logic insertion

Analog andmacro designExtraction

Test modelgeneration

DetailedplacementDetailedrouting

Patterngeneration & merge

Chip test &diagnostics

Floorplanning

Mask correctionYield optimizationSorting

Red denotes most challenging activity

Analysis PerformancemodelingPowerestimation

Powerestimation

Power, noiseanalysisSignal integrity

Powerdistributionanalysis

N/A

VerificationSystemsimulation

Functionalsimulation

Circuit simulation

LVS/DRCFormal checking

N/A

Static timing verification

Equivalence checking

Spec Xtrs MasksRTL/code Gates/Cells Chip

Yesterday 1000nm Today 180nm Tomorrow 50nm

Required Advance in Design System Architecture

FunctionalPerformance

TestabilityVerification

SPEC

Hw/Sw

SWLogicCircuitPlaceWireother

Perf.TimingPowerNoiseTestMfg.other

Repository

Hw/SwData

Model

Optimize AnalyzeComm.

Cockpit

Auto-Pilot

EQ

ch

eck

MASKS

System Design

System Model

Perf.Model

System Design

System Model

File

Synthesis+ Timing Analysis+ Placement Opt

File

Place/Wire+ Timing Analysis

+ Logic Opt

SW Opt

PerformanceTestabilityVerification

FunctionalVerification

MASKS

RTLSW

Equ

ival

ence

che

ckin

g

Hw/SwOptimization

Multiple design files are converged into one efficient Data ModelDisk accesses are eliminated in critical methodology loopsVerification of Function, Performance, Testability and other design criteria all move to earlier, higher levels of abstraction followed by

equivalence checking andassertion driven design optimizations

Industry Standard interfaces for data access and controlIncremental modular tools for optimization and analysis

Logic Design

Software Design

FunctionalVerification

PerformanceVerificationFile

Timing Analysis

File

Place/Wire

File

Synthesis

File

Timing Analysis

RTL

MASKS

System Design

TestabilityVerification New Table 8

The Need for Built-In Self-TestThe Need for Built-In Self-Test

Chip boundary cannot support needed data volumes without increasing test time (20x - 100x!!)

0

20

40

60

80

100

120

1995 2000 2005 2010 2015

rela

tive

te

st

tim

e

roadmap pincount

constant pincount

Model for SOC DesignModel for SOC Design (a reasonable scenario)(a reasonable scenario)

Design effort = constant (small design team, short time to product)

New design productivity (logic) : + 30%/yr

(Reuse design productivity) = (New design productivity) / 2

Chip size is up to 1 cm2

Result: up to 94 % of die occupied by memory, or smaller die

A Scenario for SoC Design ProductivityA Scenario for SoC Design Productivity

Year 1999 2002 2005 2008 2011 2014Node 180 nm 130 nm 100 nm 70 nm 50 nm 35 nm

% Area New Logic 64% 32% 16% 8% 4% 2%% Area Reused Logic 16% 16% 13% 9% 6% 4%% Area Memory 20% 52% 71% 83% 90% 94%Transistor Logic Density (Mtrans/cm2) 20 54 133 328 811 2000New Logic Productivity (Mtrans/PY) 1.4 2.1 2.9 4.2 6.0 8.6Reused Logic Productivity (Mtrans/PY) 2.9 4.1 5.9 8.4 12.0 17.1Target Design Resource (PY) 10.0 10.5 10.1 9.9 9.7 9.6

0%

20%

40%

60%

80%

100%

1999

2002

2005

2008

2011

2014

% Area Memory

% Area ReusedLogic

% Area New Logic

Scenario: major increase in SOC memory content forced by insufficient design, reuse productivity increases

(Japan) ITRS meeting, San Francisco, 2000

A Scenario for SoC Design ProductivityA Scenario for SoC Design Productivity

SOC Low PowerSOC Low Power

0.1

1

10

100

1999 2002 2005 2011

size process voltage frequency total

0.01

0.1

1

10

100

1999 2002 2005 2011

size process volatage frequency total

Total Power Trend withNo Low Power Solution

Total Power Trend withLow Power Solution Scenarioto keep 3W

ITRS, meeting in Leuven

Goal: “Living Roadmap”Goal: “Living Roadmap”

Transparent, self-consistent Roadmap– Documentation of “algorithmic” relationships within, between

different parts of the Roadmap– Some relationships or derivations inherently difficult to capture, e.g.,

Max Litho Field Size derivation -- but these can be “hard-wired”

Sanity checks (e.g., cost or power), “which rule does not belong” checks, etc.

Easier calibration, adjustment to actual design or technology data points

Initial focus: ORTCs

Interactions with other ITWGs, panels (chip size, etc.)

Living Roadmap FrameworkLiving Roadmap Framework GSRC Technology Extrapolation (GTX) Engine

http://vlsicad.cs.ucla.edu/GSRC/GTX

Open source, allows flexible capture and study of impact of modeling choices, optimization constraints

System Drivers (SoC) Chapter ProposalSystem Drivers (SoC) Chapter Proposal Proposal: Evolve from SoC Chapter in 1999 ITRS

Rationale– “SOC” is too specific; ITRS should not perpetually contain such a chapter– Terms such as ASIC, MPU (with all their flavors) are not well-defined in the

ITRS front material– Should set context: “what is consuming the silicon?” with as concrete

definitions as possible (replace SoC chapter)

Four driver classes (proposed starting point)– Analog/RF/MEMS– ASIC = compiled HDL gates – High-volume custom = P, DSP, embedded memories, reprogrammable– SoC = high integration, low cost, low TTM

Design, PIDS, Interconnect, Test, Packaging, other TWGs

Under consideration by IRC

Design Chapter Organization - ProposalDesign Chapter Organization - Proposal

Five areas of Design Design Process

Infrastructure, design process metrics, … System-Level Design

Designing the system Infrastructure for design IP reuse

Functional Verification System-level, RT-level, …

Logical-Physical-Circuits Circuits includes “DSM effects”, hard-IP

reuse/migration, etc. Test

Design ITWG Schedule Design ITWG Schedule (Tentative)(Tentative)

US Design DTWG - initial draft responsibility

US Design TWG (with Test representation) met November 5

Design ITWG - meeting December 12 IEDM

US Design DTWG - teleconference December 13

First drafts of new text - January 31

Meeting (ITWG, DTWG) in February

Cross-TWG RepresentativesCross-TWG Representatives

Test Tim Cheng

Interconnect Dennis Sylvester

Assembly & Packaging Dennis Sylvester

Lithography Andrew Kahng

Global Interconnect WG Peter Bannon

Chip Size WG Andrew Kahng

Frequency/Power lines Mark Horowitz

Layout Density Rich Howard

Pkg Pins/Balls Sylvester/Kahng

The Roadmap Ahead . . .The Roadmap Ahead . . .

Heights to which technology can take us

Slipperyslope if we’re not careful

The votes have been counted.Again and again.It’s time to start the transition to

the 2001 ITRS.

I support the rule of law

(Moore’s Law, that is). Let’s count every dimple on the wafer (on selected chips).