Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon

Vladimir ZivkovicNational Institute for Subatomic

PhysicsAmsterdam, the NetherlandsMicroelectronics User Group (MUG) meeting

Topical Workshop on Electronics for Particle Physics (TWEPP) 2011Vienna, September 27th 2011

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2011

FEI4-A Architecture and Design Foundations

• Radiation hardness out of the box• Good power distribution

• Essential when making the long columns• Substrate isolation (T3)

• Essential when using standard cell synthesized logic

Innovations- Region architecture (memory on pixel)- Modular approach and distributed design

- Low current operation, fault tolerance, digital and mixed-signal Test Benches for Simulation

Multi-site collaboration -> design repository necessary (SOS Cliosoft platform)

vv 8M 130 nm CMOS

3-2-3 Stack

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2011

Layout Foundation

Isolated NMOS / PMOS

T3 isolates the switching activity of digital circuits from the substrate and other blocks- very convenient for modular (core) – based designs

DM option chosen over LM for :• More flexibility to provide good power distribution (low resistivity M8 and M7)• Good shielding (M7 is less resistive, so M8 can be sacrificed to provide for a

solid shield)• Good for inter-block routing (low RC)• Full MOSIS support

Mind: local routing restricted to 3 metal layers due to bad local high density routing

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2011

Standard Cell Library – ARM

• Fully characterized and qualified, low-power version also available, as well as SEU-resistant

• Extensive use of inherited connections– Some problems during delivery exchange experienced there due to the non-

uniform distribution of the library

• All digital blocks placed in T3-isolated pwells

• A stable substrate (under T3 isolation) is guaranteed by enforcing a maximum distance of 100 μm between substrate contacts

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Design RepositorySOS design repository from cliosoft.com Repository hosted at LBNL and mirrored at all other sites

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Design Flow for FEI4 at NIKHEF (digital)

• RTL creation with Verilog (no VHDL!)• Two-pass mapped flow for synthesis and DfT

– Synopsys Design and DfT Compiler, Version B-2008.09-SP2 for linux

• Placement and Routing– Cadence Encounter Digital Implementation (EDI) 9.1 – Cadence SoC Encounter v07.10-s219_1 (reference, backup)

• Physical Netlist Verification and Sign-off– Statistical Timing Analysis (STA) with .spef, Synopys PrimeTime, Version B-

2008.09-SP2 for linux

• Physical Verification– Virtuoso 6.1.3 _> 6.1.4 Open Access– DRC, LVS, netlist extraction with parasitics with Calibre 2009.3_32.2

• ATPG – Synopsys TetraMAX ATPG, Version B-2008.09-SP2 for linux

• Simulations– Cadence NcSim 8.2 -> NcSim 9.2

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Readout Core Modification• Layout boundary fixed• Pin positions fixed• Timing constraints the same• 15% larger design had still to be fit in

Design Flow going back and fourth between Synopsys and Cadence

Top-level integration issues

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2011

Design Flow for FEI4 at NIKHEF (analog)

• Schematic capture, layout creation– Virtuoso 6.1.3

• Simulations– MMSIM 7.0

• Physical Verification– DRC

– Assura 3.1.7 OA (easy to use, primary)– Calibre 2009.3_32.2 (final)

– LVS – Assura 3.1.7 OA– Calibre 2009.3_32.2

• Extraction – QRC EXT 7.12

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Design Verification Efforts• Standalone block simulations with extracted parasitics • Open Verification Methodology Environment (OVM)

– This means that the real life commands/functions are converted into the testbench.

• Digital full chip simulations• Parasitic capacitances, process

variations, interconnect delays included• Digital (block interconnect) extraction

using Assura black-box approach

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2011

Mixed-Signal Top-level TestbenchAnalog/Mixed-signal functionality check from the top-level

Model driven test & verification development

IC model

Loadboard & instrument model

Test description

Each hardware component can be modeled at arbitrary level of abstraction

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ATPG and Test Assembly Flow

DIB Integration

WaveForm {

Pin = rzClocks;

Drive = RZ, t1, t2;

}

WaveForm {Pin = outputs;Expect = SB, t1, t2;

}

WaveForm {

Pin = inputs;

Drive = NR, tdel;

}

tdel

vector

waveform

tdel

t

period

t1

vector

waveform

t2

t

period

t1

vector

waveform

t2

t

period

t1 t2

Timing TetraMax

ATPG

STILvectors

test bench

NCsim

DfT

Protocols

test lib

Physical netlist

ATPG constraints