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2.1 The Xilinx XC4000 Series Design Process 1

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THE ECE 554 XILINX DESIGN

PROCESS

Design Process Overview

Design References

Xilinx Libraries

Design Tutorial

Whats Next

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Design Process Steps Definition of System Requirements

Example: ISA (Instruction Set Architecture) for CPU

Includes software and hardware interfaces includingtiming.

May also include cost, speed, reliability andmaintainability specifications

Definition of System Architecture

Example: High-level HDL (Hardware Description

Language) representation - this is not required inECE 554 but is done in the real world)

Useful for system validation and verification and as abasis for lower level design execution and validationor verification.

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Design Process Steps(Continued)

Refinement of System Architecture

In manual design, descent in hierarchy, designingincreasingly lower-level components

In synthesized design, transformation of high-levelHDL to synthesizable register transfer level (RTL)HDL

Logic Design or Synthesis

In manual or synthesized design, development of logicdesign in terms of library components

Result is logic level schematic or netlist representationor combinations of both.

Both manual design or synthesis typically involveoptimization of cost, area, or delay.

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Design Process Steps (Continued)

Implementation

Conversion of the logic design to physical

implementation

Involves the processes of:

mapping of logic to physical elements,

placing of resulting physical elements,

and routing of interconnections between the elements.

In case of SRAM-based FPGAs, represented by theprogramming bitstream which generates the physical

implementation in the form of CLBs, IOBs and the

interconnections between them

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2.1 The Xilinx XC4000 Series Design Process 5

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Xilinx HDL/Core Design Flow

- HDL Functional Simulation

Compile HDL Files

Waveformsor List Files

Set Up and Mapwork library

RTL HDL Files

Test Inputs orForce Files

HDL instantiationmodule forcore_name

EDIF netlists forcore_names

Functional Simulate

Testbench HDLFiles

MODELSIM

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Gate/Primitive NetlistFiles (EDIF or XNF)

Xilinx HDL Design Flow- Synthesis

Select Top Level

Select Target Device

Edit FPGA ExpressSynthesis Constraints

Synthesize

All HDL Files

Synthesis/Implement-ation Constraints

Synthesis ReportFiles

EDIF netlists forcore_names

FPGAEXPRESS

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Model Extraction

Xilinx HDL/Core Design Flow -

Implementation

NetlistTranslation

Map

Place &Route

BIT File

CreateBitstream

Timing Model Gen

Gate/Primitive NetlistFiles (XNF or EDN)

Standard DelayFormat File

HDL or EDIF forImplemented Design

XILINX DESIGNMANAGER

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Xilinx HDL/Core Design Flow- Timing Simulation

Test Inputs,

Force Files

MODELSIM

Compile HDL Files

Waveformsor List Files

Set Up and Mapwork Directory

Compiled HDL

HDL Simulate

Standard Delay Format FileHDL or EDIF forImplemented Design

Testbench HDL Files

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2.1 The Xilinx XC4000 Series Design Process 8

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Manuals On-Line Using dtext Viewer (Docsan) - Forprinting, download zipped pdf files. Go to:

http://toolbox.xilinx.com/docsan/3_1i/

The following guides are occasionally useful, but far lessfrequently: Design Manager/Flow Engine Guide

Development System Reference Guide 3.1i

Timing Analyzer Guide 3.1i

Foundation Series 3.1i Quick Start Guide

Foundation Series 2.1i User Guide

FPGA Compiler II/FPGA Express VHDL Reference Manual 3.1i

Databook, App. Notes, and Answers database On-Line at:

http://support.xilinx.com/support/support.htm

Design References (Continued)

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The Xilinx Libraries Useful only if you have to instantiate (in your

HDL) Xilinx primitives or macros (not all can

be instantiated) from the Libraries Guide 3.1i

Note selection guide includes CLB counts and

section at front on notation used to describe

macros.

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2.1 The Xilinx XC4000 Series Design Process 9

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Design Practices

Use Synchronous Design

CLBs are actually reading functions from SRAM!

Avoid Clock Gating

Avoid Ripple Counters

Avoid Use of Direct Sets and Resets except for

initialization

Synchronize asynchronous signals as needed.

Study Timing Issues handout

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Whats Next

Verilog HDL Introductory lecture next

week will give an overview of Verilog, our

HDL language of choice

HDL/Core Design Flow Design tutorial

next week will employ the flow described

for a Verilog HDL/core example