Design Review

AVI1005 A1

Sean Wang2010/10/21

1. Driver FET floor plans and layout sizes2. Bias Circuit Analysis with Equation3. Comparator Offset Analysis & Sensitivity to Tail Current4. Condition to Cause Initial Latch Problem & Solutions5. Hystersis Comparator to Replace Latch?6. Chip simulation results (open-loop simulation)7. Rbias, Raout Determine VDS (Derive Equation)8. Loss of Power MOSFET9. Meas System, in Particular Base Noise

Item

1. Driver FET floor plans and layout sizes820 um

1000 um1000 um

780 um

180um x 250um85um x 245um

Pre-DriverGATE

Vcc

PGND

Iso-Asy-NMOS Asy-PMOS

Floor Plan

2. Bias Circuit Analysis with Equation

22

1

2

1

22

2

R

VV

R

IV

R

V

R

VI vovt

tGSB

1121min, RIVVV GSGSDD

)/()]1

([ 2111122

22 RgmRRgmRgm

RgmVV mnmn

mn

mnVDDVDD

VDDVIf VDD Variation

2R

VVDD

3.1 Comparator Offset Analysis & Sensitivity to Tail Current

IMPD1

IMPD2

VSP1

VOUT

VNVP

2

4,32,1

2,12,12,1

2

2,1

4,32,2

2

2,1

2,12,122,1

2

mncmncpmp

pcpcmncmncpcpcm

pdmpd

ncncncncm

pdpdm

ncncncncmpdpd gg

Vthgg

g

Vthg

g

VthgVthoffrdn

MLW

AVth vt

3.2 Comparator Offset Analysis & Sensitivity to Tail Current

IMPD1

IMPD2

VSP1

VOUT

VNVP

Origin (nS) Improve (nS)T_Rise_ comp 6.87 6.52T_Fall_ comp 6.94 5.49ppg_r_comp 56.98 49.09ppg_f_comp 126.70 18.20ppg_r_totall 282.40 145.10 ppg_f_totall 106.20 119.80

4.1 Condition to Cause Initial Latch Problem & Solutions

Rising time is too slow

A. 假如使用 Latch的方式，則在上述情況下，會發生 Initial Latch的情形Problem

4.2 Condition to Cause Initial Latch Problem & Solutions

A. 讓 AOUT 的 Rising Time加快B. 設計電源進來時產生 Blanking Time，時間內不判斷 Aout訊號，並導通 POWERMOS

Solution

Use for Blanking

Use for improve rising time

High Side : PMOS

5. Hystersis Comparator to Replace Latch?

A. 考慮 Drain電壓在 DCM T3時會造成 Ringing，使得 AOUT = Vdrain x gm x Raout AOUT變化過大，因此使用 Hysister無法解決此現象B. 可考慮使用 Latch 或 Blanking的方式，解決此問題

6. Chip simulation results (open-loop simulation)Zoon In

VDRAIN dc 0.1V

7.1 Rext, Rint Determine VDS (Derive Equation)

TDRB

TQB

TQBC

TQB

TQBC

TBE

TQBE

TQBC

VVV

VV

ext

QBCC

QE

DRonoutQC

VV

VV

ext

QBCC

QE

VV

VVQE

QE

VVS

VVS

QE

QE

QEext

QBCC

extQECCQB

e

eR

VV

I

VRIVe

eR

VV

I

e

eII

eI

eI

I

I

IR

VV

RIVV

/

/1,

2,

1,

/

/1,

2,

/

/1,

2,

/

/

2,

1,

1,1,

1,1,

1

1,

1,

1,

1,

2

2,

1,

mvV

kRVvVVif

Re

eR

VV

V

DR

CCQBBE

INTVVV

VV

ext

QBCC

CC TDRQB

TQB

97.8

10 ,12V ,0.7 3

2

2,

/)(

/1,

1,

1,

8.1 Loss of Power MOSFET

8.2 Loss of Power MOSFET