FACULTY OF ENGINEERING

FACULTY OF ENGINEERING & TECHNOLOGY

MULTIMEDIA UNIVERSITY

DESIGN PROJECT HANDOUT

INTEGRATED VLSI SYSTEMS

EEE 3196

TRIMESTER 2 (2014/2015)

VLSI1: Schematic Design Entry, Simulation & Verification

VLSI2: Custom Layout Drawing -DRC - LVS - Parasitic Extraction

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EEN3196: Integrated VLSI Systems

Design Laboratory

1. Objective

To sharpen students’ design skills, which after completing the two lab phases,

students will be able to design the basic digital integrated circuit building blocks

based on given specifications.

To expose students to the design tools used by the industries in designing digital

integrated circuits. During the course of the design labs, students will be going

through digital IC circuits design flow, from the initial design to final verification.

At the completion of the design project, students should be able to:

understand how the logic gates are constructed out of transistors.

Measure the circuit parameters such as propagation delay and power consumption.

understand and apply low-power high-performance design techniques in their

design.

draw the layout of a small IC block, including the routing.

understand and apply advanced layout techniques to minimize the effects of

parasitics, especially on high-speed circuitries.

Programme Outcomes (% of contribution)

Programme Outcomes Level of Emphasis

PO2 - Acquire technical competencies in a specialised

engineering discipline to solve complex engineering problems. High

PO6 - Create, select and apply appropriate techniques, resources Low and modern engineering and IT Tools to complex engineering

activities.

2. Introduction

In the first induction lab (IVS1), students are asked to go through the process of

designing and simulating a CMOS inverter.

In the second induction lab (IVS2), students will be asked to continue to the second

part of the design which are Circuit Layout, Parasitic Extraction & Layout Versus

Schematic (LVS) Verification.

The two induction labs will familiarize students with Mentor Graphics as an

Electronic Design Automation (EDA) tool package for VLSI design. After going

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through the labs, students are required to create their own design from a selected

topics. Detailed methodology on how to design the system are not given in the lab

sheet. Students will have to use their creativity in designing the system, taking into

consideration design tradeoffs. This will also sharpen students’ design skills, as

engineers are not procedure-followers.

3. Design Task/Expected Outputs

Students are required to design one VLSI circuit building block using CMOS TSMC

0.35, CMOS 0.25, or CMOS 0.18-micron technology. After forming a group of at

most 2 students, students should choose one of the topics to be proposed on Week 1

of the trimester, or students can propose their own topic that must obtain instructor’s

approval.

Mentor Graphics should be used to implement and verify the correct functionalities of

your design, similar to the 2 walk-through labs.

The circuit and layout must be designed with the following goals in mind:

1. Minimum chip area

2. Minimum transistor count

3. Minimum power dissipation

4. Minimum propagation delay (maximum speed possible)

Before capturing the design using the EDA tool, students must do some homework.

This includes reading background theory of the chosen building block. After that,

students must hand-analyze the chosen circuit architecture to get maximum

performance. Students should come up with their own testing methodology, to prove

that the circuit is functional and meet every design specification. Students will have to

enter the lab and implement their designs at their own time, and complete the design

by week 11.

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4. Report

After completing the design project, a project report should be submitted by each

group. The quality of your report is as important as the quality of your design. One

must sell the design by justifying the design decisions and providing all the vital

information, while eliminating the unnecessary materials. Organization, conciseness,

and completeness are of paramount importance. Remember, a good report is like a

good layout: it should perform its function (convey information) in the smallest

possible area with the least delay (to the reader) possible. In the report, the following

information must be included:

(a) Functional explanation of the design

(b) Hand analysis

(c) The schematic diagram of the design

(d) Layout

(e) Input test vectors and expected results

(f) Simulation results of the schematic

(g) Design methodology and flow

(h) Simulation results of the parasitic-extracted layout

(i) Design summary on layout size (m m), transistor count, and maximum

delay/maximum frequency, average power consumption, specification, etc.

(j) Discussions – analyze the differences among results for hand-analysis, schematic

capture and layout.

(k) Conclusions

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EEN3196 Integrated VLSI Systems – Design Project

Computer Accounts for Project

Accounts will be set up on VLSI systems to run Mentor Graphics – after you have

handed in your proposal by Thursday midnight, Week 2.

Propose Project Topics :

1. 4-bit parallel adder (The student must select any one 4 bit parallel adder out

of 7) Ripple carry adder, or carry propagate adder, Carry look-ahead adder,

Carry skip adder, Manchester chain adder, Carry select adders, Pre-Fix Adders,

Multi-operand adder, Carry save Adder and Pipelined parallel adder

Use one of the fast carry-generation methods to design the adder. Optimize the

design for the worst-case propagation delay, tp for the outputs. Refer to section

11.3 of [2] for details.

2. 4-bit parallel multiplier (The student must select any one 4 bit parallel

multiplier out of 3) Carry save multiplier (CSM), Braun Multiplier and Bough-

Wooley multiplier

Choose suitable multiplier architecture to optimize the design for the minimum

area-delay product. Refer to section 11.4 of [2] for details.

3. 4-by-4 Non Restoring array Divider

Design a Non restoring divider circuit to optimize the minimum area, minimum

power consumption and high speed arithmetic circuits. 4-bit binary counter

Other than the proposed topics above, students could proceed with their own

design topics upon instructor's approval. Design must be done at transistor level.

Project Requirements:

1. A team of at most three per project.

2. All projects should involve circuit schematic, layout, parasitic extraction, pre-

layout and post-layout simulations.

3. The functionality of the circuits must be validated and the specifications for

nominal process corner and temperature range of 0 C to 85 C must be met.

4. Students are encouraged to discuss with other groups.

Deadlines / Timelines / Assessment Stages:

Week 1: The project topics are released to the students. The students must submit

the name of the group members by midnight, Thursday.

Week 2: Students must submit project proposal (title, abstract) by midnight,

Thursday.

Week 3: Submit Hand-Analysis for the proposed project by midnight, Friday

Week 5: Submit progress report (Design verification at Schematic Capture stage

should start on Week 3. Design should be validated for NOM process, and meet

all design specifications across 0 - 85 C).

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Week 10: Submit complete report by midnight, Thursday. Design verification at

layout stage, including parasitic extraction and back-annotation should be done

starting from Week 6 up to Week 11. Final verification should prove that the

circuit meets all design specifications for NOM process, and temperatures from 0

- 85 C. )

Week 12: Presentation. Students are to present their design in the class, and

convince the instructor/class that the design is successful. This requires EVERY

team member to understand how the circuit works, the function of each transistor

in the circuit, circuit limitations, trouble-shooting techniques, test/validation

approaches.

Every team member is responsible for the entire design flow.

Students are encouraged to propose their own project/title, but it must get

approval from the instructor first.

One report to be submitted per project.

Reference

[1] Weste, N. H. E. and Eshraghian, K. “Principles of CMOS VLSI Design: A

Systems Perspective” (2nd Ed.), Addison-Wesley, 1994.

[2] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated

Circuits: A Design Perspective (2nd Ed.), Prentice Hall, 2003.

[3] M.Morris Mano, “Digital Design 2nd Edition”, Prentice-Hall, 1991.

[4] M.S. Sulaiman, T. Dryburgh, , M.I. Elmasry, "A Fully Integrated 3.3-V, 325-

MHz, +/- 95-ps jitter CMOS PLL", Proceedings of the IEEE International

Conference on Semiconductor Electronics, pp. 67-71, December 2002.

[5] M.S. Sulaiman, N. Khan, "A Novel Low-Power High-Speed Programmable Dual

Modulus Divider for PLL-based Frequency Synthesizer", Proceedings of the IEEE

International Conference on Semiconductor Electronics, pp. 77-81, December

2002.

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LAB GUIDE

IVS1: Schematic Design Entry, Simulation & Verification

Create project folder

Before creating a design, you must create a folder storing all the design files.

From the desktop, right click on the mouse and open a terminal window.

At the command shell, make a training directory, and inside the training directory,

create another schematic directory as follows:

> mkdir training

> cd training

> mkdir schem

Schematic capture

Setup

To draw schematic, use the Design Architect IC.

> da

From the menu, choose the 0.35 m technology by keying in “2”.

You need to setup the DA-IC Session. If the setup pallet is not shown on the right

side of the tool, click on the “MGC -> Setup -> Session icon”, to bring up the

setup window.

Check the “Show Palette” option and click “OK”. This will display a schematic

palette on the right side of the tool.

Next you should setup the working directory, click on “MGC -> Location map ->

Set Working Directory”. Set the working directory to schematic directory just

created earlier, e.g. “/home/training /schem”.

Create a schematic sheet

To create a schematic, click on the “Schematic” option on the palette on the right.

Type in the path to store the schematic, e.g. “/home/training/schem/inverter”.

Click on “Editable” option and click “OK”.

Now you should be able to see the schematic window with grids.

Insert components

Click on “ADK IC Library” on the palette on the right side. The palette is now

changed to “ic library” where there are many components.

For example, if you wish to insert an NMOS transistor, click on the “nmos”, and

place the “nmos” in the schematic.

Components you need in creating an inverter are:

o nmos, pmos, VDD, GND, In and Out

To change properties of a component (e.g. changing width and length of the

transistor), select the component and right click on it. Choose “Properties” then

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“modify multiple”. You have to click the “apply” button after changing each

parameter, otherwise the changes wont be saved.

Refer to the following schematic to insert desired components.

To name a component, highlight the component, then right click and select “Name

Instance: -> Manual” at the Instance menu.

Key in the new component name in the “New Value” column at the bottom of the

window. Name the components as shown (M1, M2).

When done, click “OK”.

Add wires

To add wire/net, click the right mouse button, in the “ADD” menu, choose “Wire”

or simply press “W” on the keyboard.

To add a wire between 2 points, click once on the starting point, move the cursor

to the other point, and double click.

To exit from this adding wire function, press “Esc”.

Name ports

Unselect all components first (by pressing “F2”), then select the wire connected to

the net.

Right click and choose “Name Nets” from the “NET” menu.

Key in the new net name in the “New Value” column at the bottom of the

window. Name the nets as shown (input, output).

When done, click “OK”.

Check Schematic

After the schematic is captured, you need to check the schematic to make sure

there are no errors on it.

At the main menu, click on File -> Check Schematic.

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Check to see if the process is passed or failed. Notice that at the bottom of the

window, it reads “inverter/schematic/sheet1 passed check”

If schematic check failed, fix the schematic accordingly by referring the log

window. Otherwise, the log window can be closed. This can be done by clicking

on the middle mouse button and dragging it towards the left and let go.

Generate Symbol

Next is to generate a symbol to represent the design.

Click on Miscellaneous -> Generate Symbol from the main menu.

At the “Generate Symbol” window, choose the options (default) as shown below:

Component Name: export/home/training/schem/inverter

Symbol name: inverter

Replace existing? No

Once generated … Edit Symbol

Activate symbol? No

Choose source: Schematic

Schematic Name: schematic

Pin Spacing: 2

Sort Pins? No

Click “OK” when done.

The symbol generated will be seen.

To check the symbol, click on File -> Check Symbol at the main menu.

Check to make sure the symbol passed check at the bottom of the window.

Close the log window. Hold on to the middle mouse button, drag it to the left and

let go.

You can save the symbol by clicking File -> Save Symbol -> Default.

Close the symbol window. Hold on to the middle mouse button, drag it to the left

and let go.

Save schematic

To save the schematic, click on File -> Save Sheet -> Default.

After saving, you can close the schematic window by holding on to the middle

mouse button, dragging it to the left and let go.

Simulation

Creating a testbench

What you need to do next is to create a testbench graphically. This testbench is

used to create stimulus to simulate your inverter.

Click on “Schematic” at the palette on the right.

In the “component name” column, change the “inverter” to “inverter_tb”. This is

to create another schematic file with the name inverter_tb. Click on “Editable”

option and click “OK”.

An empty schematic window pops up. The first thing you need to do is to

instantiate your inverter design in the testbench.

Click on “Add Instance” on the palette on your right.

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An “Add Instance” window pops up. Select the “inverter” which is the inverter

symbol that you have designed earlier.

Click on “OK”.

Move your cursor to place the instance in the schematic sheet.

After placing the inverter, click on “Library”.

Components you need to add to the test bench are:

Capacitor, VDD, DC, GND and PULSE

Refer to the following to insert the components and to connect the wires.

To modify the DC source, unselect everything first by pressing “F2”.

After that, click on the DC source and it will be highlighted. Then, right click and

select “Properties -> Modify Multiple”.

A “Modify Editable Properties” window pops up. On the “DC” column, change

value to “5V”. Then, click on “OK”. Notice that “Mag=1V” in the DC source is

now changed to “Mag=5V”.

Change the value of the capacitor to 500fF.

To modify the PULSE source, unselect everything. Then, click on PULSE and

right click. Select “Properties ->Modify Multiple”.

When the “Modify Editable Properties” window pops up, change the data to the

following:

delay: 1ns

initial_value: 0V

INST: VP1

period: 50ns

pulse_value: 5V

t_fall: 1ns

t_rise: 1ns

width: 20ns

Click “OK” when done.

To name the nets (input, output), unselect everything first. Select the net to be

named and it’ll be highlighted. Right click and select “Name Nets”.

C=0.5pF

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Key in the net name (input or output) in the “Property Value” column at the

bottom of the window.

After creating the testbench, you now need to check the schematic of the testbench

to make sure it is correct.

To check schematic, click on “File ->Check Schematic”.

Once passed, save the schematic by clicking on “File -> Save Sheet ->Default”.

Simulation mode

Click on the “Simulation” key on the palette.

Click on “Session -> Simulator/Viewer. The “Setup Simulator/Viewer” window

pops up. Change the working directory for running simulations to your schematic

folder. e.g. /export/home/training/schem/inverter_tb

Then, select “Eldo” for simulator and select “Ezwave” for viewer. Click “OK”

when done.

Click on “Session -> Netlister” at the palette.

A “Setup SPICE Netlister” window pops up. Choose the “Eldospice” as output

type and at the “Set Node 0” column, key in “GND VSS”. This tells the netlister

that any nodes with the name GND or VSS is the ground. Click “OK” when done.

Click on “Lib/Temp/Inc -> Libraries”. A “Set Library Paths” window pops up. Put

in the path “/EDA/Mentor-training-ADK/technology/accusim/tsmc035.mod”.

Click “OK” at the bottom of the window.

Click on “Analyses” and a “Setup Simulation Analysis” window pops up. Choose

“Transient” and click on “Setup”. A “Setup Transient Analysis” window pops up.

Change the stop time to “300ns” and time step to be “1ns”. Click on “OK” for

both pop up windows.

Click on “Probes/Plots -> Probe”. A “Set Probes” window pops up. Click on

“select all” then select “TRAN” for the Analysis Type. Click “OK”.

After setting the probes, you are now ready to run simulation.

If you click on “Netlist”, the toold will generate the spice netlist for your design.

However, you can just click on “Run Eldo”. This option will automatically run the

netlist option and then simulate.

Take note that 2 window pops up, one to generate the netlist and the other to

simulate.

Make sure if your simulation is successfully done. Notice that at the bottom of the

window, it reads “Simulation completed successfully”. When simulation is

successfully done, you can just hit “ENTER” to close the two pop up windows.

If your simulation fails, end your simulation by clicking “End Sim” and do the

corrections on your schematic, before repeating the whole simulation process

again.

View simulation result

If your simulation is successfully done, it’ll generate two output files, inverter.chi

and inverter.cou. You can view the content of inverter.chi using a text editor.

inverter.cou contains the waveform outputs. To view the output waveforms,

invoke the Spice Explorer. To do that, minimize everything. When you are at the

desktop, open a new terminal. In the command prompt, type “EZWave”. This will

bring up the “WaveViewer” tool for waveform analysis.

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Click on “File -> Open” from the main menu. Browse for the file where we stored

the simulation result. E.g. “training -> schem -> inverter_tb -> tsmc035 ->

inverter_tb_tsmc035.cou.

Click “OK”.

Notice at the top left window, you will see the waveform file. Click on the “+”

sign. This will open up the file to show you the “toplevel” of the waveform file.

Click on the “toplevel” word and notice the signals in the toplevel are now

displayed at the bottom left window.

To view the waveforms of the signals, double click on every displayed signal.

You can now see your waveform on your waveform window (black window).

Check your waveform.

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LAB GUIDE

IVS2: Custom Layout Drawing –DRC - LVS – Parasitic Extraction

Introduction

When the system and circuit simulations of your design are passed, you are ready to

design the physical layout of your circuit. The physical layout creates mask data to

fabricate the desired circuit. There are three ways to generate the layout: full custom,

semi automatic and full automatic. In this course custom layout drawing is being

practiced. You also need to compare the netlist of your schematic and the extracted

circuit from layout to check whether they match or not?

Generating the LVS viewpoint from design schematic:

The inverter schematic has been drawn in the first lab. Now, you need to create an

LVS viewpoint from the schematic.

Open the schematic diagram using the Design Architect IC.

Enter the simulation mode by clicking on “Simulation” button.

To generate a new netlist to be used in the LVS (Layout Versus Schematic)

process, click on “Session -> Netlister” at the palette.

A “Setup SPICE Netlister” window pops up.

This time, choose the “LVS” option in the “Output Type” column.

Check “Wrap Netlist in .subckt” option.

Again make sure the “Set Node 0” is specified: GND VSS

Click OK to close the dialog. Then, click on execute “Netlist” at the “schematic

sim” palette to generate the netlist. The new netlist is then generated.

Note that the tool will inform you that the netlisting completed successfully at the

bottom of the window.

Exit from design architect.

Create layout folder

Before creating a layout, you must create a folder storing all the layout files. Just like

what you did for schematic capture, make a layout directory inside the training

directory.

Startup

To draw layout, invoke IC Station at the command shell.

Type: ic

Choose the ADK Design Kit by keying in “2”.

You need to setup the IC Station. Select “Setup -> New Window” from the main

menu.

Check the “Snap Grid On” option.

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Specify the grid setting

o Snap: X = 0.5 Y = 0.5

o Minor = 1 Major = 10

o Offset: X = 0 Y = 0

o Drawing cull = 5

Click “OK” when done.

You should now setup the working directory. From the main menu, click on

“MGC -> Location map -> Set Working Directory”. Set the working directory to

the layout directory just created earlier: …/training/layout

Creating new custom layout

From the session palette, click on Create

Cell name: specify the name of the cell. (It must be the same as the schematic

name e.g. inverter)

Make sure to select the proper directory.

Attach library: select tsmc035 library.

Process: Choose tsmc035 process library.

Rule file: Choose tsmc035.rules design rule file.

Connectivity: Select No Connectivity

OK

Layout editing

From the main menu, select “Other -> Layers -> Show Layer Palette”. A Show

Layer Palette window pops-up. Select the following layers to be added to the layer

palette by pressing Ctrl and left mouse button.

m1txt, contact, p_well, n_well, poly, metal1, active, contact_to_active,

contact_to_poly, n_plus_select, p_plus_select,

The layer palette should appear on the top-right side of the window.

We can now begin drawing the layout. With the cursor in the “IC Palettes”, click

the right mouse button and select “Show Scroll Bars”. This allows you to scroll up

and down within the palette.

There are many ways to draw layout, using Expert Edit or Easy Edit. Click on

“Expert Edit” in the “IC Palette”.

Select “PAT+” in the “Expert Edit” palette, which will draw a path. Select the

layer to draw, eg. metal1, from the menu above the “Expert Edit” palette.

Click on the starting point of your path in the layout window. An “ADD PA”

window appears. Click on “Options”. The width of the path can be specified here.

Enter “3” for width. (which means the width is 3 lambda in size)

Back to the layout window and try placing the path. Double click to complete the

path.

To unselect highlighted objects, press F2.

Press ESC key to terminate commands that are still active.

Try using the other commands in the Expert Edit palette. You can try COP+

(copy), NOTC+ (notch, add or remove a portion of a polygon), SLI+ (slice),

MOV+ (move), MVED+ (move edge), etc.

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The Expert Edit commands are listed below:

o Select

AR+ area GR group

ED+ edge

o Unselect

AL all ED+ edge

ALED all edge GR group

o Add

SH+ add shape CE* add cell

PAT+ add path VIA* add via

TE* add text DEV* add device

PR* add property PAN* add panel

PRT* add property text RU+ add ruler

LAY set IC layer ASP set aspect

WID set path width GRID set grid

o Edit

COP+ copy MVED+ move edge

FIL+ fillet NOTC+ notch

FLI+ flip ROT* rotate

MOD+ modify centerline SLI+ slice

MOV+ move ALGN align

STR+ stretch CUT/S+ cut/stretch

MEAS* measure PRO protect

UNDO undo UNPR unprotect

DEL delete Rpt* repeat

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Draw NMOS

A NMOS transistor consists of a source, gate, drain and bulk.

Draw the active and poly of the transistor as shown in the diagram:

(active: 13 x 5, poly: 9 x 2)

The active area is the area where the field oxide is etched. The overlap of

poly and active is the gate.

Next, add drain and source contacts using the “contact_to_active” layer.

This will connect the active to metal1 layer.

Add the metal1 layer above contacts.

To make this layout into an nmos device, it must be within N-Plus-Select.

Draw the N-Plus-Select region. It has to encompass the entire Active region

drawn earlier. (9 x 17)

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A nmos device must sit inside a p-type substrate or a p-well.

Draw a P-well around the whole device. (24 x 17)

Note: for large designs, several nmos will be grounded together inside one P-

well.

Finally, the connection to the P-well must be made. Draw an Active polygon

(6 x 6). Then draw Metal1 that covers Active layer. Inside the active layer

draw a “contact-to-active” polygon (2 x 2). Finally add a “p-plus-select”

layer (minimum 10 x 10)

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The cross section of a nmos transistor is like:

Draw PMOS

The steps for drawing pmos layout are similar to those for nmos.

Place the poly and active layers.

Then place the “contact-to-active” followed by “metal1”

Enclose everything in a “p-plus-select”, so that it becomes a pmos.

Place an N-well around every thing.

Create an N-well contact.

Complete Inverter

Now that the layout of both nmos and pmos transistors are created, we should connect

them together to make a CMOS inverter. The following figure shows the connections

of the inverter layout that you supposed to draw.

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Bring the poly layer out of the nmos and pmos transistors.

Connect the poly layers of the two transistors with Metal 1. (To connect Metal1 to

Poly, you need to add a Poly contact (2 x 2) on Poly layer and cover it with

Metal1 layer (min 4 x 4)).

Using metal 1, connect the drain of two transistors together. Metal 1 width should

be 3 lambdas.

Now, place the VDD and GND lines. Use Metal 1 but make the width wider now

e.g. 10 lambda. Make sure the Metal 1 covers all of the n-well contact and p-well

contact.

The source of the pmos is tied to VDD while nmos goes to GND.

Extend the n-well and p-well accordingly to the layout diagram shown.

To label a net, select “TE*” in the palette. In the ADD TE window that comes up,

click on “Options”. Select “Metal1 Port”, then click OK.

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In the ADD TE box, enter the net name (e.g. VDD) and then click OK.

With the cursor, click at where you want to place the text (e.g. VDD metal1

layer). The text must be within the Metal1.

Once the text is placed, you can still edit the text. Place the cursor at the text and

press SHIFT-F7. A Change Text dialog appears. The value, height, and

justification of the text can be modified.

Repeat the same steps until all VDD, GND, input and output nets are named.

Make sure that the names are same as the ones you named in your schematic.

Note: select Metal1 Port layer only if the layout metal connection is metal1 layer.

When the layout of your inverter is done, save the cell by clicking on the “blue

diskette” tab from the main menu.

Note: Whenever you close the layout window and reopen back your layout, you have

to press “CTRL-M” (to reserve the cell) before you can do any editing. This is to

prevent more than one designer edit the same layout.

Your layout for CMOS inverter is done. Now you have to check for the design rules.

Design Rule Check

From the main menu, select “Calibre > Run DRC”.

If this is the first time Calibre is invoked, the software will request to specify the

Calibre home directory. Browse to “/EDA/ixl_cal_2005.1_10.20”. Then, click

“OK”.

The Calibre Interactive window appears and asks for rules file.

Browse the rules file from “/EDA/Mentor-training-ADK/technology/ic/process”

directory and select the file: tsmc035.rules.

Specify the “Calibre-DRC Run Directory” as “…/training/layout”.

When the necessary Rules File and Calibre-DRC Run Directory have been

specified, the Rules tab turns green.

Click on the “Inputs” tab. Select “Flat” option.

All the setup is done now. Click on “Run DRC”.

DRC Summary Report will be shown, scroll through to view the report.

Another window shown is the RVE (Result Viewing Environment) window. This

window shows DRC errors.

If there is no DRC error, the DRC report will indicate there is 0 DRC Results

generated and you’re done.

If there are errors, click on the error to see the details. Double click on the DRC

error will highlight the error in layout window.

You can automatically zoom in the DRC error. At the Calibre DRC RVE window,

select “Setup->Options” from the main menu. Click on “Zoom cell view to

highlights by:”. Enter a number (e.g. 0.7). This is the zoom ratio. Click OK to

close. Double click on an error to see the zoom in.

Fix all the DRC errors accordingly.

After editing, save the cell and rerun the DRC. This is done by going back to the

Calibre DRC and click on Run DRC again. When prompted to Overwrite Layout

File, click OK.

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As mentioned earlier, runset saves the settings for running Calibre DRC. Save the

runset file by selecting “File -> Save Runset As” from the Calibre Interactive’s

main menu. Specify the runset file as “…/training/layout/drc.runset”.

Close the RVE and Calibre DRC windows.

The next time you need to run the DRC on the design, just invoke the Calibre

DRC and choose the runset file you saved earlier. All the settings done earlier are

preserved.

LVS (layout versus schematic)

We will be comparing the netlist from the schematic (which you have generated

befor) and the netlist from the layout (which will be automatically generated).

In IC-Station, invoke Calibre LVS by selecting Calibre -> Run LVS from the

main menu. (If needed to specify the Calibre home directory, browse to

“/EDA/ixl_cal_2005.1_10.20”)

Click on the “Rules” tab. Specify the Calibre-LVS Rules file as “/EDA/Mentor-

training-ADK/technology/ic/process/tsmc035.rules”, which is the same as DRC

rules file.

Specify the run directory as “…/training/layout”.

Click on the “Inputs” tab. Select “Layout vs Netlist”.

Then click on the “Netlist” tab in the same window. Specify the schematic netlist

to be used in LVS. The file should be

“…/training/schem/inverter/tsmc035/inverter_tsmc035.spi”.

Click on “Run LVS”. Click “OK” when asked to overwrite.

Once completed, the LVS Report and the RVE windows will appear.

Take a look at the LVS Report. If you see a big X, it means there are errors.

The RVE window is useful to debug the layout. Click on an error, an explanation

will appear at the bottom pane. To debug, right click near the error and select

Highlight Net. The IC-Station will highlight the respective net.

Try fixing all the errors and rerun the LVS by simply click on Run LVS.

After modifying the layout, remember to run DRC again. Make sure your layout is

DRC and LVS clean.

Remember to save the LVS runset file similar to the DRC runset file. You can

specify the runset file as “…/training/layout/lvs.runset.

Close the LVS Report, RVE, and Calibre windows.

22

Parasitic extraction

Parasitic extraction is after DRC and LVS checking. The purpose of parasitic

extraction is to extract the parasitics (R & C) from the circuit layout.

Make sure that your layout is DRC and LVS clean.

In IC-station, invoke LVS: Calibre -> Run LVS

Add the rules file and run directory

Setup your LVS inputs for layout like you normally do for LVS

Setup your LVS inputs for netlist like you normally do for LVS – specify where

your spice files are.

In the output window, click on “Generate data for xRC or xCalibre” tab.

Click on “Run LVS” tab

When your LVS is clean, it will generate a “_tsmc035.rules_” file in the working

directory. (the file is needed for RC extraction)

From the IC station menu, Calibre Run PEX. The PEX screen pops up.

In the “Rules” choose the “_tsmc035.rules_” file that is generated when LVS is

clean.

Setup the run directory

Click on the “Inputs” tab. Setup the layout options similarly to what you normally

setup for LVS.

Choose “Calibre-xRC” for extraction.

Setup netlist options.

Click on the “Outputs” tab.

Choose “RC” and “Distributed” for extraction type.

Choose the “Names:” as “LAYOUT”

Choose the format as “HSPICE”

Enter a name for the output netlist file e.g. “inv.pex.netlist”

Click on “Run PEX”. This will start RC extraction.

Re-simulate the design with the parasitic data.