design of low power tpg using lp-lfsr.doc

8/14/2019 Design of Low Power TPG Using LP-LFSR.doc

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Design of Low Power TPG Using LP-LFSR

AIM:

The main aim of the project is to design and implement “Design of Low

Power TPG Using LP-LFSR”.

ABSTRACT:

This paper presents a novel test pattern generator which is more suitable for

built in self test (BIST) structures used for testing of VLSI circuits. The objective

of the BIST is to reduce power dissipation without affecting the fault coverage.

The proposed test pattern generator reduces the switching activit among the test

patterns at the most. In this approach! the single input change patterns generated b

a counter and a gra code generator are "#clusive$%&ed with the seed generated

b the low power linear feedbac' shift register L*L+S&,. The proposed scheme

is evaluated b using! a snchronous pipelined -#- and # Braun arra

multipliers. The Sstem*%n*/hip (S%/) approach is adopted for implementation

on 0ltera +ield rogrammable 1ate 0rras (+10s) based S%/ 'its with 2ios II

soft*core processor. +rom the implementation results! it is verified that the testing

power for the proposed method is reduced b a significant percentage.

Proposed e!"od:

In this paper while implementing the adder we need #or gate . actuall it re3uires

4- transistor5s to implement . 0nd 6*flip flop with onl 7 transistors.we can

implement this #or gate with 8 transistors . in this wa we reduce the area! dela!

power consumption

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY Branch!: "#$ra%a$ &Na'()r



BL#C$ DIAGRAM:

+ig9 Low ower Test attern 1enerator

T##LS:

hspice_vA-!!".!#$ t-spice

APPLICATI#% AD&A%TAG'S:





The seed generated from (L*L+S&) is "#*%&ed with the single input

changing se3uences generated from gra code generator! which effectivelreduces the switching activities among the test patterns.

The proposed method significantl reduces the power consumption during

testing mode with minimum number of switching activities using L*L+S&

in place of conventional L+S& in the circuit used for test pattern generator.

The proposed method gives better power reduction compared to the e#iting

method.

R'F'R'%C'S:

• BalwinderSingh! 0run 'hosla and Su'hleen Bindra :ower %ptimi;ation of

linear feedbac' shift register(L+S&) for low power BIST< ! =>>? I"""

international 0dvance computing conference(I0//) atiala!India @*A.

• .Corian! :0 6istributed BIST control scheme for comple# VLSI devices!<

roc. VLSI Test Smp.! .-*?.

• .1irard!< surve of low*power testing of VLSI circuits!< I""" design and

test of computers! Vol. 4?!no.8! >*?>.

• Dechrdad 2ourani!<Low*transition test pattern generation for BIST* Based

0pplications<! I""" T&02S0/TI%2S %2 /%DET"&S! Vol 7A!2o.8.

• B%" and Tian*Fang Li!< 0 novel BIST scheme for low power testing!<

I""".



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