design methodology for systems-on-chip what is needed and what is not
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Design Methodology for Systems-on-Chip What is needed and what is not. Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine www.cecs.uci.edu/~gajski. Who we are?. Center for Embedded Computer Systems (www.cecs.uci.edu) - PowerPoint PPT PresentationTRANSCRIPT
Design Methodology for
Systems-on-ChipWhat is needed and what is not
Daniel D. GajskiCenter for Embedded Computer Systems
University of California, Irvine
www.cecs.uci.edu/~gajski
Copyright 2002 Daniel D. Gajski 2IEEE OCCS, 8/26/02
Who we are?
• Center for Embedded Computer Systems (www.cecs.uci.edu)
• Independent Research Organization in UC
• 15 faculty and over 60 Ph.D. students
• Methodology group:• first system contract 1989 from SRC• over 50 person years in system methodology since 1990• over 10 Ph.D. in system design flow since 1990• published first books on:
– RTL Sythesis 1992
– Embedded Systems 1994
– System Design 2001
• developed SpecC language• leaders in SpecC Open Technology Consortium (www.specc.org)• “Inspired” SystemC
Copyright 2002 Daniel D. Gajski 3IEEE OCCS, 8/26/02
Outline
• System gap• Semantics, styles and refinements• RTL Semantics• System-Level Semantics• Where are we going?• Conclusion
Copyright 2002 Daniel D. Gajski 4IEEE OCCS, 8/26/02
Past Design Flow
Simulate
Capture & Simulate
Physical
Logic
Specs
Design
Manufacturing
Algorithms
System Gap
1960’s
Copyright 2002 Daniel D. Gajski 5IEEE OCCS, 8/26/02
Past and Present Design Flow
Describe
SimulateSimulate
System Gap
Capture & Simulate
Physical
Logic
Specs
Design
Manufacturing
Algorithms
1960’s
Describe & Synthesize
Manufacturing
Specs
Algorithms(software)
Physical
Logic
Design
1980’s
Copyright 2002 Daniel D. Gajski 6IEEE OCCS, 8/26/02
Past, Present and Future Design Flow
Communications
Functionality
Connectivity
Protocols
TimingDescribe
SimulateSimulate
Physical
Logic
Specs
Design
Manufacturing
Capture & Simulate
Algorithms
Describe & Synthesize
Manufacturing
Specs
Algorithms(software)
Physical
Logic
Design
Specify, Explore & Refine
Architecture
Manufacturing
Executable Spec
Algorithms
Physical
Logic
Design
System Gap
1960’s 2000’s1980’s
Copyright 2002 Daniel D. Gajski 7IEEE OCCS, 8/26/02
Missing Semantics:Simulation Dominated Design Flow
Finite State Machine
3.4152.715
case X is
when X1 =>
when X2 => Table Lookup
Controller Memory
• Simulatable but not synthesizable
Copyright 2002 Daniel D. Gajski 8IEEE OCCS, 8/26/02
Y Chart
Behavior Structure
Physical
Synthesis
PhysicalDesign
Copyright 2002 Daniel D. Gajski 9IEEE OCCS, 8/26/02
Y Chart
Behavior Structure
Physical
Logic
Transistor
RTL
System
Copyright 2002 Daniel D. Gajski 10IEEE OCCS, 8/26/02
Y Chart
Behavior Structure
Physical
Logic
Transistor
RTL
System
MoC
MoC
MoC
MoC
Copyright 2002 Daniel D. Gajski 11IEEE OCCS, 8/26/02
Abstraction Algebra
Algebra := < {objects}, {operations} >
SoC Algebra := < {models}, {transformations} >
Ordered set of transformations < tm, … , t2, t1 > is a refinement iff
model B = tm( … ( t2( t1( model A ) ) ) … )
Question: { models } ? ; { transformations } ?
Copyright 2002 Daniel D. Gajski 12IEEE OCCS, 8/26/02
Why Abstraction Algebra?
1. Enabling standard for ESDA
2. Discover truth behind system-level myths
3. Define system-level field (abstract semantics)
4. Introduce interoperability
5. Identify system-level methodology
6. Apply system-level methodology to SystemC, SpecC
and others.
Copyright 2002 Daniel D. Gajski 13IEEE OCCS, 8/26/02
Semantics, Styles & Refinements
• Each model uses well defined semantics• Each model has simple style• Each style uniquely expressed
– no syntactic variance or semantic ambiguity
• Each model needs style checker
• Each model can be refined from its predecessor• Clear refinement rules• Clear application order of refinement rules• Model refinements are verifiable
Copyright 2002 Daniel D. Gajski 14IEEE OCCS, 8/26/02
RTL Computational Models
• Finite State Machine with Data (FSMD)• Combined model for control and computation
– FSMD = FSM + DFG
• Implementation: controller plus datapath
FSMD model
S1 S2
S3
Op2 Op3
Op4
Op6
Op1
Op5Op1 Op2
Op3
Op1 Op2
Copyright 2002 Daniel D. Gajski 15IEEE OCCS, 8/26/02
RTL Processor
Bus1
Bus2
Bus3
Datapath
D Q
D Q
D Q
Control
inputs
Next-Sate
Logicor
Addressgenerator
Outputlogic
orProgrammemory
Stateregister
orPC
Controloutputs
Register
Selector
Register
Datapathoutputs
RFCache
ALU
Signalstatus
Controller
Latch
Datamemory
IR
SR
Cotrolsignals
Copyright 2002 Daniel D. Gajski 16IEEE OCCS, 8/26/02
RTL Synthesis
Op2 Op3
Op4
Op6
Op1
Op5Op1 Op2
Op3
Op1 Op2
S1 S2
S3
FSMD modelRTL Processor
D
Q
D
Q
D
Q
Controlinputs
Next-statelogic
orAddress
generator
Outputlogic
orProgrammemory
Stateregister
orPC
Controloutputs
Controlsignals
Bus1
Bus2
Selector
Register
Datapathoutputs
ALU
Bus3
Datapath
Signalstatus
Controller
Register Memory
RF
SR
IR
Latch
Datamemory
RTL
Copyright 2002 Daniel D. Gajski 17IEEE OCCS, 8/26/02
RTL Synthesis
Op1 Op2
Op3
Op1 Op2
S1 S2
S3
FSMD model
Allocation
Rescheduling
Variable binding Operation Binding
Bus Binding
FSM Synthesis
RTL Processor
D
Q
D
Q
D
Q
Controlinputs
Next-statelogic
orAddress
generator
Outputlogic
orProgrammemory
Stateregister
orPC
Controloutputs
Controlsignals
Bus1
Bus2
Selector
Register
Datapathoutputs
ALU
Bus3
Datapath
Signalstatus
Controller
Register Memory
RF
SR
IR
Latch
Datamemory
Op2 Op3
Op4
Op6
Op1
Op5
RTL
Copyright 2002 Daniel D. Gajski 18IEEE OCCS, 8/26/02
System Computational Models
• Program State Machine– States described by procedures in a programming language
• Example: SpecC! (SystemC!)
PSM modelProc
Proc
Proc
Proc
Proc
Copyright 2002 Daniel D. Gajski 19IEEE OCCS, 8/26/02
System Synthesis
PSM model
Proc
Proc
Proc
Proc
Proc
Memory
Memory
µProcessor
Interface
Comp.IP
Bus
Interface
Interface
Interface
Custom HW
System architecture
System
Copyright 2002 Daniel D. Gajski 20IEEE OCCS, 8/26/02
System Semantics
Objects:- Behaviors- Channels
Composition:- Hierarchy- Order • Sequential • Parallel • Piped • States- Transitions • TI • TOC, TOS, ...- Synchronization
Objects:- Components • Proc • IP • Memories • IF- Connections • Buses • Wires
Composition:(same as in Behavior Model)
System
Copyright 2002 Daniel D. Gajski 21IEEE OCCS, 8/26/02
System Synthesis
PSM model
Proc
Proc
Proc
Proc
Proc
Memory
Memory
µProcessor
Interface
Comp.IP
Bus
Interface
Interface
Interface
Custom HW
System architecture
Profiling
Allocation IF Synthesis
Refinement
Behavior Binding Channel Binding
System
Variable Binding
Copyright 2002 Daniel D. Gajski 22IEEE OCCS, 8/26/02
System Synthesis (continued)
RTL/IS Implementation+ results
Mem RFState
Control
ALU
Datapath
PC
Control Pipeline
IF FSM
IF FSMIP Netlist
RAM
IR
Memory
State
State
HCFSMD model
FMDS4
FSMD5
FSMD3
FSMD2
FSMD1
RTL MoC
Copyright 2002 Daniel D. Gajski 23IEEE OCCS, 8/26/02
EDA Approach: Simulation
System
RTL
Logic
TransistorVHDL, Verilog,
Copyright 2002 Daniel D. Gajski 24IEEE OCCS, 8/26/02
C++ Approach: Syntax
System
RTL
Logic
Transistor
Copyright 2002 Daniel D. Gajski 25IEEE OCCS, 8/26/02
MoC Approach: Diversity
System
RTL
Logic
Transistor
MoC
Copyright 2002 Daniel D. Gajski 26IEEE OCCS, 8/26/02
SystemC Approach: Language First
Source: J. Kunkel, VP Synopsis, (CODES, May 2002)
C++
SystemC
CSupported
Subset
Copyright 2002 Daniel D. Gajski 27IEEE OCCS, 8/26/02
SpecC Approach: Semantics First
System
RTL
Logic
Transistor
MoC
Copyright 2002 Daniel D. Gajski 28IEEE OCCS, 8/26/02
SystemC/SpecC
SpecC
C++
SystemC
C
Copyright 2002 Daniel D. Gajski 29IEEE OCCS, 8/26/02
Quote from SystemC
FUNCTIONAL SPECIFICATION FOR
SYSTEMC 2.0
Version 2.0-MJanuary 17, 2001
1.8 ACKNOWLEDGEMENTS
“Many companies and individuals have contributed time and resources in the development of both SystemC 1.0 and SystemC 2.0. Some of these contributors are listed in the contributors section of this specification and in the SystemC 1.0 Users’s Guide.
It should be noted that the fundamental mechanisms used to model communication and synchronization in SystemC 2.0 - interfaces, channels, and events - were inspired by similar constructs in Professor Daniel Gajski’s SpecC language. (For further information, see “SpecC: Specification Language and Methodology” at www.wkap.nl)”
Copyright 2002 Daniel D. Gajski 30IEEE OCCS, 8/26/02
Conclusion
Work to be done:
1. Abstraction Levels
2. Model Semantics
3. Refinement Rules
4. Methodology
5. Language
6. Simulation, Synthesis, Verification Tools
7. ESDA Market/Community Emergence
Prediction: No success in 7 without 1-6