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Design and Verification of a High Voltage, Capacitance Voltage Measurement System for Power MOSFETs
Parrish Ralston
Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of
Master of Science
In The Bradley Department of Electrical and Computer Engineering
Dr. Kathleen Meehan Dr. Jason Lai
Dr. Masoud Agah Dr. Charles Bostian Dr. Robert Hendricks Dr. Sanjay Raman
December 12th, 2008 Blacksburg, VA
Keywords: power electronics, power MOSFET, capacitance, capacitance voltage measurements, silicon carbide
Design and Verification of a High Voltage, Capacitance Voltage Measurement System for Power MOSFETs
Parrish Ralston
Abstract
There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the
measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study
discusses the circuit layout and automation software for a measurement system that can perform CV
measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can
perform low voltage (0‐40V) and high voltage (40‐5kV) measurements. Accuracy of the measurement
system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An
IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their
results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified
with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove
that more testing and further development of SiC MOSFET fabrication is needed.
iii
Table of Contents List of Figures ............................................................................................................................................ v
List of Tables ........................................................................................................................................... vii
Forward .................................................................................................................................................. viii
Chapter 1 : Background ................................................................................................................................. 1
1.1 The Power MOSFET Structure and Operation .............................................................................. 1
1.2 Internal Capacitances of the Power MOSFET ............................................................................... 3
1.2.1 Basic MOS Capacitance ................................................................................................................ 3
1.2.2 Power MOSFET Capacitance Values ............................................................................................ 6
1.3 Power MOSFET Capacitance and Switching Performance .......................................................... 12
1.3.1 Hard Switching ........................................................................................................................... 13
1.3.2 Soft Switching ............................................................................................................................ 18
1.4 Limitations of the Power MOSFET and SiC Devices ......................................................................... 23
1.4.1 Blocking Voltage and RDS‐ON ....................................................................................................... 23
1.4.2 Silicon vs. Silicon Carbide ........................................................................................................... 24
Chapter 2 : High Voltage, Capacitance‐Voltage Circuit and Analysis .......................................................... 26
2.1 High Voltage Circuit Layout ............................................................................................................... 26
2.1.1 CGD Configuration ....................................................................................................................... 28
2.1.2 CDS Configuration ........................................................................................................................ 29
2.1.3 CGS Configuration........................................................................................................................ 30
2.2 Analysis Capacitance‐Voltage Measurement System ....................................................................... 30
2.2.1 A Look at the Agilent 4284A LCR Meter ..................................................................................... 31
2.2.2 Accuracy Analysis of CV circuitry ............................................................................................... 32
2.3 Verification of Accuracy Analysis ...................................................................................................... 32
2.4 Cost and Benefit of High Voltage CV Accuracy ................................................................................. 38
iv
Chapter 3 : High Voltage CV Measurement Software and User Interface .................................................. 41
3.1 The CVI Interface ............................................................................................................................... 41
3.1.1 CV Measurement Setup ............................................................................................................. 41
3.1.2 Monitoring the CV Measurement .............................................................................................. 44
3.1.3 Saving CV Data ........................................................................................................................... 45
3.2 The CVI Code ..................................................................................................................................... 46
Chapter 4 : Measurement Results............................................................................................................... 52
4.1 The IRF1010N HEXFET ....................................................................................................................... 52
4.2 The IPW60R045CP CoolMos ............................................................................................................. 56
4.3 The SiC Power MOSFET ..................................................................................................................... 60
Chapter 5 : Conclusions and Future Work ................................................................................................. 64
References .............................................................................................................................................. 66
Appendix A ................................................................................................................................................ A‐1
A.1 Accuracy Calculation for CDS ........................................................................................................... A‐1
A.2 Accuracy Calculation for CGD ........................................................................................................... A‐3
A.3 Accuracy Calculation for CGS ........................................................................................................... A‐6
Appendix B ................................................................................................................................................ A‐9
v
List of Figures
FIGURE 1‐1 BASIC VDMOS CROSS SECTION .................................................................................................................. 1
FIGURE 1‐2 THREE PRIMARY MODES OF OPERATION FOR THE POWER MOSFET. ........................................................ 2
FIGURE 1‐3 POWER MOSFET CAPACITANCE ................................................................................................................. 3
FIGURE 1‐4 CHARGE WITHIN A BASIC MOS STRUCTURE .............................................................................................. 4
FIGURE 1‐5 BLOCK CHARGE DIAGRAMS FOR A P‐TYPE MOS DEVICE UNDER DC BIASING CONDITIONINGS ................ 4
FIGURE 1‐6 CROSS SECTION OF A LATERAL P CHANNEL MOSFET. ................................................................................ 6
FIGURE 1‐7 EQUIVALENT SUBCIRCUIT MODEL FOR POWER MOSFET USING LATERAL MOSFET MODELS. ................. 7
FIGURE 1‐8 THE FOUR PRIMARY STATES THAT DESCRIBE MOSFET CAPACITANCE AS ASSOCIATED WITH GATE‐
SOURCE VOLTAGE. .............................................................................................................................................. 8
FIGURE 1‐9 GATE‐DRAIN CAPACITANCE VERSES VOLTAGE.. ......................................................................................... 9
FIGURE 1‐10 GATE‐SOURCE CAPACITANCE VERSES VOLTAGE. .................................................................................. 10
FIGURE 1‐11 DRAIN‐SOURCE CAPACITANCE VERSES VOLTAGE. ................................................................................. 11
FIGURE 1‐12 BUCK CONVERTER WITH INDUCTIVE LOAD ........................................................................................... 13
FIGURE 1‐13 TURN ON VOLTAGE AND CURRENT WAVE FORMS FOR THE GATE‐SOURCE AND DRAIN‐SOURCE
TERMINALS OF THE MOSFET .............................................................................................................................. 14
FIGURE 1‐14 POWER MOSFET IV CURVE AND LINEARIZED TRANSFER CURVE OF A POWER MOSFET. ....................... 14
FIGURE 1‐15 EQUIVALENT CIRCUIT USED FOR TURN ON CURRENT AND VOLTAGE ................................................... 15
FIGURE 1‐16 TURN OFF VOLTAGE AND CURRENT WAVE FORMS FOR THE GATE‐SOURCE AND DRAIN‐SOURCE
TERMINALS OF THE MOSFET. ............................................................................................................................. 17
FIGURE 1‐17 (A) CURRENT‐MODE RESONANT SWITCH (B) VOLTAGE‐MODE RESONANT SWITCH ............................. 18
FIGURE 1‐18 DC‐DC BOOST STRUCTURE ..................................................................................................................... 19
FIGURE 1‐19 EQUIVALENT CIRCUITS OF THE VZS BOOST CONVERTER ....................................................................... 20
FIGURE 1‐20 ZVS WAVEFORM DURING HALF WAVE MODE OPERATION .................................................................... 22
FIGURE 1‐21 ELECTRIC FIELD DISTRIBUTION ACROSS A PLANAR P‐N JUNCTION ........................................................ 23
FIGURE 2‐1 HIGH VOLTAGE CAPACITANCE‐VOLTAGE CIRCUITRY ............................................................................... 27
FIGURE 2‐2 CONFIGURATION FOR CGD MEASUREMENTS. ......................................................................................... 29
FIGURE 2‐3 CONFIGURATION FOR CDS MEASUREMENTS. ........................................................................................... 29
FIGURE 2‐4 CONFIGURATION FOR CGS MEASUREMENTS. ........................................................................................... 30
FIGURE 2‐5 PICTURES OF THE BUILT HV CV CIRCUIT .................................................................................................. 31
FIGURE 2‐6 BASIC SKETCH OF AGILENT LCR MEASUREMENT METHOD. ..................................................................... 32
FIGURE 2‐7 EQUIVALENT CIRCUIT DIAGRAMS FOR THE CGD CONFIGURATION ........................................................... 33
FIGURE 2‐8 A SIMPLIFIED VERSION OF THE CGD CONFIGURATION CONNECTED WITH THE LCR METER ..................... 34
FIGURE 2‐9 A CIRCUIT DIAGRAM WHICH HIGHLIGHTS THE EFFECT OF ZCCG ON THE IMPEDANCE MEASUREMENT. . 35
vi
FIGURE 2‐10 THREE FILM CAPACITORS SOLDERED ..................................................................................................... 36
FIGURE 2‐11 BODE PLOTS SHOWING THE CALCULATED ACCURACY OF EACH CV CONFIGURATION .......................... 37
FIGURE 2‐12 ACCURACY OF A CGD MEASUREMENT WITH MOSFET CAPACITANCES INCREASED BY AN ORDER OF
MAGNITUDE ........................................................................................................................................................ 39
FIGURE 3‐1 USER INTERFACE FOR THE CAPACITANCE‐VOLTAGE MEASUREMENT SYSTEM. ...................................... 42
FIGURE 3‐2 ATTRIBUTES WINDOW USED TO EDIT PARAMETERS FOR A CV MEASUREMENT. .................................... 43
FIGURE 3‐3 TWO SAMPLES OF A SAVED CV DATA FILE ............................................................................................... 45
FIGURE 3‐4 THE FLOW CHART DESCRIBING SWEEPGATEDRAINVOLT_FUNC_CGDMSR ROUTINE. ............................. 47
FIGURE 3‐5 FLOW CHART FOR SWEEPDRAIN_ANODEVOLT SUBROUTINE .................................................................. 49
FIGURE 3‐6 FLOW CHART FOR CVSVPLOT SUBROUTINE. ............................................................................................ 50
FIGURE 3‐7 FLOW CHART FOR CHECKERROR SUBROUTINE. ....................................................................................... 51
FIGURE 4‐1 GATE‐SOURCE CAPACITANCE MEASUREMENTS FOR THE IRF1010N HEXFET. ........................................ 53
FIGURE 4‐2 GATE‐DRAIN CAPACITANCE MEASUREMENTS FOR THE IRF1010N HEXFET. ......................................... 54
FIGURE 4‐3 GATE‐DRAIN CAPACITANCE MEASUREMENTS FOR THE IRF1010N HEXFET. .......................................... 55
FIGURE 4‐4 SINGLE CELL CROSS SECTION OF COOLMOS TRANSISTOR. ...................................................................... 56
FIGURE 4‐5 GATE‐SOURCE CAPACITANCE MEASUREMENTS FOR THE IPW60R045CP COOLMOS. ........................... 57
FIGURE 4‐6 GATE‐DRAIN CAPACITANCE MEASUREMENTS FOR THE IPW60R045CP COOLMOS. ............................... 58
FIGURE 4‐7 DRAIN‐SOURCE CAPACITANCE MEASUREMENTS FOR THE IPW60R045CP COOLMOS. ........................... 59
FIGURE 4‐8 GATE‐SOURCE CAPACITANCE MEASUREMENTS FOR A HIGH VOLTAGE SIC POWER MOSFET. ............... 61
FIGURE 4‐9 GATE‐DRAIN CAPACITANCE MEASUREMENTS FOR A HIGH VOLTAGE SIC POWER MOSFET ................... 62
FIGURE 4‐10 DRAIN‐SOURCE CAPACITANCE MEASUREMENTS FOR A HIGH VOLTAGE SIC POWER MOSFET. ........... 63
vii
List of Tables
TABLE 1‐1 TABLE SHOWING DIFFERENCES BETWEEN THE PROPERTIES OF SILICON AND THE PROPERTIES OF SILICON
CARBIDE. ............................................................................................................................................................. 24
TABLE 2‐1 COMPONENT VALUES OF CIRCUIT SHOWN IN FIGURE 2‐1 ........................................................................ 27
TABLE 2‐2 TERMINAL CONNECTIONS FOR EACH TYPE OF CV MEASUREMENT TO BE PERFORMED ON A POWER
MOSFET. .............................................................................................................................................................. 28
TABLE 2‐3 COMPONENT VALUES OF PROTOTYPE HIGH VOLTAGE CV CIRCUIT. .......................................................... 38
TABLE 2‐4 A SUMMARY OF MEASURED AND CALCULATED CAPACITANCE VALUES. .................................................. 38
viii
Forward
The establishment of the field of solid state power electronics began in the 1950’s. In the past
30 years, power electronics has played an indispensible role in the advancement of technology. The
more electronic our world becomes, the more necessary it is to utilize inexpensive, efficient power
conversion and conditioning circuitry. These power conversion systems are often required to be small,
portable, durable, and highly reliable. Not only have power electronics made our world more
convenient, well connected, and mobile, their role in the future of global energy expansion is becoming
essential for our electronic lifestyle to continue.
For many decades after inception of the power grid, it was acceptable to maintain power
systems that yielded as little as 10% efficiency [1]. From the coal fired steam that turned a turbine and
converted chemical energy into electric power to the light bulb that converted this electricity to light,
little focus was placed on efficient conversion techniques. This is no longer the accepted standard. The
present norm, exclusively using fossil fuel powered generators to create three‐phase energy, is dirty,
wasteful, and unsustainable. Clean, stable, and more efficient methods of energy generation,
transportation, and utilization must prevail.
Alternative energy sources, high voltage DC transmission, and the application of adjustable‐
speed drive motors are a few of the many research efforts that are currently being investigated to
address our current energy crisis. But refinement of a good idea is not the only step to make these
initiatives a reality. The development of reliable and efficient high power solid state electronics for
power conversion and conditioning are the only way that better ideas will leave the research lab and be
introduced into commercial markets.
All commercial power grids around the world transmit three phase, alternating current. When
power grids were initially established, direct current power could not be changed from a low voltage to
a high voltage for transmission and then changed back to low voltage for safe use[2]. AC transmission
reigns today because we can modify rated AC voltage with relative ease using a transformer. The
advent of power electronics has made low and medium DC to DC voltage conversion cheap and
efficient. Good power DC‐DC converters can achieve efficiencies better than 95%[3]. With better high
power and high frequency solid state devices, high voltage DC transmission could become a feasible
ix
option. High voltage DC transmission not only suffers lower losses compared to AC transmission, but
would make many DC‐generating energy sources more “grid friendly”.
Currently, alternative forms of energy generation are simply not effective enough to be
competitive with traditional forms of generation. The recent record for solar‐to‐grid efficiency is
31.25%, in a lab setting[2]. For a wind turbine, the yield of power generated in a year versus the power
rating of the wind turbine is typically in the range of 20‐40% [3]. Solar, wind, fuel cells, and many other
proposed forms of large scale alternative energy produce direct current power. Large scale power
conversion from DC voltage to the rated AC grid voltage is a very important . Even if our present power
grid made the change to DC transmission, there is still significant advanced power conditioning that
needs to be utilized in order for alternative energy systems to have the kind of flexible, variable outputs
that make them most effective at converting light, wind, or hydrogen into electricity. Likewise, when
alternative forms of energy generation still cost much more per watt than coal or natural gas energy
generation, investing in quality power electronics that will not waste significant portions of generated
energy is a very practical concept.
Adjustable speed motor drives prove to be a powerful advancement from the more traditional
motor drives, and are intensely dependant on power electronics. For example, conventional pumps are
driven by a constant speed motor, with adjustments to flow rate made by a throttling valve. This system
is terribly inefficient at low flow rates. A better approach uses an adjustable speed motor drive which
directly modifies the pump rate. Power electronics can drive these kinds of motors accurately and
efficiently[4]. The expanse of applications that adjustable speed motor drives will improve is virtually
limitless. One simple example of their range of use is the carbon capture system on coal fired plants,
where huge pumping systems force carbon emissions into underground chambers rather than releasing
these emissions into the atmosphere[5]. Adjustable speed motor drives also can play a vital role in a
more familiar and necessary application, electric cars, where a powerful induction motor turns a
vehicle’s wheels rather than an internal combustion engine.
The heart of power electronics resides in the devices that make up these circuits, particularly
the power semiconductor switch. There are three groups of semiconductor switches, which are
categorized by their level of controllability; diodes, thyristors, and controllable switches. Power metal‐
oxide‐semiconductor field effect transistors (MOSFETs) fall into the category of controllable switches.
Other types of controllable switches include insulated gate bipolar transistors (IGBTs), gate turn off
thyristors (GTOs), and bipolar junction transistors (BJTs).
x
Power MOSFETs, often termed Vertical Diffusion MOSETS, or VDMOSFETS were first developed
in the mid‐1970’s[6]. Before the advent of IGBTs, the power MOSFET was matchless for its high
impedance gate structure, which greatly simplified the driver circuit for this controllable switch. Isolated
gate bipolar transistors, IGBTs, were developed more than a decade later and incorporate some of the
best aspects of a BJT with the gate structure of a MOSFET. In present technical reality, there is still yet
to be a controllable switch developed for high power applications that has better switching
characteristics than the power MOSFET.
Presently, all standard commercial power MOSFETs are built in silicon technology. These power
MOSFETS are consistently used for power applications where the operation voltages applied to the
MOSFETs do not exceed 200V. When MOSFET blocking voltage exceeds 200V, the on‐state resistance
of the device increases to a point that power dissipation during forward conduction is not competitive
with other semiconductor switches. For lower current applications of around 10A or less, a MOSFET
may be acceptable for voltages as high as 1kV, but typical silicon MOSFETS do not exceed this limit.
The power MOSFETs’ high frequency of switching paired with the low power dissipation during
switching operations have given researchers good reason to try and push the voltage and current
limitations of this device. No other power switch has faster switching speeds, and the high frequency of
operation translates to beneficial aspects of conversion such as higher power density, lower cost, and
decreased number of converter stages[4]. At higher frequencies, converter parts, such as transformers
and filters, become smaller. The decrease in size not only decreases the cost of these parts, but also
generally means there is less power dissipation in the transformers and filters and an extended lifetime
for these devices.
Structures like the CoolMOS have pushed the limits to what a silicon power MOSFET can
handle[7]. In order to significantly improve the current voltage capabilities of a power MOSFET device,
researchers must use a completely different starting material. Groups such as the Department of
Energy and the Defense Advanced Research Projects Agency, DARPA, have poured money in research
efforts that focus on the fabrication and testing of power silicon carbide, SiC, devices[8]. The properties
of SiC allow devices made of this material to have voltage ratings that are more than an order of
magnitude larger than comparable silicon as described in Section 1.4 of this thesis. SiC power MOSFETs
and Schottky diodes are already being built and different phases of these device designs are currently
tested by the National Institute of Standards and Technology, or NIST[9].
xi
There are numerous tests that have been developed to characterize the performance of
semiconductor switches. One test that is very important is capacitance‐voltage (CV) measurement,
which gives a description of how much charge is stored between two terminals of a device at different
values of voltage. These measurements are a reaction caused by the physical characteristics of a
MOSFET. In addition, CV measurement show to how a device will respond during switching procedures.
In order to fully test silicon carbide power MOSFETs there is a need for a test platform that can perform
CV measurements at high enough voltage values to fully characterize the full range of the power
MOSFET’s operation in the power electronic circuits.
The following paper describes the test circuitry used to fulfill the needs of a measurement
structure which allows users to safely test power MOSFETs up to a blocking voltage of 5kV. This paper
covers the circuit structure, analysis performed to understand the accuracy of the C‐V measurements,
initial tests used to confirm the circuit’s operation, software made to automate the entire measurement
procedure, and finally, initial low voltage tests performed with the fully built CV measurement platform.
1
Chapter 1 : Background
1.1 The Power MOSFET Structure and Operation
Figure 1‐1 shows the cross section of a lateral n‐channel power MOSFET cell, often termed
VDMOS, vertically diffused MOSFET. The device is fabricated by epitaxially growing the N‐ drift region
on top of the N+ drain contact[4]. The P body region and the N+ source contact are created using a
diffusion process. Many thousands of these cells exist in a single power MOSFET. There are various
configurations of the power MOSFET that have been developed to yield improved performance, such as
the trench‐FET , the HEXFET and the CoolMOS[7, 10] . For the purpose of this device examination, focus
will remain on the basic vertical diffusion power MOSFET cross section.
Figure 1‐1 Basic VDMOS cross section
There is a parasitic npn BJT between the drain and source of the MOSFET with the body region
acting as the base of the BJT. Current can be fed to the body region of the MOSFET by changing the
voltage across the drain and source terminals. To avoid the occurrence of this parasitic BJT turning on,
the source and the body region are shorted together, creating an integral diode within the MOSFET.
This integral diode can be used in half and full bridge converters.
As with all enhancement mode, n‐channel MOSFETS, when a small positive bias is applied to the
gate of the power MOSFET, a depletion region forms in the body immediately underneath the gate
oxide layer. As this gate bias increases to a value that is greater than or equal to VTh, the electric field
created by gate charge attracts a high density of free electrons to the body‐oxide interface. This
accumulation of negative charge, the inversion layer, effectively allows free electrons to pass through
the p‐type body region as if the free electrons were moving through a n‐type semiconductor.
2
Figure 1‐2 Three primary modes of operation for the power MOSFET (a) conduction in the ohmic region; (b) conduction in
the saturation region; (c) forward blocking.
There are three primary modes of operation for the power MOSFET: ohmic, saturation, and
forward blocking or cutoff. These modes of operation are shown in Figure 1‐2. In the ohmic region
where VGS>VTh, VDS is small in comparison to VGS ensuring nearly uniform thickness from source to the
drain side of the inversion layer. As VDS increases and the voltage potential between the gate and drain
decreases, the inversion layer narrows on the drain end of the channel, and thus current density at this
side of the channel increases. When VDS becomes large enough where VGS – VDS < VTh, the drain side of
the inversion layer disappears, but current flow is maintained by the electric field between the source
and drain areas. If the gate voltage is removed, the inversion layer completely disappears and electrons
are no longer injected anywhere into the body region of the MOSFET.
3
1.2 Internal Capacitances of the Power MOSFET
In order to accurately model even the most basic characteristics of a power MOSFET, it is very
important to understand the capacitance effects and adequately predict capacitance values. Figure 1‐3a
shows the three junction capacitances within a MOSFET and the equivalent lumped component model is
shown in Figure 1‐3b. The power VDMOSFET structure is more complex than more standard lateral
MOSFETs used in digital technology. This causes the various C‐V curves for power MOSFETs to be less
predictable than the CV curves of lateral MOSFETS. Before going into the detailed analysis of each
capacitor value, it is reasonable to discuss the qualitative theory used to describe MOS‐capacitance
characteristics.
Figure 1‐3 Power MOSFET capacitance: (a) cross section with each kind of capacitance displayed; (b) equivalent circuit
containing model of the parasitic capacitors
1.2.1 Basic MOS Capacitance
The value of capacitance across a metal‐oxide‐semiconductor junction can be summarized using
three primary states of the junction; accumulation, depletion and inversion. Charge across the device is
managed differently for each of these three stages. The following example uses a MOS interface with p‐
type semiconductor.
Accumulation occurs when the DC voltage applied to the gate causes majority carriers to
accumulate at the semiconductor‐oxide interface, as seen in Figure 1‐4a. In this case, a negative voltage
is applied to the gate, causing positive charge (holes) to concentrate at the surface of the semiconductor
material. This existing charge can quickly respond to changes in the system’s state, with a time constant
on the order of 10‐10 to 10‐13 seconds, meaning applied alternating current effectively has instantaneous
4
response from this majority charge residing at the semiconductor surface[11]. Figure 1‐5a describes
how this changing AC charge is distributed on both sides of the oxide. The capacitance of the MOS
device in this situation is essentially
OX
GOXOX t
ACaccC
)( , (1-1)
where εOX is the oxide dielectric constant, AG is the area of the p‐type channel under the gate, and tOX is
the thickness of the oxide.
Figure 1‐4 Charge within a basic MOS structure during (a) accumulation; (b) depletion; (c) inversion.
Figure 1‐5 Block charge diagrams for a P‐type MOS device under DC biasing conditionings corresponding to (a) accumulation; (b) depletion; (c) inversion with a low frequency AC signal applied; (d) inversion with a high frequency AC signal applied.
5
When a small positive bias is applied to the device, a depletion region forms at the oxide‐
semiconductor interface. The net negative charge of the depletion region is simply the lack of majority
carriers in this area of the device; therefore there is no charge within the depletion region to move with
an AC voltage. The width of the depletion region must fluctuate, shrinking and widening as the AC
voltage at the gate decreases and increases. Effectively, this is like having two capacitors in series, COX
and CS, as shown in Figure 1‐5b. Qualitatively, this is described as
SOX
SOX
CC
CCdeplC
)( , (1-2)
where,
W
AC GSS
. (1-3)
The variable, εS, is the semiconductor dielectric constant and W is the depth of the depletion into the
semiconductor surface,
21
2
S
A
S
qNW
, (1-4)
where NA is the acceptor doping concentration in the depletion region and φS is the potential at the
surface of the semiconductor.
The inversion layer forms when the positive bias applied at the gate of the MOS device becomes
large enough that an additional, negative charge, minority carriers (electrons) build up underneath the
oxide layer, as shown in Figure 1‐4c. Once an inversion layer begins to develop, the depletion width has
reached a maximum value, WT. One of two scenarios can occur at this point. For very low frequency AC
signal applied at the gate, the negative charge will be able to react to the changes in gate bias.
Therefore the thickness of the inversion layer will fluctuate in response to an AC signal, portrayed in
Figure 1‐5c. The capacitance of the MOS device is again equal to COX in this case. For very high
frequency AC signal, the carriers cannot be generated or removed fast enough to adequately respond to
the AC signal. In this case, the depth of depletion adjusts in response to the AC signal, as if the charge in
the inversion layer was not there, shown in Figure 1‐5d where CSmin represents the smallest value of
depletion capacitance. How quickly charge in the inversion layer can respond AC signal is dependent on
how quickly minority carriers can be generated and removed. In the P‐base region of a power MOSFET,
6
charge in the N+ source contact quickly supplies the charge needed for the base region capacitance to
effectively respond transient gate signals[6].
1.2.2 Power MOSFET Capacitance Values
Even though power MOSFETs were developed in the 1970’s, good models that adequately
described the characteristics of the device’s capacitance took another 20 years to establish. Two of the
more commonly used models to describe power MOSFET capacitance are the Cordonnier macro model
and, more predominantly, the lumped‐charge physically based model established by I. Budihardjo and
P.O. Lauritzen [12‐14].
Figure 1‐6 Cross section of a lateral P channel MOSFET.
The lateral MOSFET structure is much more predominant in the semiconductor world and
therefore the physics of this MOSFET structure has been very well developed. The simple cross section
of a lateral P channel MOSFET is shown in Figure 1‐6. Some studies have exploited lateral MOSFET
models to explain the power MOSFET [15]. Figure 1‐7 shows this. In the VDMOSFET there are two P‐
type bodies with an N‐type, lightly doped drain in between the bodies. This looks like, and can be
described as a lateral, P channel MOSFET, where the capacitance between the gate and drain of the
VDMOSFET can be described with some of the same equations used to describe the capacitance
between the gate and bulk of a lateral MOSFET. Setting the drain overlap capacitance of M1 to 0, these
first order lateral structures sufficiently represent the capacitance of a VDMOSFET. As a few minor
details, Rd1 and Rd2 are used to describe the additional resistance of the lightly doped drain. There are
two PMOS transistors, M2 and M3, connected from the drain to the gate which are used to describe the
effects of the built‐in voltage and depletion region of the of the P‐N junction between the P body and
the N‐ drain. This depletion region affects accumulation and inversion of charge at the semiconductor
7
surface. To account for this, an additional PMOS transistor, M3, which is identical to M2 aside from the
offset voltage source set in series with it.
During the operation of a power MOSFET there are four main situations that occur that affect
the shape of interelectrode capacitance‐voltage curves. All of these situations are summarized in Figure
1‐8 where VDS is assumed to be zero. For simplicity of explanation each state is designated a name.
Body inversion (Figure 1‐8a), body depletion (Figure 1‐8b), drain depletion (Figure 1‐8c), and drain
inversion (Figure 1‐8d) are the four states we will focus on and are specifically associated with how the
charge applied to the gate of this device affects the interelectrode capacitance. Effects caused by VDS
will also be covered in the following three subsections.
Figure 1‐7 Equivalent subcircuit model for power MOSFET using lateral MOSFET models.
CGD
The value of gate drain capacitance indicates the quantity of stored charge between the gate
layer and the large area of drain that is underneath the gate’s oxide layer. In Figure 1‐8a, VGS is greater
than Vth and there is an inversion layer in the p‐body, immediately underneath the gate oxide.
Additionally, the gate charge has created an accumulation layer at the drain‐oxide interface. Figure 1‐
8b shows a similar situation with the voltage across the gate source terminals still greater than zero but
8
Figure 1‐8 The four primary states that describe MOSFET capacitance as associated with gate‐source voltage. VDS is assumed to be zero for all pictures. (a) When VGS is greater than Vth, the MOSFET has inversion in the body region and accumulation in the drain, and there is continuous, negative charge under the gate; (b) The inversion layer disappears but a depletion region in the P‐body remains when VGS is less than Vth but still greater than 0; (c) As VGS becomes negative, an accumulation forms in the P‐body and a depletion forms in the drain; (d) when the threshold of the N
‐ drain is exceeded (Vth,PMOS) an inversion layer forms in the drain and there is a positive, continuous, positive charge connecting the source terminal and shielding the
gate.
9
less than the threshold voltage. These two situations produce very similar results with one caveat. The
accumulation layer in the drain means that the capacitance, CGD, will be a maximum value, as explained
in 1.2.1. CGD is at its highest value immediately before the inversion layer develops in the p‐body. Once
current is allowed to flow through the P body region, the voltage at the drain‐oxide interface is no
longer constant; it is larger close to the edges of the p body region than it is at the center of the drain‐
oxide surface. This causes the slight capacitance decrease during forward conduction. A set of generic
C‐V curves for CGD are shown in figure 1‐9. The section of the C‐V curve in Figure 1‐9a defined with
bracket 1 shows this transition for the body inversion state to the body depletion state.
Figure 1‐9 Gate‐drain capacitance verses voltage. (a) CGD verses VGS. The numbered brackets parse out the different state
transitions that occur in the power MOSFET. (b) CGD verses VDS.
As VGS decreases and transitions from an applied positive charge on the gate to a negative
charge, the body region changes from depletion into accumulation and the drain region goes from
accumulation into depletion, as show in Figure 1‐8c. The expansion of the depletion region in the drain
causes CGD to drop monotonically with increasing VGS. Bracket 2 in Figure 1‐9a identifies this transition.
As VGS continues to drop, it exceeds the “threshold voltage” of the body/drain PMOS transistor, creating
an inversion layer in the drain of the power MOSFET. When this happens, an interesting phenomena
occurs that is unique to the power MOSFET; there is a continuous, positive charge stretching from either
source contacts as shown in Figure 1‐8d. This positive charge connects the source across the body and
drain and effectively blocks the charge that is on the power MOSFET gate. This causes the gate‐drain
capacitance to decrease rapidly, which is a physical characteristic that the designers of converters can
10
use to their advantage and is often termed the shielding effect. Bracket 3 of Figure 1‐9a labels the
switch into the drain inversion stage as can be seen by the dramatic drop on gate‐drain capacitance.
When VDS increases, it has two principal effects on the capacitance. The depletion region in the
drain begins developing once VGS becomes less than VDS; therefore for a given, small value of VGS the
capacitance in the drain is much smaller for increasing values of VDS. As VDS increases, the PMOS
inversion threshold for the drain region increases, a phenomena occurs that can be likened to the body
effect in a PMOS transistor. We see this in Figure 1‐9a, the rapid drop in CGD happens at more negative
values of VGS.
CGS
Figure 1‐10 Gate‐source capacitance verses voltage. (a) CGS verses VGS; (b) CGS versus VDS.
The gate‐source capacitance as a function of applied voltage, shown in Figure 1‐10, most closely
resembles a low frequency structure MOS structure as it was described in the previous section. When
the power MOSFET is on and an inversion layer is present in the P body, the charge in the inversion layer
can quickly respond to variations in charge applied to the gate by moving free electrons in and out of the
N+ contact. Therefore gate‐source capacitance is high. When VGS drops below the threshold voltage
and the device is in body depletion state, the capacitance drops quickly. Capacitance then recovers as
VGS becomes less than zero and the P body goes into accumulation. The value of CGS further increases
as the inversion layer underneath the drain is established and the shielding effect connects the source
across the drain. As mentioned in the previous section, increasing values of drain‐source voltage delays
11
the onset of inversion in the drain. This causes shielding effects to occur at greater values of VGS,
delaying CGS from reaching its maximum value. Figure 1‐10a CGS verses VGS and this delayed onset in
shielding is observed for a greater value of VDS. Figure 1‐10b is a good depiction of how shielding effect
influences the value of CGS. For increasing values of VDS and a constant value of VGS, the inversion layer
in the drain disappears as the drain voltage increases the P‐inversion threshold. The abrupt drop in CGS
in figure 1‐10b is the reaction to this loss of shielded charge.
CDS
The output capacitance of a power MOSFET, CDS, represents the coupling of the drain and the
source electrode. During forward conduction in a power MOSFET, the source and drain have a direct
connection and current is allowed to flow between these two terminals, so the capacitance is very low.
When the power MOSFET is turned off, and the inversion layer between the source and drain
disappears, the capacitance between these two terminals is represented by the depletion region
between the p‐body and the N‐ drain. A CDS verses VDS curve looks very similar a C‐V curve for a diode;
as the drain voltage increases, the P‐N depletion layer increases which decreases the capacitance
between these two terminals. This common shape in the C‐V curve is present in Figure 1‐11b.
Figure 1‐11 Drain‐source capacitance verses voltage. (a) CDS verses VGS; (b) CDS versus VDS.
But Figure 1‐11b does not look exactly like a diode’s C‐V curve. If it did, changing that value VGS
would have no effect on the CDS verses VDS curve. Figure 1‐11b shows three unique curves for three
12
different values of gate‐source voltage. This variation is caused by the shielding effect; the inversion
layer underneath the drain connects the source charge through the drain region. This effectively
extends the area of the source region to include the area of the drain that is underneath the oxide layer.
The rapid increase in capacitance in Figure 1‐11a shows the onset of the inversion layer in the drain.
Increasing values of VDS shift the onset of this jump in capacitance.
1.3 Power MOSFET Capacitance and Switching Performance
Some of the main aspects of three terminal power devices that researchers work to optimize are
forward conduction efficiency, switching efficiency, blocking voltage, and maximum switching
frequency[6]. Improving one aspect of the device often affects other characteristics of the device. For
instance, improving forward conduction efficiency intrinsically reduces the blocking voltage a power
MOSFET can withstand. Switching frequency of a converter plays a significant role in the overall cost
and degree of complexity of a given converter[4]. Higher frequency converters with low power
dissipation during switching events will allow for smaller and therefore cheaper, passive components
and fewer converter stages. Maximizing these device characteristics has a positive impact on the whole
power electronics system.
Because the power MOSFET is not a minority carrier device, its switching characteristics are
intrinsically faster with less power dissipation than the characteristics of other high power, three
terminal semiconductor devices. When a power BJT or IGBT is conducting high current, very high levels
of minority carriers exist in their drift region. When these devices are turned on they must first establish
this high level of minority carriers before they may reach a steady state. And then when turned off, the
minority charge has to be swept out of the device. MOSFETs do not have this issue; the only charge they
have to move is caused by the built‐in capacitance of the device. These capacitances largely dictate the
switching speeds of power MOSFETs, power dissipation during switching, and the efficiency of MOSFET
gate driver circuits. All the capacitance values shown in Figure 1‐3a play a significant role on the shape
and speed of voltage and current switching waveforms. The following sections on hard and soft
switching quantify the significance of MOSFET capacitance in dictating the voltage and current
waveform shape, speed, and the associated power dissipation.
13
1.3.1 Hard Switching
The term, hard switching, refers to the traditional form of switching performed in pulse width
modulated (PWM) converters. During a hard switching transitions, a MOSFET switches from off to on
with full voltage potential across its terminals. While switching from on to off there is full current
through the device. For a simple, first order analysis of power MOSFET switching, we apply the MOSFET
in a step down, buck converter configuration with an inductive load. Figure 1‐12 shows a diagram of a
diode clamped inductive load with a MOSFET used as the switch. This is a fundamental circuit used in a
step down DC‐DC converter, and the following switching analysis presented can apply to any buck,
boost, or buck‐boost converter[4].
Figure 1‐12 Buck converter with inductive load, IO. CGD and CGS represent the internal capacitances of the MOSFET.
Turn On Transition
In region A of the turn‐on transition, described in Figure 1‐13, Figure 1‐14, and Figure 1‐15a, the
gate voltage, VGG, is stepped from zero volts to a voltage that exceeds the threshold voltage of the
power MOSFET. The application of gate voltage induces gate current that charges CGD and CGS,
dt
dvC
dt
dvCi GD
GDGS
GSAG )(
.
(1-5)
The voltage applied at the gate of the MOSFET is equal to,
14
GtGGAGS eVv /
)( 1 (1-6)
where time constant, τG, is
GSGDGG CCR . (1-7)
Once the gate‐source voltage exceeds the MOSFET’s threshold voltage, the switching waveform moves
into region B. The current through the drain source terminals begins to increase at a rate that matches
Figure 1‐13 Turn on voltage and current wave forms for the gate‐source and drain‐source terminals of the MOSFET. The
circuit is assumed to contain an ideal freewheeling diode.
Figure 1‐14 (a) A power MOSFET IV curve showing the path a turn on transition follows; (b) linearized transfer curve of a
power MOSFET.
15
Figure 1‐15 Equivalent circuit used for turn on current and voltage characteristics of MOSFET in a diode‐clamped inductive load circuit. (a) equivalent circuit for region A; (b) equivalent circuit for region B; (c) equivalent circuit for region C; (d)
equivalent circuit for region D; (e) equivalent circuit for region E.
16
the linearized transfer curve, as seen in Figure 1‐14b. Even while current through the MOSFET rapidly
increases, the voltage drop across the drain‐source terminals of the MOSFET will maintain a constant
voltage of approximately VD. Until the iD(t) is equal to Io, the freewheeling diode, DF, will conduct the
additional current and will therefore maintain a negligible voltage drop.
Once iD(t) reaches IO, the freewheeling diode turns off and the voltage across the MOSFET begins
to drop. In this stage of turn‐on, region C, the gate current and gate voltage are temporarily clamped,
with
Thfs
OIGS V
g
IV
O, , (1-8)
G
IGSGGDCG R
VVi O,
),(
. (1-9)
This clamped current dictates the rate of voltage drop across the drain‐source terminals of the power
MOSFET as follows:
.,
GDG
IGSGG
GD
GDSDG
CR
VV
C
i
dt
dv
dt
dvO
(1-10)
The transition from region C to region D indicates the MOSFET traversing from the active region of
operation to the ohmic region of operation as seen in figure 1‐15d. Additionally, the value of internal
capacitance, CGD, is largely dictated by the value of voltage across the drain‐source terminals of the
MOSFET. As the voltage across the drain of the device decreases to a potential that is on the order of
VTh, CGD rapidly increases.
When the drain‐source voltage becomes stable, in region E, the gate voltage becomes
unclamped and proceeds with its exponential growth to the value, VGG. The time constant, τG, is still
described with equation 2, but because CGD has greatly increased in value, this second stage of gate
voltage exponential growth is slower than in regions A and B. Gate current exponentially decays to
zero during this final period, as described in equation 1‐5.
Voltage/Current Ringing
For the analysis of MOSFET turn on discussed above, the freewheeling diode is assumed to be
ideal and there are no parasitic inductances included. These two aspects of the circuit cause current and
voltage ringing in the converter during real hard switching. As the circuit moves from region B to region
17
C of the switching waveform, the freewheeling diode turns off. When the diode turns off, the additional
charge inside the diode, referred to as reverse recovery charge, Qrr, gets swept out. This swept charge
causes a current spike that is forced to flow through the MOSFET. The surge in extra energy rings in the
circuit and the magnitude and time of ringing is dependent on resistive, capacitive, and inductive
components of the circuit[16]. Energy dissipation caused by this oscillation can be quantified as
DossrrDturnonring VQQVE2
1_ (1-11)
where Qrr is the reverse recovery charge that is swept out of the freewheeling diode and Qoss is the
charge stored on the output capacitance of the MOSFET,
DSDSGDDSossoss VCCVCQ )( . (1-12)
Consequently the output capacitance will cause additional power dissipation during hard switching.
Figure 1‐16 Turn off voltage and current wave forms for the gate‐source and drain‐source terminals of the MOSFET.
18
Turn Off Transition
The same analytical approach can be used to find the turn off wave form as was used for the
turn on waveform, with the inverse sequence of events occurring in the turnoff waveform. Figure 1‐16
shows the turn‐off currents and voltages.
Switching the gate voltage to negative values is a way of taking advantage of the shielding
effect, and reducing CGD to its minimum value. This affects the gate’s turn off time constant and allows
the turn off wave form to switch faster. Changing the value of gate resistance is another way to force
the turn‐off switching time to be different from the turn‐on time[4].
1.3.2 Soft Switching
During a power converter’s typical operation, the power MOSFET suffers conduction and
switching losses. Over the past several decades, power density has become a driving performance
characteristic for many different power applications. Higher power densities are largely achieved with
higher frequency circuitry. With standard hard switched, pulse width modulated (PWM) circuits the
optimal switching frequency is 30‐50kHz, which puts an upper threshold on the power density of such
circuit topographies[17]. At higher frequencies, the power loss during switching becomes the dominant
problem. Zero current switching (ZCS) and zero voltage switching (ZVS) techniques were developed to
overcome this issue by greatly reducing switching losses. These switching techniques have the common
title of soft switching techniques.
Figure 1‐17 (a) Current‐mode resonant switch (b) Voltage‐mode resonant switch
In general, ZCS uses a current mode resonant switch. This entails having three terminal
switching device, such as a power MOSFET, in series with an inductor and this switch and inductor are
the placed in parallel with a capacitor, as shown in Figure 1‐17a [18]. ZVS uses a voltage mode resonant
switching with the switch in parallel with a capacitor and these two components in series with an
inductor, shown in Figure 1‐17b. The following section describes ZVS for a simple boost converter and
how the parasitic capacitances of power MOSFETs affect the efficiencies of such circuits.
19
Zero Voltage Switching
Figure 1‐18a shows a basic DC‐DC boost converter with a voltage mode resonant switch, and
Figure 1‐18b shows a simplified version of this circuit. The internal, anti‐parallel diode of the power
MOSFET, D1, causes this circuit to be operating in the half‐wave mode because it clamps the voltage
across the capacitor, CR, to a minimum value. The circuit’s behavior is largely determined by the values
of LR and CR, the following parameters are defined:
,r
rn C
LZ (1-13)
,1
rrCL (1-14)
and .0
nZ
Rr (1-15)
where Zn is the characteristic impedance, ω is the resonant angular frequency, and r is the normalized
load resistance.
Figure 1‐18 DC‐DC boost structure (a) with voltage mode resonant switch; (b) simplified input and output terminations
20
The zero voltage switching cycle can be broken up into four stages. The first stage is the
capacitor charging stage. Starting at time, t0, the voltage, VC, across the power MOSFET and CR is zero
and the MOSFET is switched off. The gate source voltage of the power MOSFET drops exponentially,
with a time constant that is consistent with Equation 1‐7 of the previous section. The voltage drop
across the MOSFET is dictated by the charging capacitor, CR, rather than the hard switching turn‐off
voltage waveform, so vGS(t) does not experience a “plateau” during soft switching. The rate of voltage
increase across the capacitor and MOSFET drain‐source terminals can be described as
R
iC
C
I
dt
dV . (1-16)
when the charging capacitor reaches the voltage value, Vo, at time ti the cycle transitions into the second
stage.
Figure 1‐19 Equivalent circuits of the VZS boost converter during the four switching stages from (a) t0 to t1; (b) t1 to t2; (c) t2 to
t3; (d) t3 to t0.
The second stage is the resonant stage starting at time t1. Once the value of voltage across CR
exceeds Vo, some of the current from source Ii begins to flow through LR, Do, and Vo. The equivalent
circuit is shown in Figure 1‐19b. The current and voltage equations during this period are
))(cos(1()( 0ttItI iL (1-17)
21
and ))(sin()( 0ttIZVtV inoC , (1-18)
assuming that the voltage drop across Do is approximately zero. At VC(t2) the voltage is clamped to
approximately zero by the power MOSFET’s anti‐parallel diode. Current flowing through the inductor at
this transition point is
)cos1()( 2 iL ItI (1-19)
in
o
IZ
V1sin . (1-20)
Once the voltage across the resonant capacitor drops to zero, the power MOSFET is switched on. This
begins the inductor discharging stage. The inductor current decays at a rate
r
oL
L
V
dt
dI . (1-21)
A short pulse of negative voltage circulates through the power MOSFET caused by the reverse recovery
charge stored in the integral diode. The waveform, IM(t) shown in Figure 1‐20 illustrates this negative
reverse recovery voltage. In the fourth and final stage of zero voltage switching, the inductor has
completely discharged and all currents is flow through the power MOSFET.
In summary, the resonant components of ZVS topologies dictate the overall switching
waveforms as oppose to hard switching waveforms which are largely dictated by the capacitance of the
MOSFET used. The input gate waveforms are still largely dictated by input capacitance, CGS and CGD, for
soft switching converters, but less emphasis is placed on those waveforms because output response is
no longer directly linked to the input[12]. Additionally, as observed from figure 1‐20, the voltage across
the MOSFET is always zero while the MOSFET is on, greatly reducing the switching losses and the
stresses the power MOSFET has to tolerate.
Parasitic Capacitance Loss Effects
The most significant contribution to switching loss during soft switching are the parasitic
capacitors, which causes the voltage/current ringing that is somewhat similar to the ringing described in
the hard switching section. As mentioned above, when the ZVS circuit transitions from the second to
the third stage of operation at t = t2, the MOSFET turns on and the internal diode of the power MOSFET
no longer conducts current. The reverse recovery of this internal diode causes a negative spike in
current, creating high frequency oscillations that are superimposed onto the output current and voltage
22
Figure 1‐20 ZVS waveform during half wave mode operation
waveforms of the power MOSFET. The frequency of these oscillations are based on the magnitude of
the MOSFET’s output capacitance, COSS, and the resonant inductor. The frequency is quantified as,
OSSRCL/1 [19]. Energy lost during this ringing is equal to
2
2
1oOSSonturn VCE . (1-22)
A less significant ringing loss also occurs during MOSFET turn off. The sudden drop in current across the
MOSFET causes the capacitor, CR, to quickly pick up all the current, Ii. But the MOSFET output
capacitance and CR are in parallel, so charge oscillates between the two capacitors and the inductor.
The energy dissipated is approximately
R
OSSoOSSoffturn C
CVCE 2
2
1. (1-23)
23
Again, the ratio of MOSFET output capacitance to resonant capacitance is typically small, so this value of
dissipated energy is usually trivial compared to turn‐on power loss. But as converter circuits are pushed
to higher and higher values of frequencies, these losses become more prevalent not only because
switching events occur more frequently but because the resonant capacitor, CR, is reduced in value.
1.4 Limitations of the Power MOSFET and SiC Devices
As mentioned in the introduction of this thesis, even though power MOSFETs have the best
switching characteristics, as a silicon device, power MOSFETs have a blocking voltage upper limit of
about 1kV. As the blocking voltage of a power MOSFET increases, the on‐state resistance must also
increase. This blocking voltage to on‐state resistance relationship is a function of the physical limitations
of silicon. Therefore, in order to push capabilities of power MOSFETs to higher currents and voltage
ratings, a new semiconductor material must be used. The following sections summarizes the
relationship between on‐state resistance and breakdown voltage, and presents the properties of SiC
which cause it to have significantly improved blocking voltage characteristics.
1.4.1 Blocking Voltage and RDSON
When a power MOSFET is in forward blocking mode, as depicted in Figure 1‐2c, the MOSFET
carries all the blocking voltage across the p‐n junction of the body and drift regions. With increasing
values of voltage, the depletion region’s electric field at the p‐n junction will increase. Figure 1‐21
shows the electric field potential at a one dimensional p‐n junction.
Figure 1‐21 Electric field distribution across a planar p‐n junction, with a doping profile similar to one of a power MOSFET.
Avalanche breakdown is the phenomena that limits the maximum operating voltage for power
devices. Carriers that are accelerated through the depletion region’s electric field attain enough energy
24
to generate additional electron‐hole pairs by passing their energy to an electron that exists in the
valence band of the semiconductor. Assuming that voltage is only supported by the lightly doped drain
side of the structure, the depletion width and doping concentration of the drain can be defined with the
equations,
CD E
BVW
2 (1-24)
and qBV
EN CSD 2
2 , (1-25)
where BV is the blocking voltage of the p‐n junction and EC is the critical electric field of the
semiconductor material[6]. Specific resistance of the drift region is then limited by blocking voltage and
critical electric field,
3
2
,
4
CnSDn
Dspon E
BV
Nq
WR
. (1-26)
Therefore, increasing values of on blocking voltage rapidly increases the resistance of the drift region in
a MOSFET device. This issue affects all majority carrier devices.
1.4.2 Silicon vs. Silicon Carbide
Table 1‐1 shows some of the material properties of silicon and silicon carbide[8]. High values of
breakdown electric field give SiC the ability to block much higher voltages. Additionally, larger band gap
and higher thermal conductivity make solid state devices made from SiC better suited for high
temperature applications[20]. Higher values of thermal conductivity and saturation drift velocity also
make SiC devices posses better fault tolerances.
Table 1‐1 Table showing differences between the properties of silicon and the properties of silicon carbide.
Semiconductor material
Energy Bandgap (eV) Breakdown Electric
Field (V/cm) Thermal Conductivity
(W/m•K) Saturated Electron
Drift Velocity (cm/sec)
4H‐SiC 3.26 2.2•106 380 2.0•107
Si 1.12 2.5•105 150 1.0•107
The importance of CV measurements with regards to MOSFET switching properties has been
demonstrated in this section of the thesis. Power MOSFETs with ratings of up to 10kV have been
developed from SiC, and it is important now to have the capability to perform high voltage CV
25
measurements on these devices which encompass its full voltage blocking range. The remaining
sections of this thesis discuss the circuit system that was built and validated to perform accurate, high
voltage CV measurements. The system is automated to simplify and speed up the measurement
process.
26
Chapter 2 : High Voltage, CapacitanceVoltage Circuit and
Analysis
2.1 High Voltage Circuit Layout
The circuit layout for the high voltage, capacitance‐voltage, HV CV, apparatus is shown in Figure
2‐1, and Table 2‐1 displays the static component values of the circuit. Capacitor and resistor values not
listed in this table are subject to change for different experiments. The complexity of this circuit arises
because the Agilent 4284A LCR meter, or any other three terminal LCR meter available, is voltage
sensitive and cannot withstand applied, DC voltages on the order of 1kV or more. The goal of this
equipment is to achieve CV measurements that can apply blocking voltages of up to 5kV across the
drain‐source terminals of a SiC power MOSFET. Therefore, protection circuitry must be added to keep
these high voltages away from the LCR meter. This quickly sets hurdles in what would otherwise be a
fairly straight forward measurement.
Figure 2‐1a shows the main CV system, which attaches to the circuit shown in Figure 2‐1b at
terminals CM1 and CM2. The main CV system consists of six connection terminals that are used to
generate the three capacitance measurement configurations; CGD, CDS, and CGS. Two voltage sources
control the voltages, VGS and VDS, and two voltage meters measure the voltages of these terminals as
current leakage through the MOSFET terminals will cause supplied and measured voltage values to
deviate. For low values of VDS, output 1 of the E3647A Dual Power Supply is used. For high voltage
measurements, the PS350 High Power Supply is used. The E3647A power supply must be used for low
voltage measurements because the PS350 Power Supply as a lower voltage limit of 40V. Voltage applied
at the gate‐source terminals should have a maximum threshold of about ‐20V, so output 2 of the
E3647A Dual Power Supply is always used to control VGS. Resistors are placed in series with the voltage
meters to suppress any small signal noise that the voltage meters generate. The resistors in series with
the Keithley 2010 serve an additional purpose; the floating voltage values on the low and high input
terminals of this voltage meter are limited to 500V and 1000V, respectively[21]. The internal resistance
of this device is 10MΩ, so a 100MΩ resistor is placed in series with the high terminal and a 10MΩ
resistor is placed in series with the low terminal to ensure that there is no chance of damaging the
meter with an overvoltage. These resistors also keep current levels at the Keithley terminals at a
27
minimal level to ensure safety. The output voltage reading is normalized in the software to compensate
for these series resistors.
Figure 2‐1 High voltage capacitance‐voltage circuitry; (a) main circuitry showing terminal points, voltage supply, voltage meter and DC blocking capacitors; (b) hookups to LCR meter and diode bridge
Table 2‐1 Component values of circuit shown in Figure 2‐1 which remain constant for all forms of testing.
Device Circuit
C1 1mF
C2 1mF
R3 3.3kΩ
R4 3.3kΩ
R5 330Ω
RD 3MΩ
RG 3MΩ
28
Capacitors, CCD and CCG, block the high power DC voltage from the terminals of the LCR meter. If
the device should suddenly fail during a high voltage capacitance measurement and a short develops
between the drain and source terminals or the drain and gate terminals of the MOSFET, there will be a
large, transient pulse in energy that will pass from the terminals of one blocking capacitor to the other.
This sudden change in charge of the capacitors will induce a current. The resistors, RCD and RCG, exist in
this circuit to control the magnitude of this current during a possible failure, and the purpose of the
diode bridge shown in Figure 2‐1b is there to prevent this current from reaching the LCR meter. The
additional circuitry consisting of R3, R4, C1, C2, and the AC adaptor are present to ensure that the diode
bridge is always in reverse bias during normal circuit operation and, therefore, this bridge’s impedance
is always very high. This minimizes the bridge’s effects on the CV measurement.
Table 2‐2 describes all three allowed terminal connections for each type of MOSFET capacitance
measurement that can be performed. These six terminal connections allow for the flexibility to utilize
one basic circuit to accurately measure all different forms of capacitance in a MOSFET or any other three
terminal devices with a high impedance switch input, such as an IGBT or GTO. The following sections
give a brief overview of the operation of each configuration.
Table 2‐2 Terminal Connections for each type of CV measurement to be performed on a power MOSFET.
TEST TERMINAL CONNECTS TO:
CGD
1 42 Gate3 65 Drain6 Source & 3
CDS
1 42 Source3 65 Drain6 Gate & 3
CGS
1 62 Gate3 45 Drain6 Source & 1
2.1.1 CGD Configuration
For a gate drain capacitance measurement, the source of the MOSFET is attached to the
shielded ground of the Agilent LCR meter (denoted terminal 3 in Figure 2‐2 and Table 2‐2) and terminal
29
6. Terminal 5 connects to the drain of the MOSFET for this configuration and all other configurations,
and the gate connects to terminal 2. Output 2 of the E3647A Dual power supply applies voltage at the
gate and since the source terminal is grounded, VGS equals VG. The same is true for the drain voltage;
voltage applied at the drain terminal is equal to VDS.
Figure 2‐2 Configuration for CGD measurements.
2.1.2 CDS Configuration
Comparing Figures 2‐2 and 2‐3, the CDS and CGD configurations look very similar. Only the gate
and source terminals of the MOSFET swap places, the rest of the terminals remain the same. However,
the way in which the CDS measurement is performed is very different from the way the CGD measurement
is performed. Instead of applying a negative value of voltage at the VG terminal of the MOSFET to
achieve negative VGS, a positive value of voltage is applied to source to get the equivalent potential
between these two terminals. Therefore, the terminals of output 2 of the E3647A Dual Power Supply
need the opposite polarity used in the CGD measurement to achieve the same values of VGS.
Figure 2‐3 Configuration for CDS measurements.
30
Applying non‐zero voltage potentials at the source terminal of the MOSFET will affect the value
of VDS. So when measuring VDS the voltage output of the Keithley 2001 has to be subtracted from the
voltage output of the Keithley 2010. Additionally, the change in potential applied at the source also has
to be applied at the drain to change the value of VGS, but keep VDS constant.
2.1.3 CGS Configuration
At first glance, Figure 2‐4 appears to be an unworkable circuit. Based on this crude circuit
diagram, none of the MOSFET terminals are grounded. But what is not obvious in these diagrams is that
the low terminal of the LCR meter, terminal 1 in this circuit, is a virtual ground. So even though the
source terminal appears to be floating, the voltage potential on the source will always be zero or nearly
zero during CGS testing. In this situation, voltage is directly applied at the gate and drain terminals with a
grounded source.
Figure 2‐4 Configuration for CGS measurements.
Figure 2‐5a shows the entire system, with voltage meters and source on the left of the picture,
and the HV CV circuitry all contained in the plastic box on the left of the picture. The LCR meter resides
behind the circuit box. Figure 2‐5b shows a close up of the CV apparatus and Figure 2‐5c shows the
terminals where the MOSFET can be attached for measurement.
2.2 Analysis CapacitanceVoltage Measurement System
After developing a wiring diagram for the HV CV circuit, it was necessary to verify that the
additional passive and active components of this circuit would not cause inaccuracies in the capacitance
data taken by the LCR meter. The following sections examine the method the LCR meter performs
31
measurements, the total impedance of the whole measurement system, and the equations developed
to describe the system’s overall accuracy.
Figure 2‐5 Pictures of the built HV CV circuit. (a) Complete system with voltage sources, meters, and HV circuit box. (b) A
closer look at the HV circuitry. (c) Circuit terminals where the MOSFET attaches to the apparatus.
2.2.1 A Look at the Agilent 4284A LCR Meter
The Agilent LCR meter has two input terminals, high and low. Figure 2‐6 shows a crude diagram
of how the LCR meter measures impedance[22]. An AC voltage with a user determined frequency is
applied to the high terminal connection and the change in voltage is monitored at this high terminal.
The change in current is monitored at the low terminal connection. Because there is a virtual ground at
the low input terminal, any impedance from the low input terminal to shielded ground is shorted, and
no current will flow through ZL. The impedances ZMSR and ZH are now in parallel. The voltage across ZMSR,
and its corresponding current are unafffected by ZH. The derivative of impedance with respect to time,
ZMSR is simply
32
1
dt
dI
dt
dV
dt
dZMSR . (2-1)
Using this simple calculation, all manner of information concerning device impedance can be derived.
Figure 2‐6 Basic sketch of Agilent LCR measurement method.
2.2.2 Accuracy Analysis of CV circuitry
There are many components, passive and active, that make up this circuit. These components
could have an effect on the total accuracy of the LCR impedance measurement. It is important to come
up with a strategy to ensure that, regardless of MOSFET’s capacitance, the measured CV data is accurate
to within a certain, known percentage. The following analysis evaluates impedances of CGD
configuration, but the general approach to examining circuit impedance is used to develop similar
accuracy calculations for all MOSFET capacitance configurations.
Figure 2‐7a shows the CGD circuit with all of the associated impedances and Figure 2‐7b is a
schematic of the reduced equivalent circuit. The impedance of the diode bridge, denoted with RPROT and
CPROT, have no effect on the overall capacitance measurement, as was described by section 2.2.1.
However, impedances ZCCD and ZCCG are not in parallel with the measured impedance, shown in Figure 2‐
8, and will cause CV measurements to suffer some inaccuracies. If the impedance branches ZGS and ZDS
were not present, the static values of ZCCD and ZCCG could simply be subtracted out of the final
measurement. But the dynamic value of ZGS and ZDS cause the overall effect of ZCCD and ZCCG to be
unpredictable. The effect of ZCCD and ZCCG are examined separately.
33
Figure 2‐7 Equivalent circuit diagrams for the CGD configuration; (a) a complete diagram showing the more complex
components of the circuit as basic equivalent devices; (b) a condensed equivalent circuit that groups reducible elements of impedance.
ZCCD
AC current flowing through the drain coupling capacitor and coupling resistor will cause a
voltage drop between CGD and the virtual ground. Therefore, the parallel ZDS branch will have an equal
voltage and some of the current, IGD, will be diverted from reaching LCR’s internal am meter, depicted in
34
Figure 2‐8. The ratio of current that is diverted from LCR’s terminals is can be described with a current
divider equation,
CCDDS
DSGDLCR ZZ
ZII . (2-2)
We must also take into consideration the voltage drop across ZCCD,
DSCCD
DSCCDGD
GDTOTGD
ZZ
ZZZ
ZVV
(2-3)
where VTOT is the voltage drop across both ZGD and ZCCD. Based on these equations, the smaller ZCCD is
compared to ZGD and ZDS, there is less voltage across ZCCD and current diverted from the LCR meter.
Therefore, it is desirable to have large values of ZDS. Out of all impedance components that make up ZDS,
the internal MOSFET capacitance, CDS, will typically have the smallest impedance. Resistors RD and RDMSR
have values on the order of several megohms. Consequently, the larger the value of CDS, the more
current is diverted from the LCR’s terminal and the less accurate the LCR’s measurement will be.
Figure 2‐8 A simplified version of the CGD configuration connected with the LCR meter, showing the series impedances, ZCCG
and ZCCD, and highlighting the effects of ZCCD on the impedance measurement.
ZCCG
Focusing on the effects caused by ZCCG, the circuit in Figure 2‐9 is used. In order to reduce the
voltage across ZCCG, the equivalent impedance of ZGD in parallel with ZGS must be much larger than ZCCG.
Solving the voltage divider in terms of VGD and VOC gives the transfer function
35
GSGD
GSGDCCG
OCGD
ZZ
ZZZ
VV
1
. (2-4)
The larger ZGD and ZGS are compared to ZCCD, the smaller the voltage across ZCCG will be. Similarly to the
discussion above on ZCCD, the value of ZGS is chiefly dictated by the value of CGS other impedances in
parallel with CGS, will be much larger than CGS for most measurement situations.
In summary, the presence of ZCCD within the circuit reduces the current that the ammeter reads
and the effects of ZCCG causes the voltage across the device under test to be larger than it should be.
Both of these effects cause the LCR meter to inflate the true value of the MOSFET’s impedances, causing
these capacitance measurements to be smaller than the true MOSFET interelectrode capacitances.
Figure 2‐9 A circuit diagram which highlights the effect of ZCCG on the impedance measurement.
The total accuracy of an LCR measurement taken with this circuitry can be derived using
Equations 2‐2, 2‐3 and 2‐4. If these equations are normalized by dividing them by ILCR, VGD and VOC,
respectively, and then one multiplies the results of each calculation together, the product gives the
accuracy of the measurement,
DSCCD
DSCCDGD
GD
GSGD
GSGDCCG
CCDDS
DS
ZZ
ZZZ
Z
ZZ
ZZZ
ZZ
ZAccuracy
1
1, (2-5)
Re* AccuracyCC ACTUALMEASURED . (2-6)
Now that an equation for accuracy has been developed, it must be confirmed that this will predict
accuracy of a capacitance measurement.
36
2.3 Verification of Accuracy Analysis
Equation 2‐5 is verified by conducting a controlled measurement with a network of three
capacitors all connected with one another. This simulates the interelectrode capacitance within a
MOSFET in a static way so we can determine whether or not the predicted accuracy is on target with the
measured accuracy of MOSFET capacitance.
The exact value of each of the capacitors is measured directly with the LCR meter, not using the
high voltage CV circuitry. These capacitance values are recorded and then the three capacitors are
connected to one another so that each capacitor resembles terminal to terminal MOSFET capacitance.
A picture of this capacitance network is shown in Figure 2‐10. The capacitors’ impedance is again
measured, this time using a prototype high voltage CV circuit with the circuit values shown in Table 2‐3.
The frequency used to perform the measurement was 20kHz.
Figure 2‐10 Three film capacitors soldered together to create a network that replicates MOSFET capacitance.
Finally, the precision of the HV CV apparatus is calculated using Equations 2‐5 and 2‐6. MATLAB
programs were developed to calculate the accuracy of each circuit configuration based on real HV CV
circuit values and the fixed values of MOSFET internal capacitance. The program makes bode plots of
the magnitude and phase of the measurement precision over a frequency range of 1‐100kHz. Figure 2‐
11 show the results of these MATLAB calculations. These graphs display the normalized accuracy of a
measurement. Thus, for a given frequency, results displaying a magnitude of 0.92 and a phase of nearly
zero means the accuracy of such a measurement would be 92%. The complete MATLAB scripts can be
found in Appendix A. Table 2‐4 summarizes the comparison of measured and calculated accuracy.
The calculated and measured accuracies are all within 1% of each other. An explanation as to
why these two values are not closer together is because the exact CV circuit values, such as the coupling
capacitors, CCD and CCG, were not measured. The tolerances for the coupling capacitor values are as
much as 10% which could certainly have some effect on the exactness of the prediction. Even so, with a
37
Figure 2‐11 Bode plots showing the calculated accuracy of each CV configuration for the devices values stated in Table 2‐3.
38
Table 2‐3 Component values of prototype high voltage CV circuit.
Prototype HV, CV Circuit
CCD 0.1µF
CCG 0.1µf
RCD 2.7Ω
RCG 2.7Ω
RD 3MΩ
RG 3MΩ
CGS 3.929nF
CDS 1nF
CGD 3.037nF
maximum offset between measured and calculated accuracy of only 1%, it is reasonable to assume that
the equation developed to predict the accuracy of this high voltage CV circuit is correct.
Table 2‐4 A summary of measured and calculated capacitance values.
Capacitor Real Capacitance
Measured Capacitance
Accuracy of Measurement
Calculated Accuracy
CGD 3.037nF 2.726nF 89.76% 89.86%
CDS 1.000nF 0.9219nF 92.19% 91.60%
CGS 3.929nF 3.698nF 94.12% 93.56%
The larger the MOSFET’s capacitance, the larger the coupling capacitors must be in order to
achieve precise measurements. Figures 2‐12a and 2‐12b are an example of this. The capacitors in Table
2‐3 are all on the order of 1‐4nF. Increasing these capacitance values by and order of magnitude, to 10‐
40nF, significantly affects the correctness of the CV measurement, as shown in figure 2‐13a. The values
of the coupling capacitors must be increased to compensate for larger MOSFET capacitance. In Figure 2‐
13b, the coupling capacitors are increased from 0.1µF to 1µF, and the accuracy of the measurement
returns to a more acceptable value.
2.4 Cost and Benefit of High Voltage CV Accuracy
As mentioned in the previous section, the lower the impedance associated with the coupling
capacitors, the greater the accuracy of the CV measurement. Based on this assessment, it would be
easy just to find the largest value capacitor with a 5kV rating available, apply it to the CV circuit, and
assume that this is the optimal solution. However, this approach raises several issues. One issue is that
larger coupling capacitors will increase the RC time constant of the circuit. Larger RC time constants
mean more time will be needed to allow the voltages to reach steady state as input voltages are
39
changed. Most importantly, large capacitors with high voltage ratings are big and expensive. They are
also dangerous. Energy stored on a capacitor is
2
2
1CVE , (2-5)
so the larger the value of capacitance the more energy which the capacitor stores and could possibly
Figure 2‐12 Accuracy of a CGD measurement with MOSFET capacitances increased by an order of magnitude; CGS equal to 39.29nF, CDS equal to 10nF, and CGD equal to 30.37 nF, (a) with CCD and CCG equal to 0.1µF and (b) with CCD and CCG equal to
1µF.
40
discharge all at once. This puts the connected passive and active elements of the CV circuit at risk if
there is a failure and it also puts circuit users at risk if they are managing parts of the circuit before,
during, or after a measurement has been performed.
Safe operation of the measurement system, a major priority at NIST, is a criteria in the selection
of circuit components. When the final version of this circuit was built, the engineers at NIST put many
levels of protection into this measurement apparatus to ensure the safety of the user is never comprised
during a high voltage measurement. Even so, one has to question the acceptable risk versus
measurement accuracy. To obtain a measurement accuracy of 99%, the values of the capacitors are five
times larger than the capacitors needed to obtain an accuracy of 95%.
Overall, this situation proves the usefulness of the accuracy calculation beyond simply validating
the circuit. MOSFET capacitance is generally the largest for small values of drain and gate voltages.
Knowing this, preliminary low voltage CV measurements can be made using large values of coupling
capacitance. Based on the low voltage capacitance measurements, and using the MATLAB scripts shown
in Appendix A to perform accuracy calculations, the best case values can be established which minimizes
energy stored in the circuit while providing acceptably accurate data.
41
Chapter 3 : High Voltage CV Measurement Software and
User Interface National Instruments’ Labwindows/CVI, referred to in this thesis simply as CVI, is the software
program used to control the network of meters and voltage sources that execute an automated CV
measurement. CVI is a powerful C based complier that allows users to write data acquisition code,
develop personalized user interfaces for different acquisition programs, and utilize powerful math
libraries to perform specialized data analysis[23]. Using a General Purpose Interface Bus (GPIB)
controller, the program communicates with the test and measurement equipment, sending control
commands and receiving meter data. The following sections give an overview of how to operate the
CVI interface and brief look at the program structure that controls the HV CV system.
3.1 The CVI Interface
Figure 3‐1 is a screen shot of the graphical the user interface used to control the CV
measurement system. This interactive measurement tool allows the user to setup a measurement
which is then carried out automatically. The user is safely removed from the actual measurement
process. Safety checks built into the software will discontinue the measurement and reset the voltage
sources to zero if certain protection parameters are exceeded. The following sections explain how to
properly setup, run, and save a CV measurement.
3.1.1 CV Measurement Setup
When the program begins running, it first attempts to communicate with all the required meters
and voltage sources. Immediately after the user interface opens, the text box shown at the top left
portion of Figure 3‐1 will display whether or not each instrument is on and connected to the PC. As can
be seen in this text box, all instruments are on except for the PS350 High Power Supply. When
performing low voltage measurements, the high power supply does not need to be on. If this text box
states that any other instruments are not online, the program needs to be closed and the user should
check to make sure that the device in question is on and properly connected to the control computer.
On the bottom, left side of the Figure 3‐1, there is a pull down menu with the title, “Select an
Instrument”. If “E3647A” is selected, the drain and gate voltages are controlled by the low voltage,
E3647A Power Supply which can sweep from 0 to 40 volts. If “PS350” is selected, the drain voltage is
42
controlled by the PS350 HV Power Supply and the gate is still controlled with the E3647A. The PS350
provides voltage input ranging from 40V to 5kV. Using the controls on the bottom right side of Figure 3‐
1, the user can select which measurement to execute. The user specifies what type of capacitance will
be measured and which voltage will be swept. If the “Drain” option is selected on the “Sweep Type”
ring control, the program will sweep through many values of drain voltage while holding the gate
voltage stationary. After completing one full sweep, the gate voltage is “stepped” to the next value and
the drain voltage, again, sweeps through many values. If the “Gate” option is selected the opposite
happens; the gate voltage is swept while the drain voltage remains fixed.
Figure 3‐1 User interface for the capacitance‐voltage measurement system.
After selecting the drain terminal’s voltage supply and the desired type of measurement, the
measurement parameters must be set up. To do this, the user selects the “Attributes” button on the
menu bar, and then selects “Setup Attributes” in the pull down menu. Figure 3‐2 shows the attributes
window that will then appear. In the “LCR Small Signal” box, the frequency and magnitude of the LCR’s
43
AC signal can be adjusted. For high voltage measurements the drain voltage parameters are edited from
the “PS350 HV Power Supply” box. For low voltage measurements, the drain parameters are controlled
with input entered in the “E3647A Dual DC Power Supply, Drain Setup” box. The user specifies the
minimum and maximum voltages applied to the device and the increment voltage step between each
capacitance data point taken. The “Fixed Delay” parameters control the amount of time the program
will pause between applying a voltage to the drain or gate terminals and taking data from the meters.
This allows the circuit and instruments to reach a steady state before retrieving information from the
devices. Typical delay times are on the order of one second for coupling capacitor values that are less
than 1µF. The “Protection” parameter is the upper limit of voltage applied by the power supplies. Even
Figure 3‐2 Attributes window used to edit parameters for a CV measurement.
if the measured voltage has not reached its maximum value, the measurement system will stop
increasing input voltage once the input voltage is greater than or equal to the protection parameter.
The parameters “Slew Rate” and “Multiplier” are not used for any purpose, currently.
44
The “Measurement Error” box contains two parameters; Relative and Delta Error. If the gate or
drain terminals of the MOSFET leak enough current, the measured gate‐source voltage or drain‐source
voltage will be less than the applied voltage provided by the respective power supply. Relative error is a
percentage that the measured voltages are allowed to stray from the supply voltage. Based on the
Relative Error parameter shown in Figure 3‐2, if the applied voltage becomes 40% larger than the
measured voltage, the measurement will cancel. An error message will appear indicating that the
Relative Error has been exceeded and the user will have to either increase the Relative Error or use a
different, less leaky device in order to run the complete measurement.
Ideally, the gate voltage should not change when the drain voltage is being swept. And when
the gate voltage is swept the drain voltage should not change. During the course of each voltage sweep,
the stepped voltage is monitored to ensure that it does not stray by more than a certain percentage
from its starting value. This percentage parameter is the Delta Error value. If the change in stepped
voltage exceeds this specified error percentage, the measurement stops and an error message will
appear, indicating Delta Error has been exceeded. The user then must increase the delta error value or
use a different MOSFET to carry out the measurement. After filling in all required parameters, the
Attributes window is closed. Clicking the “Sweep Gate & Drain” button will begin the measurement.
3.1.2 Monitoring the CV Measurement
Once the measurement process begins the “Busy Light”, which appears at the bottom, far right
of the screen, will change from black to red. For each voltage sweep, the text box will display the sweep
parameters; the step voltage, and the LCR meter’s AC voltage frequency and magnitude. Each CV data
point is plotted in the graph area as the data is received from the meters. The swept voltage starts at
the minimum value, and increases to the maximum value. The data is displayed in the plot area as a
solid purple line. At the maximum value, the voltage is swept back to a minimum value, plotted as a
dashed, green line. By sweeping voltage from the minimum to maximum and then from the maximum
back to the minimum, the user can visually confirm that the fixed delay parameter is large enough. If
the software is iterating through the sweep voltage too quickly, the CV curves will not lay on top of each
other. The curves will likely also appear to be noisy and discontinuous.
Noisy curves may also be the result of low frequency measurements. If the frequency of a
measurement is on the order of 1 kHz or less, the reactive impedance of the Keithley voltage meters
cause noise to propagate to the LCR meter. When the user observes such irregular data, the
45
measurement can be stopped by clicking the “Stop” button located in the bottom, center of Figure 3‐1.
Adjusting the measurement frequency and/or fixed delay should improve the uniformity of the data.
3.1.3 Saving CV Data
Once the program completes all measurements, the Busy Light will return to black. The “Notes
Box” in Figure 3‐1 can be used to add any additional comments about the measurement. This
information will be added to the first line of the saved file. The user saves the acquired data by selecting
the “File” on the menu bar, then “Save Data” on the pull down menu, and then clicking on the “Save
Notes from “Notes Box”
Type of Capacitance Measurement
Type of Sweep
Number of Data Columns
Frequency of Measurement
Total Number of Data Points
Total Number of Sweeps
Number of Data Points in Sweep 1
Input Vds Output Vds Input Vgs Output Vgs Cgs, Cds, or Cds
Number of Data Points in Sweep 2
Input Vds Output Vds Input Vgs Output Vgs Cgs, Cds, or Cds
(a) Bad data point in Vds = 8V sweep.
Cgs
Gate Sweep
5
8000
770
5
154
Input Vds Output Vds Input Vgs Output Vgs Cgs
0 0.00395 0 ‐0.0014 7.57E‐09
0 0.00018 0.2 ‐0.14768 7.68E‐09
0 ‐0.0006 0.4 ‐0.33445 7.80E‐09
(b) Figure 3‐3 Two samples of a saved CV data file; (a) showing a description of each line of a header file and the header for each
voltage sweep, (b) and a real example of a CV data set.
MOSFET C vs. V” option. Subsequently, the user chooses the location to save the data with a standard
browser window that appears.
46
The data is saved in a “.tiv” format, which can be opened with Excel, or Notepad. Figure 3‐3a
gives a short description of each line in the header file. The stored data is divided into sections for each
voltage sweep performed during the data acquisition process. There is a short header for each section,
stating the number of data points taken for the voltage sweep and a description of each data column.
Figure 3‐3b shows an example of the first 13 lines of a real data file. The data acquired from a
measurement will remain stored in the program until the user either starts a new measurement or exits
the program, so data must be saved in‐between each measurement executed.
3.2 The CVI Code
Figures 3‐4 to 3‐7 show flow charts of the primary software functions used to control the CV
measurement system. A complete copy of the measurement code is available in Appendix B. When the
“Sweep Gate & Drain” button in Figure 3‐1 is pressed, the “SweepGateDrainVolt_Func_CGDMSR” is
called. This program runs a loop that iterates through the step voltages. In between these increases in
step voltage, a subroutine is called, “SweepDrain_AnodeVolt” which carries out each voltage sweep.
In SweepDrain_AnodeVolt, the voltage sweep is performed in two loops. The first loop starts at
the minimum value of sweep voltage and raises the voltage to the maximum value. The second loop
starts at the maximum value of sweep voltage and returns to the minimum. Both loops send the value
of sweep voltage to the appropriate voltage source and wait the specified “Sweep Delay” time. Then
the “CvsVPlot” subroutine is called. The purpose of this subroutine is to obtain the output of the voltage
and LCR meters and then save these values into global arrays. SweepDrain_AnodeVolt calls another
subroutine, “CheckError”. This program verifies that offsets of output voltage values are within the
limits of Relative and Delta Error parameters the user entered in the Attributes window. If the limits of
Relative or Delta Error are exceeded, the program will display an error message so the user is aware of
the problem, and then break out of the measurement procedure.
In conclusion, using the CVI environment, the program and user interface developed automate a
measurement process that would otherwise be very tedious and time consuming to complete manually.
This program not only saves the user time, but runs procedures that keep the users and circuitry
protected. When measuring intact MOSFETS, this program only requires the user to develop good
parameters for a successful measurement run.
47
Figure 3‐4 The flow chart describing SweepGateDrainVolt_Func_CGDMSR routine.
48
(a)
49
(b)
Figure 3‐5 Flow chart for SweepDrain_AnodeVolt subroutine, (a) first half of the subroutine, (b) second half of the subroutine.
50
Figure 3‐6 Flow chart for CvsVPlot subroutine.
51
Figure 3‐7 Flow chart for CheckError subroutine.
52
Chapter 4 : Measurement Results
The following section gives the results of three MOSFETs that were tested with the new CV
system. Each subsection below will present data taken from these measurements and be used to assess
some of the MOSFET’s characteristics.
High voltage measurements have not yet been conducted because NIST safety protocol requires
that the system has formal safety approval before it can be operated with high voltages. The system has
gone through a safety review and once the head of Semiconductor Electronics Division, David Seiler,
gives his formal authorization, high voltage measurements can be performed by qualified operators[24].
4.1 The IRF1010N HEXFET
Some of the first measurements performed on the CV system were done with the IRF1010N,
designed and built by International Rectifier. The IRF1010N is a HEXFET with a maximum blocking
voltage, VDSS, of 55V, maximum current, ID, of 85A, and a typical on‐state resistance of 11mΩ[25].
HEXFETs are planar power MOSFETs[6]. Their cell cross section is essentially the same as the VDMOSFET
cross section that was discussed in Chapter 1 of this thesis. Therefore, their CV curves should strongly
resemble the CV curves as they were described in Section 1.2.2. The data sheet for this power MOSFET
give values for capacitances COSS, CISS, and CRSS, where COSS is the sum of CGS and CDS, CISS is the sum of CGS
and CGD, and CRSS is CGD. Results given below match the capacitance values given in the data sheet.
Figure 4‐1a is a chart of the gate‐source capacitance verses drain‐source voltage data.
Capacitance is the lowest when the gate‐source voltage is zero. There is no charge stored between the
gate and source terminals; therefore capacitance is at a relatively constant minimum. The curve for VGS
equal to ‐2V shows a slight increase in the capacitance because positive charge is accumulating in the p‐
body region of the power MOSFET. Based on these measurements, it is apparent that the inversion
threshold of the internal PMOS transistor must be between ‐2 and ‐4 volts, because shielding effects are
observed in the VGS = ‐4V curve. As discussed in Section 1.2.2, increasing the drain voltage of the power
MOSFET mimics the body effect which occurs in lateral MOSFETS. Thus, curves for VGS equal to ‐4 and ‐6
display a sharp decrease as the accumulation later in the lightly n doped drain disappears.
Figure 4‐1b is also a chart of gate‐source capacitance, but for varying values of gate‐source
voltage. The data shown in this graph also strongly resemble predicted trends. When the magnitude of
53
Figure 4‐1 Gate‐source capacitance measurements for the IRF1010N HEXFET. (a) Sweeping the drain voltage, and (b)
sweeping the gate voltage.
gate‐source voltage is low, the capacitance only increases gradually with increasing charge accumulation
in the p‐body. This plot shows very precisely at what gate voltage the inversion layer in the drain region
develops. It also demonstrates how the body effect from applied drain‐source voltage delays the onset
of this inversion layer. Change in threshold voltage is proportional to the root of body voltage[26], and
54
it can be observed that the increase in threshold in these graphs is approximately equal to the root of
the drain‐source voltages. This detail further confirms the postulations made about the effects caused
by inversion of the drain.
Figure 4‐2 Gate‐drain capacitance measurements for the IRF1010N HEXFET. (a) Sweeping the drain voltage, and (b)
sweeping the gate voltage.
55
Figures 4‐2a and 4‐2b are the graphs of the IRF1010N gate‐drain capacitance. The
consequences of expanding depletion at the drain‐oxide interface and shielding effect are seen plainly in
these figures. For increasing values of drain‐source voltage the drain’s depletion width increases,
decreasing the gate‐drain capacitance. Shielding effects cause the gate‐drain capacitances to sharply
descend to a minimum value.
Figure 4‐3 Gate‐drain capacitance measurements for the IRF1010N HEXFET. (a) Sweeping the drain voltage, and (b) sweeping
the gate voltage.
56
Drain‐source capacitance has a negative correlation to increasing values of drain‐source voltage,
since the depletion width of the body‐drain interface increase for increasing values of VDS. However, the
shielding effect causes an increase in capacitance, because it forms a continuous surface charge from
the p‐body region through the drain region of the device. This effectively increases the surface area of
the source. The drain‐source capacitance curves of Figure 4‐3 reflect these MOSFET attributes.
4.2 The IPW60R045CP CoolMos
The IPW60R045CP is a power MOSFET with a voltage rating of 650V. At room temperature, this
device can maintain up to 60A of continuous current and has a maximum RDS,ON of 0.045Ω[27]. The
Infineon CoolMos is a new kind of power MOSFET, which has been on the market for less than a decade.
The CoolMos device uses charge compensation concepts similar to those employed by super‐junction
fast recovery epitaxial diodes[28]. The structure of a CoolMos ultimately reduces the on‐state
resistance of the device by a factor of 4 or 5 compared to other power MOSFETs of similar voltage
ratings[7, 29]. Figure 4‐4a shows a cross section of the CoolMos’s cell structure.
Figure 4‐4 Single cell cross section of CoolMos transistor.
The CoolMos’s most prominent feature is the additional column of p‐type doping that isolates
the more heavily doped n‐type drain column. In this structure, the area of the p‐type body is
significantly increased. This has little to no effect on the overall gate‐source and gate‐drain capacitance
curves, as displayed in Figures 4‐5 and 4‐6. The capacitance curves shown in these two figures look very
similar to the low voltage HEXFET discussed in the previous section. However, the drain‐source
57
Figure 4‐5 Gate‐source capacitance measurements for the IPW60R045CP CoolMos. (a) Sweeping the drain voltage, and (b)
sweeping the gate voltage.
capacitance of a CoolMos is substantially larger than typical CDS values from more traditional power
MOSFET structures. Figures 4‐6a and b are the graphs of drain‐source capacitance. The capacitance
caused by the depletion region between the body and drain boundaries is so large that the effects of
gate‐source voltage are barely observable. In figure 4‐6a, there is a very slight increase in capacitance
58
for more negative values of gate voltage. The onset of inversion in the drain region is most apparent in
the VDS = 0 curve in Figure 4‐6b. As with the results from the IRF1010N power MOSFET, the results
from these measurements match the CoolMos’s data sheet values.
Figure 4‐6 Gate‐drain capacitance measurements for the IPW60R045CP CoolMos. (a) Sweeping the drain voltage, and (b)
sweeping the gate voltage.
59
Figure 4‐7 Drain‐source capacitance measurements for the IPW60R045CP CoolMos. (a) Sweeping the drain voltage, and (b)
sweeping the gate voltage.
60
4.3 The SiC Power MOSFET
Low voltage measurements were performed on one of the SiC power MOSFETs supplied to NIST
by CREE. These SiC power MOSFETs have a voltage rating of 10kV, a maximum current rating of 10A,
and can be switched at a frequency of 20kHz. NIST was assigned the task of characterizing these
prototype MOSFETs. Some of the testing that was conducted on these MOSFETs was stressful to the
device and eventually damaged several of the MOSFET. Some of the results of the following CV
measurements are unexpected, and this may be caused by a characteristic of all SiC MOSFETs, a defect
that had not been resolved in this early prototype MOSFET, or the consequence of some defect that
developed in the device over usage. Further study of a larger pool of devices would be required to
make scientific conclusions.
Based on the CV curves shown in Figure 4‐8, the onset of inversion in the drain happens at a
more negative value of VGS than for a Si based power MOSFET. In Figure 4‐8b, the onset of inversion in
the MOSFET’s drain appears to be occurring at nearly the same values of VGS, even with significant
differences in the VDS. This implies that body effect in SiC devices is less consequential than in Si devices.
The full equation describing body effect is
fSBfth VV 22 , (4-1)
where φf is the Fermi level and VSB is the body voltage[26]. The parameter, γ, is defined as
ASOX
NqC
21
, (4-2)
and the Fermi level is described with
i
Af n
N
q
kTln . (4-3)
The Boltzmann constant is represented as k, and ni is the intrinsic carrier concentration of the
semiconductor. The intrinsic carrier concentration of SiC is very small, on the order of 1*10‐9 cm‐3[6].
Therefore, the energy of Fermi level of a SiC drain region will be much larger than that the Fermi level of
a Si device, making increasing values of VDS less effective at delaying the onset of inversion in the drain
region.
61
Figure 4‐9 shows the curves for CGD measurements. An interesting phenomenon is shown in the
CGD verses VGS curves. During the voltage sweep, the capacitance values do not overlap, regardless of the
magnitude of time delay applied to the measurement. The value of capacitance is substantially lower
during the sweep from 0 to ‐7 volts than measurements taken during the sweep from ‐7 to 0 volts.
Figure 4‐8 Gate‐source capacitance measurements for a high voltage SiC power MOSFET. (a) Sweeping the drain voltage,
and (b) sweeping the gate voltage.
62
This spreading of measured capacitance values for a given value of gate and drain voltage could
be due to mobile ions which exist in the oxide layer of the device[11]. Charge that is trapped in gate
oxide can move. As they shift closer or farther from the surface of the semiconductor, their effects on
the applied gate voltage can be sizable. Based on the experimental observations, the mobile charge
Figure 4‐9 Gate‐drain capacitance measurements for a high voltage SiC power MOSFET. (a) Sweeping the drain voltage, and
(b) sweeping the gate voltage.
63
is coming from a negative ion impurity. Understanding exactly which impurity has created this effect
would require a detailed knowledge of the device’s fabrication.
Another possible explanation for this occurrence is traps that could exist at the SiC/SiO2
interface. If oxide traps exist, other characteristics of the device, such as the threshold voltage, would
appear to be instable[30].
Figure 4‐10 is a graph of CDS verses VDS. A gate‐source voltage sweep could not be performed at
the time of this device’s testing. The results of this test are extremely unpredictable and no reasonable
explanation for the device’s behavior can be provided at this time. There is no correlation between the
value of gate‐source voltage and the measured capacitance. Further investigation of this measurement
will require analyzing more SiC MOSFETs that have not already been exposed to other stressful testing.
In summary, the results of all measurements taken on these three devices prove a number of
arguments. Measurements made on the IRF1010N confirm what is already known about VDMOSFETs.
Further insight for less established devices, like the CoolMos, can be provided with these
measurements. For novel structures, like the SiC MOSFET, these CV measurements can be used to
define some of the more fundamental device characteristics, and influence of defects on the device
performance.
Figure 4‐10 Drain‐source capacitance measurements for a high voltage SiC power MOSFET.
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 5 10 15 20 25 30Drain Source Cap
acitan
ce, n
F
Drain Source Voltage, V
CDS verses VDS
Vgs = 0 V Vgs = ‐2 V Vgs = ‐4 V Vgs = ‐6 V Vgs = ‐8 V
64
Chapter 5 : Conclusions and Future Work
Power electronics is a field that will continue to grow in scope and importance as efficient
energy production becomes more critical to sustain an electrified culture. The development of good
power electronics starts with adequate power devices. Characterization, including accurate CV
measurements, is essential to validate these power devices. This high voltage, capacitance voltage
measurement system is a small part of a major strategy to make our electric civilization cleaner and
sustainable. The direct contributions and capabilities of the high HV, CV measurement system are:
Performs six different MOSFET capacitance measurements
Drain sweep for CGD, CGS, and CDS
Gate sweep for CGD, CGS, and CDS
Can safely carry out high voltage measurements of up to 5kV
Utilizes accuracy analysis to ensure capacitance measurements are within a user
determined precision
Automation of measurement procedure for speed and ease of use.
The contents of this thesis cover the development of this CV measurement system. Chapter
summarizes the circuitry that was built to perform measurements for three different forms of MOSFET
capacitance, CDS, CGD, and CGS. This circuitry is capable of safely executing low voltage and high voltage
measurements. Analysis of the circuit’s accuracy confirms that this circuit can be made to complete
accurate measurements. By utilizing the equations developed in Chapter 2 of this thesis the user can
easily optimize accuracy and safety based on the approximate magnitude of the measured MOSFET’s
capacitance.
Making use of the capabilities of the software package, CVI, the process of acquiring large
amounts of CV data is greatly simplified with computer automation. Operation of the CV measurement
user interface was discussed in detail and an overview of the developed programming is covered in
Chapter 3.
Some of the first low voltage measurements this measurement system performed are presented
in Chapter 4. These measurements highlight what is already understood about capacitance behavior in
silicon power MOSFETs, and demonstrate how important capacitance measurements will be for
characterizing innovative SiC power MOSFET designs.
This measurement system was designed specifically for characterizing SiC MOSFETs. Once the
65
system is given approval to execute high voltage measurements, the full range of a SiC MOSFET’s
operation voltage range can and will be tested.
While the primary motive for developing this system is for characterizing SiC MOSFETs, the full
utility of an flexible, automated CV measurement system that can measure a wide range of voltage
values is virtually limitless. As discussed in Chapter 1 of this thesis, the power MOSFET capacitance
heavily influence the efficiency of both hard and soft switching procedures. Typical data sheets provide
curves for input and output MOSFET capacitance that are only dependant on applied drain‐source
voltages. The measurement results from Chapter 4 prove that applied gate source voltage will have
strong influence on capacitance values, particularly at low values of drain source voltage. During zero
voltage switching, switching events occur with little to no voltage applied across the drain source
terminals of the device, thus better models for MOSFET capacitance would be appropriate.
With respect to zero voltage switching, good equivalent models for output MOSFET capacitance
could make parallel, resonant capacitors unneeded. Removing the resonant capacitor from a zero
voltage switch architecture would simplify the circuit, allow for increased switching frequency, and
reduce the cost of construction. Developing equivalent capacitor models would be greatly simplified
employing the capabilities of the CV measurement system, since data acquisition is no longer a
protracted step in the modeling process.
The CV measurement system, as it currently is setup, adequately fulfills the requirements of its
intended purpose. Additional features could always be added to make the measurement procedure
even more straightforward, such as the integration of the MatLab code into the CVI software so that the
user has an estimate of the measurement accuracy during or immediately after completing
measurements.
One improvement that would greatly increase the ease and speed of measurements is replacing
the current low voltage source with a bipolar low voltage source so that voltage values can be swept
from a negative to a positive value and vice versa. Currently, if a user wishes to sweep through positive
gate values or negative drain values, the polarity of the input voltage terminals much to reversed and a
separate measurement must take place. A bipolar voltage supply for the gate and drain would speed up
total measurement time and simplify data analysis.
66
References
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USA: John Willey & Sons, Inc., 2003. [5] Sulzer, "Carbon Capture and Storage: Putting a Chill on Global Warming," 2008. [6] B. J. Baliga, Fundamentals of Power Semiconductor Devices. New York: Springer, 2008. [7] L. Lorenz, G. Deboy, A. Knapp, and M. Marz, "COOLMOS
TM ‐ A New Milestone in High Voltage Power MOS," in Power Semiconductor Devices and ICs, Toronto, Canada, 1999, pp. 3‐10.
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2.7V," in IEEE International Symposium on Power Semiconductor Devices and ICs, 1996, pp. 53‐56. [11] R. F. Pierret, Semiconductor Device Fundamentals. Reading, Massachusetts: Addison Wesley Longman, 1996. [12] I. K. Budihardjo, P. O. Lauritzen, and H. A. Mantooth, "Performance Requirements for Power MOSFET Models," IEEE
Transactions on Power Electronics, vol. 12, pp. 36‐45, January 1997. [13] C. E. Cordonnier, "SPICE Model for TMOS," Motorola Application Note 1989. [14] I. K. Budihardjo and P. O. Lauritzen, "The Lumped‐Charge Power MOSFET Model, Including Parameter Extraction,"
IEEE Transactions on Power Electronics, vol. 10, pp. 379‐387, May 1995. [15] R. S. Scott, G. A. Franz, and J. L. Johnson, "An Accurate Model for Power DMOSFETs Including Interelectrode
Capacitances," IEEE Transactions on Power Electronics, vol. 6, pp. 192‐198, April 1991. [16] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, "Analytical Loss Model of Power MOSFET," IEEE Transactions on Power
Electronics, vol. 21, pp. 310‐319, March 2006. [17] F. C. Lee, "High‐Frequency Quasi‐Resonant and Multi‐Resonant Converter Technologies," in International
Conference on Industrial Electronics, Singapore, 1988, pp. 509‐521. [18] K. H. Liu and F. C. Lee, "Zero‐Voltage Switching Techniques in DC/DC Converter Circiuts," in Power Electronics
Specialists Conference, Vancouver, Canada, 1986, pp. 58‐70. [19] L. F. Casey and M. F. Schlecht, "A High‐Frequency, Low Volume, Point‐of‐Load Power Supply for Distrubuted Power
Systems," IEEE Transactions on Power Electronics, vol. 3, pp. 72‐82, January 1988. [20] J. Hornberger, A. B. Lestetter, and e. al., "Silicon‐Carbide (SiC) Semiconductor Power Electroncis for Extreme High‐
Temperature Environments," in Ieee Aerospace Conference Proceedings, 2004. [21] K. I. Inc., "Model 2010 Multimeter User's Manual," Cleveland, OH, 1996. [22] Agilent, "Agilent 4284A Prescision LCR Meter Operation Manual," Japan, 1999. [23] N. Insturments, "Introduction to LabView
TM/CVI," 2008.
[24] A. Hefner, "Safety Review for the High Voltage C‐V Measurement System and Procedure," National Institute of Standards and Technology2008
[25] I. Rectifier, "IRF1010N HEXFET(c) Power MOSFET," 2001, Available at
ec.irf.com/v6/en/US/adirect/ir?cmd=catProductDetailFrame&productID=IRF1010N. [26] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York:
John Wiley & Sons, Inc., 2001. [27] Infineon, "CoolMosTM Power Transistor," 2007, Available at
www.infineon.com/cms/en/product/findProductTypeByName.html?q=IPW60R045CP. [28] E. D. Wolley and W. R. V. Dell, "Fast Recovery Epetaxial Diodes (FRED)," in Industry Applications Society Annual
Meeting, 1988, pp. 655‐663. [29] Infineon, "Product Brief for CoolMos C3 900V ", 2008. [30] A. Lelis, D. Habersat, F. Olaniran, B. Simons, J. McGarrity, F. B. McLean, and N. Goldsman, "Time‐Dependant Bias
Stress‐Induced Instability if SiC MOS Devices," in Material Research Society Symposium 2006.
A‐1
Appendix A The following sections display the MatLab M‐files that execute accuracy calculations for each
measurement configuration.
A.1 Accuracy Calculation for CDS
function[] = CdsFullCircuit(Cgs,Cgd,Cds) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; Cgd = 3.037e‐9; Cds = 1e‐9; Cgs = 3.929e‐9; Cccd = 0.1e‐6; VoltageOff = ZccgCompZgs(Cgd, Cds); CurrentOff = ZccdCompZds(Cgs); Zccd = 1./(s*Cccd); Zds = 1./(s*Cds); Offset = VoltageOff.*CurrentOff.* (Zds./CurrentOff)./((Zds./CurrentOff)+Zccd); magnitude = abs(Offset); phase = angle(Offset); figure(6);axes('FontSize',14); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude','FontSize',14); title('Cds Calculated Accuracy','FontSize',14); %axes('FontSize',14) subplot(2,1,2); plot(Hz/1000, phase) ylabel('Phase','FontSize',14); xlabel('Frequency, kHz','FontSize',14); end %%voltage divider for the front impedences of LCR meter function[VoltageTF] = ZccgCompZgs(Cgs, Cgd) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; linecolor = ['y','r','g','b','k']; %%Cgs = 10e‐9;
A‐2
%%Cgd = 4e‐9; Cgsmsr = 150‐12; Rgsmsr = 10e6; Rg = 3e6; Cccg = 0.1e‐6; Rccg = 2.7; %%Rgs = 0; %%1e3; Top = s*Cgsmsr*Rgsmsr*Rg + Rg; Bottom = s.^2*Cgsmsr*Cgs*Rgsmsr*Rg + s*(Cgsmsr*Rgsmsr + Cgs*Rg + Cgsmsr*Rg) + 1; Zgs = Top./Bottom; Zgd = 1./(s*Cgd); Zccd = Rccg + 1./(s*Cccg); VoltageTF = 1./(1 + Zccd.*(Zgs + Zgd)./(Zgs.*Zgd)); ImaginaryPT = imag(VoltageTF); RealPT = real(VoltageTF); magnitude = abs(VoltageTF); theta = angle(VoltageTF); figure(4) %%title('Vgs/Voc'); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude'); title('Cds Vgs/Voc'); subplot(2,1,2); plot(Hz/1000, theta) ylabel('Phase'); xlabel('Frequecny, kHz'); end function[CurrentTF] = ZccdCompZds(Cds) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; linecolor = ['y','r','g','b','k']; %%Cds = 1e‐9; %%Cgd = 4e‐9; Cdsmsr = 120‐12; Rdsmsr = 10e6;
A‐3
Rd = 3e6; Cccd = 0.1e‐6; Rccd = 2.7; %%Rds = 0; %%1e3; Top = s*Cdsmsr*Rdsmsr*Rd + Rd; Bottom = s.^2*Cdsmsr*Cds*Rdsmsr*Rd + s*(Cdsmsr*Rdsmsr + Cds*Rd + Cdsmsr*Rd) + 1; Zds = Top./Bottom; %%Zgd = 1./(s*Cgd); Zccd = Rccd + 1./(s*Cccd); CurrentTF = Zds./(Zccd + Zds); ImaginaryPT = imag(CurrentTF); RealPT = real(CurrentTF); magnitude = abs(CurrentTF); theta = angle(CurrentTF); figure(5) %%title('Vgs/Voc'); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude'); title('Cds Ilcr/Igd'); subplot(2,1,2); plot(Hz/1000, theta) ylabel('Phase'); xlabel('Frequecny, kHz'); end
A.2 Accuracy Calculation for CGD
function[] = CgdFullCircuit(Cgs,Cgd,Cds) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; Cgd = 3.0037e‐9; Cds = 1.00e‐9; Cgs = 3.0929e‐9; Cccd = 0.1e‐6; VoltageOff = ZccgCompZgs(Cgs, Cgd); CurrentOff = ZccdCompZds(Cds); Zccd = 1./(s*Cccd);
A‐4
Zgd = 1./(s*Cgd); Offset = VoltageOff.*CurrentOff .* (Zgd./CurrentOff)./((Zgd./CurrentOff)+Zccd);%‐Zccd./(Zgd*100); magnitude = abs(Offset); phase = angle(Offset); figure(3); subplot(2,1,1); plot(Hz/1000,magnitude) hold on axis([0 100 0.905 0.91]) ylabel('Magnitude','FontSize',14); title('Cgd Calculated Accuracy','FontSize',14); subplot(2,1,2); plot(Hz/1000, phase) ylabel('Phase','FontSize',14); xlabel('Frequency, kHz','FontSize',14); end %%voltage divider for the front impedences of LCR meter function[VoltageTF] = ZccgCompZgs(Cgs, Cgd) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; linecolor = ['y','r','g','b','k']; %%Cgs = 10e‐9; %%Cgd = 4e‐9; Cgsmsr = 220‐12; Rgsmsr = 10e9; Rg = 3e6; Cccg = 0.1e‐6; Rccg = 2.7; %%Rgs = 0; %%1e3; Top = s*Cgsmsr*Rgsmsr*Rg + Rg; Bottom = s.^2*Cgsmsr*Cgs*Rgsmsr*Rg + s*(Cgsmsr*Rgsmsr + Cgs*Rg + Cgsmsr*Rg) + 1; Zgs = Top./Bottom; Zgd = 1./(s*Cgd); Zccd = Rccg + 1./(s*Cccg); VoltageTF = 1./(1 + Zccd.*(Zgs + Zgd)./(Zgs.*Zgd)); ImaginaryPT = imag(VoltageTF); RealPT = real(VoltageTF); magnitude = abs(VoltageTF); theta = angle(VoltageTF);
A‐5
figure(1) %%title('Vgs/Voc'); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude'); title('Cgd Vgs/Voc'); subplot(2,1,2); plot(Hz/1000, theta) ylabel('Phase'); xlabel('Frequency, kHz'); end function[CurrentTF] = ZccdCompZds(Cds) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; linecolor = ['y','r','g','b','k']; %%Cds = 1e‐9; %%Cgd = 4e‐9; Cdsmsr = 120‐12; Rdsmsr = 10e6; Rd = 3e6; Cccd = 0.1e‐6; Rccd = 2.7; %%Rds = 0; %%1e3; Top = s*Cdsmsr*Rdsmsr*Rd + Rd; Bottom = s.^2*Cdsmsr*Cds*Rdsmsr*Rd + s*(Cdsmsr*Rdsmsr + Cds*Rd + Cdsmsr*Rd) + 1; Zds = Top./Bottom; %%Zgd = 1./(s*Cgd); Zccd = Rccd + 1./(s*Cccd); CurrentTF = Zds./(Zccd + Zds); ImaginaryPT = imag(CurrentTF); RealPT = real(CurrentTF); magnitude = abs(CurrentTF); theta = angle(CurrentTF); figure(2)
A‐6
%%title('Vgs/Voc'); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude'); title('Cgd Ilcr/Igd'); subplot(2,1,2); plot(Hz/1000, theta) ylabel('Phase'); xlabel('Frequecny, kHz'); end
A.3 Accuracy Calculation for CGS
function[] = CgsFullCircuit(Cgs,Cgd,Cds) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; Cgd = 3.037e‐9; Cds = 1e‐9; Cgs = 3.929e‐9; VoltageOff = ZccgCompZgs(Cgs, Cgd); CurrentOff = ZccdCompZds(Cds); Offset = VoltageOff.*CurrentOff; magnitude = abs(Offset); phase = angle(Offset); figure(9); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude','FontSize',14); title('Cgs Calculated Accuracy','FontSize',14); subplot(2,1,2); plot(Hz/1000, phase) ylabel('Phase','FontSize',14); xlabel('Frequency, kHz','FontSize',14); end %%voltage divider for the front impedences of LCR meter function[VoltageTF] = ZccgCompZgs(Cgs, Cgd) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; linecolor = ['y','r','g','b','k']; %%Cgs = 10e‐9; %%Cgd = 4e‐9; Cgsmsr = 150‐12; Rgsmsr = 10e6;
A‐7
Rg = 3e6; Ccg = 0.1e‐6; Ccd = 0.1e‐6; R1 = 2.7; %%Rgs = 0; %%1e3; Z1 = 1./(s.*Cgd) + 1./(s.*Ccd); Z2 = Rgsmsr + 1./(s.*Cgsmsr); Z3 = Rg; Zgs = 1./(s.*Cgs); Zccg = R1+1./(s.*Ccg); inv = 1./Z1 + 1./Z2 + 1./Z3; Zgd = 1./inv; VoltageTF = 1./(1+Zccg.*(Zgs+Zgd)./(Zgs.*Zgd)); ImaginaryPT = imag(VoltageTF); RealPT = real(VoltageTF); magnitude = abs(VoltageTF); theta = angle(VoltageTF); figure(7) %%title('Vgs/Voc'); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude','FontSize',14); title('Cgs Vgs/Voc','FontSize',14); subplot(2,1,2); plot(Hz/1000, theta) ylabel('Phase','FontSize',14); xlabel('Frequecny, kHz','FontSize',14); end function[CurrentTF] = ZccdCompZds(Cds) Hz = 1e3:10:100e3; w = 2*pi*Hz; s = j*w; linecolor = ['y','r','g','b','k']; %%Cds = 1e‐9; %%Cgd = 4e‐9; Cdsmsr = 120‐12; Rdsmsr = 10e6; Rd = 3e6; Ccd = 0.1e‐6; Rccs = 2.7; %%Rds = 0; %%1e3;
A‐8
Z1 = (1./(s.*Ccd).*Rd)./(1./(s.*Ccd) + Rd); Z2 = 1./(s.*Cds) + Z1; Z3 = Rdsmsr + 1./(s.*Cdsmsr); Zds = Z2.*Z3 ./ (Z2+Z3); Zccs = Rccs; CurrentTF = Zds ./(Zccs + Zds); ImaginaryPT = imag(CurrentTF); RealPT = real(CurrentTF); magnitude = abs(CurrentTF); theta = angle(CurrentTF); figure(8); subplot(2,1,1); plot(Hz/1000,magnitude) ylabel('Magnitude'); title('Cgs Ilcr/Igd'); subplot(2,1,2); plot(Hz/1000, theta) ylabel('Phase'); xlabel('Frequecny, kHz'); end
A‐9
Appendix B The following is the C code which executes the automated CV measurement from the CVI user interface.
/*============================================================================================ = Function: SweepGateDrainVolt_Func_CGDMSR(). = = Purpose: To call the SweepGateDrainVoltage() function. = ============================================================================================*/ int CVICALLBACK SweepGateDrainVolt_Func_CGDMSR (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) int i,testHV,AllClear,TypeSweep,CapMeasurement, PreviousSweepPoints=0; double MosfetBiasVoltMin, MosfetBiasVoltMax, FixedDelay, MosfetBiasVoltInc, DrainProtection; double GateMax, GateMin, GateInc, GateProtect,GateDelay; double firstSweepMin, firstSweepMax, firstSweepInc, firstSweepProt; double secondSweepMin, secondSweepMax, secondSweepInc, secondSweepProt; char buf[200]; switch (event) case EVENT_COMMIT: ClearReferenceVariables(); // PER 6/16/08 Initialize_hp428xa (); SetCtrlVal(panelCgdmsr, PANELCGGMS_BUSYLED, 1); DeleteGraphPlot (panelCgdmsr, PANELCGGMS_PLOT, -1, 1); /* Set up parameters of Low or High Voltage tests */ GetCtrlVal(panelCgdmsr, PANELCGGMS_DRAINSELECTINST, &vbiasselectinst); if (vbiasselectinst == E3647A) testHV = 0; AllClear = CheckEquipment(1,testHV); if (AllClear == 0) return 0; GetCtrlVal(attrHandle, ATTR_DRAINVOLTMIN, &MosfetBiasVoltMin); GetCtrlVal(attrHandle, ATTR_DRAINVOLTINCREMENT, &MosfetBiasVoltInc); GetCtrlVal(attrHandle, ATTR_DRAINVOLTMAX, &MosfetBiasVoltMax); GetCtrlVal (attrHandle, ATTR_FIXEDDELAY, &FixedDelay); GetCtrlVal (attrHandle, ATTR_DRAINPROTECT, &DrainProtection); E3647A_DrainSetup(); else testHV = 1; AllClear = CheckEquipment(1,testHV); if (AllClear == 0) return 0; GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTMIN, &MosfetBiasVoltMin); GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTINCREMENT, &MosfetBiasVoltInc);
A‐10
GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTMAX, &MosfetBiasVoltMax); GetCtrlVal (attrHandle, ATTR_HVFIXEDDELAY, &FixedDelay); PS350_DrainSetup(); DrainProtection = 5000; /*Get gate parameters, set up dual power source and gate voltage protection*/ GetCtrlVal(attrHandle, ATTR_GATEVOLTMIN, &GateMin); GetCtrlVal(attrHandle, ATTR_GATEVOLTINCREMENT,&GateInc); GetCtrlVal(attrHandle, ATTR_GATEVOLTMAX, &GateMax); GetCtrlVal(attrHandle, ATTR_GATEVOLTPROTECT, &gateVoltProtect); GetCtrlVal(attrHandle, ATTR_FIXEDGATEDELAY, &GateDelay); ibwrt(dualpower,"OUTP ON", 7); // TURN dualpower OUTPUT ON ibwrt(dualpower,"INST:SEL OUT2",13); Fmt(gateVoltProtect_buf,"VOLT:PROT %f",gateVoltProtect); ibwrt(dualpower,gateVoltProtect_buf,StringLength(gateVoltProtect_buf)); if (GateMin < 0 && GateMax > 0) MessagePopup("Error:", "Cannot perform gate sweep from negative to positive gate value"); return 0; GetCtrlVal (attrHandle, ATTR_FIXEDGATEDELAY, &fixedGateDelay); // Gets the the fixedGateDelay value GetCtrlVal(panelCgdmsr, PANELCGGMS_RINGSLIDE_3, &TypeSweep); // Gets the kind of sweep to be performed //The following if/else statements allows the user to choose which voltages are swept and which voltages //are iterated after each sweep if (TypeSweep == 0) firstSweepMin = MosfetBiasVoltMin; firstSweepInc = MosfetBiasVoltInc; firstSweepMax = MosfetBiasVoltMax; firstSweepProt = DrainProtection; secondSweepMin = GateMin; secondSweepInc = GateInc; secondSweepMax = GateMax; secondSweepProt = gateVoltProtect; SetCtrlAttribute(panelCgdmsr, PANELCGGMS_PLOT, ATTR_XNAME, "Vds, (V)"); Fmt(buf,"\nDrain Sweep: %fV to %fV in %fV increment.",MosfetBiasVoltMin, MosfetBiasVoltMax, MosfetBiasVoltInc); else secondSweepMin = MosfetBiasVoltMin; secondSweepInc = MosfetBiasVoltInc; secondSweepMax = MosfetBiasVoltMax; secondSweepProt = DrainProtection; firstSweepMin = GateMin; firstSweepInc = GateInc; firstSweepMax = GateMax; firstSweepProt = gateVoltProtect; FixedDelay = GateDelay; SetCtrlAttribute(panelCgdmsr,PANELCGGMS_PLOT, ATTR_XNAME, "Vgs, (V)");
A‐11
Fmt(buf,"\nGate Sweep: %fV to %fV in %fV increment.",GateMin,GateMax,GateInc); InsertTextBoxLine(panelCgdmsr, PANELCGGMS_TEXT, -1, buf); memset(buf,0,200); //The following for loop steps through different values for the gate or drain (termed "gateVolt" in this code) //and then calls "SweepDrain_AnodeVolt" to perform a sweep of the drain or the gate values for (gateVolt=secondSweepMin; gateVolt<=secondSweepMax; gateVolt=gateVolt+secondSweepInc) SecondSweepVoltSetup(gateVolt,testHV,TypeSweep); if(TypeSweep == 0) Fmt(buf,"\nGate Voltage = %f",gateVolt); else Fmt(buf,"\nDrain Voltage = %f",gateVolt); InsertTextBoxLine(panelCgdmsr, PANELCGGMS_TEXT, -1, buf); SweepDrain_AnodeVolt(firstSweepMin, firstSweepMax, firstSweepInc, firstSweepProt, 1, testHV,FixedDelay); // Stops loop if the "Stop" button is pressed if(Abort==1) break; //creates an array that contains how many points are in each individual sweep if (GateSweeps) GateSweepPoints[GateSweeps] = arrayIndexCounter_ref - PreviousSweepPoints; else GateSweepPoints[GateSweeps] = arrayIndexCounter_ref; //set up input voltage array for second sweep applied voltage if (TypeSweep == 0) for (i=PreviousSweepPoints;i<arrayIndexCounter_ref;i++) InputGateVoltage_ref[i] = gateVolt * -1; else for (i=PreviousSweepPoints;i<arrayIndexCounter_ref;i++) InputGateVoltage_ref[i] = gateVolt; PreviousSweepPoints = arrayIndexCounter_ref; GateSweeps++; //end of for loop SetCtrlVal(panelCgdmsr, PANELCGGMS_BUSYLED, 0); // (THD 9/1/2005) added to set the LED OFF break; return 0; // End the SweepGateDrainVolt_Func_CGDMSR() function
A‐12
/*============================================================================================ = Function: SweepDrain_AnodeVolt (VoltageSend, TestHV, MeasureMOSFET) = = Purpose: Performs a forward and backward CV sweep on a diode or MOSFET, starting at = = minVolt and ending at maxVolt = = minVolt: Starting point of CV sweep = = maxVolt: Ending point of CV sweep = = increVolt: Voltage Increment that is used to perform the sweep = = protectVolt: Voltage protection value for the power supplies and DUT = = HVtest: Boolean value that indicates whether or not the test performed is a HV test = = measureMosfet: Boolean vale that indicates whether or not a MOSFET CV measurement is = = being performed = ============================================================================================*/ void SweepDrain_AnodeVolt(double minVolt, double maxVolt, double increVolt, double protectVolt, int measureMosfet, int HVtest, double FDelay) double inputVoltage,measuredVoltage,HVincre,SentVoltage; int arrayIndexCounter1 = 0; int arrayIndexCounter2 = 0; double voltageValues[5000]; //double totalVds[5000]; double FirstStepVal = 0.0; int TypeSweep,CapMeasurement; int Panel_Name, Button; SetCtrlAttribute(panelCgdmsr, PANELCGGMS_ABORT, ATTR_CMD_BUTTON_COLOR,VAL_RED); GetCtrlVal(panelCgdmsr, PANELCGGMS_RINGSLIDE_3, &TypeSweep); // Gets the kind of sweep to be performed /*sets the frequency and AC voltage level in LCR meter*/ FormatLCRfreq(); Multimeter_1_2010_Setup(HVtest); //Need two volt meters for MOSFET measurement if (measureMosfet) Multimeter_2_2010_Setup(); inputVoltage = minVolt; measuredVoltage = minVolt; if (HVtest) HVincre = increVolt; /*this loop performs CV measurements, incrementing the input voltage to the circuit while the voltage drop across the device is less than the maximum voltage value*/ while (measuredVoltage < maxVolt && (measuredVoltage*-1) < maxVolt) voltageValues[arrayIndexCounter1] = inputVoltage; //For first measurement there is extra delay
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if (arrayIndexCounter1 == 0) Delay(2); GetUserEvent(0,&Panel_Name,&Button); if (Button == PANELCGGMS_ABORT) SetCtrlAttribute(panelCgdmsr, PANELCGGMS_ABORT, ATTR_CMD_BUTTON_COLOR,VAL_WHITE); Abort = 1; //if the "Abort" flag has been set to one for any reason, turn off the voltage suppies if (Abort == 1) TurnOfVoltSupply(measureMosfet,HVtest); break; SentVoltage = VoltInputVoltMeter(inputVoltage, HVtest, measureMosfet,TypeSweep,arrayIndexCounter1,protectVolt); /* Maximum input voltage cannot exceed the protection, so the while loop will discontinue if this occurs*/ if (SentVoltage > protectVolt) break; Delay(FDelay); ProcessSystemEvents; RCDelay(); inputVoltArray[arrayIndexCounter1] = inputVoltage; CvsVPlot(arrayIndexCounter1, measureMosfet); FirstStepVal = CheckError(measureMosfet,HVtest,TypeSweep,arrayIndexCounter1,inputVoltage,FirstStepVal); //the following if/else statements ensure that the correct voltage is plotted on the interface graph //and the correct voltage value, "measuredVoltage" is compared to the maximum allowable voltage for this C-V //measurement while loop if (TypeSweep==0 || measureMosfet == 0) plotFormat(arrayIndexCounter1+1,measuredVoltArr); measuredVoltage = measuredVoltArr[arrayIndexCounter1]; else plotFormat(arrayIndexCounter1+1,measuredGateVoltArr); measuredVoltage = measuredGateVoltArr[arrayIndexCounter1]; arrayIndexCounter1++; /*Increment input voltage value; if sweeping the drain and performing a high voltage measurement increase the increment so that it sweeps through high voltage values faster */ if (HVtest && TypeSweep == 0) inputVoltage = inputVoltage + HVincre; HVincre = HVincre + 1;
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else inputVoltage = inputVoltage + increVolt; //end of while loop //make adjustments to arrayIndexCounter arrayIndexCounter1 = arrayIndexCounter1 - 1; /*Copy first pass of CV sweep arrays into reference array*/ for ( x = 0; x <= arrayIndexCounter1; x++) measuredVoltArr_ref[arrayIndexCounter_ref] = measuredVoltArr[x]; measuredCapArr_ref[arrayIndexCounter_ref] = measuredCapArr[x]; inputVoltArray_ref[arrayIndexCounter_ref] = inputVoltArray[x]; if (measureMosfet) measuredGateVoltArr_ref[arrayIndexCounter_ref] = measuredGateVoltArr[x]; arrayIndexCounter_ref++; /* Check for array index out of bound 5000*MAXCGDVSVOLTCURVE*/ if(arrayIndexCounter_ref> (5000*MAXCGDVSVOLTCURVE)) MessagePopup("Error:", "Array sire is out of bound!"); return; //end of if statment //end of for loop /*this loop performs CV measurements, incrementing the input voltage to the circuit while the voltage drop across the device is less than the maximum voltage value*/ for (x = arrayIndexCounter1; x >= 0; x--) inputVoltage = voltageValues[x]; //For first measurement there is extra delay //if (arrayIndexCounter2 == 0) Delay(1); GetUserEvent(0,&Panel_Name,&Button); if (Button == PANELCGGMS_ABORT) Abort = 1; SetCtrlAttribute(panelCgdmsr, PANELCGGMS_ABORT, ATTR_CMD_BUTTON_COLOR,VAL_WHITE); if (Abort == 1) TurnOfVoltSupply(measureMosfet,HVtest); break; VoltInputVoltMeter(inputVoltage, HVtest, measureMosfet,TypeSweep,arrayIndexCounter1+arrayIndexCounter2,protectVolt); Delay(FDelay); ProcessSystemEvents; RCDelay();
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inputVoltArray[arrayIndexCounter2] = inputVoltage; CvsVPlot(arrayIndexCounter2, measureMosfet); FirstStepVal = CheckError(measureMosfet,HVtest,TypeSweep,arrayIndexCounter2,inputVoltage,FirstStepVal); //the following if/else statements ensure that the correct voltage is plotted on the interface graph if (TypeSweep==0 || measureMosfet == 0) retracePlotFormat(arrayIndexCounter2+1,measuredVoltArr); else retracePlotFormat(arrayIndexCounter2+1,measuredGateVoltArr); arrayIndexCounter2++; //end of for loop /*Copy second pass of CV sweep arrays into reference array*/ for ( x = 0; x < arrayIndexCounter2; x++) measuredVoltArr_ref[arrayIndexCounter_ref] = measuredVoltArr[x]; measuredCapArr_ref[arrayIndexCounter_ref] = measuredCapArr[x]; inputVoltArray_ref[arrayIndexCounter_ref] = inputVoltArray[x]; if (measureMosfet) measuredGateVoltArr_ref[arrayIndexCounter_ref] = measuredGateVoltArr[x]; arrayIndexCounter_ref++; /* Check for array index out of bound 5000*MAXCGDVSVOLTCURVE*/ if(arrayIndexCounter_ref> (5000*MAXCGDVSVOLTCURVE)) MessagePopup("Error:", "Array sire is out of bound!"); return; //end of if statment //end of for loop SetCtrlAttribute(panelCgdmsr, PANELCGGMS_ABORT, ATTR_CMD_BUTTON_COLOR,VAL_WHITE); //end of SweepDrain_AnodeVolt /*============================================================================================ = Function: FormatLCRfreq() = = Purpose: To set up the frequecy and AC voltage, then send these values to the = = LCR meter, HP 4284A = ============================================================================================*/ void FormatLCRfreq(void) GetCtrlVal(attrHandle,ATTR_VOLTLEVEL, &voltLevel); GetCtrlVal(attrHandle,ATTR_FREQLEVEL ,&freqLevel);
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/*=Format and write the "freqLevel" parameter to the LCR meter=*/ Fmt(write_buf,"FREQ %fHz",freqLevel); hp428xa_writeInstrData (A428XAd, write_buf); InsertTextBoxLine(panelCgdmsr, PANELCGGMS_TEXT,-1,write_buf); textLine++; /*=Format and write the "voltLevel" parameter to the LCR meter=*/ Fmt(write_buf,"VOLT %fV",voltLevel); // Keep this value as small as possible! hp428xa_writeInstrData (A428XAd, write_buf); InsertTextBoxLine(panelCgdmsr, PANELCGGMS_TEXT,-1,write_buf); textLine++; //end of FormatLCRfreq subroutine /*============================================================================================ = Function: TurnOfVoltSupply(int MOSFETmeasure,int TestHV) = = Purpose: If the measurement sequence is aborted this subroutine is called to turn off the = = voltage of each volt meter = ============================================================================================*/ void TurnOfVoltSupply(int MOSFETmeasure,int TestHV) if (TestHV) Fmt(drainVolt_buf,"VSET%f", 40.0); ibwrt (ps350,drainVolt_buf,StringLength(drainVolt_buf)); if (TestHV == 0 || MOSFETmeasure) Fmt(drainVolt_buf,"VOLT %f", 0.0); ibwrt(dualpower,drainVolt_buf,StringLength(drainVolt_buf)); //ibwrt(dualpower,"OUTP OFF", 8); /*============================================================================================ = Function: VoltInputVoltMeter (VoltageSend, TestHV, MOSFETmeasure) = = Purpose: To set multimeters to continuous read mode and send the proper voltage value = = to the to the voltage supply = = VoltageSend: Voltage to sent to the dual power supply or HV power supply; an input to = = the test circuit = = TestHV: Boolean value that indicates whether or not the test performed is a HV test = = MOSFETmeasure: Boolean vale that indicates whather or not a MOSFET CV measurement is = = being performed = ============================================================================================*/
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double VoltInputVoltMeter(double VoltageSend, int TestHV, int MOSFETmeasure, int SweepType, int counter, double ProtectVoltage) char code[255]; int TypeSweep, CapMeasurement ; double DrainVoltage,OffsetVoltage, DrainProt; /*Sets multimeter 1 to continuous read mode*/ Fmt(code, ":INIT:CONT 1"); ibwrt(multimeter1_model_2010,code,strlen(code)); /*If performing mosfet measurement, sets multimeter2 to continous read mode*/ if (MOSFETmeasure) Fmt(code, ":INIT:CONT 1"); ibwrt(multimeter2_model_2010,code,strlen(code)); GetCtrlVal(panelCgdmsr, PANELCGGMS_RINGSLIDE_2, &CapMeasurement); // Gets type of capacitance measurement that is being taken //The following section of code determines if the capacitance being measured is Cds. If this is the case, //the drain and the source voltage have to be adjusted according one each others values. //If the Vds is being swept, the voltage applied at the MOSFET source must be added to input drain voltage. //If the source voltage is being swept (changing the value of Vgs), the value of the drain has to also be adjusted to //maintain a relatively constant value for Vds. if (CapMeasurement == 1 && MOSFETmeasure) //if performing a Cds measurement on a MOSFET OffsetVoltage = GetCdsOffsetVoltage(SweepType, counter,TestHV); if (SweepType == 0) VoltageSend = VoltageSend - OffsetVoltage; //Apply a new value of drain voltage to the drain as the source voltage increases else DrainVoltage = VoltageSend + OffsetVoltage; if (TestHV) GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTMAX, &DrainProt); if (DrainVoltage > DrainProt) VoltageSend = 1+ProtectVoltage; else Fmt(drainVolt_buf,"VSET%f", DrainVoltage); ibwrt (ps350,drainVolt_buf,StringLength(drainVolt_buf)); else GetCtrlVal (attrHandle, ATTR_DRAINPROTECT, &DrainProt); if (DrainVoltage > DrainProt) VoltageSend = 1+ProtectVoltage; else ibwrt(dualpower,"INST:SEL OUT1",13); // ACTIVATE OUTPUT 1 (DRAIN VOLTAGE) Fmt(drainVolt_buf,"VOLT %f", DrainVoltage); ibwrt(dualpower,drainVolt_buf,StringLength(drainVolt_buf)); //end of nested if/else statment ibwrt(dualpower,"INST:SEL OUT2",13); // ACTIVATE OUTPUT 2 (NEGATIVE GATE VOLTAGE or POSTIVE SOURCE VOLTAGE) //end of SweepType if/else
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//end of "Cds measurement" if statment if (VoltageSend <= ProtectVoltage) //The following if/else statment sends the input voltage to the correct voltage source if (SweepType == 0 || MOSFETmeasure == 0) //if drain is swept first or measuring capacitance of diode /*Sends drain/anode voltage to the hv power supply or the dual power supply*/ if (TestHV) Fmt(drainVolt_buf,"VSET%f", VoltageSend); ibwrt (ps350,drainVolt_buf,StringLength(drainVolt_buf)); else Fmt(drainVolt_buf,"VOLT %f", VoltageSend); ibwrt(dualpower,drainVolt_buf,StringLength(drainVolt_buf)); //end of nested if/else statment else Fmt(gateVolt_buf,"VOLT %f",VoltageSend); // Sends voltage command to dualpower suppply gate/source voltage ibwrt(dualpower,gateVolt_buf,StringLength(gateVolt_buf)); // end of if/else f return VoltageSend; //End of VoltInputVoltMeter subroutine /*============================================================================================ = Function: GetCdsOffsetVoltage() = = Purpose: In order to maintain the correct drain voltage to get the desired Vds the value = = of the source voltage must be take into account. The following program gets the = = offset voltage that corrects the drain voltage value. = = count: Index of the present measurement being taken, if = 0, gate or drain values are = = retrieved from the multimeters. = = DrainOrGate: Boolean value that indicates whether the gate or drain is being swept = ============================================================================================*/ double GetCdsOffsetVoltage(int DrainOrGate,int count,int HV) char code[255]; char VoltageBuffer[512]; double Min, Inc; //if first measurement taken, get a value of voltage from the mulitmeter if (count == 0) if (DrainOrGate == 0) Delay(1);
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//get gate voltage Fmt(code, ":INIT:CONT 0"); ibwrt(multimeter2_model_2010,code,strlen(code)); Fmt(code,":DATA?"); ibwrt(multimeter2_model_2010,code,strlen(code)); ibrd(multimeter2_model_2010, VoltageBuffer,512); //reset the multimeter 2 to continuos read mode Fmt(code, ":INIT:CONT 1"); ibwrt(multimeter2_model_2010,code,strlen(code)); //for this measurement, offset voltage cannot be a negative value if (atof(VoltageBuffer)< 0) return 0; else return atof(VoltageBuffer)*-1; else if (DrainOrGate == 0) return measuredGateVoltArr[count-1]; else if (HV) GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTMIN, &Min); GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTINCREMENT, &Inc); return Min+(Inc*GateSweeps); else GetCtrlVal(attrHandle, ATTR_DRAINVOLTMIN, &Min); GetCtrlVal(attrHandle, ATTR_DRAINVOLTINCREMENT, &Inc); return Min+(Inc*GateSweeps); //end of HV If/else //end of SweepType (Gate or Drain) if/else //end of count = 0 if/else return 0; // end of GetCdsOffsetVoltage function /*============================================================================================ = Function: CjvsVPlot(Counter1,MOSFETmeasure) = = Purpose: To capture the Capacitance value from the LCR meter and the Voltage of the = = multimeter and perform the correct calaculations to adjust their values = = Counter1: Index of the present measurement being taken = = MOSFETmeasure: Boolean vale that indicates whather or not a MOSFET CV measurement is = = being performed = ============================================================================================*/ void CvsVPlot(int Counter1, int MOSFETmeasure)
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int CapMeasurement; char code[255]; char VoltageBuffer1[512] ,VoltageBuffer2[512]; char buf[255]; double Model2010VoltValue; double DrainMeterResistanceConstant = 3.09; //resistance is placed in series with volt meter to reduce capacitive noise //This constant multiplier is used to correct the voltage meter reading. GetCtrlVal(panelCgdmsr, PANELCGGMS_RINGSLIDE_2, &CapMeasurement); // Gets type of capacitance measurement that is being taken /*Stops multimeter 1 and retrieves a data point from the device and calculates the drain/anode voltage*/ Fmt(code, ":INIT:CONT 0"); ibwrt(multimeter1_model_2010,code,strlen(code)); Fmt(code,":DATA?"); ibwrt(multimeter1_model_2010,code,strlen(code)); ibrd(multimeter1_model_2010, VoltageBuffer1,512); Model2010VoltValue = atof(VoltageBuffer1); measuredVoltArr[Counter1]=Model2010VoltValue * DrainMeterResistanceConstant; /*If performing a MOSFET measurement, stop multimeter 2 and retrieve a data point from the device and calculates the drain/anode voltage */ if (MOSFETmeasure) Fmt(code, ":INIT:CONT 0"); ibwrt(multimeter2_model_2010,code,strlen(code)); Fmt(code,":DATA?"); ibwrt(multimeter2_model_2010,code,strlen(code)); ibrd(multimeter2_model_2010, VoltageBuffer2,512); Model2010VoltValue = atof(VoltageBuffer2); //if Cds measurement, the physicsal measurement is Vsg, so flip polarity to make Vgs if (CapMeasurement == 1) measuredGateVoltArr[Counter1]=Model2010VoltValue * -1; else measuredGateVoltArr [Counter1]=Model2010VoltValue; if (CapMeasurement == 1 && MOSFETmeasure) measuredVoltArr[Counter1] = measuredVoltArr[Counter1] + measuredGateVoltArr[Counter1]; //else if (CapMeasurement == 2 && MOSFETmeasure) measuredVoltArr[Counter1] = measuredVoltArr[Counter1] *-1; /*get capacitance value from the multimeter and calculate DUT capacitance*/ hp428xa_writeInstrData (A428XAd, "TRIG"); hp428xa_writeInstrData (A428XAd, "FETC:IMP?"); ibrd (LCRIntrument, measured_buf, 12); //Isolated diode capacitance is calculated differently than mosfet capacitance if (MOSFETmeasure) measuredCapArr[Counter1] = atof(measured_buf)*multiplier; else
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Cjmsr=atof(measured_buf)*multiplier - 9e-12; CjValue=Cjmsr/(1 - 20000000*Cjmsr) - 76e-12; measuredCapArr[Counter1]=CjValue; if (measuredCapArr[Counter1] == 9.9e37) measuredCapArr[Counter1] = NotANumber(); if (ibsta & ERR) // Device read error Fmt(buf, "%s<ERROR...Could not read from device"); InsertTextBoxLine(panelCgdmsr, PANELCGGMS_TEXT, -1, buf); textLine++; //end of CvsVPlot /*============================================================================================ = Function: CheckError(int MOSmeasure,int HVmeasure, int SweepType,int count,double = = AppliedVolt,double initialVoltage) = = Purpose: To ensure that the voltages applied at the terminals of the devices do not stray = = significantly from the applied voltages = ============================================================================================*/ double CheckError(int MOSmeasure,int HVmeasure, int SweepType,int count,double AppliedVolt,double initialVoltage) double StepMin, StepInc; double StepOffset, SweepOffset; double SweepVoltage, StepVoltage; double StepInput; double MaxError, MinError; char StepName[6],SweepName[6]; char Messagebuf[500],Titlebuf[50]; //int Relative, Input; //Get input and relative error from attribute screen //GetCtrlVal(attrHandle,ATTR_RELATIVEERROR, &RelativeError); //GetCtrlVal(attrHandle,ATTR_DELTAERROR, &DeltaError); //following if/else statements get the minimum and increment values of the stepped voltage //and sets up the stepped and sweep voltages if (SweepType == 0 && MOSmeasure) GetCtrlVal(attrHandle, ATTR_GATEVOLTMIN, &StepMin); GetCtrlVal(attrHandle, ATTR_GATEVOLTINCREMENT,&StepInc); StepVoltage = measuredGateVoltArr[count]; SweepVoltage = measuredVoltArr[count]; Fmt (StepName,"Gate"); Fmt (SweepName,"Drain"); else if (SweepType == 1 && MOSmeasure)
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if (HVmeasure) GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTMIN, &StepMin); GetCtrlVal(attrHandle, ATTR_HVDRAINVOLTINCREMENT, &StepInc); else GetCtrlVal(attrHandle, ATTR_DRAINVOLTMIN, &StepMin); GetCtrlVal(attrHandle, ATTR_DRAINVOLTINCREMENT, &StepInc); //end of nested if/else StepVoltage = measuredVoltArr[count]; SweepVoltage = measuredGateVoltArr[count]; Fmt (StepName,"Drain"); Fmt (SweepName,"Gate"); //end of primary if/else else SweepVoltage = measuredVoltArr[count]; Fmt (SweepName,"Diode"); //if Mosfet measurement, check step voltage offset if (MOSmeasure) StepInput = StepMin + StepInc*GateSweeps; if (count < 5) return StepVoltage; else StepOffset = StepVoltage / initialVoltage; if (StepOffset < 0) StepOffset = StepOffset * -1; MinError = 1 - (DeltaError/100.0); MaxError = 1 + (DeltaError/100.0); if ((StepOffset>MaxError || StepOffset<MinError) && StepVoltage > 0.5) Abort = 1; Fmt(Messagebuf,"The %s voltage is straying too far from its inital value at the start of this measurement. \nCheck your circuit and / or increase the value for delta error in the attributes window",StepName); Fmt (Titlebuf,"Leaky %s terminal",StepName); MessagePopup (Titlebuf, Messagebuf); StepOffset = StepVoltage / StepInput; if (StepOffset < 0) StepOffset = StepOffset * -1; MinError = 1 - (RelativeError/100.0); MaxError = 1 + (RelativeError/100.0); if ((StepOffset>MaxError || StepOffset<MinError) && StepInput > 1) Abort = 1; Fmt(Messagebuf,"The %s voltage is straying too far from the voltage source's input voltage. \nCheck your circuit and / or increase the value for relative error in the attributes window",StepName); Fmt (Titlebuf,"Leaky %s terminal",StepName); MessagePopup (Titlebuf, Messagebuf); // end of nested if/else statement // end of if(MOSmeasure) statement //check sweep voltage offset SweepOffset = SweepVoltage / AppliedVolt;
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MinError = 1 - (RelativeError/100.0); MaxError = 1 + (RelativeError/100.0); if (SweepOffset < 0) SweepOffset = SweepOffset * -1; if ((SweepOffset>MaxError || SweepOffset<MinError) && AppliedVolt > 1) Abort = 1; Fmt(Messagebuf,"The %s voltage is straying too far from the voltage source's input voltage. \nCheck your circuit and / or increase the value for relative error in the attributes window",SweepName); Fmt (Titlebuf,"Leaky %s terminal",SweepName); MessagePopup (Titlebuf, Messagebuf); return initialVoltage;
/*============================================================================================ = Function: CheckEquipment() = = Purpose: To check that the attributes menu has been accessed and the correct power = = supplies and multimeters have been turned on = = GateSweep: Parameter that represents whether or not the gate of the MOSFET will be swept = = HVmeter: Parameter that represents wheter or not a HV test will be performed = ============================================================================================*/ int CheckEquipment(int GateSweep,int HVmeter) if (attrHandle <=0) MessagePopup("Error:", "Please setup the attributes first!"); return 0; if (HVmeter == 0 || GateSweep == 1) if (DevicePresentArr[1]<=0) MessagePopup("Error:", "E3647A Dual Output Power Supply is not ON!"); return 0; if (DevicePresentArr[4]<=0) MessagePopup("Error:", "Multimeter 2010 is not ON!"); return 0; if (HVmeter == 1) if (DevicePresentArr[2]<=0) MessagePopup("Error:", "PS350 High Power Supply is not ON!"); return 0;
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if (DevicePresentArr[3]<=0) MessagePopup("Error:", "Multimeter 2001 is not ON!"); return 0; return 1; //end of CheckEquipment routine