Design and validation of a multi-core embedded

platform under high performance requirements

University of L’AquilaCenter of Excellence DEWS

Department of Information Engineering, Computer Science and Mathematics DISIM

4th Workshop on High-performance and Real-time Embedded Systems (HiRES 2016)

V. Muttillo, G. Valente, F. Federici, L. Pomante, M. Faccio

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Overview

Introduction

Proposed Platform

Evaluation and Validation

Conclusions and future developments

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Introduction

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Multi-core Embedded SoC

On-Chip embedded systems are characterized by several F/NF requirements

• Response time, power consumption, time-to-market etc.Multi-core embedded systems design

• Suffers from the lack of uniform pathways to system realization and application deployment

Parallel programming model• Allows to obtain a speed-up for a multi-threaded

application by splitting the workloadRun-time monitoring solutions

• Allows to monitor system behaviour during life-time

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Proposed SolutionThis work presents the development of an

embedded multi-core platform on FPGA with:• Multi-LEON3 SMP HW architecture• Non-intrusive distributed HW profiling subsystem• Integrated customized Linux OS distribution• OpenMP parallel programming models• RVS profiling tool support

Final goal of the work• Development of high-performance multi-core

embedded platform with run-time resource monitoring components and off-line verification tools support

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Platform in development flow

The work is related to the Artemis-JU ASP CRAFTERS European project

• It has led to uniform embedded system development flow in the research and industry domains

• The platform has been proposed to execute and validate industrial case studies

• Support to embedded system designers

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Proposed Platform

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LEON3 32-bit synthesizable soft-processors, multi-core mode, dedicated FPU, MMU for Linux OS etc.

HW Architecture

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OS and Parallel Programming Model

Operating System• A Linux distribution has been customized, starting from

LEON LINUX kernel• Cross-compiler toolchain, buildroot tool to build user space

application and RAM loader have been provided by Aeroflex Gaisler

Parallel Programming Model• Libraries required to implement parallel applications

using OpenMP C/C++, have been added to the customized Linux distribution

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HW Profiling System

AIPHS (AdaptIve Profiling Hardware Subsystem)• Event and Time monitoring functionalities

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Final Platform4-core Leon 3 with Linux operating system,

OpenMP libraries and hardware profiling system

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ML605 (Virtex 6) Development Board

THE PLATFORM HARDWARE ARCHITECTURE

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Final Platform4-core Leon 3 with Linux operating system,

OpenMP libraries and hardware profiling system

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ML605 (Virtex 6) Development Board

THE PLATFORM HARDWARE ARCHITECTURE

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Platform Functionalities

• High performance multi-processing software execution• Run-time event and time monitoring• Reconfigurable HW architecture• Resource monitoring application using MW layer

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Evaluation and Validation

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Reduction Parallel SPMD No false Sharing0

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Simulated resultsVIPPE-based speed-up evaluation on selected

benchmark• Verify if OpenMP program parallelization made sense in

a scenario with a given memory organization (i.e. single cache, DDR3 interface for external memory etc.)

• To check if specific OpenMP library implementation works well with the proposed memory organization

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Experimental resultsAIPHS-based speed-up evaluation on selected

benchmark• Execution time increases with number of threads• Multi-core architecture, based on LEON3 and one level

cache, using OpenMP leads to optimal performances• False sharing problem is quite influent in this system

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Reduction Parallel SPMD No false Sharing0

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RVS SupportRapita Verification Suite provides a framework for

on-target verification of embedded software

The use of AIPHS enables the designer to analyze time information offline by using Rapita tools

AIPHS allows reducing the need for code instrumentation so providing information more related to the real behavior of the considered application

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Conclusions and future

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ConclusionsThis work has described the design and the

validation of an embedded SoC multi-core platform• early verification and validation• enhanced performances in execution time (OpenMP) • on-chip run-time monitoring (AIPHS)

Support for Rapita Verification Suite (RVS) allows designers to evaluate meaningful statistics

• WCRT• Average time execution• etc…

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Future developmentsImprovement of the profiling system to collect

more data and events while better filtering overhead due to OS and ISR

Improvement of multi-core monitoring support for RVS

Preliminary simulation step with VIPPE tool integrated in the multi-core embedded systems specific design flow

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Thanks for the attention

Questions?

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