Design and Physical Implementation of an Analog Receiver for a 2.5Gbps SerDes

Ernesto Conde Almada, Esdras Juarez Hernandez and Esteban Martinez-Guerrero

Instituto Tecnológico y de Estudios Superiores de Occidente (ITESO), Guadalajara, Jalisco, 45604, Mexico, E-mail: es685570@iteso.mx, esdras@iteso.mx, MARGRES@iteso.mx.

Abstract — An analog receiver module for a SerDes with a data rate of 2.5 Gbps for PCI Express Gen 1, is presented. The module is composed by a high-speed differential amplifier, a replica bias circuit and a CML to CMOS converter with duty-cycle correction. The circuit was designed in CMOS 130nm process technology with a supply voltage of 1.2V. A high gain amplifier using the self-cascode technique allows to overcome the low output impedance limitation set by the 130nm technology. Simulation results exhibit no functional issues under PVT corners and mismatch analysis, showing the circuit accomplishes the PCIe Gen 1 specification. Index Terms — Analog, IC design, Receiver, PCI Express, SerDes, High-Speed I/O’s, duty cycle correction, CML.

I. INTRODUCTION

High-speed serial I/O’s are the backbone of modern wired communications; they are present in most if not all computing systems and today’s high-bandwidths applications push data rates to the gigabit-per-second speed [1, 2, 3, 4]. Serial communications and parallel communications currently coexist in those systems. A Serializer/Deserializer (SerDes) system is a good example where both parallel and high-speed serial communications are used. In this system, transmitter serves to transmit data to the receiver through a high-speed serial data link, and the receiver receives data from the serial data link and delivers parallel data to next stage for further signal processing [5]. According to [6], traditional low-power SerDes architectures either provide good channel loss performance at lower speeds or good speed for lower loss channels. However, these architectures have limitations in addressing the need for low-power and high-speed performance on the higher loss channels of next generation applications. Therefore, supporting the latest communications protocol specifications, including Peripheral Component Interconnect Express (PCIe) [7], calls for a new type of SerDes architecture that addresses the following needs with minimal power dissipation.

In this work, the design of an analog receiver module of a SerDes system at 2.5 Gbps data rate, suitable for PCIe Gen1 is presented. The proposed analog receiver consists of three main blocks: a high-speed and low jitter differential amplifier (HS-Amp), a replica bias circuit and a Current Mode Logic (CML) to CMOS converter with duty cycle correction. The analog receiver was designed in 130nm CMOS technology with a supply voltage of 1.2V.

The rest of this paper is organized as follows: Section 2 presents the approach of receiver architecture, Section 3 the circuit design and analysis of the receiver architecture,

simulation results are presented in Section 4 and concluding remarks of this work in Section 5.

II. ANALOG RECEIVER ARCHITECTURE

Figure 1 shows the architecture of the proposed analog receiver. It is composed by an HS-Amp cascaded with a CML to CMOS circuit. HS-Amp amplifies the analog input at 1.25 GHz. The bias circuit ensures not only the HS-Amp is properly biased, but the output common mode level is set to the right value which avoids the use of complex common-mode feedback circuitry. Finally, the CML to CMOS circuit converts the HS-Amp output signal to CMOS logic levels in order to be properly processed by the clock and data recovery circuit (CDR) of the SerDes. In addition, the CML to CMOS circuit contains a duty cycle corrector circuit (DCC) that helps the output duty cycle to remain as close as possible to 50% across Process Voltage and Temperature (PVT) and mismatch variations. Figure 2, shows the receiver circuit at transistor level.

III. CIRCUIT DESIGN

As it can be appreciated in Fig. 2, the HS-Amp consists of a cascade of two simple differential amplifiers with resistive loads. This circuit was designed for a total voltage gain of 20 dB (to amplify 10 times the receiver differential input of 40 mV pk-pk at 1.25 GHz) and 2.0 GHz of bandwidth according to PCIe Gen1 base specifications [7].

Figure 1 Analog Receiver Architecture.

IEEE MTT-S Latin America Microwave Conference (LAMC-2016) Puerto Vallarta, Mexico; Dec. 12-14, 2016

978-1-5090-4287-6/16/$31.00 ©2016 IEEE

Figure 2: Transistor Level Analog Receiver Architecture.

Each stage of HS-Amp was designed with similar voltage gain and bandwidth, following the classical equations for gain (1) and bandwidth (2) of a simple OTA: = ≈ (1) = 1/ ≈ 1/( ) (2) The followed equal stage design approach, allows to get an easy way for parasitic capacitance estimation and amplifier bandwidth compensation, besides to enable fully layout reuse.

The bias circuit is composed by a resistor divider network, a high-gain amplifier and a replica circuit of the HS-Amp. The resistor divider network is designed to generate a reference voltage equal to 0.7VDD. The high-gain amplifier compares the reference voltage and the output common mode from the replica circuit, and generates an error voltage proportional to the detected difference. This error voltage is converted into a current through the PM5 transistor (Fig.2). The replica circuit senses the changes in the load resistor and the tail bias current induced by PVT variations. Then the signals generated by the replica circuit modify the bias voltage in the tail transistors of the HS-Amp to maintain the output common mode at 0.7VDD. Since the low NMOS output impedance in the 130 nm technology, the high gain amplifier was designed using the self-cascode technique [8]. The high-gain amplifier was designed for 40 dB of gain and 8 MHz of GBW using equations (3) and (4): = ∗ ( )|( ) (3) = / (4)

The CML to CMOS circuit consists of two differential to single ended converters, cascaded with two inverter chains providing the rail to rail swing conversion. Cross-coupled latches at the first and second inverter outputs forms the duty cycle correction through these stages, thus reaching nearly 50% duty cycle at the final outputs across PVT and mismatch.

Since the total bandwidth is 2.0 GHz for the HS-Amp, there is a tradeoff between input capacitance and the maximum conversion speed in the differential to single ended converter. In consequence, the sizing of the differential to single-ended circuit needs to be carefully done to avoid an excessive load increase which can degrade the total amplifier performance. Taking into account the fact that analog circuits are sensitive to process variations and mismatch as a function of layout position in the wafer, common centroid layout technique, dummy devices, and guard-rings were used in the layout in order to minimize mismatch effects. Figure 3 shows the layout of the analog receiver. The total area of layout is 108 µm x 240 µm. The layout distribution of the analog receiver was determined by the floorplan requirements of the SerDes system. DRC and LVS verifications were done using Calibre tool from Mentor Graphics.

Figure 3: Analog Receiver Layout.

IV. SIMULATION RESULTS

Figure 4 shows a comparison between pre-layout and post-layout AC responses of the receiver at nominal PVT conditions (Typ, 1.2V, 65°C). Simulations were performed with Virtuoso-Cadence. Notice on Fig. 3, the HS-Amp performance fulfills the frequency requirements to make the system work at 2.5 Gbps.

Figure 5 shows the transient response of the analog receiver

module top at different PVT conditions (Process: SS, FF, and TT, Voltage: +/- 5% of VDD and T: -40, 65 and 125 °C). Figure 6 shows the transient response of mismatch analysis. Both simulations results indicate that the output tracks the input signal of 40 mv pk-pk at 1.25 GHz correctly under different PVT conditions and mismatch without functional failures.

Figure 7: Jitter Sensitivity at Nominal PVT.

Figure 7 shows the circuit jitter sensitivity under different power supply noise levels at low frequencies. As it can be appreciated, the pure analog circuitry has a very low sensitivity to the power supply noise due to its differential nature. On the other hand, the digital part (first, second and third buffers) of our circuit is the most sensitive, i.e. being the biggest contributor to the overall RX jitter performance. Table 1 shows the jitter contribution of each stage under different PVT conditions. In all cases it can be seen that starting from column three, the jitter contribution start to increase significantly. Under all conditions the CMOS stages make up > 80% of the total jitter contributions. Figure 8 shows the eye diagram measurements of the last three CMOS stages, where it can be seen how the jitter increases on each stage. Notice however, that the overall jitter contribution of receiver block is only 5% of the data width defined in the PCIe Gen1 specification.

TABLE 1: Jitter Contribution Per Stage Under PVT Conditions. Table 2 shows the current and power consumption of the circuit under different PVT corners, giving us the worst case of 7.74 mW of power at slow corner (Process: SS, 1.14 VDD & 125 C).

0

2

4

6

8

10

12

14

16

0 10 20 30 40 50 60

Pea

k to

Pea

k Ji

tter

in P

s

Peak to Peak Noise in mV

1st_Stage_HS-Amp

2nd_Stage_HS-Amp

Diff2Single

First_Buffer

Second_Buffer

Final Output

Analog Stages Digital Stages

Jitter %

PVT Corner

HS-Amp Differential To Single-

Ended

First Buffer

Second Buffer

Final Buffer

Typical 11.49% 6.08 % 35.14 % 33.78 % 13.51 % Fast 9.86 % 2.82 % 33.80 % 35.21 % 18.31 % Slow 5.33 % 10.22% 34.22 % 33.78 % 16.44 %

Figure 4: Analog Receiver AC Response at Nominal PVT.

Figure 5: Analog Receiver Output Reponses under PVT conditions.

Pre-Layout Gain: 26.32 dB

3 dB BW: 2.828 GHz

Post-Layout Gain: 26.74 dB

3 dB BW: 2.371 GHz

Frequency (Hz) 10

0 103 10

6 109 10

11

Vol

tage

(dB

)

-20

-10

0

10

20

30

Input 40 mV pk-pk

Outputs

Vol

tage

(V

)

Time (ns)0 2.5 5.0 7.5 10

0

0.5

1.0

1.25

0.25

0.75

Figure 6: Analog Receiver Output under mismatch analysis.

Time (ns) 0 2.5 5.0 7.5 10

Vol

tage

(V

)

0

0.5

1.0

1.25

0.25

0.75

Input 40 mV pk-pk

Outputs

PVT Corner Current (mA) Power (mW)

Typical 5.36 6.44 Fast 6.15 7.74 Slow 4.72 5.38

TABLE 2: Power Consumption Under PVT Conditions.

Finally, the comparison between the receiver design specifications vs. final post-layout results are shown in Table 3.

Figure of Merit Design Target Final Results Margin (%)

HS-Amp 3dB Bandwidth 2.0 GHz 2.37 GHz 18.50 %

HS-Amp Voltage Gain 20 dB 26.74 dB 33.70 %

High-Gain OTA Gain 40 dB 40.07 dB 0.18 %

High-Gain GBW 8 MHz 8.29 MHz 3.62 %

Common Mode Output 600 mV 618.04 mV 3.01 %

Total Jitter < 30 ps 14.80 ps 50.6 %

Power Consumption < 10 mW 6.44 mW 35.6 %

TABLE 3: Design Specifications vs. Post-layout Results.

V. CONCLUSIONS

In this work, the design, physical implementation and design verification of an analog receiver module for a SerDes in 130 nm CMOS process was presented. Simulation results have shown that design meets specifications required to work at 2.5 Gbps for the PCI Express Gen 1 Protocol. The full design cycle as covered in an industrial-like fashion by doing extensive verification both pre-layout and post-layout, covering PVT corners and mismatch analysis giving good results.

ACKNOWLEDGEMENTS This work was developed as a final project in the specialty of system on chip design graduate program at ITESO University. The authors would like to thank CONACYT for their financial support.

REFERENCES [1] W. Sheng, et al, System design considerations of wideband multi-standard receiver for 3rd generation mobile system applications, Southwest Symposium on Mixed-Signal Design 2000 SSMSD, 27-29 Feb 2000, San Diego, CA, 103 – 108. [2] Long-Fei Wei, et al, Multi-Rate SerDes Transceiver for IEEE 1394b Applications, J. Electronic Science and Technology 2012, Vol. 10, 4, 327 – 333. [3] Sh. Kirkire et al, Characterization of high speed data transmission interface for future IRS payloads, 2013 Nirma University International Conference on Engineering (NUiCONE), 28 – 30, Nov. 2013, Ahmedabad, 1 – 6. [4] B. Garlep et al, A 1-10 Gbps PAM2, PAM4, PAM2 partial response receiver analog front end with dynamic sampler swapping capability for backplane serial communications, Symposium on VLSI Circuits 2005, 376 – 379. [5] Shuai Yuan et al, A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology, IEEE Trans. on Circuits and Systems I: Regular Papers, 2016, Vol. 63, 7, 939 – 949. [6] E. Naviasky, Defining a New High-Speed, Multi-Protocol SerDes Architecture for Advanced Nodes, http://ip.cadence.com/uploads/652/Multi_protocol_SerDes_PHY_IP_WP_final-pdf [7] PCI-SIG, PCI Express Base Specification, http://composter.com.ua/documents/PCI_Express_Base_Specification_Revision_3.0.pdf/ [8] David Comer et al, The utility of the composite cascode in analog CMOS design, Int. J. Electron. 2004, 91(8), pp 491 – 502

Figure 8: Eye Diagram Measurements of the Last Three CMOS Stages.

Time (ps)

Vol

tage

(V

)

0 100 200 300 400 500 600 700 800

-1.5

-1.0

-0.5

0

0.5

1.

1.5 Final output 1st Buffer 2nd Buffer

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