DESIGN AND IMPLEMENTATION OF USART USING VHDL

USART FUNCTION •U

niversal Synchronous Asynchronous Receiver Transmitter

•u

sed to send and receive small packets over a serial line– full or half duplex

• typically asynchronously• 5 – 9 bits of data• 2 or 3 framing bits

– start bit– 1 or 2 stop bits

• 0 or 1 parity bits

MAIN FUNCTIONS

Universal Synchronous Asynchronous Receiver

Transmitter:

•can be synchronous or asynchronous

•can receive and transmit

•Full duplex asynchronous operation

Most common use:

•RS-232 communications to a PC serial port

DATA FORMAT

M

ust be agreed on by sender and receiver before any exchanges can be

made

s

top bit (1 to 0 transition)

5

– 9 data bits

0

or 1 parity bits (odd or even parity)

1

or 2 stop bits (logic 0)

SCHEMATIC OF TRANMITTER

SENDING DATAR

emember synchronization is on a character by character basis

c

heck status

l

oad data register

s

tart transmit

w

ait for transmission complete status or for interrupt

r

epeat

RECEIVING DATA

p

oll status register for data ready or wait for interrupt

r

ead data (save it)

r

epeat

SCHEMATIC OF RECEIVER

PROGRAMMING MODEL

D

ata input register

D

ata output register

C

ontrol register• speed, data bits, parity, stop bits, start, stop

BAUD RATE GENERATOR

BAUD RATE GENERATOR

T

his module is designed to generate a square clock

irrespective of the divisor value .

I

n synchronous mode of communication ,this clock is

transmitted along with the data.

SIMULATION RESULTSTRANSMITTER

RECEIVER

Receiver

CONCLUSION

T

his design uses VHDL as design language to achieve the

modules of UART.

T

he results are stable and relaible.

T

he design has great flexibility,high integration with some

reference value.

FUTURE SCOPE

W

e can implement this project for the designing of

USARTS for system on chip devices.