design and implementation of the link capacity … · multi-frame indicator: the multi frame...

DESIGN AND IMPLEMENTATION OF THE LINK CAPACITY ADJUSTMENT SCHEME FPGA

Alfred Leung Bachelor of Applied Science and Engineering, University of Toronto, 2001

PROJECT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF ENGINEERING

In the School of

Engineering Science

O Alfred Leung 2007

SIMON FRASER UNIVERSITY

Spring 2007

All rights reserved. This work may not be reproduced in whole or in part, by photocopy

or other means, without permission of the author.

APPROVAL

Name:

Degree:

Title of Project:

Alfred Leung

Master of Engineering

Design and Implementation of the Link Capacity Adjustment Scheme FPGA

Examining Committee:

Chair: Dr. Jie Liang

Assistant Professor of Engineering Science

Dr. Stephen Hardy

Senior Supervisor

Professor of Engineering Science

Dr. Daniel Lee

Supervisor Associate Professor of Engineering Science

Korby Mraze Supervisor Applications Engineer Leader of PMC-Sierra Inc

Date DefendedfApproved:

SIMON FRASER ti? UNiVERsinlibrary &&4

DECLARATION OF PARTIAL COPYRIGHT LICENCE

The author, whose copyright is declared on the title page of this work, has granted to Simon Fraser University the right to lend this thesis, project or extended essay to users of the Simon Fraser University Library, and to make partial or single copies only for such users or in response to a request from the library of any other university, or other educational institution, on its own behalf or for one of its users.

The author has further granted permission to Simon Fraser University to keep or make a digital copy for use in its circulating collection (currently available to the public at the "lnstituticnal Repository" link of the SFU L i b r q website <www.lib.sfu.ca> at: <http:llir.lib.sfu.calhandle/l892/112>) and, without changing the content, to translate the thesislproject or extended essays, if technically possible, to any medium or format for the purpose of preservation of the digital work.

The author has further agreed that permission for multiple copying of this work for scholarly purposes may be granted by either the author or the Dean of Graduate Studies.

It is understood that copying or publication of this work for financial gain shall not be allowed without the author's written permission.

Permission for public performance, or limited permission for private scholarly use, of any multimedia materials forming part of this work, may have been granted by the author. This information may be found on the separately catalogued multimedia material and in the signed Partial Copyright Licence.

The original Partial Copyright Licence attesting to these terms, and signed by this author, may be found in the original bound copy of this work, retained in the Simon Fraser University Archive.

Simon Fraser University Library Burnaby, BC, Canada

ABSTRACT

Link Capacity Adjustment Scheme (LCAS) is a control mechanism that allow

network service providers to dynamically increase or decrease the bandwidth of a

Ethernet over SONET (EoS) Iink according to the network's bandwidth demand. The

key function of LCAS is to establish a messaging channel between the traffic sources and

traffic sinks, so that bandwidth change can be done with no or minimal service

interruption to the network.

The PMC-Sierra ARROW 2xGE device is a dual port gigabit Ethernet mapper

device. It was design and implemented prior to the publication of the LCAS

specification, and the LCAS frmctionality was not implemented in this device. Recently,

communication equipment builders have great demand for the LCAS functionality.

With the ARROW 2xGE device, the immediate solution for this requirement is to

implement the LCAS functionality using an external companion FPGA. For this project,

the LCAS FPGA will be designed and implemented.

TABLE OF CONTENTS

.. Approval ............................................................................................................................ ii

... Abstract .......................................................................................................................... ill Table of Contents ............................................................................................................. iv

List of Figures ................................................................................................................. vi .. List of Tables ................................................................................................................... vii ... Glossary ......................................................................................................................... viii

1 Introduction ................................................................................................................ 1

2 Background ................................................................................................................. 3 2.1 SONETISDH ......................................................................................................... 4. 2.2 Generic Framing Procedure (GFP) Encapsulation ............................................ 6 2.3 Virtual Concatenation ............................................................................................ 7 2.4 Link Capacity Adjustment Scheme (LCAS) ......................................................... 8

3 ARROW-2xGE ............................................................................................. ........... 13 3.1 ARROW 2xGE Device Overview ....................................................................... 13 3.2 Implementing LCAS with the ARROW 2xGE ................................................... 15 3.3 ARROW 2xGE Receive Path Overhead Port ...................................................... 16 3.4 ARROW 2xGE Transmit H4 Insertion Port ........................................................ 18

4 LCAS FPGA Design and Implementation ............................................................. 20 4.1 LCAS FPGA features ........................................................................................ 20 4.2 LCAS FPGA Device Top Level .......................................................................... 21 4.3 Microprocessor Interface h g i c .......................................................................... 22 4.4 Transmit Control Packet Random Access Memory ............................................ 24 4.5 Receive Control Packet Random Access Memory .............................................. 26 4.6 Transmit H4 Byte Path Over Head Insertion Interface ....................................... 28

4.6.1 MFI Counter ................................................................................................. 29 4.6.2 Bit Counter ...................................... .. 4.6.3 TPOHH4EN Signal Generator ................................................................... 30 4.6.4 RAM Address Pointer Generator ................................................................. 30 4.6.5 4-to-1 Shift Register ..................................................................................... 31 4.6.6 GPIORegisterBlock .................................................................................... 31 4.6.7 TPOHH4 Interface Captured Waveform ...................................................... 31

4.7 Received Path Overhead Extraction Interface ..................................................... 32 4.7.1 Bitcounter ................................................................................................... 34

................................................................................................ POH Counter 34 ................................................................................................ Path Counter 35

............................................................. Serial-In-Parallel-Out H4 Extractor 35 Per Path Address Pointer Generator ............................................................. 36 RAM Address and Data Signal Generator ................................................... 37 RAM Control Signal Generator ..................................... ... ........................... 38

............................................................................................. MST Framer 38 MST Register Interface Block ...................................................................... 39

.................................................................... 512 ms Frame Pulse Generator 40 .................................................................. RPOH Port Captured Waveform 40

5 Operation ................................................................................................................... 42 ........................................................................................ 5.1 LCAS ADD Operation 42

................................................................................ 5.2 LCAS REMOVE Operation 44

6 LCAS FPGA Pin Description .................................................................................. 46

Appendix ........................................................................................................................... 50

Bibliography ..................................................................................................................... 70

LIST OF FIGURES

Figure 1 . SONET STS- l/SDH STM-0 Frame Format ....................................................... 5

Figure 2 . GFP Frame Structure ........................................................................................... 7

Figure 3 - Virtual Concatenation ......................................................................................... 8

Figure 4 . Bandwidth Increase using LCAS ....................................................................... 9

Figure 5 . PM5397 ARROW 2xGE Block Diagram ......................................................... 13

Figure 6 . System Architecture ......................................................................................... 16

Figure 7 . RPOH Timing Diagram .................................................................................... 17

Figure 8 . RPOH STS-l/STM-0 Time Slots Output Timing ............................................ 17

Figure 9 . TPOH H4 Functional Timing Diagram ............................................................ 18

Figure 10 .. Link Capacity Adjustment Scheme (LCAS) FPGA Simplified Block Diagram ........................................................................................................ 20

Figure 11 . LCAS FPGA Device Top Level Diagram ...................................................... 22

Figure 12 . Microprocessor Read Write Access Capture .................................................. 24

Figure 13 . TPOHH4 Dual-Port Block Memory ............................................................... 24

Figure 14 . TPOHH4 Interface Block ............................................................................... 29

Figure 15 . TPOHH4 Interface Waveform Capture .......................................................... 32

Figure 16 . Receive Path Overhead Extraction Interface Block ....................................... 33

Figure 17 . Per Path Address Pointer ................................................................................ 37

Figure 18 . RPOH Interface Waveform Capture 1 ........................................................... 40

Figure 19 . RPOH Interface Waveform Capture 2 ........................................................... 41

Figure 20 . LCAS ADD Operation ................................................................................... 43

Figure 21 . LCAS REMOVE Operation ........................................................................... 45

LIST OF TABLES

............................................................. Table 1 . SONETISDH Bandwidth Nomenclature 4

Table 2 -Typical Ethernet Rates vs SONETISDH rates using Virtual Concatenation ................................................................................................. 8

Table 3 . LCAS Control Packet Frame Structure ............................................................. 10

Table 4 . CTRL Byte Code ............................................................................................... 12

......................................................................................... Table 5 . Device Register Map 23

Table 6 . Transmit Control Packet RAM Data Structure .................................................. 26

Table 7 . Receive Control Packet RAM Data Structure ................................................... 27

Table 8 . Member Status (MST-OK) Structure ................................................................ 39

Table 9 . LCAS FPGA Pin Descriptions .......................................................................... 46

Table 10 . CTRL Field Definition ..................................................................................... 60

vii

GLOSSARY

CRC

EoS

GE

LAN

LCAS

OC-N

POH

SDH

SONET

STS

WAN

VCAT

Cyclic Redundancy Check: Error checking byte(s) used to verify the integrity of a data block

Ethernet over SONETISDH: A technology to allow Ethernet packets to transmit over the SONET transport network.

Gigabit Ethernet: A variant of Ethernet that operates at a transmission rate of 1GbitIs.

Local Area Network: In this report, LAN is referring the Gigabit Ethernet network.

Link Capacity Adjustment Scheme: A control mechanism used to increase or decrease the bandwidth of an EoS link. The LCAS standard is defined by ITU-T G.7042lY.1305.

Optical Carrier Level N: The terninology used to define the rate of an optical network. The different level N specifies a speed multiple of the slowest supported optical rate (51.84 Mbps).

Path Overhead: A column in a SONETISDH frame used to carry path level overhead information.

Synchronous Digital Hierarchy: The optical standard used in Europe and Asia. The SDH standard is defined by the ITU-T G.707.

Synchronous Optical Network: The optical standard used in North America. The SONET standard is defined by Telcordia GR- 253-CORE.

Synchronous Transport Signal: Terminology used to refer to rates of linksldevices in a SONET network.

Wide Area Network: In this report, WAN is referring to the SONET network.

Virtual Concatenation: Virtual Concatenation is a multiplexing technique that allows SONETISDH channels to be grouped together in arbitrary arrangements

VCG

GFP

CTRL

MST

RS-ACK

TVCP

RVCP

TPOHH4

TPOHEN

RPOH

Virtual Concatenation Group: A bundle of SONETISDH channels grouped together for Virtual Concatenation implementation.

Generic Framing Procedure: GFP allows mapping of variable length Ethernet packets over a SONETISDH transport network

Multi-Frame Indicator: The Multi Frame Indicator (MFI) is a 12bit counter that increments by one every 1 2 5 ~ s . It is used by the de-mapper at the receiver to align the recovered payloads. The first 4 bits of the multi-frame counter is referred as the first multi-frame indicator (MFII). The 8 MSB of the counter is referred as the second multi-frame indicator (MFI2). This is a LCAS control packet field.

Control Word: It is used to transfer information from data source to the sink. It is used to synchronize the sink with the source and provides the status of the individual member of the group. This is a LCAS control packet field.

Member Status: It reports the status from sink to source with two states: OK (MS= 0) or FAILED (MS=l). 'This is a LCAS control packet field.

Re-Sequence Acknowledge: It indicates that a re-sequence event has occurred. This is a LCAS control packet field.

Transmit Virtual Concatenation Processor: This is a functionai block inside the ARROW 2xGE device.

Receive Virtual Concatenation Processor: This is a functional block inside the ARROW 2xGE device.

Transmit Path Overhead H4: This is the signal that carries the data bit on the ARROW 2xGE TPOHH4 interface.

Transmit Path Overhead H4 Enable: This is the signal that carries the enable bit on the ARROW 2xGE TPOHH4 interface.

Receive Path Overhead: This is the signal that carries the data bit on the ARROW 2xGE RPOH interface.

INTRODUCTION

Link Capacity Adjustment Scheme (LCAS) is a control mechanism that allow

network service providers to dynamically increase or decrease the bandwidth of a

Ethernet over SONET (EoS) link according to the network's bandwidth demand.

The key function of LCAS is to establish a messaging channel between the traffic

sources and traffic sinks, so that bandwidth change can be done with minimal service

interruption to the network. The LCAS protocol is currently specified in ITU-T

G.70421Y. 1305 (1 112001):

The PMC-Sierra PM5397 ARROW 2xGE device is a dual port gigabit Etheinel

mapper device. It is designed to map and de-map two 1 Gbitls Ethernet traffic into a

STS-48 SONET transport frame. Because the ARROW 2xGE device was designed

prior to the publication of the LCAS specification, the LCAS functionality was not

implemented in this device. Recently, communication equipment builders have great

demand for the LCAS functionality, and this has created a weakness for the ARROW

2xGE device. Fortunately, the ARROW 2xGE device supports both external

extraction and insertion access to the SONET H4 path overhead byte with its path

overhead ports. With this function, the LCAS functionality can be implemented

using an external companion FPGA.

This report provides the background information on SONET and Ethernet

over SONET technology, the implementation details and result of the LCAS FPGA,

and operation instruction on using the ARROW 2xGE with the LCAS FFGA in a

system for fulfilling the LCAS feature.

2 BACKGROUND

Today's communications network is dominated by two technologies: Ethernet

and SONETISDH. Ethernet is widely used for business enterprise networks while

SONETISDH in transport networks. Ethernet is simple, efficient and sufficiently

reliable for the local area network environment. SONETISDH is high performance

and most reliable for metro and long haul network services. When businesses need to

communicate with each other, or a business head office wants to connect to its branch

offices using the same LAN, the inter-worlung between the LAN and WAN are

required.

Traditionally, technologies such as frame relay, ATM, or Packet over SONET

are used for this inter-working function. These technologies would either require the

termination of the Ethernet packet, then mapping the underlying IP traffic into a new

Layer 2, or encapsulating the Ethernet within another L2 technology. These

techniques introduce additional complexity and cost into the network.

To address this problem, the Generic Framing Procedure (GFP), Virtual

Concatenation (VCAT) and Link Capacity Adjustment Scheme (LCAS) have been

developed. These technologies allow Ethernet packets to map directly over the

SONETISDH link. GFP is specified in ITU-T G.7041; it allows mapping of variable

length, higher-layer client signals over a transport network like SONETISDH. VCAT

is specified in ITU-T G.783; it is a multiplexing technique that is used to split

SONETISDH bandwidth into logical groups, which may be transported or routed

independently. LCAS is specified in ITU-T G.7042; it is a method to dynamically

increase or decrease the bandwidth of virtual concatenated containers. The following

sections will provide an introduction to each of this technology and will begin with a

brief description of SONETISDH.

2.1 SONETISDH

SONETJSDH is a time division-multiplexing layer 1 protocol used on optical

networks. The current SONETISDH Framers can handle speed from 51.84 Mbps up

to 40 Gbps. A rate of 51.84 Mbps is referred to as OC-1 when talking in terms of the

fiber optic bandwidth, and STS-11STM-0 when talking in terms of device bandwidth.

Table 1 shows a list of common bandwidth used in the industry as well as the optical

and device bandwidth name associated with it.

Table 1 - SONETISDH Bandwidth Nomenclature

Bandwidth (Mbps) 51.84 155.52

1 39812 1 OC-768 I STS-768 I STM-192

The SONETISDH protocol uses frame structure to align the data it carries.

The STS-11STlM-0 frame consists of 90 columns and 9 rows for a total of 810 bytes

as illustrated in Figure I. The STS-3lSTM-1 frame consists of 270 columns and 9

rows for a total of 2430 bytes. The STS-12lSTM-4 frame consists of 1080 columns

Fiber Optic Terminology

622.08 2488 9953

OC- 1 OC-3

SONET Terminology

OC- 12 OC-48 OC- 192

SDH Terminology

STS-1 STS-3

STM-0 STM-1

STS-12 STS-48 STS- 192

STM-3 STM- 12 STM-48

and 9 rows for a total of 9720 bytes. A SONETISDH frame is always 125 ys long

regardless of the bandwidth.

In Figure 1, the column highlighted in bold is the path overhead column. The

path overhead column is used to carry the alarms status, performance monitoring, and

other information associated with the payload it carries. In the virtual concatenation

and LCAS protocol, the H4 byte in the path overhead is used carry the control packet.

Control packet is used by the traffic source and sink when provisioning the Ethernet

over SONET links.

Figure 1 - SONET STS-11SDH STM-0 Frame Format

Column

ROW

1

a

3

4

5

6

7

8

9

Framing !+ Data Corn I D l

Pointer

BIP-8 t Data Corn

Data Corn

Data Corn I D l 0

SSM I s1

Framing Trace

OrderW ire

Pointer Pointer

APS APS

FEBE I 0rd;:ire MO

Trace J1

Signal Label C2

Path Status G1

User F2

Ctrl Packet H4

User F3

Growth K3

TCM N 1

ff 90 - /J

Payload

Payload

Payload

Payload

Payload

Pay load

Payload

Payload

Payload t

2.2 Generic Framing Procedure (GFP) Encapsulation

GFP encapsulation allows mapping of variable length Ethelnet packets over a

SONETISDH transport network. GFP uses a length and HEC field to delineate each

of the frames in the data stream. The HEC field is used to find the start of a frame

position and the length field is used to indicate the length of that frame.

There are two types of GFP frames: GFP client frame and GFP control frame.

A GFP client frame can be further classified as either client data frame or client

management frame. The former is used to transport client data, while the latter is

used to transport point-to-point management information like loss of signal. Client

management frames can be differentiated from the client data frames based on the

payload iype indicator. The GFP control frame currently consists only of a core

header field with no payload area. This frame is used to compensate for the gaps

between the client signal where the transport medium has a higher capacity than the

client signal, and is better known as an idle frame. The frame structure of a GFP

frame is shown in Figure 2.

Figure 2 - GFP Frame Structure

2 ~ d t e t s PDU Length Indicator (PLI) +i 2 Octets

o - 6d Octets

I 2 Z E I Optional eHEC I stination Address (DA)

Source Address (SA)

Octets MAC Client LengtWType C + I (LT) I

Client DATA

tional PAD

IAC FCS

I GFP Core Header

f GFP TYPE field

GFP Payload

Informalion field

4 Octets Optional GFP FCS C -- I

2.3 Virtual Concatenation

Virtual Concatenation is a multiplexing technique that allows SONETISDH

channels to be grouped together in arbitrary arrangements. This allows custom sized

SONETISDH pipes to be created in multiple STS-1 or Virtual Tributary rates. Using

virtual concatenation, the SONETISDH transport pipes adjusted for Ethernet

transport. For example, the SONET pipe size may be any multiple of 5OMbitIs for

STS-1 high-order virtual concatenation, or 1.6 m i t t s for VT1.5 low-order virtual

concatenation. Virtual concatenation rates are designated by STS-m-nv for high-order

concatenation, where the izv indicates a multiple n of the STS-m base rate. Similarly,

low-order virtual concatenation is designated by VT-m-nv.

Table 2 - Typical Ethernet Rates vs SONETISDH rates using Virtual Concatenation

I Data Bit Rate I Rate 1 Rate I Efficiency Effective Payload Bandwidth

1 10 Mbit/s Ethernet I VT-1.5-7v 1 -1 1 -2 Mbit/s 1 89% I 1 100 Mbit/s Ethernet I STS-1-2v 1 -96.77 Mbit/s ( 102% I

In virtual concatenation, data is striped over the multiple channels in the

Virtual Concatenation Group as illustrated in Figure 3. Control packets, which

contain the necessary information for reassembling the original data stream, are

inserted into the H4 SONET overhead bytes. This information contains the sequence

1 Gbit/s Ethernet

of the channels and a frame number, which is used as a time stamp. The receiving

end-point is then responsible for reassembling the original byte stream.

STS-1-21 v 1 -1.02 Gbit/s 1 98%

Figure 3 - Virtual Concatenation

Traffic Source (Head office)

2.4 Link Capacity Adjustment Scheme (LCAS)

Along with virtual concatenation, the capability to dynamically change the

bandwidth used for a virtual concatenated channel has been developed. This

capability is known as Link Capacity Adjustment Scheme (LCAS). Signalling

SONETISDH Traffic Sink

1 STSI-Sv (Office branch)

messages are exchanged within the SONETISDH H4 overhead byte in order to

change the number of path members being used by a Virtually Concatenated Group

(VCG). The number of members may be either increased or reduced, and the

resulting bandwidth change may be applied without loss of data in the absence of

network errors.

Bandwidth can be adjusted based on time-of-day demands and seasonal

fluctuations. For instance, businesses can subscribe to lower bandwidth connections

when the demand is low and increase the bandwidth when demand is high, hence

optimizing the operation cost.

Figure 4 - Bandwidth Increase using LCAS

SONETISDH

1 STSI-Sv

GE GE - m

I Bandwidth Demand

Increase

LCAS is also useful for fault tolerance and protection since the protocol has

the ability to remove failed links from the VCG. The LCAS protocol provides a

mechanism to detect the tributary in error and automatically remove it from the

group. The VCG ends up operating at a reduced bandwidth, but the VCG still

continues to carry data that is error-free.

A control packet consists of a number of fields: the Multi Frame Indicator,

Sequence Indicator, Control Word, Group Identification, Member Status, Re-

Sequence Acknowledge, and the CRC code. A complete control packet is consisted

of 4096 bytes and is transmitted across 4096 SONET frames. Since each SONET

frame is transmitted once every 125ps, the complete control packet is transmitted

once every 512 ms.. The control packet structure is illustrated in Table 3.

Table 3 - LCAS Control Packet Frame Structure

I H4 bvte I MFI I MFI

I Sequence indicator MSBs (bits 1-4) 1 1 1 1 1 1 1 0 1 1 4 I n - 1

I Sequence indicator LSBs (bits 5-8) ( 1

1 Bit 1 2 Bit 4

2" multi-frame indicator MF12 MSBs (bits 1-4)

2" multi-frame indicator MF12 LSBs (bits 5-8)

CTRL

1 Member status 1 8 1

Bit 2

Reserved ("0000")

Reserved ("0000")

CRC-8

Bit3 Bit 5 ( Bit 6

0

0

0

0

0

0

Member status

RS-ACK ("000X")

1'' Multi-frame indicator MFI1 (Bits 1-4)

Bit 7

0

0

0

Bit 8

1

1

1

1

1

0

0

1

0

0

1

0

0

0

1

0

0

1

0

0

1

0

1

2

4

5

6

n

1

0

9

10

Member status 1 0

The Multi Frame Indicator (MFI) is a 12-bit counter that incremefits by one

every 1 2 5 ~ s . It is used by the de-mapper at the receiver to align the recovered

payloads. The first 4 bits of the multi-frame counter is referred as the first multi-

frame indicator (MFII). The 8 MSB of the counter is referred as the second multi-

frame indicator (MFI2).

The Sequence Indicator (SQ) is an 8-bit field. It indicates the sequence in

which the individual member is ordered in each VCG. The Control Word (CTRL) is

used to transfer information from data source to the sink. It is used to synchronize

the sink with the source and provides the status of the individual member of the

group. Table 4 shows the different messages associated with the control word.

Table 4 - CTRL Byte Code

I 0001 I ADD I This member is about to be added to the a r o u ~

Value

0000

1 0101 I IDLE I This member is not part of the group of about to be removed

Command

FIXED

001 0

001 1

Remarks

This is an indication that this end uses fixed bandwidth (non-LCAS mode)

Group identification (GID) provides the receiver an identification for verifying

that all the amving members are originated from one transmitter. The contents are

expected to be dynamically pseudo-random, but the receiver is not required to

synchronize with the incoming stream.

NORM

EOS

1111

The Member Status (MST) field reports the status from sink to source with

two states: OK (MS= 0) or FAILED (MS=I). For channels that are not currently part

of the VC channel all the unused MS bits should be set to the Fail status. The Re-

Sequence Acknowledge (RS-ACK) indicates that a re-sequence event has occurred.

This can be an increase or a decrease in the number of active members in the VCG.

Finally the CRC-8 field is for errors checking the control bytes of the virtually

concatenated channel.

Normal transmission

End of Sequence Indication

DNU Do Not Use (sink reported FAIL status)

3.1 ARROW 2xGE Device Overview

The PMC-Sierra ARROW-2xGE device provides the mapping function for

two Gigabit Ethernet data clients into two Virtually Concatenated SONETISDH

payloads using either GFP or HDLC data encapsulation. The device has integrated

the SERDES and PHY client interface, gigabit Ethernet Media Access Controller

(MAC), encapsulation processor, virtual concatenation engine and the

SONET/SONET path processor.

Figure 5 - PM5397 ARROW 2xGE Block Diagram

PM5397 ARROW 2xGE

Engine

SERDES

SONETI SDH

Processor

The integrated SERDES enables the ARROW 2xGE to connect

directly to Gigabit Ethernet optics modules. The GMII interface allows the

ARROW 2xGE to connect to an external 1000BASE-T Gigabit Ethernet PHY

or direct connection to a Gigabit Ethernet switch device.

The Gigabit Ethernet MAC subsystem provides two key functions. It

provides the necessary Gigabit Ethernet performance monitoring functions,

and supports flow control that will prevent data loss in the case of an over

subscribed SONETISDH channel.

The data encapsulation processor supports GFP framing and provides

standards based mapping of Gigabit Ethernet to the SONET payload. It also support

HDLC frame delineation scheme to enable inter-working with legacy systems.

The Virtual Concatenation engine maps data across the member channels of the

virtually concatenated payload. On the receive side, the VC engine aligns the

member channels and reassemble the Ethernet data stream.

The SONETISDH Path Processor provides the path termination function for a

path terminating equipment that interfaces onto a SONETISDH network. The

SONETISDH path overhead insertion and extraction mechanism is provided in this

subsystem. This is the key interface to the LCAS FPGA. This subsystem also

provide performance monitoring functions, such as path trace message support

together with bit error monitoring and alarm signalling.

The SONETISDH system side interface can be used to connect to a high-

speed backplane or to a SONETISDH based switching fabric. Alternatively, the

ARROW-2xGE can be connected directly to a SONETISDH framer.

3.2 Implementing LCAS with the ARROW 2xGE

The ARROW 2xGE does not monitor or regenerate any control packet field

that are specific for LCAS. Hence, it cannot establish the LCAS communication

channel. To support LCAS, this function will need to be handled by the LCAS

FTGA.

In the WAN to LAN direction, the LCAS FPGA extracts the H4 byte from the

receive path overhead port and recover the LCAS message that is sent by the far end

data source. In the LAN to WAN direction, the LCAS FPGA inserts the local LCAS

message into the H4 byte. The message will be constructed by the system software

and inserted into the LCAS FPGA transmit control packet RAM using a local

microprocessor bus.

The member addition and removal function will be implemented by simply

re-provisioning the ARROW 2xGE RVCP and TVCP block using system software.

Figure 6 illustrates thz system architecture diagram of the ARROW 2xGE device

with the LCAS FTGA.

Figure 6 - System Architecture

Timmg Generator

,f

I GE Optic PM5397 ARF 2xGE FRAMER

1 GE Optic /e*

3.3 ARROW 2xGE Receive Path Overhead Port

The ARROW 2xGE Receive Path Overhead (RPOH) port serially outputs all

the path overhead bytes of the STS payloads. A 20.736 MHz clock is generated to

provide timing for the RPOH port. Figure 7 shows the RPOH functional timings.

The RPOH signal is used to output the POH bytes of the STS (VC) payloads. The

path overhead bytes are transmitted on the RPOH signal with the most significant bit

first in the same order that they are received. Since the ROHFP signal is

synchronized to the transport frame, zero, one or two path overheads can be output

per interval. The RPOHEN signal is used to indicate if there are new POH bytes on

the RPOH port. RPOHEN is either asserted or de-asserted for the nine POH bytes.

Figure 7 shows that RPOH and RPOHEN are aligned with the falling edge of

RPOHCLK. The rising edge of RPOHCLK should be used by the LCAS FPGA to

sample the RPOH and RPOHEN signals. Sampling RPOHFP high identifies the

MSB of the path trace byte of STS-1ISTM-0 #1 on RPOH.

Figure 7 - RPOH Timing Diagram

RPOHEN I 1 I

Figure 8 shows the case of four VC-4 payloads carrying four TUG3 payloads.

Both the master and the slave VC-4 STS-l/STM-0 time slots contain valid POH

bytes.

Figure 8 - RPOH STS-1ISTM-0 Time Slots Output Timing

B ~ E ( ~ v c - ~ ) n n n n n n n n n n n n I

RPOHEN(4 TUG9 n 1 1 1 1 1 1 1 1 f I I 1 I 1 I 1 I I 1 I I I I I I I l

B3E (4 TUGS) n n n n n n n n n n n n n n n n n n n n n n n n

3.4 ARROW 2xGE Transmit H4 Insertion Port

The ARROW 2xGE Transmit Path Overhead (TPOHH4) insertion port is

used to insert data into the LCAS fields in the H4 byte position. The interface

consists of five signals as shown in Figure 9.

Figure 9 - TPOH H4 Functional Timing Diagram

TPOHH4CLK is a clock that provides timing reference for the rest of the

signals. The TPOHFP signal is asserted by the TVCP for one TPOHH4CLK clock

cycle to indicate that i t is ready to accept the first of the 48 H4 overlay nibbles in the

following cycle. In this example, TPOHH4FP is asserted in cycle T2, to indicate that

the H4 overlay nibble corresponding to timeslot 1 is expected in cycle T3. The

overlay nibble is expected on the TPOHH4 signal in four cycles, with the most

significant bit in the first cycle and the least significant bit in the fourth cycle. In this

example, the H4 overlay nibble for the first timeslot is available in cycles T3 - T6

with a value of "lOll". The TPOHH4EN signal is sampled asserted in cycle T3,

along with the most significant bit on TPOHH4. This tells the ARROW 2xGE device

that the corresponding H4 overlay nibble "101 1" should be inserted into the first

timeslot of the outgoing STS-48lSTM-16 frame. Similarly, 47 more H4 overlay

nibbles are expected in the following cycles till the next TPOHFP assertion for the

rest of the 47 STS-1ISTM-0 timeslots.

4 LCAS FPGA DESIGN AND IMPLEMENTATION

4.1 LCAS FPGA features

Figure 10 shows the simplified block diagram of the LCAS FPGA. For

configuration and status monitoring purpose, the LCAS FPGA has integrated a non-

multiplexed address and data Intel mode microprocessor interface.

Figure 10 - Link Capacity Adjustment Scheme (LCAS) FPGA Simplified Block Diagram

LCAS FPGA

Transmit LCAS Packet Processor

RAM Address Pointer

Generator i 4-bit Shift Register

L LCAS Packet RAM

Received LCAS Control Packets RAM

Transmit LCAS Control Packets RAM P Microprocessol Bus Interface

Logic

Device Registers

The Transmit H4 Path Overhead Interface is compatible with the PMC-Sierra

PM5397 ARROW 2xGE TPOHH4 interface. All fields in the LCAS control packet

can be individually configured and transmitted at a per STS-1 path basis. The LCAS

control packet information is stored in the Transmit LCAS Control Packet RAM. For

future enhancement purpose, the transmit H4 path overhead interface block has

integrated a number of general-purpose registers.

The Receive Path Overhead Interface can be connected directly to the

ARROW 2xGE RPOH interface. It filters and extracts only the LCAS control packet

fields for all 48 STS-1 paths into the microprocessor bus accessible register spaces. It

realigns the received control packets by using the lWI1 field, and monitor and stores

the Member Status for each LCAS member to microprocessor bus accessible register

space. For system synchronization, it generates a 512 ms multi-frame pulse. For

future enhancement purpose, the received path overhead interface block has

integrated a number of general-purpose registers.

The LCAS FPGA VHDL source code and test bench can be provided upon

request. Please contact PMC-Sierra Inc.

4.2 LCAS FPGA Device Top Level

Figure 11 illustrates the detailed signal diagram of the LCAS FPGA. The

following subsections describe the implementation details for each functional block

in the design.

Figure 11 - LCAS FPGA Device Top Level Diagram

>AS FPGA

-- - -- - - TPOHH4lNTERFACEBLOCK

R M INTERFACE

TFOWCLK TWHHd_BYTEIN17 0

T P O H W D P ~ W . ~ A O ~ R ~ ~ ~ I ~ a

REGISTER IMERFACE

RESElB TFoHHr_GPIO_Rffijl: 117 01

CLK4 WEA

c ENA - b m ~ n ~ q e o ) PORT B Wm47 01 A

OdXI -+ MNV7 OI - C U B

0 -b WEB 1 -b M B

+

I REGISTER BLOCK I

I RPOH DUAL PORT RAM

P D O V 7 0 l PORTA WlJTq70;

PDOWB 01 REGISTERSEL

I I b UKB

p WEB EN3

4.3 Microprocessor Interface Logic

The microprocessor interface logic is implemented using the Intel

microprocessor bus protocol. A read operation is initiated when the read access

signal (RDB) together with the chip selected signal (CSB) are asserted low. A write

operation is initiated when the write access signal (WRB) together with the chip

selected (CSB) are asserted low. The device address map is shown in Table 5. When

the address value is within 0x0000 to OxODFF, the contents in the register space are

accessed. When the address value is within OxOEOO to OxOFFF, the contents in

TPOHH4 RAM are accessed. When the address value is within 0x1000 to Oxl7FF,

the contents in the RPOH RAM are accessed. The microprocessor bus logic is

implemented in the device top level "a2xge-poh.vhd" code. Please refer to the

Appendix for the device register description.

Table 5 - Device Register Map

I Address [12:0] 1 Memory Map

0x0000

OxODFF

LCAS FPGA Register Space

OxOEOO I TPOHH4 RAM Space

OxOFFF

Ox1 000 RPOH RAM Space 1

0x1 1 FF

RPOH RAM Space 2

I RPOH RAM Space 3

RPOH RAM Space 4

Figure 12 shows the captured waveform of the microprocessor interface. In

this waveform, the first three read operations accessed the device ID and revision

code register. The value read back are OxF5,0x39 and 0x71. The next read

operation accessed a general-purpose register. Following that is a read and write

access to the TPOHH4 RAM. The default values in the RAM are all zeros, and a

value of OxAB is written to it.

Figure 12 - Microprocessor Read Write Access Capture

4.4 Transmit Control Packet Random Access Memory

The Transmit Control Packet RAM is implemented using the Xilinx Dual-

Port Block memory cell. The memory module has two independent ports that allow

shared access to a single memory space. Both ports are functionally identical, with

each port providing read and write access to the memory. Simultaneous reads from

the same memory location may occur, but all other simultaneous, reading-from; and

writing to the same memory location is not allowed. In the LCAS FPGA

implementation, Port A of the Dual-Port Block Memory is connected to the

microprocessor interface and it is configured to support read and write operation.

Port B of the Dual-Port Block Memory is connected to the TPOHH4 Interface Block

and is configured to Read Only.

Figure 13 - TPOHH4 Dual-Port Block Memory

Connected to Microprocessor lnterface Block

(Read and Write)

Connect to TPOHH4

lnterface Block (Read Only)

I TPOHH4 DUAL PORT RAM

ADDRA[8:0] PORT A DOUTA(7:Ol

DINA[7:0]

CLKA W €A ENA

--..---------------.--.-.----------.------------.-AA--------

ADDRB[8:O] DOUTB[7:O]

DINB[7:0]

CLKB WEB

ENB

The Transmit Control Packet RAM is a 512 by 8-bit wide memory block. It

can store up to 4096-bit of data. The data structure of the Transmit Control Packet

RAM is shown in Table 6. The 9-bit wide ADDRA/B address bus is used to address

the memory location to be read or write. The 8-bit wide DINA bus is used to carry

the data to be written into the memory. The 8-bit wide DOUTAIB bus is used to

output the data read from the memory. The WEA control signal is used to allow

transfer of input data into the memory via Port A. The WEB control signal is tied

high to disable write operation. The ENA and ENB control signals are used to enable

read and write operation. The Transmit Control Packet RAM logic is implemented in

the device top level "a2xge-poh.vhd" code.

Table 6 - Transmit Control Packet RAM Data Structure

Ox000 Path 1 Path 2 MF12 (MSB)

Ox001 Path 3 Path 4

I 0x002 I Path 5 I Path 6 1 . . . - -. . . .

Ox01 7 Path 47 Path 48

1 0x01 8 Path 1 7 P a t h 2-- I =~(LSB) I Ox01 9 I Path 3 I Path 4 I 1 0x01 A 1 Path 5 I Path 6 I

. . . . . . . . . OxO2F Path 47 Path 48

I 0x030 Path 1 Path p 2 I C T R L

I 0x031 1 Path 3 I Path 4 1 1 0x032 I Path 5 I Path 6 I

0x047 Path 47 Path 48 - 0x048 Path 1 Path 2 GID

0x049 Path 3 Path 4

Ox04A Path 5 Path 6

I Ox1 69 I Path 3 I Path 4 I -

0x1 6A path5 Path 6 I I

I Ox1 7F 1 Path 47 I Path 48 I

4.5 Receive Control Packet Random Access Memory

The Receive Control Packet RAM is also implemented using the Xilinx Dual-

Port Block Memory. Port A of this Dual-Port Block Memory is connected to the

microprocessor intelface and it is configured to support read operation only. Port B

of the Dual-Port Block Memory is connected to the RPOH Inteiface Block and is

configured to write only. The Receive Control Packet RAM is 256 entries deep and

8-bit wide, and can store up to 2048 bit of data. The data structure of the Receive

Control Packet RAM is shown in Table 7.

Table 7 -Receive Control Packet RAM Data Structure

I Ox00 1 MF12 0000 I LCAS Packet Path 0x01

0x02

CTRL 001 0 I

MF12 0001

CTRL 001 0

OxOF -

0x1 0

0x1 F SQ 1111

0x20 MF12 0000 LCAS Packet Path

I 0x22 I CTRL 001 0 I

SQ 1111 - MF12 0000

- -

LCAS Packet Path

0x30

0x31

0x32

... Ox3F -

I OxB2 I CTRL 001 0 I

MF12 0000

MF12 0001

CTRL 001 0

....

SQ 1111 - I

LCAS Packet Path

OxBO

OxB1

... OxOF

MF12 0000

MF12 0001

.... SQ 1111

LCAS Packet Path 12

The Receive Control Packet RAM logic is implemented in the device top level code

"a2xge-poh-vhd".

4.6 Transmit H4 Byte Path Over Head Insertion Interface

The Transmit H4 Byte Path Overhead Insertion Integace block generates and

inserts the LCAS control packet into the ARROW 2xGE TPOHH4 port. It extracts

48 (1 for each STS-1) LCAS control packet from the Transmit Control Packet RAM

and converts them into a TPOHH4 port compatible format. The Transmit H4 Byte

Path Overhead InterSace block is implemented with six functional blocks, and it is

illustrated in Figure 14. They are the MFI Frame Counter, Bit Counter, TPOHEN

Signal Generator, 4-to-1 Shift Register and the GPIO Register block. The following

subsections describe each of the functional blocks in details. The source code of the

Transmit H4 Byte Path Overhead Inte$ace block is inciuded in

"tpohh4-interface.vhd7'.

Figure 14 - TPOHH4 Interface Block

TPOHH4 PORT

TPOHH4-DATA-

TPOHH4EN - TPOHH4MFFP -

TPOHH4FP - TPOHH4ClK -

REGISTER IMERFACE

TPOHHI-GPIO - .REG[8 127 01

GPlO REGIS1

TPOHH4_GPIO_REGjB

RAM IMERFACE

- TWHH4-BYTE-IN 17 0)

4.6.1 MFI Counter

The M~ilti Frame Indication (MFI) ccunter block tracks the MFIl frame

number of the LCAS control packet. The MFI counter counts from 0 to 15, and it

increments by 1 count when it detects the assertion of the 125 ps TPOHH4FP frame

pulse. It resets to 0 when it detects the assertion of the 2 ms TPOHH4MFFP multi

frame pulse or when the global reset signal is asserted. The MFI counter block is

used by the TPOHH4EN Signal Generator block.

4.6.2 Bit Counter

The Bit Counter Block tracks the bit position of the data byte to be inserted

into the TPOHH4 port. The Bit Counter counts from 0 to 7, and increments by 1

count when it detects the assertion of the 1.536MHz TPOHH4CLK clock. It reset to

0 when i t detects the assertion global reset signal or the assertion of the TPOHH4FP.

The Bit Counter is used by the RAM Address Generator and the Shift Register block.

4.6.3 TPOHH4EN Signal Generator

The TPOHH4EN Signal Generator block generates the TPOHH4EN signal of

the Transmit Path Overhead H4 Byte Interface. The TPOHH4EN signal is asserted

high during the most significant bit of an H4 nibble on the TPOHH4 port. The

ARROW 2xGE device uses the TPOHH4EN signal to validate the data on the

TPOHH4 port. When TPOHHEN is asserted, the data on the TPOHH4 port is

accepted by the ARROW 2xGE device. When TPOHKEN is de-asserted, the data on

the TPOHH4 port is ignored. The TPOHH4EN Signal Generator set the

TPOHH4EN high during MFIl frame # 2 to 13, and set it low during MFI frame #

0,1, 14 and 15. This is because MFI frame # 0, 1, 14 and 15 carry MF12 counts and

SQ Index, and must not be modified. The TPOHH4EN Signal Generator uses the

counter in the MFI Counter block to keep track of the lWI1 frame count.

4.6.4 RAM Address Pointer Generator

The RAM Address Pointer Generator generates a 9-bit address pointer used

for accessing the Tralzsrnit Control Packet RAM. The RAM address pointer

flywheels from a value from 0 to 383. See section 4.4 for more information on the

transmit control packet RAlM structure. The address pointer is incremented by one

when the Bit Counter reaches 8, since this indicates a byte has been transmitted. The

address pointer is reset to 0 when the TPOHH4MFFP frame pulse is asserted or when

the RAM address pointer has reached 384.

4.6.5 4-to-1 Shift Register

The 4-to-1 Shift Register converts the 4-bit wide data extracted from the

Transmit Control Packet RAM into a 1 bit serial signal. The 4-to-1 Shtft Register

latches a byte from the RAM every eight TPOHH4CLK clock cycle, and transmits 1

bit every TPOHH4CLK clock cycle. The output of the 440-1 Shift Register is used

to drive the TPOHH4 signal of the TPOHH4 port.

4.6.6 GPIO Register Block

The GPIO register block provides the logic for the general-purpose device

registers. A 64-bit TPOHH4_GPIO_REG[8: 1][7:0] control signal is integrated for

providing up to eight 8-bit configurations or status registers. The eight 8-bit registers

are hard coded to all zeros, and are intended as a placeholder for f~ tu re enhancement

or customisation.

4.6.7 TPOHH4 Interface Captured Waveform

Figure 15 shows a 2-ms capture of the signals on the TPOHHLC interface. To

generate this waveform, the tpohh4_test{ } test bench command is used. This

tpohh4-test command initializes the LCAS entries for the first STS-1 path in the

TPOHH4 RAM with a value of Ox0 to OxF. After the TPOHH4 RAM is setup, the

TPOHH4 interface begins data transmission.

The capture shows the TPOHH4MFFP frame pulse get asserted once every 2-

ms to indicate the MFIl frame alignment. The TPOHH4FP signal get asserted once

every 125 us to indicate the SONETISDH frame alignment. The TPOHH4EN signal

is asserted between MFIl # 2 to #13, and is de-assei-ted at MFIl #0, 1, 14 and 15.

The zoomed in portion shows the transmitted data during MFIl #13, and shows a

value of OxD is being transmitted serially.

Figure 15 - TPOHH4 Interface Waveform Capture

la2xge-poh/tpohh4mffp I I /a2xge-poWtpohh4-dala I I I I I I I I I I I I I I I /a2xge_poh/tpohh4en

Value O m 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 OxA OxB OxC OxD Ox€ OxF

4.7 Received Path Overhead Extraction Interface

The Received Path Overhead Extraction InterJace block extracts the LCAS

control packets from the ARROW 2xGE RPOH port, and store the packets into a

microprocessor accessible memory. In this process, the Received Path Overhead

Extraction block locates the H4 byte on the RPOH port for each STS-1 path and filter

out the other inapplicable path overhead bytes. Using the MFIl field of data, it

locates the LCAS control packet start of frame alignment and stores the LCAS

control packet in an organized memory location. See Figure 4.5 for an illustration.

In addition, the Received Path Overhead Extraction Interfnce block provides

a Member Status (MST-OK) framer that reports the status of each LCAS channel to

the microprocessor register. This feature is provided to allow the reduction in the

number of microprocessor access required by the system when monitoring MST-OK

message. Also, for system synchronization purpose, the Received Path Overhead

Extraction Interface block generates a 512 ms frame pulse. This frame pulse is used

for synchronizing the system hardware and software during the system initialisation

process.

The Receive Path Overhead Extraction Interface block is implemented with

ten functional blocks as illustrated in Figure 16. They are the Bit Counter, POH

Counter, Path Counter, Serial In Parallel Out (SIPO) H4 Extractor, Per Path RAM

Address Pointer Generator, RAM Control Signal Generator, RAM Data and Address

Signal Generator, MST Framer, MST Register and 512 ms Frame Pulse Generator

block. Each Receive Path Overhead Extraction Interface block is capable to process

up to 12 LCAS channels. Four blocks are integrated in the LCAS FPGA to support

48 channels.

Figure 16 -Receive Path Overhead Extraction Interface Block

The following subsections describe each of the functional blocks in details. The

source code for the Receive Path Overhead Extraction Interface block is included in

rpoh-interface.vhd.

4.7.1 Bit Counter

The Bit Counter block tracks the bit position of the serial data extracted from

the RPOH port. The Bit Counter counts from 0 to 7, and increments by 1 count when

i t detects the assertion of the 25.92 MHz RPOHCLK[n] clock. It reset to 0 when it

detects the assertion global reset signal or the assertion of the RPOHFP[n]. The Bit

Counter is used by the POH Counter, Path Counter, SIP0 H4 Extractor and the Per

Path RAM Address Pointer Generator block.

4.7.2 POH Counter

The ARROW 2xGE RPOH port outputs the J1, B3, C2, G1, F2, H4,23,Z4,

and Z5 path overhead bytes from each STS-1 path. Since the LCAS control packet is

located in the H4 byte, the LCAS FPGA only require to extract the H4 byte and can

ignore the other eight bytes.

The POH Counter block tracks the path overhead byte position of the data

byte to be extracted from the RPOH port. The POH counter counts from 0 to 8, with

each value represent a path overhead byte: 0 represents J1, 1 represents B3, 2

represent C2, 3 represents G1 ,4 represents F2, 5 represent H4, 6 represents 2 3 , 7

represents 24 and 8 represents Z5.

The POH Cotinter increments by 1 count when i t detects the assertion of eight

25.92 lVIHz RPOHCLK[n] clock. It reset to 0 when i t detects the assertion global

reset signal, the assertion of the RPOHFP[n], or when the POH counter has reached

8. The POH Counter block is used by the Path Counter, SIPO H4 Extractor and the

Per Path RAM Address Pointer Generator block.

4.7.3 Path Counter

The Path Counter tracks the current STS-1 path number on the RPOH port.

The Path Counter counts from 0 to 11, with 0 represent the first STS-1 path, and 11

represent the twelve path. The Path Counter increments by 1 count when the POH

counter has reached 8, and it reset to 0 when it detects the assertion of the global reset

signal, RPOHFP[n] frame pulse, or when the Path Counter has reached 11.

The Path Counter is used by the Per Path RAM Address Pointer Generator,

RAM Address and Data signal Generator, RAM Control Signal Generator, Serial In

Parallel Out H4 Extractor, and the MST Framer.

4.7.4 Serial-In-Parallel-Out H4 Extractor

The Serial In Parallel Out H4 Extractor block extract the H4 byte from the

ARROW 2xGE RPOH port, and convert it from a serial signal format into a parallel

8-bit data format. The SIPO H4 Extractor block uses the Path Counter to determine

the H4 byte location, and the Bit Counter to determine the bit position of the H4 byte.

When the Path Counter is indicating a value of 5 and when the RPOHEN signal is

asserted, it starts to accept the data on the RPOH port for the next eight RPOHCLK

clock cycles. The accepted data is stored into an 8-bit register. When the Path

Counter is indicating a value other than 5 or when the RPOHEN signal is de-asserted,

the data on the RPOH port is ignored.

The SIP0 H4 Extractor block uses the Bit Counter to distinguish the bit

position of the extracted information. When the Bit Counter is indicating a 0, the

extracted data is placed into the most significant bit of the 8-bit register. When the

Bit Counter is indicating a 1, the extracted data is placed into the second most

significant bit of the 8-bit register, and so on. When the Bit Counter is indicating a 7,

the extracted data is placed into the least significant bit of the 8-bit register.

The extracted H4 byte will be processed by the Per Path RAM Address

Pointer Generator, RAM Address and Data Signal Gerzemtor, RAM Control Signal

Generator, and the MST Framer. It will also be stored into the Received Control

Packet RAM for system access.

4.7.5 Per Path Address Pointer Generator

The Per Path Address Pointer Generator block takes in the MFIl field from

the extracted H4 byte and generates 12 address pointers. Each pointer is used for

generating the lower nibble of the Receive Control Packet RAM address bus. By

using the MFIl field to generate the RAM address, the control packet of each path

can be aligned to a fixed memory address location.

Figure 17 illustrates an example operation. In this example, the extracted H4

byte at STS-1 path # 1 is "00000000". Since the lower nibble of the H4 byte is the

MFIl field, and this H4 is extracted at STS-1 #1 timeslot, the address pointer for path

1 is "0000". This address pointer will be used by the downstream RAM Address and

Data Signal Generator block for generating the RAM Address.

Figure 17 - Per Path Address Pointer

Extracted H4 !7:0j at oath 1 timeslot

Per Path Addr Pointer for STS-1 # I = 0000

Per Path Addr Pointer for STS-1 #2

Per Path Addr Pointer for STS-1 #12

RPOH DPRAM ADDROUT17:Ol

0000 0010 0000 001 1 0000 01 00

Receive LCAS Control Packet RAM Structure

H- 8-bit -4 Path 1

RSVD 0100

1110 1111

Path 2

CTRL

RSVD 01 00

Path 12 :

4.7.6 RAM Address and Data Signal Generator

The RAM Address and Data Signal Generator block generates the

RPOH_DPRAM_ADDROUT[7:0] address and RPOH_BYTE_OUT[7:0] data signal

for the Receive Control Packet RAM interface. The RAM Address and Data Signal

Generator block uses the Per Path Address Pointer output to generate the lower

nibble of the address signal (RPOH_DPRAM_ADDROUT[3:0]), and the Path

Counter output to generate the upper nibble of the address signal

(RPOH-DPRAM_ADDROUT[7:4]). The Address signal is illustrated in

RPOH_DPRAM_ADDROUT[7:0] column of Figure 17.

To generate the data signal, the RAM Address and Data Signal Generator

block latches the extracted H4 byte to the RAM Data output. Both the address and

data signals are updated at the first bit of the 23 byte timeslot.

4.7.7 RAM Control Signal Generator

The RAM Control Signal Generator block generates the write-enable signals

(RPOH-DPRAM-WREN and RPOH-DPRAM-EN) for the Receive Control Packet

RAM interface. The RAM Control Signal Generator set both write-enable signals to

high for 3 RPOHCLK[n] clock cycles at the 23 extraction timeslot when the

RPOHEN signal is asserted. The write-enable signals are de-asserted low on other

timeslots.

4.7.8 MST Framer

The Menzber Status (MST) Framer block locates and store the LCAS

MST-OK bits. Each LCAS channel carries a MST-OK bit and it is available to all

LCAS channel. The MST Framer block locates the MST-OK field by framing to the

MFIl and MFI2 fields of the LCAS control packet. When the MSTfra~ner detects a

MFI2 = 0000 and MFIl = 1000, the extracted H4 byte contains the MST-OK bits for

STS-1 path #1 to 4. When the MST framer detects a MFI2 = 0000 and MFIl = 1001,

the extracted H4 byte contains the MST-OK bits for STS-1 path #5 to #8. The

complete encodjng of the MST-OK bits is illustrated in Table 8. The grey area in

this table are don't care, since the ARROW 2xGE device only support 48 x STS-1

path.

Table 8 - Member Status (MST-OK) Structure

4.7.9 MST Register Interface Block

The MST Register Interface Block convert the MST-OK bit in the latched

MST-OK register into a 12-bit MST-REG(11:O) register vector. This vector is

connected to the top level for microprocessor register access.

4.7.10 512 ms Frame Pulse Generator

The 512 ms Frame Pulse Generator block generate a 308.64 ns wide frame

pulse every 512 ms. The 512 nzs Frame Pulse Generate set the fp512ms output to

high when the MFIl and M.12 field are all zeros, and de-assert low on other value.

4.7.11 RPOH Port Captured Waveform

Figure 18 shows a 2-ms capture of the signals of the RPOH interface. To

generate this waveform, the rpoh-test{ ) test bench command is used. This

rpoh-test{ ) command generate the gapped RPOHCLK clock, the 125 us RPOHFP

frame pulse, the RPOHEN enable signal, and a test pattern of 0x00 to OxFF. Note

that the test sequence is skewed from MFI#8 to MFI#7. The LCAS FPGA will

realign the extracted data and align it into the correct memory location.

Figure 18 - RPOH Interface Waveform Capture 1

Figure 19 shows a series of read operations after the RPOH port has received

the above test sequence. Since the upper nibble of the H4 byte represents the MFIl

field, a value of 0x00 is placed in register 0x1000; a value of Ox1 1 is placed in

0x1001, and so on.

Figure 19 - RPOH Interface Waveform Capture 2

5 OPERATION

5.1 LCAS ADD Operation

In the LCAS add operation, the data source would require to insert an ADD

control word into the LCAS messaging channel to notify the data sink. When the

data sink is ready to accept the traffic, it would return member status OK back to the

data source. The data source would change control word of the previous highest

member to NORM, and update the current highest member to EOS.

Figure 20 shows a time sequence diagram for an LCAS ADD operation. In this

example channel 0, 2 and 7 are active and channel 9 is provisioned. It is desired to

add channel 9 into the VCG.

Figure 20 - LCAS ADD Operation

Source Node Sink Node

LCAS FPGA ARROW2kG ARROW2xG LCAS FPGA

Solware UP -

---------.---------- Note

. -. - - . - - - -. - - -- - -- - -. . Note 6 ----------------- ------------------------A,----

Note 7 * ...................... Note

Note 9 ---.--------.--.---.---- f t + a The cu~rent VCG channel with the highest sequence number is channel 7 and is indicated by CTRL=EOS. Channel 9 is in DLE. It has been provisioned, but has not been activate yet.

The system software at the source writes to the LCAS FPGA Transmit Control Word register with a value of ADD in the channel 9 timeslot.

The system software at the sink node detects the ADD control word via the LCAS FPGA receive control word register.

The system software at the sink node prepares the receive mapper by writing to the ARROW 2xGE RVCP shadow control RAM to include channel 9 in the VCG. The system software should not activate the shadow RAM at this moment.

The system software at the sink sends an MST = OK for channel 9 by writing the LCAS FPGA transmit MST register. This LCAS control packet is sent back to the source to indicate that the sink has accepted the request to add channel 9.

As soon as the system software at the source recognizes that it can start transmitting data to channel 9, it changes the LCAS FPGA Transmit Control Word for channel 7 to NORM and channel 9 to EOS.

The system software asserts the TVCPS pin to causes the TVCP to activate the shadow control RAM. The TVCP switches to the newly provisioned control RAM at the start of the next SPE boundary.

8. When the sink system software receives the CTRL=NORM for channel 7 and CTRL=EOS for channel 9, it asserts the RVCPS signal to activate the RVCP shadow control RAM active.

9. Finally the sink sends a RS-ACK to the source to complete the ADD operation by writing to the LCAS FPGA transmit RS-ACK register.

5.2 LCAS REMOVE Operation

In the LCAS remove operation, the data source would require to insert an IDLE

control word into the LCAS messaging channel to notify the data sink. When the

data sink has detected the IDLE word, it would remove the channel from the VCG as

quick as possible. Finally, it would return a MST = FAIL and Re-Ack to notify the

source that the member has been removed.

Figure 21 shows a time sequence diagra-m for an LCAS REMOVE operation. In this

example channel 9 is to be removed from the VCG and channel 7 becomes the

highest sequence member of the VCG.

Figure 21 - LCAS REMOVE Operation

I Source Node I I Sink Node I LCAS FPGA ARROW2xG ARROW2xG LCAS FPGA

FJ - - -

The current highest member in the VCG is channel 9, and its control word is currently transmitting EOS.

The system software at the source programs ARROW 2xGE TVCP shadow RAM to prepare the removal of channel 9.

The system software at the source write to the LCAS FPGA transmit control word register for channel 9 with a value of IDLE, and a value of EOS for channel 7.

The system software at the sink detects the IDLE control word on channel 9 and EOS control word on channel 7, and it programs the RVCP shadow RAM as fast as possible to remove channel 9

The system software at the sink write to the LCAS FPGA transmit member status and RS-ACK register to sends back to the source with MST = FAIL and a inverted RSACK bit to complete the LCAS REMOVE

6 LCAS FPGA PIN DESCRIPTION

Table 9 provides the functional description and defines the pin type for each of

the signal pin on the LCAS FPGA.

Table 9 - LCAS FPGA Pin Descriptions

Pin Name

Microprocessor Interface

Type

CSB

Function

RDB

WRB

RSTB

lnput

lnput

lnput

lnput

lnput

Active-low read enable (RDB).

The RDB signal is low during FPGA register read accesses. The FPGA drives the D[15:0] bus with the contents of the addressed register while RDB and CSB are low.

Active-low write strobe (WRB).

The W RB signal is low during a FPGA register write accesses. The D[15:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low.

Active-low chip select (CSB).

The CSB signal is low during FPGA register accesses.

-

-

-

The bi-directional data bus (D[7:0]). D[7:0] is used during FPGA register read and write accesses.

Address bus (A[12:0]).

A[12:0] selects specific registers during POH FPGA register accesses.

Active-low reset (RSTB).

RSTB provides an asynchronous active low reset. When RSTB is forced low, all device registers are forced to their default states.

I Receive Path Overhead Interface

Pin Name

lnput

lnput

Type

lnput

Function

-- --

Receive Path Overhead Frame Pulse

The receive path overhead frame pulse signal provides timing for the path overhead extraction.

RPOHFP is used to indicate the most significant bit (MSB) on RPOH. RPOHFP is set high when the MSB of the first J1 byte is present on RPOH.

Receive Path Overhead Clock.

The receive path overhead clock signal provides timing for the transmit path overhead extraction.

When ARROW-2xGE transmits one Ethernet channel into a single STS-48c, only RPOHCLK[I] is defined and RPOHCLK[4:2] are not defined. In all other configurations, RPOHCLK[4:1] are defined. The clocks are a nominal 20.736 MHz clock generated by gapping a 25.92 MHz clock. RPOHCLK has a 33% high duty cycle. - Receive Path Overhead.

The receive path overhead signal contains the path overhead bytes (J1, C2, G l , F2,23,24, and 25) to be extracted in the S T S - ~ ~ c / S T S - ~ ~ C / S T S - ~ ~ C / S T S - ~ C / S T S - ~ /STM-0 SONET/SDH path overhead.

A path overhead byte is accepted for extraction when the ARROW-2xGE indicates a valid byte (RPOHEN[4:1] set high).

Pin Name Function

lnput Receive Path Overhead Extract Enable.

The receive path overhead extract enable signal controls the extraction of the receive path overhead data.

RPOHEN[4:1] shall be set high during the most significant bit of a POH byte to indicate valid data on the RPOH[4:1] input.

Transmit Path Overhead H4 Byte Reserved Field Insertion Interface

lnput

lnput

lnput

The transmit path overhead clock provides timing for the bit-serial H4 byte reserved field insert interface.

The clock rate supports the transfer of 48 H4 nibbles every 125us. This clock is synchronous to SYSCLK.

The active high transmit path overhead frame pulse signal provides timing for the bits input through the TPOHH4 signal.

It is asserted for one TPOHH4CLK cycle to signify that the device is ready to accept the most significant bit of the H4 overlay nibble for the first of the 48 STS-IISTM- 0 on the following TPOHH4CLK rising edge. The ARROW-2xGE's TVCP processes 48 STS-11STM-0 H4 overlay nibbles or 16 STS-3cISTM-1 H4 overlay nibbles.

The active high transmit path overhead multi-frame pulse signal provides timing for the beginning of the multi-frame in the virtually concatenated mode.

TPOHH4MFFP is asserted for one TPOHH4CLK cycle to signify that the device is ready to accept the H4 overlay nibble corresponding to MF1[3:0]=0 for the first STS-IISTM-0 on the following TPOHH4CLK rising edge.

Pin Name Function

Output

Output

The active high transmit path overhead enable signal controls the insertion of the transmit path overhead H4 overlay data.

For H4 bytes in MF1[3:0]=2 to 13, when TPOHH4EN is asserted during the most significant bit of an H4 nibble on TPOHH4, the sampled H4 nibble is inserted into the corresponding POH H4 byte position. When TPOHH4EN is de-asserted during the most significant bit of an H4 nibble on TPOHH4, the sampled H4 nibble is ignored and default values are inserted into the corresponding POH H4 byte position.

TPOHH4EN can be set up to be asserted during the most significant of an H4 nibble only, or during the whole nibble.

For H4 bytes corresponding to MF1[3:0]=0,1, 14 and 15, this signal has no effect.

The active high transmit path overhead H4 signal supplies the data to be inserted into the reserved fields of the H4 POH byte. It carries bit serial data to be inserted into the POH H4 nibble for up to 48 STS- IISTM-0 frames or 16 STS-3cISTM-1 frames.

APPENDIX

The following registers are used to configure and monitor the operation of the

LCAS FPGA. There are two types of registers in the WGA: read-write (RJW) and

read-only (R). Status bits are retrieved using the read-only registers whereas any

configuration is done using the RJW registers. Writing values into unused register

bits has no effect. All configuration bits that can be written can also be read back.

Writable register bits are cleared to logic 0 upon reset unless otherwise noted.

Writing into read-only register bit locations does not affect FPGA operation.

Register 0000H: FPGA ID #1

I Bit 7 1 R FPGA -IDjl9] 1

Bit TY pe Function F e f a u l t

1 Bit 0 I R I FPGA -I D[12] I 1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

FPGA-ID:

This register indicates the FPGA ID of the FPGA load. FPGA-ID[19:O] returns OxF5397 to indicate it is a companion FPGA for the PM5397 ARROW 2xGE device.

R

R

R

R

R

R

FPGA -ID[18]

FPGA -ID[17]

FPGA -ID[16]

FPGA -ID[15]

FPGA -ID[14]

FPGA -ID[13]

1

1

1

0

1

0

Register 0001H: FPGA ID #2

Bit

Bit 7

Bit 6

Type

Bit 5

Hit 3 FPGA -ID[7]

Bit 2 FPGA -ID[6]

Bit 1 FPGA -ID[5]

Bit 0 FPGA -ID[4]

R

R

Bit 4 1 R

FPGA-ID:

Function

I I I 1 R

This register indicates the FPGA ID of the FPGA load. FPGA-ID[19:O] returns OxF5397 to indicate it is a companion FPGA for the PM5397 ARROW 2xGE device.

Default

FPGA_ID[11]

FPGA -ID[lO]

FPGA -ID[8]

Register 0002H: FPGA and Version ID #3

0

0

FPGA -ID[9]

1

1

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

FPGA-ID:

Function

FPGA -ID[3]

FPGA -lD[2]

FPGA -ID[1]

FPGA-ID[O]

VERSION-ID[3]

Type

R

R

R

R

R

Bit 1

Bit 0

This register indicates the FPGA ID of the FPGA load. FPGA_ID[l9:0] returns OxF5397 to indicate it is a companion FPGA for the PM5397 ARROW 2xGE device.

Default -

0

1

1

1

0

R

VERSION-ID:

R

R

This register indicates the version ID of the FPGA load. It is incremented from 1 to indicate FPGA revisions.

VERSION-ID[2] 0

VERSION-ID[1]

VERSION-ID[O]

0

1

Register 0003H - 000AH: TPOHH4 GPIO Register # 1 to #8

Function I Default

Bit 7

13it 6

Bit 5

I Bit 2 1 RNV I TPOH_GPI0[2] 1 0

Bit 4

Bit 3

I Bit 1 I RNV I TPOH-GPIO[I] I 0

RNV

RNV

RNV

RNV

RNV

This register is a placeholder for future enhancement.

TPOH_GP10[7]

TPOH-GP10[6]

TPOH-G P10[5]

Bit 0

Register 000BH: Received Member Status OK Path 1 to 8

0

0

0

TPOH_GP10[4]

TPOH_GP10[3]

I 1 Bit I Type , Function I Default

0

0

RNV

I Bit 7 1 R I MST-OKPath8 1 0

TPOH-GPIO[O] 0

Bit 6

Bit 5

R

Bit 3

MST-OK Path N:

R

R

MST-OK Path 5

MST-OK Path 4

Bit 2

Bit 1

Bit 0

The MST-OK Path N bit report the Member Status OK bit from the received control packet.

MST-OK Path 7

MST-OK Path 6

R

R

R

0

0

MST-OK Path 3

MST-OK Path 2

MST-OK Path 1

0

0

0

Register 000CH: Received Member Status OK Path 9 to 12

I Hit6 I X I Unused 1 x 1

Bit

Bit 7

TY pe

X

Bit 5

Bit 4

L l i t 3 1 R

MST-OK Path N:

Function

Unused

X

X

Bit 2

Bit 1

Bit 0


Default

X

MST-OK Path 12

Register OOODH - 00128: RPOH GPIO Register # 1 to #6

Unused

Unused

0

R

R

R

X

X

MST-OK Path 11

MST-OK Path 10

MST-OK Path 9

I Bit I TY pe

I Bit 5 1 R/W I RPOH_GPI0[5] ) 0 I

0

0

0

Function I Default I Bit 7

Bit 6


Riw

Riw

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RPOH_GP10[7]

RPOH_GP10[6]

R/W

Riw

Riw

Riw

R/W

0

0

RPOH_GPI0[4]

RPOH_GPI0[3]

RPOH_GP10[2]

RPOH-GP10[1]

RPOH-GP10[0]

0

0

0

0

0

Register 0013H: Received Member Status OK Path 13 to 20

Function Default

Bit 7 MST-OK Path 20



Bit 3

Bit 2

MST-OK Path N:

Bit 1

Bit 0


R

R


R

R

Type Function I Default ]

MST-OK Path 16

MST-OK Path 15

0

0

MST-OK Path 14

MST-OK Path 13

0

0

Bit 7

Bit 6

Bit 5

Bit 4

I Bit 2 1 R 1 MST-OK Path 23 1 0 1

X

X

Bit 3 1 R

1 Bit 1 1 R I MST-OKPath 22 1 0 I

Unused

Unused

X

X

Unused

Unused

MST-OK Path 24

MST-OK Path N:

0

Bit 0


R MST-OK Path 21 0

Register 0015H - 001AH: RPOH GPIO Register # 7 to #12

Function Default

Bit 7 RPOH_GPI0[7]

Hit 6 RPOH-GPIO[6]

Bit 5 RNV RPOH_GPI0[5]


Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register 001BH: Received Member Status OK Path 25 to 32

I Bit / Type I Function I Default I

RM'

RNV

RNV

RAN

RNV

MST-OK Path N:


RPOH-G P10[4]

RPOH_GPI0[3]

RPOH_GPI0[2]

RPOH_GP10[1]

RPOH-GP10[0]

0

0

0

0

0

Register 001CH: Received Member Status OK Path 33 to 36

Default

X

Bit

Bit 7 I I I

I Bit4 I X I Unused 1 x 1

Bit 6 1 X I I I




Bit 0 R MST-OK Path 33

TY pe

X

Bit 5

MST-OK Path N:

Function

Unused

Unused


X

X

Register OOlDH - 0022H: RPOH GPIO Register # 13 to #18

Unused X

13it

( Bit 4 1 RNV I RPOH_GP10[4] I 0 I

Bit 7

Bit 6

Bit 5

TY pe

I Bit 1 I RNV I RPOH_GP10[1] I 0 I

RNV

RNV

RNV

Bit 3

Bit 2

Function


I Default I

RPOH_GPI0[7]

RFOH_GPIO[6]

RPOH_GPI0[5]

RNV

RNV

Bit 0

0

0

0

RPOH_GP10[3]

RPOH_GPI0[2]

RNV

0

0

RPOH_GP10[0] 0


Bit

Bit 7

Bit 6

Bit 5

I Bit 2 1 R I MST-OK Path 39 1 0 I

Type

R

Bit 4

Bit 3

R

R

MST-OK Path N:

Function

MST-OK Path 44

R

R

Bit 1

Bit 0


Default

0

MST-OK Path 43

MST-OK Path 42

Register 0024H: Received Member'Status OK Path 45 to 48

0

0

MST-OK Path 41

MST-OK Path 40

R

R

Function Default

Bit 6 Unused

Bit 5 Unused

0

0

MST-OK Path 38

MST-OK Path 37

0

0

I I I

Bit 3

Bit 2

MST-OK Path N:

X Bit 4 1 X

Bit 1

Bit 0


Unused

R

R

R

R

MST-OK Path 48

MST-OK Path 47

0

0

MST-OK Path 46

MST-OK Path 45

0

0

Register 0025H - 002AH: RPOH GPIO Register # 19 to #24

Bit 6 RPOH_GP10[6]

Bit 5 RPOH_GP10[5]

Bit 4

Bit 3 RPOH-G P10[3]

Bit

Hit 7

Type

RNV

Bit 2 1 RNV


Bit 1

Bit 0

Register OEOOH + (n12)H : TPOH H4 Insertion RAM MF12 (MSB): n = 0,2 ,4 ,6 ,8 , A, C, E, 10,12,14,16,17, lA, lC, lE, 20,22,24,26,28,2A, 2C, 2E

Function

RPOH_GP10[7]

RPOH-GP10[2]

Path N MFI2 [7:4]:

Default

0

0

RNV

RNV

MFI2[7:4] carries the MSB MFI2 field of the transmit control packet. n represents the path number from 1 to 48. This register should be kept at default value for normal operation.

RPOH-GPIO[I]

RPOH-G P10[0]

0

0

Register OE18H + (d2)H : TPOH H4 Insertion RAM MFI2 (LSB): n = 0,2 ,4 ,6 ,8 , A, C, E, 10,12,14,16,17, lA, lC, lE, 20,22,24,26,28,2A, 2C, 2E

Bit 7

Bit 6

Bit 5

RNV

Bit 4

Bit 3

Bit 2

Path N MF12 [3:0]:

RNV

RNV

Bit 1

Bit 0

MFI2[3:0] carries the LSB MF12 field of the transmit control packet. n represents the path number from 1 to 48. This register should be kept at default value for normal operation.

Path n + 2 MF12 [3]

RNV

RNV

RNV

Register OE30H + (d2)H: TBOM H4 Insertion RAM CTRL: n = 0,2,4,6,8, A, C, E, 10,12,14,16,17, lA, lC, lE, 20,22,24,26,28,2A, 2C, 2E

0

Path n + 2 MF12 [2]

Path n + 2 MF12 [I]

RNV

RNV

I Bit I Type I Function I Default I

0

0

Path n + 2 MF12 [O]

Path n + 1 MF12 [3]

Path n + 1 MF12 [2]

0

0

0

Path n + 1 MF12 [I] Path n + 1 MF12 [O]

0

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Path N CTRL [3:0]:

Bit 0

CTRL[3:O] carries the CTRL field of the transmit control packet. n represents the path number from 1 to 48.

RNV

RNV

RNV

RNV

RNV

RNV

RNV

RNV

Path n + 2 CTHL 131 Path n + 2 CTRL [2]

Path n +2 CTRL[l]

Path n + 2 CTRL [0]

Path n + 1 CTRL [3]

Path n + 1 CTRL [2]

Path n + 1 CTRL [I]

0

0

0

0

0

0

0

Path n + 1CTRL [0] 0

Table 10 - CTRL Field Definition

CTRL[S:O]

0000

I 0011 I EOS I End of Sequence Indication I

0001

001 0

Command

FIXED

Register OE48H + (d2)H : TPOH H4 Insertion RAM GID: n=0,2 ,4 ,6 ,8 ,A,C,E,10 ,12 ,14 ,16 ,17 ,1A,1C, lE,20,22,24,26,28,2A,2C,2E

Remarks

This is an indication that this end uses fixed bandwidth (non-LCAS mode)

ADD

NORM

01 01

11 11

This member is about to be added to the group

Normal transmission

IDLE

DNU

Bit

This member is not part of the group of about to be removed

Do Not Use (sink reported FAIL status)

Bit 5

Path N GID [3:0]

Type

GID[3:0] cames the GID field of the transmit control packet. n represents the path number from 1 to 48.

RNV I

Register OE90H + (d2)H : TPOH H4 Insertion RAM CRC MSB: n=0,2,4 ,6 ,8 ,A,C,E,10,12,14,16,17,1A,1C, lE,20,22,24,26,28,2A,2C,2E

Function

Path n + 2 GID [0]

Path n + 1 GID [3]

Path n + 1 GID [2]

Path n + 1 GID [I]

Path n + IGID [0]

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I Bit I Type I Function I Default

Default

Path n + 2 GID [I]

0

0

0

0

0

RNV

RNV

RNV

RNV

RNV

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

RNV

RNV

RNV

RNV

RNV

Bit 0

RNV

RNV

Path n + 2 CRC8 [7]

Path n + 2 CRC8 [6]

Path n + 2 CRC8 [5]

Path n + 2 CRC8 [4]

Path n + 1 CRC8 [7]

RNV

0

0

0

0

0

Path n + 1 CRC8 [6]

Path n + 1 CRC8 [5]

0

0

Path n + 1 CRC8 [4] 0

Path N CRC [7:4]:

CRC[7:4] carries the MSB CRC field of the transmit control packet. n represents the path number from 1 to 48.

Register OEASH + (n/2)H : TPOH H4 Insertion RAM CRC LSB: n = 0,2,4,6,8, A, C, E, 10,12,14,16,17, lA, lC, lE, 20,22,24,26,28,2A, 2C, 2E

Bit I Type I Function I Default

Path N CKC [3:0]:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CRC[3:O] carries the LSB CRC field of the transmit control packet. n represents the path number from 1 to 48.

Register OECOH + (n/2)H : TPOH H4 Insertion RAM MST MSB: n = 0,2,4,6,8, A, C, E, 10,12,14,16,17, lA, lC, lE, 20,22,24,26,28,2A, 2C, 2E

RNV

RMI

RNV

WVV

RMI

RNV

RNV

RMI

Path N MST [7:4]:

MST[7:4] carries the MSB MST field of the transmit control packet. n represents the path number from 1 to 48.

Path n + 2 CRC8 [3]

Path n + 2 CRC8 [2]

Path n + 2 CRC8 [1]

Path n + 2 CRC8 [0]

Path n + 1 CRC8 [3]

Path n + 1 CRC8 [2]

Path n + 1 CRC8 [I]

Path n + 1 CRC8 [Oj

0

0

0

0

0

0

0

0

Register OEDSH + (d2)H : TPOH H4 Insertion RAM MST LSB: n = 0,2 ,4 ,6 ,8 , A, C, E, 10,12,14,16,17, lA, 1C, lE, 20,22,24,26,28,2A, 2C, 2E

1 Bit 7 1 RNV I Path n + 2 MST I31

Bit

( Bit 6 1 RNV 1 Path n + 2 MST [2]

1 Bit 5 1 RNV I Path n + 2 MST [ I ]

TY pe Default

=I Function

1 Bit 4 1 RNV 1 Path n + 2 MST[O] 1 0 I Bit 3 Path n + 1 MST [3]

Bit 2 Path n + 1 MST [2]

Bit 1 Path n + 1 MST [I]

Bit 0 Path n + 1 MST [0]

Path N MST [3:0]:

MST[3:O] carries the LSB MST field of the transmit control packet. n represents the path number from 1 to 48.

Register OEFOH + (d2)H : TPOH H4 Insertion RAM RS-ACK: n = 0,2 ,4 ,6 ,8 , A, C, E, 10,12,14,16,17, lA, lC, lE, 20,22,24,26,28,2A, 2C, 2E

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Path N RS-ACK:

TY pe

X

Bit 1

Bit 0

RS-ACK carries the RS-ACK field of the transmit control packet. n represents the path number from 1 to 48.

X

X

RNV

X

X

Function

Unused

X

RNV

Default

0

Unused

Unused

Path n + 2 RS-ACK

Unused

Unused

0

0

0

0

0

Unused

Path n + 1 RS-ACK

0

0

Register OFSOH + (d2)H : TPOH H4 Insertion RAM SQ MSB: n = 0,2,4,6,8, A, C, E, 10,12,14,16,17, lA, lC, lE, 20,22,24,26,28,2A, 2C, 2E

Path N SQ [7:4]:

Bit 1

Bit 0

SQ [7:4]: carries the MSB SQ field of the transmit control packet. n represents the path number from 1 to 48. This register must be kept at default value for normal operation.

Register OF68H + (nl2)H : TPOH PI4 Insertion RAM SQ LSB: n = 0,2,4,6,8, A, C, E, 10,12,14,16,17, lA, lC, 1E, 20,22,24,26,28,2A, 2C, 2E

RNV

Rhv

I Bit 7 1 Rhv 1 Path n + 2 SQ [3] 1 0 I

Path n + 1 SQ [5] Path n + 1 SQ [4]

Bit

0

0

TY pe

Bit 6

Bit 3 Path n + 1 SQ [3] Bit 2 Path n + 1 SQ [2] Bit 1 Path n + 1 SQ [I] Bit 0 RAN Path n + 1 SQ [0]

Bit 5

Bit 4

Path N SQ [3:0]:

Function

I I I

RAN

SQ [3:0]: carries the LSB SQ field of the transmit control packet. n represents the path number from 1 to 48. This register must be kept at default value for normal operation.

Default

RNV

RNV

Path n + 2 SQ [2] 0

Path n + 2 SQ [1] Path n + 2 SQ [0]

0

0

Register lrOOH + (n-1)*1OH : RPOH H4 Extraction RAM MFI2 (MSB): n = 1 to 12, = 0,2,4,6

Bit

I Bit5 I R ( Unused 1 0 1

Bit 7

Bit 6

I Bit4 ( R I Unused 1 0 1

Type

R

R

Function

MFI2[7:4] carries the MSB MFI2 field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

Default

Unused

Unused

Bit 3

Bit 2

Bit 1

Bit 0

Register lrOlH + (n-1)*1OH : WOM H4 Extraction RAM MF12 (LSB): n = 1 to 12, r = 0,2,4,6

0

0

MF12 [7] R 0

R

R

R

Bit

Bit 7

MFI2[3:0] carries the LSB MFI2 field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

MF12 [6]

MF12 [5]

MF12 [4]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

0

0

Type

R

R

R

R

R

R

R

Function Default

R I Unused

Unused

Unused

Unused

MF12 [3]

MF12 [2]

MF12 [I]

MF12 [O]

0

0

0

0

0

0

0

0

Register lr02H + (n-1)*1OH : RPOH H4 Extraction RAM CTRL: n = 1 to 12, r = 0 ,2 ,4 ,6

I Bit 7 1 R 1 Unused 1 0 1 1 Bit 6 1 R I Unused 1 0 I

Bit 5 Unused

Bit 4 Unused

Bit 3 CTRL [3]

Bit 2 R CTRL [2]

CTRL [3:0]:

Bit 1

Bit 0

CTRL [3:0] carries the CTRL field of the transmit control packet. n represents the path number from 1 to 12, and r represents siice number 1 to 4.

Register lsO3H + (n-1)*1OH': RPOH H4 Extraction RAM @ID: n = 1 to 12, r = 0 ,2 ,4 ,6

R

R

CTRL [I]

CTRL [0]

Bit

Bit 7

Bit 6

0

0

Bit 5

Bit 4

TY pe

R

R

-

Bit 3

GID [3:0]:

R

R

Bit 2

Bit 1

Bit 0

GID [3:0] caries the GID field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

Function

Unused

Unused

R

Default

0

0

Unused

Unused

GID [3] 0

R

R

R

0

0

GID [2]

GID [I]

GID [0]

0

0

0

Register lr06H + (n-1)*1OH : RPOH H4 Extraction RAM CRCS (MSB): n = 1 to 12, r = 0,2,4,6

Hit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

CRC8 [7:4] carries the MSB CRC8 field of the transmit control packet. n represents the path number f r ~ m 1 to 12, and r represents slice number 1 to 4.

TY pe

R

R

R

R

Bit 2

Bit 1

Bit 0

Register lr07H + (n-1)*1OH : RPOH H4 Extraction RAM CRCS (LSB): n = 1 to 12, r = 0,2,4,6

R

I Bit 1 Type I Function I Default 1

Function

Unused

Unused

Unused

Unused

R

R

R

Default

0

0

0

0

CRC8 [7]

1 Bit 4 1 I3 I Unused 1 0 1

0

CRC8 [6]

CRC8 [5]

CRC8 [4]

Bit 7

Bit 6

Bit 5

0

0

0

CRC8 [3:0] carries the LSB CRC8 fieId of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

R

R

R

Bit 2

Bit 1

Bit 0

Unused

Unused

Unused

R

R

R

0

0

0

CRC8 [2]

CRC8 [ I ]

CRC8 [0]

0

0

0

Register lrO8H + (n-l)*lOH : RPOH H4 Extraction RAM MST (MSB): n = 1 to 12, r = 0,2,4,6

MST [7:4]:

MST [7:4] carries the MSB MST field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

Register lr09H + (n-1)*1OH : RPOH H4 Extraction RAM MST (LSB):

I I Bit / Type 1 Function I Default

I Bit 7 1 I3 I Unused 1 0

I Bit 6 1 R 1 Unused 1 0

1 Bit 5 1 R I Unused I 0

I Bit 1 I R I MST [ I ] 1 0

Bit 4

Bit 3

Bit 2

1 Bit 0 I R 1 MST [0] 0

MST [3:0]:

R

R

R

MST [3:0] carries the LSB MST field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

Unused

MST [3]

MST [2]

0

0

0

Register lrOAH + (n-1)*1OH : RPOH H4 Extraction RAM RS-ACK:

I nit 1 Type I Function I Default p~

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

--

R

R

Bit 2

Bit 1

RS-ACK:

R

R

R

b i t 0 1 R

RS-ACK carries the RS-ACK field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

- - -

Unused

Unused

R

R

Register IrOEH + (n-1)*1OH : RPOH H4 Extraction RAM SQ MSB):

- --

0

0

Unused

Unused

Unused

RS-ACK

0

0

0

Unused

Unused

o

I Bit5 1 R 1 Unused 1 0

0

0

t3it

Bit 7

Bit 6

1 Bit 4 1 R I Unused 1 0

Default

0

0

TY I=

I?

R

Bit 3

Bit 2

SQ [7:4] carries the MSB SQ field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

Function

Unused

Unused

Bit 1

Bit 0

R

R

R

R

SQ 171

XI [GI

0

0

SQ [5]

sQ [4]

0

0

Register lrOFH + (n-1)*1OH : RPOH H4 Extraction RAM SQ (LSB): n = 1 to 12, r = 0,2,4,6

Rit

Bit 7

Type

R

Bit 6

Bit 5

Bit 4

Bit 3

S Q [3:0] carries the LSB S Q field of the transmit control packet. n represents the path number from 1 to 12, and r represents slice number 1 to 4.

Unused

Unused

R

R

Bit 2

Bit 1

Bit 0

Function

Unused

0

0

R

R

Default

0

R

R

R

Unused

SQ PI 0

0 1

SQ [21

SQ 111

SQ [ol

0

0

0

BIBLIOGRAPHY

[I] ITU-T, "Recommendation G.7042/Y,1305 - Link capacity adjustment scheme (LCAS) for virtual concatenated signals", November 2001.

[2] ITU-T, "Recommendation G.704 1/Y, 1303 - Generic framing procedure", December 2001.

[3] PMC-Sierra Inc, PMC-2020529 "ARROW 2xGE PM5397 Two Channel Gigabit Ethernet to SONET Mapping Device Data Sheet", March 2005.

design and implementation of the link capacity … · multi-frame indicator: the multi frame...

Documents