design and implementation
DESCRIPTION
Design and Implementation. of a Very Simple CPU. Sections 6.1 and 6.2. Stanton Lee. 6.1 Specifying a CPU. Overview. Determine its applications Choose an instruction set Design a state diagram. General CPU Cycle. Fetch Cycle: Fetch an instruction from memory - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/1.jpg)
Design and Implementation
of a Very Simple CPU
Sections 6.1 and 6.2
Stanton Lee
![Page 2: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/2.jpg)
6.1 Specifying a CPU
• Determine its applications
• Choose an instruction set
• Design a state diagram
Overview
![Page 3: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/3.jpg)
General CPU Cycle
Fetch Cycle: Fetch an instruction from memory then go to the decode cycle
Decode Cycle: Determine which instruction was fetched then go to the execute cycle
Execute Cycle: Execute the instruction then go back to the fetch cycle
![Page 4: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/4.jpg)
Generic CPU State Diagram
![Page 5: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/5.jpg)
6.2.1 Specifications
• The CPU can access 64 bytes of memory each byte being 8 bits wide
• The CPU will output a 6-bit address through pins A[5..0] and read an 8-bit value through pins D[7..0]
• There will only be one programmer usable 8-bit accumulator register labeled AC
![Page 6: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/6.jpg)
Instruction Set
![Page 7: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/7.jpg)
Internal Registers
AR: A 6-bit address register that supplies an address to memory via A[5..0]
PC: A 6-bit program counter that contains the address of the next instruction to be executed
DR: An 8-bit data register that receives instructions and data from memory via D[7..0]
IR: A 2-bit instruction register that stores an opcode
![Page 8: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/8.jpg)
6.2.2 Fetching Instructions from Memory
First State of the Fetch Cycle
• Copy the address in PC to AR
• AR will then send the address to memory for reading
• FETCH1: AR <-- PC
![Page 9: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/9.jpg)
Second State of the Fetch Cycle
• The memory will output the requested data to D[7..0]
• The CPU will read the data and store it in DR
• Increment PC
• FETCH2: DR <-- M, PC <-- PC + 1
![Page 10: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/10.jpg)
Third State of the Fetch Cycle
• Copy the two high-order bits of DR to IR (opcode)
• Copy the six low-order bits of DR to AR
• These six bits in AR can be used for ADD and AND or ignored for JMP and INC
• FETCH3: IR <-- DR[7..6], AR <-- DR[5..0]
![Page 11: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/11.jpg)
6.2.3 Decoding Instructions
• Determine which instruction was fetched
• Invoke the correct execution routine
• For this very simple CPU there are four routines
![Page 12: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/12.jpg)
Fetch and Decode Cycles
![Page 13: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/13.jpg)
6.2.4 Executing Instructions
The ADD Instruction
ADD1: DR <-- MFetch an operand from memory. Recall that AR alreadycontains an address from FETCH3.
ADD2: AC <-- AC + DRPerform the addition and store result in AC
Begin the Fetch Cycle again
![Page 14: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/14.jpg)
The AND Instruction
This is similar to the ADD instruction
AND1: DR <-- MObtain an operand
AND2: AC <-- AC ^ DRPerform a logical AND and store
Begin the Fetch Cycle again
![Page 15: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/15.jpg)
The JMP Instruction
JMP1: PC <-- DR[5..0]Simply copy the jump address to PC. The nextFetch Cycle will use that address.
Note that because the address was also copied to ARduring FETCH3 we can also perform PC <-- AR
Begin the Fetch Cycle again
![Page 16: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/16.jpg)
The INC Instruction
INC1: AC <-- AC + 1Just add 1 to the accumulator’s value and store theresult back into the accumulator
Begin the Fetch Cycle again
![Page 17: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/17.jpg)
Complete State Diagram
![Page 18: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/18.jpg)
6.2.5 Establishing Data Paths
We now design the internal data paths of the CPU tosupport all possible data transfers
Two Approaches
• Direct paths between each pair of components that transfer data
• A common bus used by all components that need to transfer data
![Page 19: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/19.jpg)
Data Transfers
AR: AR <-- PC; AR <-- DR[5..0]
DR: DR <-- M
IR: IR <-- DR[7..6]
These components only need to perform data loading
![Page 20: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/20.jpg)
Data Transfers (continued)
PC: PC <-- PC + 1; PC <-- DR[5..0]
AC: AC <-- AC + DR; AC <-- AC ^ DR; AC <-- AC + 1
These components not only load data but they alsoperform increments
![Page 21: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/21.jpg)
PreliminaryRegisterSection
Note the tri-statebuffers
![Page 22: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/22.jpg)
Modify the Design
• AR transfers data to memory not to the bus
• IR does not supply data to the other registers
• AC does not supply data either (unrealistic for a real CPU)
• The bus is 8 bits wide but not all transfers use 8 bits. Use bits 5..0 of the bus for AR and PC. Use 7..6 for IR.
• The CPU must be able to compute AC + DR and AC ^ DR. Therefore we need an ALU.
![Page 23: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/23.jpg)
FinalRegisterSection
Note the ALU
![Page 24: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/24.jpg)
6.2.6 Design of an ALU
We now consider the implementation of a simple ALU
• The two inputs are DR via the bus and AC (direct)
• The output goes to AC
Functions
1. Add the two inputs
2. Logically AND the two inputs
![Page 25: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/25.jpg)
A Very Simple ALU
Note the 2-1 MUX and the Control Signal
![Page 26: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/26.jpg)
6.2.7 Designing the Control Unit
Components
• Counter: Contains the current state
• Decoder: Generates individual signals for each state
• Logic Block: Generates control signals for each component
![Page 27: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/27.jpg)
Generic Control Unit
![Page 28: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/28.jpg)
CPU States
Recall that this CPU has a total of 9 states:
FETCH1, FETCH2, FETCH3ADD1, ADD2AND1, AND2JMP1INC1
We will require a 4-bit counter and 4-16 decoder
![Page 29: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/29.jpg)
Some Guidelines
• Assign FETCH1 to counter value 0 and use the CLR input of the counter to reach this state
• Assign sequential states to sequential counter values and use INC on the counter to traverse these states
• Assign the first state of each execute routine based on the opcodes and maximum number of states
![Page 30: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/30.jpg)
The Mapping Function
Some of the execute routines have two states. Thereforewe must ensure that their first states are at least two apart.
A mapping function that satisfies this is as follows:
1IR[1..0]0
![Page 31: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/31.jpg)
Diagram for Control Unit
![Page 32: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/32.jpg)
Control Signals
We create control signals for the registers
PCLOAD = JMP1PCINC = FETCH2DRLOAD = FETCH2 OR ADD1 OR AND1ACLOAD = ADD2 OR AND2ACINC = INC1IRLOAD = FETCH3
![Page 33: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/33.jpg)
Control Signals (continued)
We create control signals for the ALU, the buffers,and M.
MEMBUS = FETCH2 OR ADD1 OR AND1PCBUS = FETCH1
READ = FETCH2 OR ADD1 OR AND1
The ALU has a control input ALUSEL of either 0 or 1to select the proper function.
![Page 34: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/34.jpg)
Control Signal Diagram
![Page 35: Design and Implementation](https://reader036.vdocuments.us/reader036/viewer/2022062806/56814e8d550346895dbc3208/html5/thumbnails/35.jpg)
End of Presentation