describing combinational logic using processes
DESCRIPTION
ECE 545 Lecture 15. Describing Combinational Logic Using Processes. 2-to-4 Decoder. w. y. 0. 0. w. y. 1. 1. y. 2. y. En. 3. w. w. y. y. y. y. En. 1. 0. 0. 1. 2. 3. 0. 0. 0. 1. 0. 0. 1. 0. 1. 0. 1. 0. 0. 1. 1. 1. 0. 0. 0. 1. 0. 1. 1. 1. 0. 0. - PowerPoint PPT PresentationTRANSCRIPT
George Mason UniversityECE 545 – Introduction to VHDL
Describing CombinationalLogic Using Processes
ECE 545Lecture 15
2ECE 545 – Introduction to VHDL
2-to-4 Decoder
0 0 1 1
1 0 1
y 0 w 1
0
w 0
x x
1 1
0
1 1
En
0 0 0
1
0
y 1
1 0 0
0
0
y 2
0 1 0
0
0
y 3
0 0 1
0
0
w 0
En
y 0 w 1 y 1
y 2 y 3
(a) Truth table (b) Graphical symbol
3ECE 545 – Introduction to VHDL
VHDL code for a 2-to-4 DecoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGINEnw <= En & w ;WITH Enw SELECT
y <= “0001" WHEN "100","0010" WHEN "101","0100" WHEN "110",“1000" WHEN "111","0000" WHEN OTHERS ;
END dataflow ;
4ECE 545 – Introduction to VHDL
Describing combinational logic using processes
LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;
ARCHITECTURE Behavior OF dec2to4 ISBEGIN
PROCESS ( w, En )BEGIN
IF En = '1' THENCASE w IS
WHEN "00" => y <= "1000" ;WHEN "01" => y <= "0100" ;WHEN "10" => y <= "0010" ;WHEN OTHERS => y <= "0001" ;
END CASE ;ELSE
y <= "0000" ;END IF ;
END PROCESS ;END Behavior ;
5ECE 545 – Introduction to VHDL
Describing combinational logic using processes
LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY seg7 IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;
END seg7 ;ARCHITECTURE Behavior OF seg7 ISBEGIN
PROCESS ( bcd )BEGIN
CASE bcd IS -- abcdefgWHEN "0000" => leds <= "1111110" ;WHEN "0001" => leds <= "0110000" ;WHEN "0010" => leds <= "1101101" ;WHEN "0011" => leds <= "1111001" ;WHEN "0100" => leds <= "0110011" ;WHEN "0101" => leds <= "1011011" ;WHEN "0110" => leds <= "1011111" ;WHEN "0111" => leds <= "1110000" ;WHEN "1000" => leds <= "1111111" ;WHEN "1001" => leds <= "1110011" ;WHEN OTHERS => leds <= "-------" ;
END CASE ;END PROCESS ;
END Behavior ;
6ECE 545 – Introduction to VHDL
Describing combinational logic using processes
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY compare1 ISPORT ( A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ;END compare1 ;
ARCHITECTURE Behavior OF compare1 ISBEGIN
PROCESS ( A, B )BEGIN
AeqB <= '0' ;IF A = B THEN
AeqB <= '1' ;END IF ;
END PROCESS ;END Behavior ;
7ECE 545 – Introduction to VHDL
Incorrect code for combinational logic- Implied latch (1)
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY implied ISPORT ( A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ;END implied ;
ARCHITECTURE Behavior OF implied ISBEGIN
PROCESS ( A, B )BEGIN
IF A = B THENAeqB <= '1' ;
END IF ;END PROCESS ;
END Behavior ;
8ECE 545 – Introduction to VHDL
Incorrect code for combinational logic- Implied latch (2)
A B AeqB
9ECE 545 – Introduction to VHDL
Describing combinational logic using processes
Rules that need to be followed:
1. All inputs to the combinational circuit should be included in the sensitivity list2. No other signals should be included
in the sensitivity list3. None of the statements within the process
should be sensitive to rising or falling edges4. All possible cases need to be covered in the internal
IF and CASE statements in order to avoid implied latches
10ECE 545 – Introduction to VHDL
Covering all cases in the IF statement
Using ELSE
Using default values
AeqB <= '0' ;IF A = B THEN
AeqB <= '1' ;
IF A = B THENAeqB <= '1' ;
ELSEAeqB <= '0' ;
11ECE 545 – Introduction to VHDL
Covering all cases in the CASE statement
Using WHEN OTHERS
Using default values
CASE y IS WHEN S1 => Z <=
"10"; WHEN S2 => Z <=
"01"; WHEN OTHERS => Z
<= "00";END CASE;
Z <= "00";CASE y IS WHEN S1 => Z <=
"10"; WHEN S2 => Z <=
"10";END CASE;
CASE y IS WHEN S1 => Z <=
"10"; WHEN S2 => Z <=
"01"; WHEN S3 => Z <=
"00"; WHEN OTHERS => Z
<= „--";END CASE;
RTL Hardware Design by P. Chu
Chapter 10 12
RTL Hardware Design by P. Chu
Chapter 10 13
RTL Hardware Design by P. Chu
Chapter 10 14
RTL Hardware Design by P. Chu
Chapter 10 15
RTL Hardware Design by P. Chu
Chapter 10 16
RTL Hardware Design by P. Chu
Chapter 10 17
RTL Hardware Design by P. Chu
Chapter 10 18
RTL Hardware Design by P. Chu
Chapter 10 19