deliverable 6.1.4 final management report college cork tel: +353-21-234 6350 fax: n/a e-mail:...

PowerSWIPE (Project no. 318529)

“POWER SoC With Integrated PassivEs”

Deliverable 6.1.4

“Final Management Report” Dissemination level: PU

Responsible Beneficiary Tyndall

Due Date 31st March 2016

Submission Date 30th April 2016

D6.1.4, “Final Management Report”, March 2016

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Summary

No and name D6.1.4 – Final Management Report1 Status Released Due Month 42 Date 31-March-2016

Author(s) Nicolás Cordero

Editor Cian Ó Mathúna

DoW Report on Project Management from October 2012 to March 2016

Dissemination Level

PU - Public

Nature Report

Document history

V Date Author Description

Draft 18-Apr-2016 N.C. Draft

1.0 25-Apr-2016 N.C. et al. Inputs from all partners for WP reports

2.0 29-Apr-2016 N.C. Incl. effort vs WP and explanation use of resources

2.1 15-May-2016 N.C. et al. Feedback from Final Review

1 Disclaimer - The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.


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1. Table of Contents

1. Table of Contents .............................................................................................. 3

2. PROJECT PERIODIC REPORT .............................................................................. 4

3. Declaration by the scientific representative of the project coordinator ............ 5

3.1 Publishable Summary..................................................................................... 6

3.1.1 Description of project context and objectives ............................................................ 6

3.1.2 Description of work performed and main results ....................................................... 7

3.1.3 Final results and their potential impact and use (incl. socio-economic impact and the

wider societal implications of the project) .............................................................................. 10

3.1.4 Project website, logos and partners ......................................................................... 12

3.2 Core of the report for the period: Project objectives, work progress and

achievements, project management ..................................................................... 13

3.2.1 Project objectives for the period .............................................................................. 13

3.2.2 Work progress and achievements during the period ................................................ 13

3.2.3 Project management during the period ................................................................... 40

3.3 Deliverables and milestones tables .............................................................. 45

3.4 Explanation of the use of resources ............................................................. 49

3.4.1 Planned versus actual use of resources. Adjustments .............................................. 49


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2. PROJECT PERIODIC REPORT

Grant Agreement number: 318529

Project acronym: POWERSWIPE

Project title: Power System-on-Chip (SoC) with Integrated Passives

Funding Scheme: FP7-ICT-2011-8

Date of latest version of Annex I against which the assessment will be made: 7th

September 2015

Periodic report: 1st ■ 2nd ■ 3rd ■

Period covered: from 1st October 2012 to 31st March 2016

Name, title and organisation of the scientific representative of the project's coordinator2: Prof. Cian O’Mathuna, Senior Research Scientist, Tyndall National Institute, University College Cork

■Tel: +353-21-234 6350

Fax: n/a

E-mail: [email protected]

Project website3 address: www.powerswipe.eu

2 Usually the contact person of the coordinator as specified in Art. 8.1. of the Grant Agreement.

3 The home page of the website should contain the generic European flag and the FP7 logo which are available in electronic format

at the Europa website (logo of the European flag: http://europa.eu/abc/symbols/emblem/index_en.htm logo of the 7th

FP: http://ec.europa.eu/research/fp7/index_en.cfm?pg=logos). The area of activity of the project should also be mentioned.

http://europa.eu/abc/symbols/emblem/index_en.htm

http://ec.europa.eu/research/fp7/index_en.cfm?pg=logos


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3. Declaration by the scientific representative of the project

coordinator

I, as scientific representative of the coordinator of this project and in line with the obligations as stated in Article II.2.3 of the Grant Agreement declare that:

The attached periodic report represents an accurate description of the work carried out in this

project for this reporting period;

The project (tick as appropriate) 4:

□ has fully achieved its objectives and technical goals for the period; ■ has achieved most of its objectives and technical goals for the period with relatively

minor deviations. □ has failed to achieve critical objectives and/or is not at all on schedule.

The public website, if applicable

■ is up to date □ is not up to date

To my best knowledge, the financial statements which are being submitted as part of this report are in line with the actual work carried out and are consistent with the report on the resources used for the project (section 3.4) and if applicable with the certificate on financial statement.

All beneficiaries, in particular non-profit public bodies, secondary and higher education establishments, research organisations and SMEs, have declared to have verified their legal status. Any changes have been reported under section 3.2.3 (Project Management) in accordance with Article II.3.f of the Grant Agreement.

Name of scientific representative of the Coordinator: ....................................................................

Date: ............/ ............/ ............

For most of the projects, the signature of this declaration could be done directly via the IT reporting tool through an adapted IT mechanism and in that case, no signed paper form needs to be sent

4 If either of these boxes below is ticked, the report should reflect these and any remedial actions taken.


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3.1 Publishable Summary

3.1.1 Description of project context and objectives Combining high efficiency with cost-effective but high level of integration is the major driver in

power electronics today. Significant R&D and product development activity is being carried out to

develop power supplies that can be integrated directly with the actual semiconductor devices. These

new miniaturised product formats are known as Power Supply on Chip (PowerSoC), which

provide high integration in a small footprint for maximum power density, lowest component count

and highest reliability.

PowerSwipe responded to the call for “advanced More-than-Moore elements” and “their integration

and interfacing with existing technology” by aiming to develop innovative Power Supply in

Package (PwrSiP) and Power Supply on Chip(PwrSoC) technology platforms through highly

integrated passives and advanced CMOS. The PowerSwipe concept addresses the key challenges of

"systemability", "integratability" and "manufacturability" for System on Chip (SoC) power

management platforms.

An advanced design optimisation tool was developed with both component and system perspective.

PowerSwipe has leveraged the existing expertise of the consortium in the areas of integrated

passives and power management design to achieve a first integrated system-level design tool for

SoC applications. Additionally, high-volume MEMS manufacturing processes for the monolithic

power passives have been developed to enable deployment of the technologies in commercial

applications. A custom PwrSiP/PwrSoC was developed to maximise the system performance in

high volume silicon technology. On-chip intelligence will enable system performance to be

optimised for different applications. A top-down system design approach takes full advantage of the

benefits of the integrated magnetic and capacitive components while resolving issues due to smaller

absolute component values, higher switching losses and increased on-chip interference and

coupling.

PowerSwipe targets the challenges of system design, engineering, technology and manufacturability

of integrated power management systems. Two demonstrators (one high-voltage plus low-voltage at

10 MHz and the second one at 100 MHz) were designed and fabricated to address target

applications (e.g. automotive) and system requirements (efficiency, performance,

reliability/lifetime, cost and size).

The PowerSwipe main objective is to establish Europe as the leading global player over the coming

decade in this emerging space by creating a competitive, European supply chain in Power Supply

platform for System on Chip applications with no major missing links.


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3.1.2 Description of work performed and main results

Description Europe is a world leader in innovative automotive systems with competencies covering the full

supply chain from the main OEMs (Audi, BMW, Daimler, Fiat, PSA, RSA, VW) to Tier1 suppliers

(Bosch, Continental, Magneti Marelli) to leading semiconductor companies (Infineon, ST). Today’s

cars contain up to 70 electronic control units, using multi-core μControllers. The vision for

automotive control units in 2020 will be that multi-core μControllers will be directly connected to

different battery voltages (12-48V). Because of the different voltage domains, multiple power

supplies are needed for each μController. These will be power supplies on-chip (i.e. PowerSoC)

using granular power management system architecture.

PowerSwipe has addressed a key roadblock for PowerSoC by, for the first time, miniaturising and

integrating state-of-the-art, high density trench capacitor substrate technology with novel thin film

magnetics on silicon to deliver a multi-component LC (inductor-capacitor) interposer which is then

combined, in a 3D heterogeneous stack, with the μController chip. To achieve this miniaturisation

of the power passives, the switching frequency of the switched mode DC/DC converter needs to be

increased from the traditional 1 to 5 MHz space (with 90%+ converter efficiency) into the 10MHz

to 100MHz+ range.

Results A Power Management IC has been designed in 40 nm CMOS technology. This PMIC is mounted

onto a capacitive interposer, with an inductor on the side. The assembly is 3×3mm. Two different

IC were assembled for comparison purpose as an innovative power stage structure (3-MOSFETs

cascode) has been selected to enhance converter efficiency at 100MHz.

The 3D assembly has been mounted onto a PCB and tested. Measured efficiency at 100 MHz has

been compared against state of the art (SotA) converters. The innovative structure shows much

better results than the classical approach. It allows having efficiency comparable with that for 10

MHz converters.

Efficiency of 100MHz novel DC-DC converter vs. State of the Art

55

60

65

70

75

80

85

90

95

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Efficien

cy(%)

VOUT/VIN

Stateoftheart100MHzcascode100MHzstandard

10

20

40

100

200

500

Freq

uen

cy(MHz)


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Tasks, Milestones and Deliverables Tasks performed since the beginning of the project

6-month Extension:

Back-up run of integration/fabrication of Demo1

Functional testing of Demo1 Forensic testing of failed Demo1 samples

Functional testing of ITV2

Exploitation plan

Year 3:

Finalise fabrication of passives (inductor, capacitor and interposer)

Integration/fabrication of Demo1

Integration/fabrication of ITV2/Demo2

Functional testing of Demo1 Forensic testing of failed Demo1 samples


Demo1 validation plan

Draft exploitation plan

Year 2:

Finalise all the IC designs: LV, HV and HF DCDC

Tapeout and fabrication of ICs

Analysis and optimisation of chosen architectures and selected blocks

Improvement of models

Passives (inductor, capacitor and interposer) fabrication

Inductor technology transfer

Maintenance of project Web site. Dissemination activities (seminars, presentations,

publications)

Year 1:

Definition of target application requirements

System architecture, block-level optimisation and integrated circuit design

System level analysis and optimisation

Analysis and optimisation of integrated passives

Passives (inductor, capacitor and interposer) process development

Inductor technology transfer

Development of project Web site

Achieved milestones

Year3:

Ms4.3 – PSiP with integrated LC substrate (Demo2) (Month 35)

Ms1.4 – System architecture analysis completed (Month 32)

Ms4.1 – Intermediate test vehicle with integrated capacitors and inductors (ITV2)

(Month 31)

Ms4.2 – PSiP with functional interposer with TSvs, capacitors and inductors

(Demo1) (Month 30)

Ms3.2 – Inductor process transfer completed (Month 28)

Ms3.3 – Interposers ready for demos (Month 26)

Year2:

Ms3.1 – Passive components ready (Month 23)


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Ms1.3 – Tape-out first prototype chips. Error-free GDSII layout in time (Month 21)

Ms2.3 – Detailed analysis and optimisation of individual blocks for the selected

architectures (Month 18)

Year1:

Ms2.1 – Architecture analysis and evaluation (Month 12)

Ms2.2 – Analysis and optimisation of integrated passives (Month 12)

Ms1.2 – First system architecture (Month 9)

Ms1.1 – Application requirements defined (Month 3)

Completed and submitted deliverables

6-month Extension:

D1.4 – Optimised system architecture description (Month 42)

D1.5 – Optimised block-level specification (Month 42)

D2.6 – Analysis and Optimisation of Integrated Passives (Month 41)

D2.7 – Multi-disciplinary Platform for PwrSoC Design (Month 41)

D4.3 – Demonstrators Analysis and Characterisation (Month 41)

D4.1.2 – HW Demonstrator 1 – Back-up Run (Month 39)

D4.4.2 – Forensic Testing for Back-up Run (Month 42) Additional Deliverable

D5.2.2 – Final Dissemination Report (Month 42)

D5.3 – Technology Implementation and Exploitation Plan (Month 42)

D6.1.4 – Final Management Report (Month 42)

Year 3:

D4.4 – Forensic Testing (Month 36)

D4.2 – HW Demonstrator 2 (Month 35)

D3.5 – Report on interposer test (Month 34)

D3.6 – Report on process development for inductors (new process) (M34)

D3.7 – Report on process development on HV capacitors (M34)

D4.1 – HW Demonstrator 1 (Month 31)

D3.3 – Report on inductor technology transfer (Month 28)

D3.4 – Interposers fabricated for demos (Month 28)

D5.3 – Draft Exploitation Plan (Month 26)

Year 2:

D2.4 – Architecture optimisation of 1st prototype chips (Month 24)

D2.5 – Analysis and optimisation with improved models (Month 24)

D3.2 – Passive components fabricated (Month 23)

D1.3 – Design report of first prototype chips (Month 21)

D2.3 – Analysis and optimisation of selected architecture (Month 18)

D5.2.1 – Mid-term dissemination report (Month 18)

Year 1:

D1.1 – First system architecture description (Month 12)

D1.2 – Target block-level specification (Month 12)

D2.1 – Analysis and evaluation of first system architecture (Month 12)

D2.2 – Analysis and optimisation of integrated passives (Month 12)

D3.1 – Inductor process documentation ready for transfer (Month 6)

D5.1 – Project Web site (Month 3)


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3.1.3 Final results and their potential impact and use (incl. socio-economic impact and the wider societal implications of the project)

PowerSwipe has developed...

... a demonstrator, consisting of multi-component LC (inductor-capacitor) interposer, which

can be combined in a 3D heterogeneous stack together with the SoC/PMIC chip

... integrated passive components fulfilling the stringent temperature (125°C) and quality

requirements required by the automotive market and thus closing today’s gap in availability

of components

... inductor and capacitor based very high-frequency DC-DC converters in 40nm CMOS

operating at 5V supply, ready for 3D integration with power passives

... integrated very high-frequency DC-DC converters allowing PCB footprint reduction by

~100mm² per module, without compromising converter efficiency at 90%

... missing system and component level optimisation tools to achieve optimum system

configuration and efficiency for different operating modes

... a demonstrator system targeted for Automotive Microcontroller, with optimized complete

chain from car battery (5...48V) down to the core voltage domain (1V)

System level schematic of the PowerSwipe project innovations


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Achievements by partner

IPDiA Breakthrough: Low-loss, high-density, trench power capacitors

Established high volume, product line for new customers/applications

IFAT High efficiency for high-voltage DCDC conversion demonstrated (88% at

10MHz for a 12V/5V conversion, exceeding state-of-the-art)

IFX/IPDiA Understanding integration of IPDiA capacitor/interposer with IFX eWLB

artificial moulded wafer created for flip-chip bumping of limited number of

chips coming from MPW

Bosch Follow-on projects and collaboration with IFX and IPDiA

CEI-UPM 1st CAD tool for PwrSoC

Lab Ampere High efficiency, 100-200MHz on commercial PwrSiP platform

Tyndall Highest efficiency thin film coupled inductor

Technology transfer of magnetics on silicon to IFX


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3.1.4 Project website, logos and partners

Project Website:

www.powerswipe.eu

Project logo:

Project banner:

Project partners

Participant organisation name Short name Country

Tyndall National Institute, University College Cork Tyndall-UCC IRL

Infineon Technologies AG, Regensburg IFX D

Infineon Technologies Austria AG - Villach IFAT A

IPDiA, Caen IPDiA F

Centro de Electrónica Industrial, Univ. Politécnica de Madrid CEI-UPM E

Robert Bosch GmbH, Stuttgart Bosch D

Université de Lyon, Claude Bernard Lab Ampere F

http://www.powerswipe.eu/


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3.2 Core of the report for the period: Project objectives, work

progress and achievements, project management

3.2.1 Project objectives for the period

The main objectives of the PowerSwipe project for year 3 and the 6-month extension (Month 25 to

Month 42) were:

Finalise fabrication of passives (inductor, capacitor and interposer)

Integration/fabrication of Demo1

Integration/fabrication of ITV2/Demo2

Functional testing of Demo1


Validation of Demo1 samples

Draft exploitation plan

The following figure shows the Gantt chart with the tasks, deliverables and milestones for the

reporting period and to the end of the project (According to latest version of DoW, Sep 2015).

3.2.2 Work progress and achievements during the period

WP1 – System Specifications and Design

WP Objectives for Year 3 – Project extension Phase

Characterization of 2nd

run of Demo1 system

Finish all open deliverables


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Work Progress

Characterization of HV DCDC: finished successfully.

Characterization of Demo1: not successful due to package interface issues.

As consequence the following planned milestones and deliverables are limited:

o MS14: System architecture analysis completed

o Deliverable D1.4 Optimized system architecture description

o Deliverable D1.5 Optimized block-level specification

Achievements / Summary

A complete, fully integrated power management system targeted for Automotive applications was

developed. Based on the requirement definition the optimum system architecture was chosen, and the chip

design was carried out, bringing 2 different chips into fabrication: a) HV DCDC chip (HV – high voltage)) in

130nm BCD CMOS, to convert the car battery levels down to 3-5V, and b) Demo1 chip (LV – low voltage)

in 40nm CMOS.

Final measurements were carried out on the HV DCDC chip. Two different setups were tested successfully,

one operating the DCDC open loop, yielding up to 90% efficiency at 10MHz switching, and a second one

with optimized mixed-signal controller (V2IC/V

2IL control).

However on Demo1, no meaningful electrical measurements were possible, even after having 2 different

package manufacturing runs. Since the root causes are most probably packaging/metallisation issues, the

detailed failure analysis is done in WP4. These investigations were closely connected to technology

developments in WP3.

HV DCDC Chip

The HV DC-DC converter is an inductor-based step-down regulator that operates at a frequency of 10MHz.

At the moment only the power stage has been implemented on silicon.

The acceptable input voltage range goes from 6V to 16V while the output voltages for which the design has

been optimized are 3.3V and 5V. The maximum output current is 500mA.

Figure shows the block diagram of the implemented design. The power stage itself consists of a low-side

switch and a high-side switch which are both 20V NMOS devices.


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Figure 1.1. Block diagram of implemented design

Characterization

For test purposes a small board was created, which contains a HV DC-DC silicon die, directly bonded to the

PCB with external inductor L=1µH (Coilcraft) and external capacitors Cout=470nF, Cls=47nF (Taiyo

Yuden) Cin=220nF, Chs=22nF (Murata).

Efficiency measurement yields close to 90% at 10MHz switching frequency and quite nice matching with

simulated values, especially at higher loads.

Additionally we tested the possibility to operate at even higher switching frequencies. The converter had

shown a stable operation at frequencies up to 40 MHz with the same external components without adjust for

higher switching frequencies.

Also we built a prototype of mixed signal V2IC/V

2IL controller, which was successfully tested together with

HV DC-DC. This controller could be integrated in next silicon of HV DC-DC.


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Figure 1.2. PCB with directly bonded HV DC-DC and external passives

Figure 1.3. Efficiency measurement. Fsw=10/40MHz Vin=12; Vout=5V

Demo1a – fully integrated power management chip

The implemented Demo1a test chip is a complete, fully integrated power management chip for supplying

automotive microcontrollers. The chip contains an integrated inductor based DC-DC buck converter and an

integrated switched capacitor DC-DC converter. Beside the converters additional auxiliary circuits are

placed: linear voltage regulators, different oscillators, bandgap references, current references, ADCs,

temperature sensors, startup circuits.

Furthermore, an artificial load is placed on the chip in order to emulate steep current jumps from a

microcontroller load. The current ramps of the load are programmable and can be controlled by external

control signals.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

10 50 100 200 400 500

ILOAD [mA]

Efficiency (40MHz) -Vout=5V

Efficiency (10MHz) -Vout=5V


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Figure 1.4. Block diagram of the fully integrated power management chip Demo1a

Figure 1.5. Chip Layout of Demo1a

Passive components

The capacitors and inductors used for the circuits are implemented on the interposer that is placed between

the chip and the package. CIN = 665nF, COUT_LV = 400nF, COUT_SC = 260nF, Cfly = 30nF, LLV = 250nH.

Implemented Switched Mode Power Supplies

Two different types of power converter were developed during this project. The first one is a Switched

Capacitor DC-DC converter (SC DC-DC) and the second one is an inductor based DC-DC converter (LC

DC-DC).

HV-Chip:

130nm BCD CMOS

LV-Chip:

40nm (Flash) CMOS


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Measurement Results Demo 1

Demo 1 could not be characterized as planned due to manufacturing issues. For details please see WP4

report. Therefore the project team decided to do a 2nd

run, based on the remaining silicon dies, both the 40nm

CMOS IC provided by IFAT, and the passive silicon interposer, provided by IPDiA.

This 2nd

run did not show the expected improvement in connectivity between the package balls and the

interposer/IC. So again no meaningful electrical characterization of the 40nm chip was possible with the

Demo1 samples.

Figure 1.6. Demo1a Interposer/Package Interconnects and Signal Names


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Figure 1.7. Demo1A Interconnect Measurement Results

NOTE:

Dum1 to Dum2: Interconnect involves package only (ball-metal-ball) OK

Dum1 to Dum3: Interconnect involves package and interposer/TSVs (ball-metal-TSV-metal-TSV-metal-ball) NOT OK

Interposer CMOS PassivesSample

Number

Vdd_pwr

[Cs,RS]

Vdd_5v0

_evr

[Cs,RS]

Vout_sc_

dcdc

[Cs,RS]

Vout_lc_

dcdc

[Cs,RS]

Dum 1 to

Dum 2

Dum 1 or 2

to Dum 3

Dum 4 to

Dum 5

Dum 4 to

Dum 6

Dum 5 to

Dum 6

Dum 7 to

Dum 8

Dum 4 or 5

or 6 to

Dum 7 or 8

x x

no

inductor

inside 1 open open open open 800mOhm open 800mOhm 800mOhm 800mOhm 800mOhm open

x x

no

inductor

inside 2 open open open open 700mOhm open 800mOhm 800mOhm 700mOhm 800mOhm open

x x

no

inductor

inside 3 750nF open open open 900mOhm open 800mOhm 900mOhm 800mOhm 900mOhm open

Impedance measurements Connectivity measurements


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WP2 – Computer-aided Optimisation and Analysis

Work Package Objectives

The objective for the third year of WP2 can be summarized as follows:

2.1 Passive Components Improvement Validation The models developed for integrated inductors (both individual and coupled) have been improved accounting

for second order effects not considered in the previous models. These second order effects have been

obtained through the characterization of the first set of samples.

Integrated power inductors have been measured and characterized and their main electrical

parameters have been extracted under different operating conditions.

Variation of the inductance with the bias current. As it is shown in Figure , the inductance is

modified as the bias current is increased. This effect has been analyzed from the converter point

of view by means of accurate simulations and it has been shown that its effect is negligible.

New Models for Coupled Inductors. New analytical models for the coupled inductor structures

shown in Figure used in the High Frequency converter (100MHz- 200Mhz) have been

developed for the optimization.

Validation of coupled inductor structures. Different coupled inductor structures have been

analyzed and validated by measurements. The main design parameters for the coupled inductors

are shown in Table and their layouts are shown in Figure .

Figure 2.1. Inductance as a function of the bias current (220nH inductor sample)

Figure 2.2. Alternative Coupled inductor structures considered for the HF DC-DC Converter

50

500

0 250 500 750 1000

Ind

uct

ance

(n

H)

@ 1

0 M

Hz

Bias Current (mA)

Option A

L Tx L

Option B


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Table 2.1. Main Geometric and Electric Parameters of Integrated Coupled Inductor Samples

PowerSWIP

E

ITVs

L (nH) Core

Thicknes

s

Core

Length

Copper

width

Copper

Thickness

DCR

(Ohm)

Device

Footprint

ITV 2A 33nH 1.2 µm 1.22 mm 72.2 μm 35 μm 0.084 2 mm2

ITV 2B 47 nH

Coupled

(k=0.4)

1.6 µm 1.78 mm 50.62 15 μm 0.3425 2 mm2

ITV 2C 35 nH

Coupled

k=0.8

1.6 µm 1.83 mm 75.71 μm 15 μm 0.155 2 mm2

20 nH 1.6 µm 0.78 mm 97 μm 35 μm 0.053 2 mm2

ITV 2A

ITV2B

ITV 2C

Figure 2.3. Layout of Integrated Coupled Inductor Samples

2.2 System Level Design and Optimization

The main improvements regarding the System Level Design and Optimization Tool have been focused on:

33nH95,5 % 90.25%

90.25%94.8%

85.6%


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Implementation of the improved models for the integrated magnetic components and the addition of

multi-phase coupled converters with accurate models of the coupled inductors. These results have

been validated with the High Frequency DC-DC converter and the main results are summarized in

Table . It can be seen that even the highest efficiency is obtained with a single phase buck converter design operating at 200MHz. The reason is that the penalty on the efficiency of the semiconductors

(3%) is compensated with the improvement on the efficiency of the magnetic component (95%).

Table 2.2. Efficiency estimation for different couple inductor configurations for HF DC-DC

Converter

Inductor

design

Freq.

(MHz)

L

(nH)

Coupling

factor

Efficiency

(magnetics)

Efficiency

(IC)

Total

efficiency

ITV2a Single phase 200 33 -- 95,50% 87,40% 83%

ITV2b Coupled 100 45 ~0.4 90% 90,40% 81%

ITV2c Coupled

+Lout

100 35+21 >0.8 85.6% 90,40% 77%

The nonlinear effect of the variation of the inductance with the output current has also been validated

at system level and it has been shown that even though there is a drop of the inductance of from

220nH with a bias current of 0A to 170nH at with a bias current of 500mA (see Figure ) the effect on

the time domain is very small (with ideal inductor of 220nH the peak to peak current is Ipp= 450mA

and with the nonlinear inductor the value is Ipp= 440mA)

Figure 3.3. Comparison of the inductor current waveform for the 10MHz buck converter with ideal and non-

linear inductor (Red- non-linear Inductor, Blue- Ideal Inductor)

Work Progress Regarding WP2 most of the objectives have been met. There are some tasks pending that have been delayed

due to the problems encountered with the measurements of the samples:

Coupled inductor models have been developed and validated.

Analytical Models for Two different coupled inductor structures have been developed and

validated by means of Finite Elements and Measurement.

The system level optimization tool has been improved with more accurate models of the single

inductors and coupled inductors.

Additional fast ripple based controllers have been added to the optimization tool that allows

improving the dynamic response and reduce the output capacitance to be integrated.

Deliverables

The deliverables of WP2 have been moved to M41 since they depend on the measurements to be

performed to the samples, and were the cause of the extension of the project.


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D2.6 “Analysis and optimisation of integrated passives” has been moved to M41

D2.7 Multi-disciplinary platform for PwrSoC design” has been moved to M41


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WP3 – Technology Development

Work Package Objectives and Significant Results

1) Inductor fabrication for Demo 1, ITV2 and Demo2

Fabricate inductors for Demo1, ITV2 and Demo2 and carry out reliability and testing of the fabricated

inductors.

Complete initial characterisation of inductors for Demo1, ITV2 and Demo2 and die-level reliability

testing for same.

Further optimise the lamination process for improving performance of inductors

Complete the detailed reliability plan for inductors

2) Technology transfer and scale up (Tyndall to IFX) • Set up a magnetics processing line in Regensburg, Germany based on Tyndall’s processing of racetrack

structures • Develop optimised process for realising an air-core design on a 200 mm wafer

• Demonstrate fully fabricated device with closed magnetic core

3) Capacitor fabrication & interposer development

• Develop and demonstrate high voltage (BV=30V) process for HV stage • Execute preliminary reliability study and extrapolate lifetime under Bosch specified usage conditions

• Implement PICS capacitors and interposer technologies for demonstrators

• Fabricate Demo1 (LV and HV) and ITV2/Demo2 interposers

• Process PICS wafers • Develop and execute electrical testing and HF characterisation

• Assembly and evaluation of ITV2/Demo2 devices

The back-up batch of Demo1 devices was integrated (see WP4) using backup interposer and

inductor samples already fabricated during Year 3.

WP3 has met all these objectives. Significant results from WP3 are listed below.

Detailed description of all tasks in WP3

1) Inductor fabrication for Demo1, ITV2 and Demo2

Tyndall completed fabrication of Single Layer Metal (SLM) inductor designs for Demo1, ITV2 and

Demo2 and for inductor reliability testing programme. Double Layer Metal (DLM) devices were

completed by end of November 2014. Figure 3.1 below, shows image of a fully fabricated coupled

inductor for Demo2 devices.

All devices were tested at die-level at Tyndall before being shipped.


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Figure 3.1. Demo2 coupled inductors

Coupled

Inductor

Self-inductance

design value per phase

Self-inductance

test value – phase 1

Self-inductance

test value – phase 2

Demo2 45 nH 45.9 nH @ 10 MHz 44.8 nH @ 10 MHz

The high frequency testing was carried out at Lab Ampere. Figure 3.2 shows the measured AC

resistance and inductance as a function of frequency up to 100 MHz.

Figure 3.2 . Inductance, AC Resistance vs Frequency measurements done by Ampere Lab

Additionally, Tyndall has developed a lamination process using sputter deposition of NiFe

(permalloy) core. Figure 3.3 below shows the cross-section of a laminated NiFe core. The initial

characterisation of the laminated core shows that this structure has a higher operational frequency (6

lamination of 100 nm thick-500 MHz) compared to a single lamination core (100 MHz) due to

reduced eddy currents.

Figure 3.3. Cross-section of a laminated core structure.


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2) Magnetics processing technology transfer from Tyndall-IFX

IFX and Tyndall worked together in establishing a magnetics processing line in Regensburg. Figure

3.4 shows some inductors fabricated at IFX (NiFe core is sputtered, 200nm thick std. permalloy

target).

Figure 3.4. Inductors fabricated at IFX

The following processes were carried out. The resulting wafers and parts were sent to Tyndall for

characterisation:

Electro Chemical Plating of NiFe on dummy wafers

Pattern Plating has been tested on Cu Seed

Seed Etch has been demonstrated successfully (equals plating of first NiFe bottom core) NiFe plating on high topology has also been demonstrated (equals plating of the second NiFe core).

The ‘Magnetics on Silicon’ process from Tyndall has been successfully transferred and scaled up to

8” technology at IFX.

3) Development of new capacitor design method for low ESR

Reduction of capacitance parasitic is a key challenge for performance of DCDC converters. For

input capacitors, excessive resistance will result into slower response to load step. For the output

capacitor, an excessive ESR would result in higher ripple / lower efficiency and an excessive ESL

would limit the frequency of operation. Historically, most of the silicon integrated capacitor

technologies show intrinsic limitation in term of ESR. This is mainly caused by the 3D

structure/nature of refractory materials that are employed to build the capacitive structure within the

3D structures. IPDIA PICS technology naturally has such limitation.

To address this limitation, IPDIA has been developing within PowerSwipe a new approach for

routing silicon embedded capacitor. This approach has conducted to submission of a patent

(application EP15189001.9) in the course of the year 2. The concept relies on the build-up of a


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large network of elementary cells to build the capacitive element. The elementary cell (PCELL) is

optimized in term of individual ESR/ESL such that the parasitic of the large network meet the

specified target. Beside demonstration of the concept, a design methodology including parasitic

predictive model and physical layout rules has been established. To support this work, a Multi

Project silicon run has been designed and characterized in year1, a predictive model defined and

correlated to experimental results, and a new layout approach defined. Figure 3.5 illustrates the

benefit related to this design methodology compared to the native PICS design approach.

Figure 3.5: Extracted ESR VS Capacitance value for different PICS layout approach. Blue dots are

native PICS technologies. Other colours dots correspond to the new design approached developed

in PowerSwipe.

4) Design, production and assembly of LV1, LV2 and HV test vehicles

In year2, C-interposers embedding input/output capacitors, internal routing and landing patterns for

PMIC and inductors have been designed (see figure 3.6). Two different mask sets have been

produced, and corresponding silicon processed onto 2 different PICS nodes addressing both LV and

HV voltage flavour (i.e. respectively <6V and <15V VUse). In parallel with the development of the

C-Interposer, engineering tests have been conducted to demonstrate a PICS technology capable to

withstand the HV voltage rating. Indeed the native PICS3 technology has an immediate breakdown

voltage ~12V that gives sufficient lifetime margin for the LV demonstration, but is not capable for

the HV.


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Figure 3.6: Illustration of the C_Interposer layout: from left to right LV2, HV and LV1

To enhance the voltage robustness, the native PICS3 dielectric (ONO composite) has been resized

in terms of thickness. A Time Dependant Dielectric Breakdowns campaign has been conducted on

the different thickness variations to determine the best trade-off capacitive density/lifetime. This

resulted in a new PICS technology node that corresponds to the PICS3HV flavour and that is

capable to withstand the 15V with the appropriate mission profile (T°/ducty cycle).

In year 3, the silicon corresponding to the different demonstrators, LV1 (INSA) / LV2 (INFINEON)

and HV (INFINEON) has been finalized and delivered. It is worth to note, that the LV1 was not

embedding Through Silicon Vias technology and no EWLB packaging, contrary to the LV2 and HV

modules. This resulted in shorter lead time. Finally, IPDIA assembled the PMIC on the different

interposers (see figure 3.7).

Figure 3.7: Illustration of the Cinterposer after PMIC assembly: from left to right HV, LV2 and

LV1

The PowerSwipe project has enabled the development of a new layout approach to enhance PICS

silicon integrated capacitor parasitic. The benefit of the approach was demonstrated up to the

functional level on LV1 demonstrator. The approach has been generalized to other products in the

field of the power processing and PDN decoupling.


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IPDIA has also been developing a PICS technology flavour with higher breakdown voltage which is

generalized as the PICS3HV platform that is now qualified for commercial designs.

5) Testing

Main tests carried out:

Measurement of inductors under probe, up to 110 MHz. Transient measurement of inductor

current and voltage. Both single and coupled inductors (ITV2 and Demo2).

Measurements on 1st version of interposer.

Test of inductors on PCB: Preliminary test on board at 100 MHz, using wideband fixed gain amplifier, to

emulate power stage and load the inductor.

Re-characterisation of all received devices using Kelvin probes.

Figure 3.8. Setup of transient inductor measurement

Figure 3.9 shoes the measured time domain waveforms for various frequencies and duty cycles

(Test on board with wideband amplifier) for loosely coupled (k=0.4) inductors. These can be used

to identify L, R and k values.


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Figure 3.9. Measured time domain waveforms

-1

-0.5

0

0.5

1

1.5

2

0 5 10 15 20 25 30 35 40 45 50-60

-40

-20

0

20

40

60

Volt

age

(V)

Cu

rren

t (m

A)

Time (ns)

Integration resultL1=48.85 nH, L2=44.91 nH, K=-0.31, R1=0.92, R2=0.51 Ohms

at 50 MHz, R21=0.976, R

22=0.978

VL1 (V)

VL2 (V)

IL1MEASURE (mA)

IL2MEASURE (mA)

IL1CALC (mA)

IL2CALC (mA)


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WP4 – System Integration

Work Package Objectives

Demo1 Integration and fabrication

Demo1 Functional Testing

ITV2/Demo2 Integration

ITV2/Demo2 Functional Testing

Demo1 Validation

Demo1, ITV2 and Demo2 samples were fabricated and integrated as planned. The testing of the

ITV2/Demo2 devices has been carried out (See below for further details).

The functional testing of Demo1 was carried out as planned, however no device showed the

expected functionality. Therefore it was required to adjust the objectives and planning. The forensic

testing of the failed samples was carried out and it was decided to fabricate a second run of Demo2

devices addressing the issues identified. The validation testing was delayed accordingly.

The updated objectives for the 6-month extension (Month 37 to Month 42) were:

Fabrication/integration of Demo1 devices: Back-up run

Functional testing of Demo1 back-up run devices

Validation testing of Demo1 back-up run devices

Continue functional testing of ITV2/Demo2 devices

Progress towards objectives

Task 4.1.1 System-in-Package Technology (embedded solution) – Demo1

Developing a power supply in package (PSiP) solution containing a functional interposer including

Through Substrate Vias (TSV), passive devices (Inductor & Capacitor) and the respective logic IC.

By adapting eWLB technology in order to scope with the requirements of advanced CMOS

technology (e.g. ultra low k, Thermal mismatch, etc.) in terms of stress and strain adjustment an

optimum Frontend/Backend interface will be achieved. The SiP technology is aimed to be scalable

to sub 28 nm technologies.

Task 4.1.2 System-in-Package Technology (flipped solution) – ITV2-Demo2

Developing a power supply solution containing LC substrate including passive devices (Inductor &

Capacitor) and the respective logic IC based on an intermediate test vehicle). This test vehicle is

used to show the principal system feasibility by early functional and reliability characterisation. For

the demonstrator the PMIC will be microbumbed onto this functional fan out substrate. With

monolithic integrated inductors and capacities.

Task 4.2: Characterisation and reliability analysis of individual components and Demo1A

Board level characterisation according to defined electrical and reliability requirements to evaluate

the manufacturability, functionality and reliability is performed on the individual components

(inductors, trench capacitors and interposer) and the whole demonstrator system.

Development of an adequate application test board and verify the performance in the test board in

real automotive environment. Result will be an assessment whether this will fit into automotive

environment.


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Task 4.3: Forensic testing

Identify the issues causing non-functional Demo1 samples.

Significant results

Demo1

The Demo1 (both HV and LV) samples were packaged using the eWLB (Embedded Wafer Level

BGA) technology at Infineon Regensburg. Figure 4.1 shows a cross-section diagram of the eWLB

integration of PMIC (LV/HV), inductor on Si interposer with capacitors.

Figure 4.1 eWLB integration of Demo1 devices

Figure 4.2 shows the fabricated devices on virtual wafer.

Figure 4.2. HV & LV 3A527029 wafers

ITV2-Demo2

Major tasks by Ampere lab on WP4 were the setup of the measurement test-benches and the actual

measurements on the demonstrators. Several measurements were carried out to assess the

performances of the demonstrators and validate the design approach.

The converter was first tested as a standalone, validating its functionality and allowing for a first

performance measurement. A specific test-board has been designed for this purpose, and the

functionality of the chip was validated. A picture of the on-board converter is presented in the

figure below. Note that due to physical constraints, decoupling capacitors can not be too close to the

IC, limiting the effectiveness of these decoupling capacitors. Furthermore this type of assembly

requires a lot of area.


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Figure 4.3: Microphotograph of the board assembly.

Following these preliminary tests, the integrated circuit was reported onto the passive interposer,

making it a 3D assembly with a more compact full converter. The 3D assembly configurations were

processed by IPDiA. Specific test-boards have then been developed, as well as an automated test-

bench that allows for testing the converters over an important number of frequency, duty cycle and

load current values. A full characterization of the samples has then been carried out. The superiority

of the 3D assembly over the board assembly was demonstrated. The advantage of the cascode

power stage has also been validated by measurements.

Pictures of the 3D assembly and test-board are presented in the figures below.

Figure 4.4: Left: 3D assembly connected to the test-board. Right: 3D assembly test-board

Validation

Component-level reliability (CLR) of the Silicon inductors and board-level reliability (BLR) of the

eWLB packages for automotive applications was carried out.

The CLR involved thermal cycling of Tyndall‘s silicon inductors with automotive load profile for

component level. 20 inductor samples were built, packaged and measured. 1000TC were performed,

no optical damage detected. However the degradation was higher than expected. Therefore this

degradation of impedance must be covered by control IC. The results of the test show that Tyndall‘s

silicon inductors fulfil automotive requirements at component level.

The BLR involved thermal cycling of the eWLB192 (pitch 0.5mm) package with and without

underfill. Test boards were subjected to thermal cycling (Temperature range -40°C/+125°C.


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Holding time at high/low temperature: 30 min. Ramp up/down time <1 min using 2 chamber

system). The test results show that eWLB192 does not fulfil automotive requirements without

underfill. The packages with underfill show an improvement of mean time to failure to approx.

3700TC. Considered as improved variant, however still not in target for potential automotive ECU-

level applications.

Figure 4.5: Test results after 1000TC. Left: With underfill. Right: Without underfill

Forensic Testing. Identify failure mechanisms leading to LV2 and HV non functionality

Finally, in Year3 and Year4, systematic functionality issues (OPEN) have been detected on the HV

and LV2 demonstrators (embedding TSVs and packaged with EWLB) while LTV1 was functional

and performing as expected. A first failure analysis campaign did reveal on the initial run, an

insufficient copper filling within the TSVs that was a direct cause for the OPEN. Cracks were also

observed on the interposer backside revealing a large level of stress built between the RDL and the

backside deeper copper trace. This has never been seen on other IPDIA products implementing

TSVs, and therefore it is likely due to the interaction with the packaging (see figure 4.6).


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Good

die

Bad die

Figure 4.6: Physical analysis of the TSV (lot MH3496) after assembly. Left inset corresponds to

visual inspection after side polishing, right inset to SEM inspection.

An ultimate C-interposer silicon run was produced by IPDIA for the LV2. For this run IDPIA

improved the copper coverage on the backside of the wafer and did implement systematic testing of

dummies TSV-intensive structures on the wafer backside. Dies having proper continuity have been

populated with the remaining LV2 PMIC.

However, after packaging continuity issues (OPEN) were observed on all the samples. IPDIA has

been conducting an additional FA campaign on some of the failing chains. IPDIA concluded that

the copper filling was improved and behaving according expectations.

However non-critical delamination re-occurs on the wafer backside (as observed on initial run). A

critical delamination systematically occurs on the interface between the TSV and the front side

routing of the interposer. Considering the aspect of the bottom of the TSV, it appears that a large

level of stress is built-up (membrane is strained to a concave shape whereas it is normally observed

flat after processing). It is recalled that the analysed structures was electrically tested OK prior to

the assembly. This demonstrates an interaction between the TSV and the packaging process,

resulting in too large level of stress causing catastrophic failures.


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Improved

copper

Via

bottom

strain

Overview

on critical

bottom

crack

Top crack

already

observed

on run1

Figure 4.7: FA analysis of the TSV resulting from the second delivery run. It can be seen that

copper integrity is confirmed. However delamination occurred on both interfaces with minor

electrical impact on the backside and major electrical impact on the front side (bottom of via).


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LV2 and HV demonstration have been hampered by continue issue. The causes of the different

failure mechanisms have been analysed and are all related to failures in the TSV structure. IPDIA

has demonstrated that the mechanisms related to discontinuity of coper in the TSVs could be

resolved. However, another mechanism related to stress build-up during packaging could not be

resolved in the course of the project. This would require further collaboration with INFINEON, in

order to optimize the process stack, and define specific DFM rules.


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WP5 - Dissemination

Web site and LinkedIn Group

The Web site (http://www.powerswipe.eu) was kept active during the course of the project. All

public deliverables are uploaded to the Downloads page. Furthermore, a list of all publications and

presentations is kept in the Results page, including Digital Object Identifier links to allow access to

those with subscriptions.

The LinkedIn Power Supply on Chip (PwrSoC) has continued growing and now has more than 80

active members.

Tutorials

On March 2015, as part of the APEC (Applied Power Electronics Conference and Exposition) in

Charlotte (North Carolina), the PowerSwipe consortium presented a Professional Development

Seminar on Power Supply on Chip, which was well attended with over 100 attendees.

The PowerSwipe consortium also organised a two day ECPE PowerSoC workshop on

“Micropower Electronics: Powering Low-Power Systems” which took place in Munich on June 16-

17, 2015.

Papers and presentations

PowerSwipe has been very active disseminating the results of the project during the course of the

project and especially during the final year. We have presented the results of PowerSwipe research

at nine international conferences. We have also submitted 2 peer-reviewed papers which have

already been accepted for publication. The following is the list of titles presented/published in Y3

and the six-month extension (for the full list of publications and bibliographical details, check

D5.2.2, “Final Dissemination Report”):

Papers (Published or accepted for publication)

Neveu, F.; Allard, B.; Martin, C.; “A review of state-of-the-art and proposal for high

frequency inductive step-down DC–DC converter in advanced CMOS”, Analog Integrated

Circuits and Signal Processing, Vol. 87, Issue 2, May 2016, pp. 201-11.

Neveu, F.; Allard, B.; Martin, C.; Bevilacqua, P.; Voiron, F. “A 100 MHz 91.5% Peak

Efficiency Integrated Buck Converter With a Three-MOSFET Cascode Bridge”, IEEE

Transactions on Power Electronics, Vol. 31, Issue 6, June 2016, pp. 3985-8.

Anthony, R.; Wang, N.; Casey, D.P.; Ó Mathúna, C.; Rohan, J.F. “MEMS based fabrication

of high-frequency integrated inductors on Ni–Cu–Zn ferrite substrates”, Journal of

Magnetism and Magnetic Materials, vol 406, 15 May 2016, pp. 89-94.

Anthony, R.; Ó Mathúna, C.; Rohan, J.F. “Permalloy Thin films on palladium activated self-

assembled monolayer for magnetics on silicon applications”, Procedia Physics, vol 75,

2015, pp. 1205-13.

Anthony, R.; Shanahan, B.J.; Waldron, F.; Ó Mathúna, C.; Rohan, J.F. “Anisotropic Ni–Fe–

B films with varying alloy composition for high frequency magnetics on silicon

applications”, Applied Surface Science, vol 357, part A, 1 December 2015, pp. 385-90.


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Cortes, J.; Svikovic, V.; Alou, P.; Oliver, J.; Cobos, J.A. “v1 concept: designing a voltage

mode control as current mode with near time-optimal response for Buck-type converters”,

IEEE Transactions on Power Electronics, Vol. 30, Issue 10, October 2015, pp. 5829-41.

Conference Proceedings

• APEC’16 (Long Beach USA, 20-24 March 2016)

– Tyndall: “Large-Signal Power Circuit Characterization of on-Silicon Coupled

Inductors for High Frequency Integrated Voltage Regulation”

– Infineon Austria: “A Mixed-Signal Ripple-Based Controller for a 16V, 10MHz

Integrated Buck Converter”

• AACD’16 (Villach, Austria, 26-28 April 2016)

– Lab Ampere: “Heterogeneous Integration of High-Switching Frequency Inductive

Converters”

• MNE'15 (The Hague, September 21-24)

– Tyndall: “Electrochemical process for fabrication of laminated micro-inductors on

silicon”

• ECCE 2015 (Montreal, 20-24 September)

– Tyndall: “High Efficiency on-Silicon Coupled Inductors using Stacked Copper

Windings”

• EuMW, (Paris, 6-11 September)

– IPDiA: “New Ultra Low ESR Mosaic PICS Capacitors for Power Conversion”

• ICM 2015 (Barcelona, 5-10 Jul)

– Tyndall: “Permalloy Thin Films on Palladium Activated Self-Assembled Monolayer

for Magnetics on Silicon Applications”

• IWIPP'15 (Chicago, 3-6 May)

– IPDiA: “High-Density Capacitors for Power Decoupling Applications”

• ICECS 2014 (Marseille, 7-10 December)

– Lab Ampere presentation (WYMPhD Forum)

• 3DIC (Kinsale, Dec’14)

– Tyndall: “Advanced Processing for High Efficiency Inductors for 2.5D/3D Power

Supply in Package” (Best Poster Award)

• PwrSoC 2014 (Boston, 6-8 October)

– Presentations: IFAT, IPDiA, CEI-UPM, Lab Ampere

– E-posters: IFAT, Lab Ampere


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WP5 - Exploitation

All partners have been continuously looking at potential exploitation routes for the knowledge and

technologies developed through PowerSwipe. The following figure shows the PUDF spreadsheet,

with the list of potential project outcomes identified so far.

Description Type Sector IPR

Exploitation

Lead Partner

Process for fabrication of racetrack inductor

Commercial Power Electronics Own/Licence Tyndall

Multi DC-DC converter PMIC with Passives

Adv. Knowledge

Commercial

Power Electronics, Automotive,

General Own/Licence IFAT

Integrated Magnetic Design Tool Commercial CAD Licence UPM

Component embedding Si trench based capacitors

Commercial Power Electronics Own/Licence IPDiA

SiP for multi DC-DC Converter PMIC with Passives

Adv. Knowledge

Commercial

Power Electronics, Automotive,

General Own/Licence IFX

Microcontroller with embedded voltage controller

Commercial Power Electronics,

Automotive Own Bosch

Multi DC-Dc converter design used in next generation Aurix Microcontroller family

Commercial Power Electronics,

Automotive, General

Own IFAT

Figure 5.2. List of identified project outcomes from PUDF

Based on this list, the PowerSwipe consortium has produced an Exploitation Plan (Deliverable

D5.3). Two US patents on DC-DC converters have been filed by Infineon Austria and one

European patent application has been submitted by IPDiA.

Intellectual Property Rights:

Two US patent applications on “DCM regulation with digitally estimation of the zero

crossing event” by partner IFAT.

Patent pending (EP15189001.9) on novel layout approach to lower the capacitance

ESL/ESR, leveraging lithographic capabilities and combining a self-recurring capacitive

network with localized contacts.

3.2.3 Project management during the period Management tasks included the organising of consortium meetings, internal reporting on work

progress (monthly) and submission of deliverables.

Project meetings were organised on a regular basis, as well as WP specific meetings and

discussions:

Executive Steering Committee meetings were carried out on the first Tuesday of every

month via teleconference with the support of multimedia sharing facilities (WebEx)


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Consortium meetings every six months:

o 4th Six-monthly meeting: Villach (IFAT), 20-21 October 2014

o 5th Six-monthly meeting: Stuttgart (Bosch), 22-23 June 2015

WP-specific meetings were organised when required:

o WP2: Modelling meeting at UPM (Madrid) attended by Lab Ampere on 11 October

2014.

The project consortium keeps a Document Repository where all common documents and internal

reports are shared.

Problems which have occurred and how they were solved or envisaged solutions

The inductor technology transfer from Tyndall to IFX (Task 3.2) has resulted more problematic and

time consuming that originally planned. The issues identified were solved during Year 3 and this

activity is now finalised. Deliverable D3.3 describes the work carried out.

Changes in consortium

No changes

Impact of possible deviations from the planned milestones and deliverables

The PowerSwipe project progressed according to the existing version of the plan (DoW v. March

2015). Demo1, ITV2 and Demo2 samples were fabricated and their functional testing commenced

in June 2015. The ITV2/Demo2 samples are working as designed and based on the measurement

results obtained so far, they are the best in class for high frequency PwrSoC.

The Demo1 devices however did not show any functionality during testing. Furthermore, test

devices with daisy-chain structures show high resistance or no connectivity, therefore indicating

issues with interconnects within the eWLB package.

This issue was flagged by IFAT in early August as soon as it became evident. The consortium held

a number of urgent discussions to understand the issues, agree an investigation plan and consider

contingencies.

Corrective actions and contingency plan

During August 2015, the consortium started the task of Forensic Testing of Demo1 to analyse the

devices and investigate the cause of these failures. This task was finalised by the middle of

September. A confidential report was prepared (D4.4, “Failure Analysis”), including integration

design recommendations to address the identified causes of failure.

The consortium has enough back-up parts fabricated in WP3 to attempt a new integration run. After

considering a number of contingency plans to carry out this back-up integration, the consortium

decided to fabricate a full eWLB re-run.

Six-month extension

In order to achieve the original objectives of the project, the following tasks need to be undertaken

during a six-month extension (Month 37 to Month 42: 1st October 2015 to 31

st March 2016):

Completion of the Forensic Testing

Fabrication of Demo1 devices using selected integration/assembly method from the above

list


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Functional testing by IFAT

Validation by Bosch

The request for a six month extension was approved by European Commission in September 2015.

A new DoW (v. Sep 2015) has now replaced the previous DoW (v. March 2015).

Changes to Description of Work including tasks, milestones and deliverables

The main activities of the project during the requested extension will be on WP4 for Integration and

Testing. WP1 and WP3 are now finished. The activities of WP2 will wait for the results of the

functional testing to further improve the models developed during the course of the project. The

following Gantt chart shows the updated plan for WP4.

The new Task 4.3 “Forensic Testing” continued until the middle of September 2015. The back-up

fabrication run (Task 4.1) for the full eWLB re-run was started in October and finally the functional

and validation testing (T4.2) on the new Demo1 samples was carried out.

As the new back-up run samples did not show any functionality, a second Forensic Testing (Task

4.3) was carried out to identify the issues with these samples and to issue a set of recommendations

for successful integration.

Due to these changes, a new version of the DoW was agreed in September 2015, with new dates for

some of the existing deliverables. Also two new deliverables were added, one –D4.4– to report the

results of the Forensic testing and an updated version of D4.1.

Deliverable Title Current due

date

6-month

extension

D1.4 Optimised system architecture Description 33 42

D1.5 Optimised block-level specification 33 42

D2.6 Analysis/optimisation of int. passives 36 41

D2.7 Multi-disciplinary platform for PwrSoC

design

36 41

D4.1.2 Demonstrator 1 – Back-up run (new) 39

D4.3 Demonstrators analysis and characterisation 36 41

D4.4 Forensic Testing. 3D integration

recommendations

(new) 36

D5.2.2 Final Dissemination report 36 42

D5.3 Technology implementation and exploitation

plan

36 42


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D6.1.4 Final management report 36 42

Deliverables D1.4 and D1.5 When reviewing the list of due deliverables, we noticed that the consortium had made a mistake in

the updated DoW (v. Sep2015). Deliverables D1.4 and D1.5 were given a due date of M36, when

they should have been M42. The optimisation tasks related to these deliverables were originally

planned (DoW Sep2012) between the two tape-outs: Once the first tape-out devices were tested

(ITV1), they would be optimised and this optimisation included in the 2nd tape-out design. With the

updated DoW for a single tape-out, this optimisation was still carried out but once the Demo1

devices were tested. Some theoretical optimisation has already been carried out during the design

phase, and this has already been reported in D1.3. The final optimisation will be carried out once

the Demo1 (back-up run) devices are fabricated and tested (Task 4.2). Hence these two deliverables

will be submitted on M42.

Deliverables D4.1 and D4.1.2

The report on Deliverable D4.1 “Demonstrator 1” was rejected during the Year 3 Review. A new

report, describing the fabrication and integration of Demonstrator 1, covering both the original run

and the back-up run, has been prepared. This report, Deliverable D4.1.2 addresses the issues raised

with D4.1, and covers both runs therefore supersedes D4.1.


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Year 2 Review Recommendations and Actions

Update State of the Art, both

academia and industry

The consortium continuously monitors and updates the SotA

Comprehensive Exploitation plan Draft Exploitation Plan was presented during 2nd

Review.

The consortium is currently working on the Exploitation

Plan which will be presented at the Final Review

Amend DoW to reflect actual status

of the project (no 2nd

tape-out)

New DoW submitted and accepted in March 2015. A further

updated DoW to include six-month extension submitted and

accepted in September 2015

Year 3 Review Recommendation and Actions

Deliverables D4.1 and D5.3 rejected D4.1: Revised version of D4.1, updated to include back-up

run (D4.1.2) will be submitted in M42.

D5.3: Final version of D5.3 will be submitted in M42

Continuously update state of the art The consortium continuously monitors and updates the

SotA. One of the partners (Lab Ampere) has published the

following paper: Neveu, F.; Allard, B.; Martin, C.; “A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS”, Analog Integrated Circuits and Signal Processing, Vol. 87, Issue 2, May 2016, pp. 201-11. DOI: 10.1007/s10470-015-0683-z

Very tight control of the TSV

structures and, more generally, about

interconnects within the eWLB

package must be set up.

Done. Extra thickness and preliminary testing of TSVs

before integration. These TSVs are not responsible for the

failed back-up run samples.


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3.3 Deliverables and milestones tables

Deliverables

The deliverables due in this reporting period, as indicated in Annex I to the Grant Agreement have

to be uploaded by the responsible participants (as indicated in Annex I), and then approved and

submitted by the Coordinator. Deliverables are of a nature other than periodic or final reports (ex:

"prototypes", "demonstrators" or "others"). The periodic reports and the final report have NOT to

be considered as deliverables. If the deliverables are not well explained in the periodic and/or final

reports, then, a short descriptive report should be submitted, so that the Commission has a record

of their existence.

If a deliverable has been cancelled or regrouped with another one, please indicate this in the

column "Comments".

If a new deliverable is proposed, please indicate this in the column "Comments".

The number of persons/month for each deliverable has been defined in Annex I of the Grant

Agreement and cannot be changed. In SESAM, this number is automatically transferred from NEF

and is not editable. If there is a deviation from the Annex I, then this should be clearly explained in

the comments column.

This table is cumulative, that is, it should always show all deliverables from the beginning of the

project.


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Deliverables

TABLE 1. DELIVERABLES

Del. no. Deliverable name Version WP no.

Lead beneficiary

Nature

Dissem.

level5

Delivery date from Annex I

Actual / Forecast delivery

date

Status No

submitted/ Submitted

Comments

D5.1 Project Web Site 1.1 5 Tyndall O PU M3 M4 Submitted

D3.1 Inductor process documentation ready for transfer Final 3 Tyndall R PU M6 M7 Submitted

D1.1 First system architecture description Final 1 IFAT R CO M12 M13 Submitted

D1.2 Target block-level specification Final 1 IFAT R CO M12 M13 Submitted

D2.1 Analysis and evaluation of first system

architecture

Final 2 CEI-UPM R PU M12 M13 Submitted

D2.2 Analysis and optimisation of integrated passives Final 2 CEI-UPM R PU M12 M13 Submitted

D6.1.1 First Annual Management Report 2.0 6 Tyndall R PU M12 M13 Submitted

D1.3 Design report of 1st prototype chips 1.3 1 IFAT R CO M18 M22 Submitted

D2.3 Analysis and optimisation of selected

architectures Final 2 UPM R PU M18 M19 Submitted

D3.2 Passive components fabricated Final 3 Tyndall R PU M18 M24 Submitted

D5.2.1 Mid-term dissemination report 1.2 5 Tyndall R PU M18 M19 Submitted

D2.4 Architecture optimisation of 1st prototype chips Final 2 UPM R PU M24 M25 Submitted

D2.5 Analysis and optimisation with improved models Final 2 UPM R PU M24 M25 Submitted

D3.3 Report on inductor technology transfer 3 Tyndall R PU M24 M35 Submitted

D6.1.2 2nd annual management report 6 Tyndall R PU M24 M25 Submitted

D3.3 Inductor Technology Transfer 3 IFX R CO M28 M35 Submitted

5 PU = Public. PP = Restricted to other programme participants (including the Commission Services). RE = Restricted to a group specified by the consortium (including the Commission Services). CO = Confidential, only for members of the consortium (including the Commission Services). Make sure that you are using the correct following label when your project has classified deliverables. EU restricted = Classified with the mention of the classification level restricted "EU Restricted". EU confidential = Classified with the mention of the classification level confidential " EU Confidential ". EU secret = Classified with the mention of the classification level secret "EU Secret "


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D3.4 Interposers Fabricated for Demos 3 IPDiA R CO M28 M29 Submitted

D4.1 HW Demonstrator 1 4 IFX D/R CO M31 M33 Fabricated See D4.1.2

D3.5 Interposer Test 3 IPDiA R CO M34 M35 Submitted

D3.6 Process Development of Inductors 3 Tyndall R CO M34 M36 Submitted

D3.7 Process Development for HV capacitors 3 IPDiA R CO M34 M35 Submitted

D4.2 HW Demonstrator 2 4 Lab

Ampere D/R CO M35 M36 Fabricated

D4.4 Forensic Testing 4 IPDiA R CO M36 M37 Submitted

D6.1.3 3rd annual management report 6 Tyndall R PU M36 M37 Submitted

D4.1.2 HW Demonstrator 1 – Back-up Run 4 IFX D/R CO M39 M43 Fabricated

D2.6 Analysis and Optimisation of Integrated Passives 2 CEI-UPM R PU M41 M43 Submitted

D2.7 Multi-disciplinary Platform for PwrSoC Design 2 CEI-UPM R CO M41 M43 Submitted

D4.3 Demonstrators Analysis and Characterisation 4 Bosch R CO M41 M43 Submitted

D1.4 Optimised system architecture description 1 IFAT R CO M42 M43 Submitted

D1.5 Optimised block-level specification 1 IFAT R PU M42 M43 Submitted No content

D4.4.2 Forensic Testing for Back-up Run 4 IPDiA R CO M42 M43 Submitted Extra

(Not in DoW)

D5.2.2 Final Dissemination Report 5 Tyndall R PU M42 M43 Submitted

D5.3 Tech. Implementation and Exploitation Plan 5 Tyndall R PU M42 M43 Submitted

D6.1.4 Final Management Report 6 Tyndall R PU M42 M43 Submitted (This doc)


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Milestones

Please complete this table if milestones are specified in Annex I to the Grant Agreement. Milestones

will be assessed against the specific criteria and performance indicators as defined in Annex I.

This table is cumulative, which means that it should always show all milestones from the beginning

of the project.

TABLE 2. MILESTONES

Milestone no.

Milestone name Work package

no

Lead beneficiary

Delivery date from Annex I dd/mm/yyyy

Achieved

Yes/No

Actual / Forecast

achievement date

dd/mm/yyyy

Comments

Ms1.1 Application

requirements defined 1 IFAT 31/12/2012 YES 31/12/2012

Ms1.2 First system

architecture 1 IFAT 30/06/2013 YES 30/06/2013

Ms2.1 Architecture analysis

and evaluation 2 UPM 30/09/2013 YES 30/09/2013

Ms2.2 Analysis and

optimisation of

integrated passives

2 UPM 30/09/2013 YES 30/09/2013

Ms1.3 Tape-out 1st prototype

chips 1 IFAT 31/12/2013 YES 30/06/2014 New plan

Ms2.3 Detailed analysis and

optimisation of

selected architectures

2 UPM 31/03/2014 YES 31/03/2014

Ms3.1 Passive components

ready 3 Tyndall 31/03/2014 YES 31/08/2014

Ms4.1 Intermediate test

vehicle (ITV2) 4 Lab

Ampere

30/04/2015 YES 30/04/2015

Ms4.2 PSiP with functional

interposer with TSVs,

capacitors and

inductors (Demo1)

4 IFX 30/04/2015 YES 30/05/2015

Ms4.3 PSiP with integrated

LC substrate (Demo2) 4 Lab

Ampere

30/04/2015 YES 30/04/2015

Ms1.4 System Architecture

Analysis completed 1 IFAT 31/05/2015 YES 31/05/2015

Ms3.2 Inductor process

transfer completed 3 IFX 30/09/2014 YES 31/07/2015

Ms3.3 Interposers ready for

demos 3 IPDiA 30/11/2014 YES 30/11/2014


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3.4 Explanation of the use of resources Explanation of personnel costs, subcontracting and any major costs incurred by each beneficiary for the reporting period are listed in the tables below.

3.4.1 Planned versus actual use of resources. Adjustments

The table in next page shows the effort (person.month) distribution by WP and partner, both

planned and actual.

The values in this table show that there were some deviations on the allocation of effort for some

partners and over time during the course of the PowerSWIPE project. These were mainly due to the

new plan, the delay in the Technology Transfer and the non-functional Demo1 samples which

required a back-up run. The new plan required extra effort on WP1 during Year 2, to further

improve and validate the IC design, including adding extra functionality and new modules. The

delays on the Technology Transfer from Tyndall to IFX, meant that Tyndall had to place an

unplanned extra effort to fabricate and test the inductors for the Demonstrator and ITVs. There was

also extra work on the two Demo1 eWLB runs. The effort in Reliability was reduced as there were

no functional Demonstrator 1 samples.

These were the main adjustments:

• Per WP

– WP3: More effort than planned to fabricate inductors

– WP4: Effort moved to latter part of the project (Year 3 and Extension) for

integration/validation activities

• Per Partner

– Tyndall: More effort to fabricate inductors for Demonstrators

– IFAT: More design effort to get 1st tape out right and optimised

– Bosch: Most effort during latter part of the project (Extension) on

Reliability/Validation

– Ampere: Effort in design during first half of the project (Years 1 and 2), while more

effort on integration, testing and validation of Demo2 during second half (Year 3 and

Extension).

There was no major deviation between planned and actual use on consumables, travel and

equipment. Hence no adjustments on the use of resources were required.


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Effort per WP (October 2014 to March 2016)

Workpackage6 WP1 WP2 WP3 WP4 WP5 WP6

TOTAL per

Beneficiary

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual Total Planned total

Tyndall-UCC 0.3 0.4 6.2 8 30.8 16.6 11.2 8 2.8 2.6 4.3 2.4 55.6 38

IFX - - - - 18.28 11.7 16.1 11.4 2.5 1.0 2.61 1.0 39.49 25.1

IFAT 1.22 21.7 - - - - 14.18 2.7 1.37 10 1.0 1.0 17.77 26.4

IPDIA - 0.5 - - 3.61 3.5 3.63 4.5 0.26 0.5 0.5 0.15 8.0 9.15

UPM 2 8 10.5 12 0.66 - 0.2 - 2.4 0.67 0.21 0.25 15.97 20.92

BOSCH 1.01 1.67 - - 0.89 0.5 3.33 8 - - 0.23 - 5.46 10.17

UCBL 7.62 6.3 0.84 5.9 7.09 4.2 14.17 10.3 8.31 0.4 - - 38.03 27.1

TOTAL 12.15 38.57 17.54 25.9 61.33 36.5 62.81 44.9 17.64 6.17 8.85 4.8 180.32 156.84

6 Please indicate in the table the number of person months over the whole duration for the planned work, for each workpackage by each beneficiary


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Cumulative Effort per WP (October 2012 to March 2016)

Workpackage7 WP1 WP2 WP3 WP4 WP5 WP6

TOTAL per

Beneficiary

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual Total Planned

total

Tyndall-UCC 0.9 1.0 26.5 24 93.0 50 19.2 16 8.6 8.0 10.6 7.0 158.8 106

IFX 4.96 1.5 1.5 1.5 36.46 35 22.25 34 3.0 3.0 3.26 3.0 71.43 78

IFAT 66.42 65 - - - - 16.98 8.0 2.07 1.0 4.2 3.0 89.67 77

IPDIA 2.54 2.5 - - 12.74 12.5 10.38 11 0.52 0.5 1.1 0.5 27.28 27

UPM 24 24 36.5 36 0.66 - 0.2 - 3.74 2.0 0.87 1.0 65.97 63

BOSCH 2.78 5.0 0.07 1.5 0.94 1.5 5.1 16 - - 0.84 1.0 9.73 25

UCBL 24.83 19 10.02 17.8 10.75 12.6 14.72 20.6 10.38 1.0 - - 70.7 71

TOTAL 126.43 118 74.59 80.8 154.55 111.6 88.83 105.6 28.31 15.5 20.87 15.5 493.58 447

7 Please indicate in the table the number of person months over the whole duration for the planned work, for each workpackage by each beneficiary

deliverable 6.1.4 final management report college cork tel: +353-21-234 6350 fax: n/a e-mail:...

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