deliverable 6.1.3 third annual management report · d6.1.3, “3rd annual management report”,...

PowerSWIPE (Project no. 318529)

“POWER SoC With Integrated PassivEs”

Deliverable 6.1.3

“Third Annual Management Report” Dissemination level: PU

Responsible Beneficiary Tyndall

Due Date 30th September 2015

Submission Date 2nd November 2015

D6.1.3, “3rd Annual Management Report”, September 2015

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Summary

No and name D6.1.3 – Third Annual Management Report1 Status Released Due Month 36 Date 30-September-2015

Author(s) Nicolás Cordero

Editor Cian Ó Mathúna

DoW Report on Project Management from October 2014 to September 2015

Dissemination Level

PU - Public

Nature Report

Document history

V Date Author Description

Draft 18-Oct-2015 N.C. Draft

1.0 30-Oct-2015 N.C. et al. Inputs from all partners for WP reports

2.0 6-Nov-2015 N.C. Incl. effort vs WP and explanation use of resources

1 Disclaimer - The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.


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1. Table of Contents

1. Table of Contents ................................................................................................................. 3

2. PROJECT PERIODIC REPORT ........................................................................................... 4

3. Declaration by the scientific representative of the project coordinator................................... 5

3.1 Publishable summary ........................................................................................................ 6

3.1.1 Description of project context and objectives ............................................................. 6

3.1.2 Description of work performed since the beginning of the project and main results so

far 6

3.1.3 Expected final results and their potential impact and use (including the socio-

economic impact and the wider societal implications of the project so far) ................................ 8

3.1.4 Project website, logos and partners ........................................................................... 9

3.2 Core of the report for the period: Project objectives, work progress and achievements,

project management .................................................................................................................. 11

3.2.1 Project objectives for the period ............................................................................... 11

3.2.2 Work progress and achievements during the period ................................................ 11

3.2.3 Project management during the period .................................................................... 34

3.3 Deliverables and milestones tables ................................................................................ 40


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2. PROJECT PERIODIC REPORT

Grant Agreement number: 318529

Project acronym: POWERSWIPE

Project title: Power System-on-Chip (SoC) with Integrated Passives

Funding Scheme: FP7-ICT-2011-8

Date of latest version of Annex I against which the assessment will be made: 7th

September 2015

Periodic report: 1st □ 2nd □ 3rd ■

Period covered: from 1st October 2014 to 30th September 2015

Name, title and organisation of the scientific representative of the project's coordinator2: Prof. Cian O’Mathuna, Senior Research Scientist, Tyndall National Institute, University College Cork

■Tel: +353-21-234 6350

Fax: n/a

E-mail: [email protected]

Project website3 address: www.powerswipe.eu

2 Usually the contact person of the coordinator as specified in Art. 8.1. of the Grant Agreement.

3 The home page of the website should contain the generic European flag and the FP7 logo which are available in electronic format

at the Europa website (logo of the European flag: http://europa.eu/abc/symbols/emblem/index_en.htm logo of the 7th

FP: http://ec.europa.eu/research/fp7/index_en.cfm?pg=logos). The area of activity of the project should also be mentioned.

http://europa.eu/abc/symbols/emblem/index_en.htm

http://ec.europa.eu/research/fp7/index_en.cfm?pg=logos


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3. Declaration by the scientific representative of the project

coordinator

I, as scientific representative of the coordinator of this project and in line with the obligations as stated in Article II.2.3 of the Grant Agreement declare that:

The attached periodic report represents an accurate description of the work carried out in this

project for this reporting period;

The project (tick as appropriate) 4:

■ has fully achieved its objectives and technical goals for the period; □ has achieved most of its objectives and technical goals for the period with relatively

minor deviations. □ has failed to achieve critical objectives and/or is not at all on schedule.

The public website, if applicable

■ is up to date □ is not up to date

To my best knowledge, the financial statements which are being submitted as part of this report are in line with the actual work carried out and are consistent with the report on the resources used for the project (section 3.4) and if applicable with the certificate on financial statement.

All beneficiaries, in particular non-profit public bodies, secondary and higher education establishments, research organisations and SMEs, have declared to have verified their legal status. Any changes have been reported under section 3.2.3 (Project Management) in accordance with Article II.3.f of the Grant Agreement.

Name of scientific representative of the Coordinator: ....................................................................

Date: ............/ ............/ ............

For most of the projects, the signature of this declaration could be done directly via the IT reporting tool through an adapted IT mechanism and in that case, no signed paper form needs to be sent

4 If either of these boxes below is ticked, the report should reflect these and any remedial actions taken.


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3.1 Publishable summary

3.1.1 Description of project context and objectives Combing high efficiency with cost-effective but high level of integration is the major driver in

power electronics today. PowerSwipe responds to the call for “advanced More-than-Moore

elements” and “their integration and interfacing with existing technology” by aiming to develop

innovative Power Supply in Package (PwrSiP) and Power Supply on Chip(PwrSoC) technology

platforms through highly integrated passives and advanced CMOS. The PowerSwipe concept

addresses the key challenges of "systemability", "integratability" and "manufacturability" for

System on Chip (SoC) power management platforms.

An advanced design optimization tool will be developed with both component and system

perspective. PowerSwipe will leverage the existing expertise of the consortium in the area of

integrated passive and power management design to achieve a first integrated system-level design

tool for SoC applications. Additionally, High-volume MEMS manufacturing processes for the

monolithic power passives will be developed to enable deployment of the technologies in

commercial applications. A custom PwrSiP/PwrSoC will be developed to maximise the system

performance in high volume silicon technology. On-chip intelligence will enable system

performance to be optimised for different applications. A top-down system design approach will

take full advantage of the benefits of the integrated magnetic and capacitive components while

resolving issues due to smaller absolute component values, higher switching losses and increased

on-chip interference and coupling.

Two intermediate test Vehicles and two demonstrators will address a target applications (e.g.

automotive) and system requirements (efficiency, performance, reliability/lifetime, cost, size). The

project aims to establish Europe as the leading global player over the coming decade in this

emerging space by creating a competitive, European supply chain in Power Supply platform for

System on Chip applications with no major missing links.

3.1.2 Description of work performed since the beginning of the project and main results so far

Tasks performed since the beginning of the project

Year 3:

Finalise fabrication of passives (inductor, capacitor and interposer)

Integration/fabrication of Demo1

Integration/fabrication of ITV2/Demo2

Functional testing of Demo1 Forensic testing of failed Demo1 samples

Functional testing of ITV2

Demo1 validation plan

Draft exploitation plan

Year 2:

Finalise all the IC designs: LV, HV and HF DCDC

Tapeout and fabrication of ICs

Analysis and optimisation of chosen architectures and selected blocks

Improvement of models

Passives (inductor, capacitor and interposer) fabrication


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Inductor technology transfer

Maintenance of project Web site. Dissemination activities (seminars, presentations,

publications)

Year 1:

Definition of target application requirements

System architecture, block-level optimisation and integrated circuit design

System level analysis and optimisation

Analysis and optimisation of integrated passives

Passives (inductor, capacitor and interposer) process development

Inductor technology transfer

Development of project Web site

Achieved milestones

Year3:

Ms4.3 – PSiP with integrated LC substrate (Demo2) (Month 35)

Ms1.4 – System architecture analysis completed (Month 32)

Ms4.1 – Intermediate test vehicle with integrated capacitors and inductors (ITV2)

(Month 31)

Ms4.2 – PSiP with functional interposer with TSvs, capacitors and inductors

(Demo1) (Month 30)

Ms3.2 – Inductor process transfer completed (Month 28)

Ms3.3 – Interposers ready for demos (Month 26)

Year2:

Ms3.1 – Passive components ready (Month 23)

Ms1.3 – Tape-out first prototype chips. Error-free GDSII layout in time (Month 21)

Ms2.3 – Detailed analysis and optimisation of individual blocks for the selected

architectures (Month 18)

Year1:

Ms2.1 – Architecture analysis and evaluation (Month 12)

Ms2.2 – Analysis and optimisation of integrated passives (Month 12)

Ms1.2 – First system architecture (Month 9)

Ms1.1 – Application requirements defined (Month 3)

Completed and submitted deliverables

Year 3:

D1.4 – Optimised system architecture description (Month 36) Should be M42

D1.5 – Optimised block-level specification (Month 36) Should be M42

D4.4 – Forensic Testing (Month 36)

D4.2 – HW Demonstrator 2 (Month 35)

D3.5 – Report on interposer test (Month 34)

D3.6 – Report on process development for inductors (new process) (M34)

D3.7 – Report on process development on HV capacitors (M34)

D4.1 – HW Demonstrator 1 (Month 31)

D3.3 – Report on inductor technology transfer (Month 28)

D3.4 – Interposers fabricated for demos (Month 28)

D5.3 – Draft Exploitation Plan (Month 26)


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Year 2:

D2.4 – Architecture optimisation of 1st prototype chips (Month 24)

D2.5 – Analysis and optimisation with improved models (Month 24)

D3.2 – Passive components fabricated (Month 23)

D1.3 – Design report of first prototype chips (Month 21)

D2.3 – Analysis and optimisation of selected architecture (Month 18)

D5.2.1 – Mid-term dissemination report (Month 18)

Year 1:

D1.1 – First system architecture description (Month 12)

D1.2 – Target block-level specification (Month 12)

D2.1 – Analysis and evaluation of first system architecture (Month 12)

D2.2 – Analysis and optimisation of integrated passives (Month 12)

D3.1 – Inductor process documentation ready for transfer (Month 6)

D5.1 – Project Web site (Month 3)

3.1.3 Expected final results and their potential impact and use (including the socio-economic impact and the wider societal implications of the project so far)

PowerSwipe will develop ...

... a demonstrator, consisting of multi-component LC (inductor-capacitor) interposer, which

can be combined in a 3D heterogeneous stack together with the SoC/PMIC chip

... integrated passive components fulfilling the stringent temperature (125deg) and quality

requirements required by the automotive market and thus closing today’s gap in availability

of components

... inductor and capacitor based very high-frequency DC-DC converters in 40nm CMOS

operating at 5V supply, ready for 3D integration with power passives

... integrated very high-frequency DC-DC converters allowing PCB footprint reduction by

~100mm² per module, without compromising converter efficiency at 90%

... missing system and component level optimization tools to achieve optimum system

configuration and efficiency for different operating modes

... a demonstrator system targeted for Automotive Microcontroller, with optimized complete

chain from car battery (5...48V) down to the core voltage domain (1V)


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System level schematic of the PowerSwipe project innovations

3.1.4 Project website, logos and partners

Project Website:

www.powerswipe.eu

Project logo:

Project banner:

http://www.powerswipe.eu/


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Project partners:

Participant no.

*

Participant organisation name Part. short

name

Country

1 (Coordinator) University College Cork, National University of

Ireland, Cork

Tyndall-UCC IE

2 Infineon Technologies AG IFX DE

3 Infineon Technologies Austria AG - Villach IFAT AT

4 IPDiA IPDiA FR

5 Universidad Politécnica de Madrid UPM ES

6 Robert Bosch GmbH Bosch DE

7 Université de Lyon, Claude Bernard UCBL FR


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3.2 Core of the report for the period: Project objectives, work progress and achievements, project management 3.2.1 Project objectives for the period

The main objectives of the PowerSwipe project for Year 3 for were:

Finalise fabrication of passives (inductor, capacitor and interposer)

Integration/fabrication of Demo1

Integration/fabrication of ITV2/Demo2

Functional testing of Demo1

Functional testing of ITV2

Validation of Demo1 samples

Draft exploitation plan

The following figure shows the Gantt chart with the tasks, deliverables and milestones for the

reporting period and to the end of the project (According to latest version of DoW, Sep 2015).

3.2.2 Work progress and achievements during the period

WP1 – System Specifications and Design

WP Objectives for Year 1

Characterization of HV DCDC and Demo1


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Work Progress

Tasks finished

Deliverable 1.3 “Design report of first prototype chips emphasized add-ons”

Achievements

1.1 HV DCDC characterization

Summary

The HV DC-DC converter is an inductor-based step-down regulator that operates at a frequency of

10MHz. At the moment only the power stage has been implemented on silicon.

The acceptable input voltage range goes from 6V to 16V while the output voltages for which the

design has been optimized are 3.3V and 5V. The maximum output current is 500mA.

Block Diagram

Figure 1.1 shows the block diagram of the implemented design. The power stage itself consists of a

low-side switch and a high-side switch which are both 20V NMOS devices.

Figure 1.1. Block diagram of implemented design

Description of operation

The PWM signal driving the power stage can be either provided from outside (from an external

controller) or generated internally (for open loop testing). In the latter case the duty cycle can be

programmed through SPI.


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The supply for the low-side switch driver is generated by an LDO (the “low-side LDO”) which in

turn is supplied by the regulator output voltage (for higher efficiency). Because the output voltage is

initially low at startup another LDO (“the Startup LDO”) will pre-charge the output capacitor to 3V

before the switching begins.

An external bootstrap capacitor generates a voltage (higher than VIN) from which the high-side

driver is powered.

External components

The external capacitors are integrated on a separate die that will be enclosed in the same package as

the regulator IC: CIN = 200nF, COUT = 500nF (+500nF input of LV), CLS = 40nF, CHS = 20nF.

The 1uH inductor is a separate component that is also enclosed in the package.

Layout

Figure 1.2.HV DC-DC converter layout


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Simulation vs. Characterization

Simulated and measured efficiency

Figure 1.3. Simulated and measured efficiency Vin=12V, RT

(open loop operation, controller power consumption not included)

Characterization

For test purposes was created small board, which contains HV DC-DC silicon die directly bonded

to the PCB with external inductor L=1µH (Coilcraft) and external capacitors Cout=470nF,

Cls=47nF (Taiyo Yuden) Cin=220nF, Chs=22nF (Murata).

Efficiency measurement shows quite nice matching with simulated values especially at higher

loads.

Additionally was tested possibility to operate at even higher switching frequencies. Converter had

shown a stable operation at frequencies up to 40 MHz with the same external components without

adjust for higher switching frequencies.

Also was built prototype of mixed signal V2IC/V

2IL controller, which was successfully tested with

HV DC-DC. Designed controller performance and could be integrated in next silicon of HV DC-

DC.


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Figure 1.4. PCB with directly bonded HV DC-DC and external passives

Figure 1.5. Steady state operation Fsw=10MHz; Vin=12V; Iload= 100mA

in yellow – Vout; blue – Switching Node; orange – inductor current measured over sense resistor

Due to the bigger parasitic inductances we have a quite big overshoot on the switching node

commutation.


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Figure 1.6. Efficiency measurement. Fsw=10/40MHz Vin=12; Vout=5V

Figure 1.7. Prototype board of V

2IC/V

2IL controller


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Figure 8. Reaction of developed V

2IC controller for load step/release

Iload: 0 <->200 mA (tr=tf=150ns) Vin=8V Vout=3.3V

1.2 Demo1

Demo 1 could not be characterized as planned due to manufacturing issues. For details please see

WP4 report. Once the chips from the second iteration will be available a characterization will be

done as planned.

Demo1 Overview

The implemented Demo1a test chip is a complete, fully integrated power management chip for

supplying automotive microcontrollers. The chip contains an integrated inductor based DC-DC

buck converter and an integrated switched capacitor DC-DC converter. Beside the converters

additional auxiliary circuits are placed: linear voltage regulators, different oscillators, bandgap

references, current references, ADCs, temperature sensors, startup circuits.

Furthermore, an artificial load is placed on the chip in order to emulate steep current jumps from a

microcontroller load. The current ramps of the load are programmable and can be controlled by

external control signals.

VINT=

5V-3.3V

CinLV:

665nF

LV LC-DCDC

Dummy

Load 1

μC

L:250nH

CoutLV:400nF

Vcore=1.2V

LV SC-DCDC

Aux.

Circuitry/

EVR

Demo 1A

Cfly:30nF

System IC

40nm

Flash CMOS

Figure 1.9. Block diagram of the fully integrated power management chip Demo1a

Simulation Results

In this section some simulations results in PWM and PFM are shown. In each plot the upper graph

shows the current through the power inductor; the graph in the middle of the plots shows the output

voltage of the converter and the graph at the bottom of the plots shows the load current of the


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converter. It can be seen that the output voltage of the converter is regulated to 1.2V and that the

converter is stable during load jumps.

Figure 1.10. Simulation Results (PFM: top left, PWM-CCM/DCM: top right, PWM-CCM: bottom)

For more details on system IC components please refer to the 2nd

Annual Report.


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WP2 – Computer-aided Optimisation and Analysis

Work Package Objectives

The objective for the third year of WP2 can be summarized as follows:

2.1 Passive Components Improvement Validation The models developed for integrated inductors (both individual and coupled) have been improved accounting

for second order effects not considered in the previous models. These second order effects have been

obtained through the characterization of the first set of samples.

Integrated power inductors have been measured and characterized and their main electrical

parameters have been extracted under different operating conditions.

Variation of the inductance with the bias current. As it is shown in Figure , the inductance is

modified as the bias current is increased. This effect has been analyzed from the converter point

of view by means of accurate simulations and it has been shown that its effect is negligible.

New Models for Coupled Inductors. New analytical models for the coupled inductor structures

shown in Figure used in the High Frequency converter (100MHz- 200Mhz) have been

developed for the optimization.

Validation of coupled inductor structures. Different coupled inductor structures have been

analyzed and validated by measurements. The main design parameters for the coupled inductors are shown in Table and their layouts are shown in Figure .

50

500

0 250 500 750 1000

Ind

uct

ance

(n

H)

@ 1

0 M

Hz

Bias Current (mA)

Figure 2.1. Inductance as a function of the bias current (220nH inductor sample)

Option A

L Tx L

Option B

Figure 2.2. Alternative Coupled inductor structures considered for the HF DC-DC Converter


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Table 2.1. Main Geometric and Electric Parameters of Integrated Coupled Inductor Samples

PowerSWIP

E

ITVs

L (nH) Core

Thicknes

s

Core

Length

Copper

width

Copper

Thickness

DCR

(Ohm)

Device

Footprint

ITV 2A 33nH 1.2 µm 1.22 mm 72.2 μm 35 μm 0.084 2 mm2

ITV 2B 47 nH

Coupled

(k=0.4)

1.6 µm 1.78 mm 50.62 15 μm 0.3425 2 mm2

ITV 2C 35 nH

Coupled

k=0.8

1.6 µm 1.83 mm 75.71 μm 15 μm 0.155 2 mm2

20 nH 1.6 µm 0.78 mm 97 μm 35 μm 0.053 2 mm2

33nH95,5 %

ITV

2A

90.25%

ITV2B

90.25%94.8%

85.6%

ITV 2C

Figure 2.3. Layout of Integrated Coupled Inductor Samples

2.2 System Level Design and Optimization

The main improvements regarding the System Level Design and Optimization Tool have been focused on:


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Implementation of the improved models for the integrated magnetic components and the addition of

multi-phase coupled converters with accurate models of the coupled inductors. These results have

been validated with the High Frequency DC-DC converter and the main results are summarized in

Table . It can be seen that even the highest efficiency is obtained with a single phase buck converter design operating at 200MHz. The reason is that the penalty on the efficiency of the semiconductors

(3%) is compensated with the improvement on the efficiency of the magnetic component (95%).

Table 2.2. Efficiency estimation for different couple inductor configurations for HF DC-DC

Converter

Inductor

design

Freq.

(MHz)

L

(nH)

Coupling

factor

Efficiency

(magnetics)

Efficiency

(IC)

Total

efficiency

ITV2a Single phase 200 33 -- 95,50% 87,40% 83%

ITV2b Coupled 100 45 ~0.4 90% 90,40% 81%

ITV2c Coupled

+Lout

100 35+21 >0.8 85.6% 90,40% 77%

The nonlinear effect of the variation of the inductance with the output current has also been validated

at system level and it has been shown that even though there is a drop of the inductance of from

220nH with a bias current of 0A to 170nH at with a bias current of 500mA (see Figure ) the effect on

the time domain is very small (with ideal inductor of 220nH the peak to peak current is Ipp= 450mA

and with the nonlinear inductor the value is Ipp= 440mA)

Figure 3.3. Comparison of the inductor current waveform for the 10MHz buck converter with ideal and non-

linear inductor (Red- non-linear Inductor, Blue- Ideal Inductor)

Work Progress Regarding WP2 most of the objectives have been met. There are some tasks pending that have been delayed

due to the problems encountered with the measurements of the samples:

Coupled inductor models have been developed and validated.

Analytical Models for Two different coupled inductor structures have been developed and

validated by means of Finite Elements and Measurement.

The system level optimization tool has been improved with more accurate models of the single

inductors and coupled inductors.

Additional fast ripple based controllers have been added to the optimization tool that allows

improving the dynamic response and reduce the output capacitance to be integrated.

Deliverables

The deliverables of WP2 have been moved to M41 since they depend on the measurements to be

performed to the samples, and were the cause of the extension of the project.


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D2.6 “Analysis and optimisation of integrated passives” has been moved to M41

D2.7 Multi-disciplinary platform for PwrSoC design” has been moved to M41


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WP3 – Technology Development

Work Package Objectives and Significant Results

1) Inductor fabrication for Demo 1, ITV2 and Demo2

Fabricate inductors for Demo1, ITV2 and Demo2 and carry out reliability and testing of the fabricated

inductors.

Complete initial characterisation of inductors for Demo1, ITV2 and Demo2 and die-level reliability

testing for same.

Further optimise the lamination process for improving performance of inductors

Complete the detailed reliability plan for inductors

2) Technology transfer and scale up (Tyndall to IFX) • Set up a magnetics processing line in Regensburg, Germany based on Tyndall’s processing of racetrack

structures • Develop optimised process for realising an air-core design on a 200 mm wafer

• Demonstrate fully fabricated device with closed magnetic core

3) Capacitor fabrication & interposer development

• Develop and demonstrate high voltage (BV=30V) process for HV stage • Execute preliminary reliability study and extrapolate lifetime under Bosch specified usage conditions

• Implement PICS capacitors and interposer technologies for demonstrators

• Fabricate Demo1 (LV and HV) and ITV2/Demo2 interposers • Process PICS wafers

• Develop and execute electrical testing and HF characterisation

• Assembly and evaluation of ITV2/Demo2 devices

WP3 has met all these objectives. Significant results from WP3 are listed below.

Detailed description of all tasks in WP3

1) Inductor fabrication for Demo1, ITV2 and Demo2

Tyndall completed fabrication of Single Layer Metal (SLM) inductor designs for Demo1, ITV2 and

Demo2 and for inductor reliability testing programme. Double Layer Metal (DLM) devices were

completed by end of November 2014. Figure 3.1 below, shows image of a fully fabricated coupled

inductor for Demo2 devices.

All devices were tested at die-level at Tyndall before being shipped.


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Figure 3.1. Demo2 coupled inductors

Coupled

Inductor

Self-inductance

design value per phase

Self-inductance

test value – phase 1

Self-inductance

test value – phase 2

Demo2 45 nH 45.9 nH @ 10 MHz 44.8 nH @ 10 MHz

The high frequency testing was carried out at Lab Ampere. Figure 3.2 shows the measured AC

resistance and inductance as a function of frequency up to 100 MHz.

Figure 3.2 . Inductance, AC Resistance vs Frequency measurements done by Ampere Lab

Additionally, Tyndall has developed a lamination process using sputter deposition of NiFe

(permalloy) core. Figure 3.3 below shows the cross-section of a laminated NiFe core. The initial

characterisation of the laminated core shows that this structure has a higher operational frequency (6

lamination of 100 nm thick-500 MHz) compared to a single lamination core (100 MHz) due to

reduced eddy currents.

Figure 3.3. Cross-section of a laminated core structure.


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2) Magnetics processing technology transfer from Tyndall-IFX

IFX and Tyndall worked together in establishing a magnetics processing line in Regensburg. Figure

3.4 shows some inductors fabricated at IFX (NiFe core is sputtered, 200nm thick std. permalloy

target).

Figure 3.4. Inductors fabricated at IFX

The following processes were carried out. The resulting wafers and parts were sent to Tyndall for

characterisation:

Electro Chemical Plating of NiFe on dummy wafers

Pattern Plating has been tested on Cu Seed

Seed Etch has been demonstrated successfully (equals plating of first NiFe bottom core) NiFe plating on high topology has also been demonstrated (equals plating of the second NiFe core).

The ‘Magnetics on Silicon’ process from Tyndall has been successfully transferred and scaled up to

8” technology at IFX.

3) Capacitor fabrication & Interposer development

IPDiA finalised the fabrication of trench capacitors for Low voltage Demo1, High voltage Demo1,

ITV2 and Demo2. The PowerSwipe capacitors are based on IPDiA’s Silicon deep trench

technology with tripod structure to multiply surface ratio & their electrical performance is in

agreement with the design targets. Figure 3.5 shows the layout of Low Voltage Demo 1 and ITVs

being fabricated at IPDiA.


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Figure 3.5. Layout for Low voltage Demo1 & ITV2 devices

Demo1: PMIC (HV and LV) and inductors (both Tyndall and commercial discrete) were integrated

with the capacitor/interposer assembly and sent to IFX for eWLB integration.

ITV2/Demo2: PMIC and inductors were integrated and sent to Lab Ampere for mounting and

testing.

4) Testing

Main tests carried out: Measurement of inductors under probe, up to 110 MHz. Transient measurement of inductor current and

voltage. Both single and coupled inductors (ITV2 and Demo2).

Measurements on 1st version of interposer.

Test of inductors on PCB: Preliminary test on board at 100 MHz, using wideband fixed gain amplifier, to

emulate power stage and load the inductor.

Re-characterisation of all received devices using Kelvin probes.

Figure 3.6. Setup of transient inductor measurement


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Figure 3.7 shoes the measured time domain waveforms for various frequencies and duty cycles

(Test on board with wideband amplifier) for loosely coupled (k=0.4) inductors. These can be used

to identify L, R and k values.

-1

-0.5

0

0.5

1

1.5

2

0 5 10 15 20 25 30 35 40 45 50-60

-40

-20

0

20

40

60V

olt

age

(V)

Cu

rren

t (m

A)

Time (ns)

Integration resultL1=48.85 nH, L2=44.91 nH, K=-0.31, R1=0.92, R2=0.51 Ohms

at 50 MHz, R21=0.976, R

22=0.978

VL1 (V)

VL2 (V)

IL1MEASURE (mA)

IL2MEASURE (mA)

IL1CALC (mA)

IL2CALC (mA) Figure 3.7. Measured time domain waveforms

Objectives for Year 4

All activities of WP3 are now finalised.

A new batch of Demo1 devices will be integrated using backup interposer and inductor samples

already fabricated during Year 3.


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WP4 – System Integration

Work Package Objectives

Demo1 Integration and fabrication

Demo1 Functional Testing

ITV2/Demo2 Integration

ITV2/Demo2 Functional Testing

Demo1 Validation

Demo1, ITV2 and Demo2 samples were fabricated and integrated as planned. The testing of the

ITV2/Demo2 devices has been carried out (See below for further details).

The functional testing of Demo1 was carried out as planned, however no device showed the

expected functionality. Therefore it was required to adjust the objectives and planning. The forensic

testing of the failed samples was carried out and it was decided to fabricate a second run of Demo2

devices addressing the issues identified. The validation testing was delayed accordingly.

Progress towards objectives

Task 4.1.1 System-in-Package Technology (embedded solution) – Demo1

Developing a power supply in package (PSiP) solution containing a functional interposer including

Through Substrate Vias (TSV), passive devices (Inductor & Capacitor) and the respective logic IC.

By adapting eWLB technology in order to scope with the requirements of advanced CMOS

technology (e.g. ultra low k, Thermal mismatch, etc.) in terms of stress and strain adjustment an

optimum Frontend/Backend interface will be achieved. The SiP technology is aimed to be scalable

to sub 28 nm technologies.

Task 4.1.2 System-in-Package Technology (flipped solution) – ITV2-Demo2

Developing a power supply solution containing LC substrate including passive devices (Inductor &

Capacitor) and the respective logic IC based on an intermediate test vehicle). This test vehicle is

used to show the principal system feasibility by early functional and reliability characterisation. For

the demonstrator the PMIC will be microbumbed onto this functional fan out substrate. With

monolithic integrated inductors and capacities.

Task 4.2: Characterisation and reliability analysis of individual components and Demo1A

Board level characterisation according to defined electrical and reliability requirements to evaluate

the manufacturability, functionality and reliability is performed on the individual components

(inductors, trench capacitors and interposer) and the whole demonstrator system.

Development of an adequate application test board and verify the performance in the test board in

real automotive environment. Result will be an assessment whether this will fit into automotive

environment.

Task 4.3: Forensic testing

Identify the issues causing non-functional Demo1 samples.

Significant results


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Demo1

The Demo1 (both HV and LV) samples were packaged using the eWLB (Embedded Wafer Level

BGA) technology at Infineon Regensburg. Figure 4.1 shows a cross-section diagram of the eWLB

integration of PMIC (LV/HV), inductor on Si interposer with capacitors.

Figure 4.1 eWLB integration of Demo1 devices

Figure 4.2 shows the fabricated devices on virtual wafer.

Figure 4.2. HV & LV 3A527029 wafers

ITV2-Demo2

Major tasks by Ampere lab on WP4 were the setup of the measurement test-benches and the actual

measurements on the demonstrators. Several measurements were carried out to assess the

performances of the demonstrators and validate the design approach.

The converter was first tested as a standalone, validating its functionality and allowing for a first

performance measurement. A specific test-board has been designed for this purpose, and the

functionality of the chip was validated. A picture of the on-board converter is presented in the

figure below. Note that due to physical constraints, decoupling capacitors can not be too close to the

IC, limiting the effectiveness of these decoupling capacitors. Furthermore this type of assembly

requires a lot of area.


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Figure 4.3: Microphotograph of the board assembly.

Following these preliminary tests, the integrated circuit was reported onto the passive interposer,

making it a 3D assembly with a more compact full converter. The 3D assembly configurations were

processed by IPDiA. Specific test-boards have then been developed, as well as an automated test-

bench that allows for testing the converters over an important number of frequency, duty cycle and

load current values. A full characterization of the samples has then been carried out. The superiority

of the 3D assembly over the board assembly was demonstrated. The advantage of the cascode

power stage has also been validated by measurements.

Pictures of the 3D assembly and test-board are presented in the figures below.

Figure 4.4: 3D assembly connected to the test-

board

Figure 4.5: Picture of the 3D assembly test-

board

Forensic Testing

Test structures for verification of TSV continuity were included in the capacitive interposer for

Demo1 LV/HV. The structure is implemented as a set of redundant TSVs ensuring front to back

transition between tracks of IN1 and IN1B. Those tracks structures can be directly measured with

an ohm-metre. This was used to identify good and bad chains. Cross sections of both a good and a

bad chain after die complete assembly process: i.e. PMIC soldering + RDL implementation at IFX.

The corresponding results are presented in fig. 4.6. It can be observed that the good die presents a

similar aspect compared to the analysis performed prior to assembly while on the failing die ones

there are: - Reduced copper thickness with metal pinching/discontinuity nearby the TSV mesa.

- Large delamination of the backside isolation underneath the copper layer likely indicating that an

excessive stress has been applied.


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Good

die

Bad die

Figure 4.6.: Physical analysis of the TSV (lot MH3496) after assembly. Left inset corresponds to

visual inspection after side polishing, right inset to SEM inspection.

For the failing TSVs, the backside isolation is cracked, and the backside copper (IN1B) is over-

etched. This is resulting in a discontinuity of the TSV inner metallization nearby the TSV mesa. No

other cause for discontinuity could be identified in the failing chains: TSV body, isolation and

interface with front metallization are as expected. Causes for the over-etching of the copper could

be multiple and could result from TSV process control issue (over-etch of the seed layer). However,

the presence of bad delamination on the bad dies and contrast with analysis made prior assembly,

might also suggest an interaction with processes subsequent to the TSV manufacturing.

To reduce the risk on the next delivery, following countermeasures will be taken at IPDiA: - Increase of the backside copper (IN1B) thickness to reduce sensitivity to the over-etch,

- Systematic electrical measurement of the TSV daisy chains on dies subject to delivery prior PMIC

assembly,

- Verification of PMIC functionality through basic measurements implying TSV continuity (PMIC

body diode testing)

Objectives for Year 4

Fabrication/integration of Demo1 devices: Back-up run

Functional testing of Demo1 back-up run devices

Validation testing of Demo1 back-up run devices

Continue functional testing of ITV2/Demo2 devices


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WP5 - Dissemination

Web site and LinkedIn Group

The Web site (http://www.powerswipe.eu) was kept active during the course of the year. All public

deliverables are uploaded to the Downloads page. Furthermore, a list of all publications and

presentations is kept in the Results page, including Digital Object Identifier links to allow access to

those with subscriptions.

The LinkedIn Power Supply on Chip (PwrSoC) has continued growing and now has almost 80

active members.

Tutorial

On March 2015, as part of the APEC (Applied Power Electronics Conference and Exposition) in

Charlotte (North Carolina), the PowerSwipe consortium presented a Professional Development

Seminar on Power Supply on Chip, which was well attended with over 100 attendees.

Papers and presentations

PowerSwipe has been very active disseminating the results of the project during this year. We have

presented the results of PowerSwipe research at nine international conferences. We have also

submitted 2 peer-reviewed papers which have already been accepted for publication. The following

is the list of titles:

Papers (Accepted for publication)

Anthony, R.; Rohan, J.F. and O'Mathuna, C, “Permalloy Thin films on Palladium Activated

Self Assembled Monolayer for Magnetics on Silicon Applications”, Procedia Phys.

Anthony, R.; Shanahan, B.J.; Waldron, F.; O'Mathuna, C. and Rohan, J.F., “Anisotropic Ni-

Fe-B Alloys with variable composition for high frequency integrated magnetics on silicon

applications “, Appl. Surf. Sci.

Conference Proceedings

• MNE'15 (The Hague, September 21-24)

– Tyndall: “Electrochemical process for fabrication of laminated micro-inductors on

silicon”

• ECCE 2015 (Montreal, 20-24 September)

– Tyndall: “High Efficiency on-Silicon Coupled Inductors using Stacked Copper

Windings”

• EuMW, (Paris, 6-11 September)

– IPDiA: “New Ultra Low ESR Mosaic PICS Capacitors for Power Conversion”

• ICM 2015 (Barcelona, 5-10 Jul)

– Tyndall: “Permalloy Thin Films on Palladium Activated Self-Assembled Monolayer

for Magnetics on Silicon Applications”

• ECPE Workshop of microPower Electronics (Munich, 16-17 June)

– Workshop organised and delivered by Tyndall, UPM and Lab Ampere

• IWIPP'15 (Chicago, 3-6 May)

– IPDiA: “High-Density Capacitors for Power Decoupling Applications”

• ICECS 2014 (Marseille, 7-10 December)

– Lab Ampere presentation (WYMPhD Forum)

• 3DIC (Kinsale, Dec’14)


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– Tyndall: “Advanced Processing for High Efficiency Inductors for 2.5D/3D Power

Supply in Package” (Best Poster Award)

• PwrSoC 2014 (Boston, 6-8 October)

– Presentations: IFAT, IPDiA, CEI-UPM, Lab Ampere

– E-posters: IFAT, Tyndall, Lab Ampere


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WP5 - Exploitation

All partners continuously looking at potential exploitation routes for the knowledge and

technologies that are being developed through PowerSwipe. The following figure shows the PUDF

spreadsheet, with the list of potential project outcomes identified so far.

Description Type Sector IPR

Exploitation

Lead Partner

Process for fabrication of racetrack inductor

Commercial Power Electronics Own/Licence Tyndall

Multi DC-DC converter PMIC with Passives

Adv. Knowledge

Commercial

Power Electronics, Automotive, General

Own/Licence IFAT

Integrated Magnetic Design Tool

Commercial CAD Licence UPM

Component embedding Si trench based capacitors

Commercial Power Electronics Own/Licence IPDiA

SiP for multi DC-DC Converter PMIC with Passives

Adv. Knowledge

Commercial

Power Electronics, Automotive, General

Own/Licence IFX

Microcontroller with embedded voltage controller

Commercial Power Electronics,

Automotive Own Bosch

Use in next generation Aurix Microcontroller family

Commercial Power Electronics,

Automotive, General Own IFAT

Figure 5.2. List of identified project outcomes from PUDF

Based on this list, the PowerSwipe consortium has produced a Draft Exploitation Plan (Deliverable

D5.3).

3.2.3 Project management during the period Management tasks included the organising of consortium meetings, internal reporting on work

progress (monthly) and submission of deliverables.

Project meetings were organised on a regular basis, as well as WP specific meetings and

discussions:

Executive Steering Committee meetings were carried out on the first Tuesday of every

month via teleconference with the support of multimedia sharing facilities (WebEx)

Consortium meetings every six months:

o 4th Six-monthly meeting: Villach (IFAT), 20-21 October 2014

o 5th Six-monthly meeting: Stuttgart (Bosch), 22-23 June 2015

WP-specific meetings were organised when required:

o WP2: Modelling meeting at UPM (Madrid) attended by Lab Ampere on 11 October

2014.

The project consortium keeps a Document Repository where all common documents and internal

reports are shared.


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Problems which have occurred and how they were solved or envisaged solutions

The inductor technology transfer from Tyndall to IFX (Task 3.2) has resulted more problematic and

time consuming that originally planned. The issues identified were solved during Year 3 and this

activity is now finalised. Deliverable D3.3 describes the work carried out.

Changes in consortium

No changes

Impact of possible deviations from the planned milestones and deliverables

The PowerSwipe project progressed according to the latest version of the plan (DoW v. March

2015). Demo1, ITV2 and Demo2 samples were fabricated and their functional testing commenced

in June 2015. The ITV2/Demo2 samples are working as designed and based on the measurement

results obtained so far, they are the best in class for high frequency PwrSoC.

The Demo1 devices however did not show any functionality during testing. Furthermore, test

devices with daisy-chain structures show high resistance or no connectivity, therefore indicating

issues with interconnects within the eWLB package.

This issue was flagged by IFAT in early August as soon as it became evident. The consortium held

a number of urgent discussions to understand the issues, agree an investigation plan and consider

contingencies.

Corrective actions and contingency plan

During August 2015, the consortium started the task of Forensic Testing of Demo1 to analyse the

devices and investigate the cause of these failures. This task was finalised by the middle of

September. A confidential report was prepared (D4.4, “Failure Analysis”), including integration

design recommendations to address the identified causes of failure.

The consortium has enough back-up parts fabricated in WP3 to attempt a new integration run. After

considering a number of contingency plans to carry out this back-up integration, the consortium

decided to fabricate a Full eWLB re-run.

Six-month extension

In order to achieve the original objectives of the project, the following tasks need to be undertaken:

Completion of the Forensic Testing

Fabrication of Demo1 devices using selected integration/assembly method from the above

list

Functional testing by IFAT

Validation by Bosch

In order to successfully complete these tasks, the project requires an extension of 6 months, to 31

March 2016. The request for a six month extension was approved by European Commission in

September 2015. A new DoW (v. Sep 2015) has now replaced the existing DoW (v. March 2015).

Changes to Description of Work including tasks, milestones and deliverables

The main activities of the project during the requested extension will be on WP4 for Integration and

Testing. WP1 and WP3 are now finished. The activities of WP2 will wait for the results of the


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functional testing to further improve the models developed during the course of the project. The

following Gantt chart shows the updated plan for WP4.

The new Task 4.3 “Forensic Testing” continued until the middle of September 2015. Then we will

start the back-up fabrication run (Task 4.1) for the full eWLB re-run and finally we will carry out

functional and validation testing (T4.2) on the new Demo1 samples.

Due to these changes, the following deliverables will have a different due date (those not mentioned

here will stay the same). Also two new deliverables have been added, one –D4.4– to report the

results of the Forensic testing and an updated version of D4.1.

Deliverable Title Current due

date

6-month

extension

D1.4 Optimised system architecture Description 33 36

Should be 42

D1.5 Optimised block-level specification 33 36

Should be 42

D2.6 Analysis/optimisation of int. passives 36 41

D2.7 Multi-disciplinary platform for PwrSoC

design

36 41

D4.1.2 Demonstrator 1 – Back-up run (new) 39

D4.3 Demonstrators analysis and characterisation 36 41

D4.4 Forensic Testing. 3D integration

recommendations

(new) 36

D5.2.2 Final Dissemination report 36 42

D5.3 Technology implementation and exploitation

plan

36 42

D6.1.4 Final management report 36 42

Deliverables D1.4 and D1.5 When reviewing the list of due deliverables, we noticed that the consortium made a mistake in the

updated DoW (v. Sep2015). Deliverables D1.4 and D1.5 were given a due date of M36, when they

should have been M42. The optimisation tasks related to these deliverables were originally planned

(DoW Sep2012) between the two tape-outs: Once the first tape-out devices were tested (ITV1), they

would be optimised and this optimisation included in the 2nd tape-out design. With the updated

DoW for a single tape-out, this optimisation was still carried out but once the Demo1 devices were

tested. Some theoretical optimisation has already been carried out during the design phase, and this


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has already been reported in D1.3. The final optimisation will be carried out once the Demo1 (back-

up run) devices are fabricated and tested (Task 4.2). Hence these two deliverables will be submitted

on M42.

Year 2 Review Recommendations and Actions

Update State of the Art, both

academia and industry

The consortium continuously monitors and updates the SotA

Comprehensive Exploitation plan Draft Exploitation Plan was presented during 2nd

Review.

The consortium is currently working on the Exploitation

Plan which will be presented at the Final Review

Amend DoW to reflect actual status

of the project (no 2nd

tape-out)

New DoW submitted and accepted in March 2015. A further

updated DoW to include six-month extension submitted and

accepted in September 2015


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Effort per WP (October 2014 to September 2015)

Workpackage5 WP1 WP2 WP3 WP4 WP5 WP6

TOTAL per

Beneficiary

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual Total Planned total

Tyndall-UCC 0.3 0.4 6.2 8 26.7 16.6 8.6 8 2.6 2.6 3.8 2.4 48.2 38

IFX - - - - 19.01 11.7 16.17 11.4 0.5 1.0 2.16 1.0 37.84 25.1

IFAT 1.2 21.7 - - - - 14.2 2.7 1.4 0.4 1 1 17.8 25.8

IPDIA - 0.5 - - 2.54 3.5 1.97 4.5 0.24 0.5 0.29 0.15 5.04 9.15

UPM 2 8 6 8 0.66 - 0.2 - - 0.67 - 0.25 8.86 16.92

BOSCH 1.01 1.67 - - - 0.5 2.27 8 - - 0.23 - 3.51 10.17

UCBL 0.61 6.3 0.68 5.9 7.03 4.2 4.44 10.3 6.87 0.4 - - 19.63 27.1

TOTAL 5.12 38.57 12.88 21.9 55.94 36.5 47.85 44.9 11.61 5.57 7.48 4.8 140.88 152.24

5 Please indicate in the table the number of person months over the whole duration for the planned work, for each workpackage by each beneficiary


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Cumulative Effort per WP (October 2012 to September 2015)

Workpackage6 WP1 WP2 WP3 WP4 WP5 WP6

TOTAL per

Beneficiary

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual

PM

total

Planned

PM

total

Actual Total Planned

total

Tyndall-UCC 0.9 1.0 26.5 24 88.9 50 16.6 16 8.4 8.0 10.1 7.0 151.4 106

IFX 4.96 1.5 1.5 1.5 37.19 35 22.33 34 1 3.0 2.81 3.0 69.79 78

IFAT 66.4 65 - - - - 17 8.0 2.1 0.4 4.2 3.0 89.7 76.4

IPDIA 2.55 2.5 - - 11.68 12.5 8.73 11 0.5 0.5 0.86 0.5 24.32 27

UPM 24 24 32 32 0.66 - 0.2 - 1.34 2.0 0.66 1.0 58.86 59

BOSCH 2.78 5.0 0.07 1.5 0.05 1.5 4.04 16 - 0.84 1.0 7.78 25

UCBL 17.05 19 9.44 17.8 8.89 12.6 4.67 20.6 8.7 1.0 - - 48.75 71

TOTAL 118.64 118 69.51 76.8 147.37 111.6 73.57 105.6 22.04 14.9 19.47 15.5 450.6 442.4

6 Please indicate in the table the number of person months over the whole duration for the planned work, for each workpackage by each beneficiary


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3.3 Deliverables and milestones tables

Deliverables

The deliverables due in this reporting period, as indicated in Annex I to the Grant Agreement have to be uploaded by the responsible participants

(as indicated in Annex I), and then approved and submitted by the Coordinator. Deliverables are of a nature other than periodic or final reports

(ex: "prototypes", "demonstrators" or "others"). The periodic reports and the final report have NOT to be considered as deliverables. If the

deliverables are not well explained in the periodic and/or final reports, then, a short descriptive report should be submitted, so that the

Commission has a record of their existence.

If a deliverable has been cancelled or regrouped with another one, please indicate this in the column "Comments".

If a new deliverable is proposed, please indicate this in the column "Comments".

The number of persons/month for each deliverable has been defined in Annex I of the Grant Agreement and cannot be changed. In SESAM, this

number is automatically transferred from NEF and is not editable. If there is a deviation from the Annex I, then this should be clearly explained

in the comments column.

This table is cumulative, that is, it should always show all deliverables from the beginning of the project.


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Deliverables

TABLE 1. DELIVERABLES

Del. no. Deliverable name Version WP no.

Lead beneficiary

Nature

Dissem.

level7

Delivery date from Annex I

Actual / Forecast delivery

date

Status No

submitted/ Submitted

Comments

D5.1 Project Web Site 1.1 5 Tyndall O PU M3 M4 Submitted

D3.1 Inductor process documentation ready for transfer Final 3 Tyndall R PU M6 M7 Submitted

D1.1 First system architecture description Final 1 IFAT R CO M12 M13 Submitted

D1.2 Target block-level specification Final 1 IFAT R CO M12 M13 Submitted

D2.1 Analysis and evaluation of first system

architecture

Final 2 CEI-UPM R PU M12 M13 Submitted

D2.2 Analysis and optimisation of integrated passives Final 2 CEI-UPM R PU M12 M13 Submitted

D6.1.1 First Annual Management Report 2.0 6 Tyndall R PU M12 M13 Submitted

D1.3 Design report of 1st prototype chips 1.3 1 IFAT R CO M18 M22 Submitted

D2.3 Analysis and optimisation of selected

architectures Final 2 UPM R PU M18 M19 Submitted

D3.2 Passive components fabricated Final 3 Tyndall R PU M18 M24 Submitted

D5.2.1 Mid-term dissemination report 1.2 5 Tyndall R PU M18 M19 Submitted

D2.4 Architecture optimisation of 1st prototype chips Final 2 UPM R PU M24 M25 Submitted

D2.5 Analysis and optimisation with improved models Final 2 UPM R PU M24 M25 Submitted

D3.3 Report on inductor technology transfer 3 Tyndall R PU M24 M35 Submitted

D6.1.2 2nd

annual management report 6 Tyndall R PU M24 M25 Submitted

7 PU = Public. PP = Restricted to other programme participants (including the Commission Services). RE = Restricted to a group specified by the consortium (including the Commission Services). CO = Confidential, only for members of the consortium (including the Commission Services). Make sure that you are using the correct following label when your project has classified deliverables. EU restricted = Classified with the mention of the classification level restricted "EU Restricted". EU confidential = Classified with the mention of the classification level confidential " EU Confidential ". EU secret = Classified with the mention of the classification level secret "EU Secret "


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D3.3 Inductor Technology Transfer 3 IFX R CO M28 M35 Submitted

D3.4 Interposers Fabricated for Demos 3 IPDiA R CO M28 M29 Submitted

D4.1 HW Demonstrator 1 4 IFX D/R CO M31 M33 Fabricated

D3.5 Interposer Test 3 IPDiA R CO M34 M35 Submitted

D3.6 Process Development of Inductors 3 Tyndall R CO M34 M36 Submitted

D3.7 Process Development for HV capacitors 3 IPDiA R CO M34 M35 Submitted

D4.2 HW Demonstrator 2 4 Lab

Ampere D/R CO M35 M36 Fabricated

D4.4 Forensic Testing 4 IPDiA R CO M36 M37 Submitted

D6.1.3 3rd annual management report 6 Tyndall R PU M36 M37 Submitted (This doc)


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Milestones

Please complete this table if milestones are specified in Annex I to the Grant Agreement.

Milestones will be assessed against the specific criteria and performance indicators as defined in

Annex I.

This table is cumulative, which means that it should always show all milestones from the beginning

of the project.

TABLE 2. MILESTONES

Milestone no.

Milestone name Work package

no

Lead beneficiary

Delivery date from Annex I dd/mm/yyyy

Achieved

Yes/No

Actual / Forecast

achievement date

dd/mm/yyyy

Comments

Ms1.1 Application

requirements defined 1 IFAT 31/12/2012 YES 31/12/2012

Ms1.2 First system architecture

1 IFAT 30/06/2013 YES 30/06/2013

Ms2.1 Architecture analysis

and evaluation 2 UPM 30/09/2013 YES 30/09/2013

Ms2.2 Analysis and

optimisation of

integrated passives

2 UPM 30/09/2013 YES 30/09/2013

Ms1.3 Tape-out 1st prototype

chips 1 IFAT 31/12/2013 YES 30/06/2014 New plan

Ms2.3 Detailed analysis and

optimisation of

selected architectures

2 UPM 31/03/2014 YES 31/03/2014

Ms3.1 Passive components

ready 3 Tyndall 31/03/2014 YES 31/08/2014

Ms4.1 Intermediate test

vehicle (ITV2) 4 Lab

Ampere

30/04/2015 YES 30/04/2015

Ms4.2 PSiP with functional

interposer with TSVs,

capacitors and

inductors (Demo1)

4 IFX 30/04/2015 YES 30/05/2015

Ms4.3 PSiP with integrated

LC substrate (Demo2) 4 Lab

Ampere

30/04/2015 YES 30/04/2015

Ms1.4 System Architecture

Analysis completed 1 IFAT 31/05/2015 YES 31/05/2015

Ms3.2 Inductor process

transfer completed 3 IFX 30/09/2014 YES 31/07/2015

Ms3.3 Interposers ready for

demos 3 IPDiA 30/11/2014 YES 30/11/2014

deliverable 6.1.3 third annual management report · d6.1.3, “3rd annual management report”,...

Documents