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TRANSCRIPT
Defect-Tolerant Logic Implementation on Nanorossbars by Exploiting
Logic Mapping & Morphing Simultaneously
Yehua Su, Wenjing Rao
Outline
� Nanocrossbar & background
� Defect Tolerant Logic Implementation
– Mapping
– Morphing
– Integration of Mapping and Morphing
� Simulation Results
� Conclusions
Nanoscale Fabrication� Bottom-up
– Small structures
– Self-assembly process
� Why?
– Possibly the only viable way to construct nanoelectronic systems economically
�Implications:
�Lead to large # of defects
�Result in regular structures
�Require reconfigurability
�Implications:
�Lead to large # of defects
�Result in regular structures
�Require reconfigurability
On the Rise: NanoCrossbar� Advantage: Compatibility to
– Bottom-up fabrication
– PLA-like logic
– Multiple nano device candidatesIdeal crossbar vs. reality
bad PLAs
Change in the Flow
PLA manufacturing
testing
Good PLAs
Nano Crossbar manufacturing
testing
nano-crossbar With Defect Map
Behavioral Description
Logic Synthesis & Optimization
2-level Logic Function
���
D-T Logic Implementation
Defect Tolerance
Stuck open
Stuck close
Configurable
Device configurability
� Challenging
– like testing, but harder?
� Reconfigurability + regularity
– like BISR, but harder?
�Other flexibilities?
Modeling� Matrix representation for
logic function & crossbar
f=ab + bc’
a b c’
1 1 0
0 1 1
ab
bc’
X 0 X
0 1 X
1 X 1
Mapping is then…� Row & Column correspondence
mismatch
01
10
0x
00
1x
11
compatible
� Cell compatibilitya b c’
1 1 0
0 1 1
ab
bc’
X 0 X
0 1 X
1 X 0
Mapping Example
� Invalid with 3 mismatches
f =ab + bc’
f ’= b + ab
a b c’
1 1 0
0 1 1
ab
bc’
X 0 X
0 1 X
1 X 0
a b c’
ab
bc’
X 0 X
0 1 X
1 X 0
1 1 0
0 1 1
� Perfect mapping without mismatches
abc’
ab
bc’
X 0 X
0 1 X
1 X 0
0 1 1
1 1 0
f = ab + bc’a b c’
1 1 0
0 1 1
ab
bc’
X 0 X
0 1 X
1 X 0
Try another way…
v1, v2 …p1
p2
…
Backtracking Framework
………….
…
…
…
…
M1 MkMv! x p!……M2
c1, c2, … r1
r2
….crossbar
Logic function
x x x
x x x
x
Heuristicsc1 c2 c3 c4 c5 …… cn
pi1
pi2
pi3
pi4
pi5
.
.
vj1 vj2 vj3 vj4 vj5 ……
r1
r2
r3
r4
r5
.
.
rn
…
…
…
……
……
…
� BT tree structure:
– Col / Row interleaving
� Mapping trial selection
– Preserving X’s
– Efficient pruning
Challenges• Solution space is huge• NP-complete
- Runtime - mapping is per chip!- Yield
Morphing
� Some mismatches are ok…
– f & g equivalent in this case
a b c
ab
ac
0 X X 1
1 1 0 0
bc’
1 0 1 0
0 1 0 1
1 X 1 X
1 X 1 X
c’
f = ab + ac + bc’
g = abc + ac + bc’
Equivalent Morphing Forms
ab
cd
c’d’+a’c’+abcd+ab’c
c’d’+a’c’d+abcd+ab’c’ac’d’+a’c’+abcd+ab’c
ab
cdab
cd
ab
cd
10
01
c’d’+a’c’+abcd+ab’c
How would Morphing help?
Perfect
MM -> equivalent
MM -> changed function
� Promising, but…
– Infinite # of forms
– Equivalent checking overhead
– Integration with mapping
Logic Equivalence Checking
� General Logic Eq Checking is hard� But it’s much easier when…
- The two functions are similar
� Method - divide and conquer• Shannon Expansion
f (x1,x2,…, xn) = xi’ f(xi=0) + xi f(xi=1)
g (x1,x2,…, xn) = xi’ g(xi=0) + xi g(xi=1)
=
≠
?
� Mismatch -> splitting var xi
=
f =c’d’+a’c’d+acd+ab’c
Splitting on MM var makes it easy
c’d’
a’c’d
acd
ab’c
……..
……..
ac
d=0
……..
……..
ac
d=0
……..
……..
c’
d=1
……..
……..
c’
d=1
a’c’d
ab’c
a’c’
ab’c
a’c’
a’c’d
ab’c
a’c’
ab’c
g =c’d’+a’c’d+acd+ab’c d’
c’d’
a’c’
acd
ab’cd’
a’c’
ab’cd’
≠
Mapping and Morphing Simultaneously
f0
[c1] [c2]
[c1, r1] [c1, r2]
LEC xLEC √
f1
LEC √
[c1] [c2]
[c1, r1] [c1, r2]
LEC x
x x
[c1] [c2]
[c1, r1] [c1, r2]
LEC x
LEC √x x
f2
……
Mk √
fk
During mapping process, instead of BT, turn to LEC
If tolerable, move on to new f ’Otherwise, BT
Amortizing Runtime
1)Pre-profiling (off-line)- A mismatch analysis for function- limited to 1 or 2 mismatches
2)Dynamically buildup (online)- Invoke LEC during mapping process f
(3,7), (24,87), mm
location:
(10, 5)(10, 5)
Trading runtime w/ storage: Hash-table
(10, 5)
(3,7), (24,87), (10, 5)
(3,5), (4,12)
(14, 8)
………………
(3,7), (24,87)
…
Y
N
…
Y
…
key (val, product)
Y
Experimental Results: YieldBenchmark sqrt8(size 40x16) Benchmark sao2(size 58x20)
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 0.01 0.02 0.03 0.04 0.05 0.06
Mapping + Morphing
Success due to Morphing
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
00.
010.
020.
030.
040.
050.
060.
070.
080.
09 0.1
0.110.
120.
130.
140.
150.
160.
17
Mapping
Mapping + Morphing
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 0.01 0.02 0.03 0.04 0.05 0.06
Mapping
Mapping + Morphing
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%0
0.010.
020.
030.
040.
050.
060.
070.
080.
09 0.1
0.110.
120.
130.
140.
150.
160.
17
Mapping + Morphing
Success due to Morphing
Best improvement
Yield Comparison
0%
10%
20%
30%
40%
50%
60%
con1 (9x14x2) rd53
(32x10x3)
misex1
(32x16x7)
sqrt8
(40x16x4)
sao2
(58x20x4)
5xp1
(75x14x10)
bw (87x10x28) 9sym
(87x18x1)
benchmark
Yie
ld
mapping mapping+morphing
100%
Runtime cost
Benchmark con1(9x14) Benchmark sao2(size 58x20)
Average runtime cost for finding a valid mapping (not counting the ones hitting runtime upperbound)
Conclusions
� Defect-tolerant logic implementation becomes a fundamental issue for nanocrossbars
� Mapping helps – perfect implementation exploiting defects
� Morphing helps – some mismatches are tolerable due to equivalent functionalities
� The two schemes can be carried out in a unified framework
� Improving yield without adding cost