An FPGA-Based IEEE 1149.1 BST Controller

HiBu | DDIS3010 | josemmf@hibu.no

Digitale Systemer 2012/13[ November 2012 ]

Outline of this presentation

● What is the deliverable of this work?● Main functional features● Processor architecture and instruction set● Test workflow● Main challenges● Can we go further?● How do I start?

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Envisaged deliverable

Overall block diagram:

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Main functional features

● Support at least one Test Access Port (TAP)● Accept "SVF-like" commands● Receive the test code serially via RS-232C● One "Run test" push button● One "Pass" led, one "Fail" led

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Test processor block diagram

[ you can choose the values of CLmax and TVmax bits ]

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Source code

Minimum set of "SVF-like" commands:

Command Description

RESET Sets the boundary-scan logic (TAP controller FSM) in Test-Logic-Reset

TMS 0 / 1 Sets TMS to 0 / 1 and applies one clock pulse to TCK

SHF N X Shifts an N-bit sequence (X) into the [instruction | selected data] register

SHFCP N X,Y,Z Shifts an N-bit sequence (X) into the [instruction | selected data] register and compares the output sequence with its expected response (Y) using the given mask information (Z)

RUNTEST N Sets TMS to 0 and applies N [16-bit value] clock pulses to TCK

EOP End-of-program (not a real command; marks the end of the object code)

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Source code > Object code

Use the TASM shareware cross-assembler to generate the object code:

(visit http://home.comcast.net/~tasm/ for +info)

MNEM. ARGS. OPCODE BYTES MODOP. CLASS-----------------------------------------------RESET "" A1 01 NOTOUCH 1TMS * A2 02 NOTOUCH 1SHF * A3 02 NOTOUCH 1SHFCP * A4 02 NOTOUCH 1RUNTEST * A5 03 SWAPEOP "" 454F50 03 NOTOUCH 1

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Test workflow

● Produce the source code in SVF-like format● Compile to Intel Hex object code via TASM● Send the object code to the test processor

memory via RS-232C● Use the "Run" button to execute the test and

the leds to check the result

Write the source code (*.asm) using notepad++

➨ Generate the object code(tasm –XX name.asm)

➨ Send the object file (*.obj) to the Avnet board via RS-232C

➨ Run the test(press Run or send command via RS-232C)

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Challenges vs. presentations so far

● Develop the VHDL model for the test processor -- recall: design of FSMD (Morten and Hakon), the Xilinx ISE tools (Gunnar and John), and ModelSim (Alex and Per)

● Adapt existing models for the UART (Alex and Per) and Xilinx specific memory (Bard and Gunnar)

● Integrate, verify via simulation, validate via the Avnet board (John and Bard)

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Going further

● Enable a "step mode" to run the test (one command at a time)

● Support two TAPs instead of just one (enabling test actions simultaneously in both BS chains?)

● Support control and observation of parallel I/O pins in the edge connectors

● Use the LCD to display test information (Morten and Hakon)

● What else?...

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How do I start? [one possible way]

● Make sure that you understand how the test processor architecture works (draw the state diagrams for executing each instruction)

● Sketch the hardware structures that enable the implementation of each block (e.g. how do you implement the Program Counter?)

● Code and simulate each structure in VHDL ● Integrate and extend validation to the whole

test processor architecture● Integrate with RS-232C and memory...

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Thanks for your attention!

HiBu | DDIS3010 | josemmf@hibu.no

Digitale Systemer 2012/13[ November 2012 ]