datasheet - preliminary specification · for the latest version of the datasheet e2v semiconductors...

PC109Host Bridge for PowerPC

Datasheet - Preliminary Specification

Features• Processor Interface

– Supports PowerPC Processors• Freescale MPC74xx• IBM PPC 750xx

– Operates up to 200 MHz in Single Processor Mode– Operates up to 167 MHz in Dual Processor Mode

• PCI/X Interface– Support PCI 2.3 and PCI-X 1.0 Modes– Operates up to 133 MHz– Supports PCI/X Host or Agent Operation– Supports Compact PCI Hot Swap

• Memory Controller– Supports DDR2-400 Devices– Operates up to 200 MHz– Enhanced Memory Pipeline

• Other Features– Integrated Bus Arbiters for Processors and PCI/X Devices– Integrated Power Management of Processors and Memory Devices– Four Independent DMA/XOR Channels– Clock Generator with Spread-spectrum Capability– Two Independent Gigabit Ethernet Ports– HLP Interface for Flash and Other Simple I/O Devices– Two UARTs– 16-bit Parallel GPIO Port– I2C/EEPROM Interface– Programmable Interrupt Controller– JTAG Support (Boundary Scan) with Register Access Capability– Packaging: 1023-pin, 33x33 mm, FCBGA, RoHS-compliant and HITCE (TBC), Pin Compatible with Tsi108– Power Consumption: 2.5W Typical, 3.8W Maximum

DescriptionThe PC109 is an advanced host bridge for PowerPC processors that supports PCI-X, DDR2-400 SDRAM, Gigabit Ether-net, and Flash. The device contains numerous integrated features that enable customers to reduce system designcomplexity and system costs.

Visit our website: www.e2v.comfor the latest version of the datasheet

e2v semiconductors SAS 2007

PC109 [Preliminary]

ScopeThe PC109 Hardware Manual discusses electrical, physical, and board layout information for the PC109.It is intended for hardware engineers who are designing system interconnect applications with thesedevices.

Screening• Full Military Temperature Range (TJ = -55°C, +125°C)• Industrial Temperature Range (TJ = -40°C, +110°C)

1. Block Diagram

2. Features

2.1 Enhancing System PerformanceThe advanced Switch Fabric architecture of the PC109 allows designers to significantly enhance systemperformance. The Eternet Controller and PCI-X Interface offer superior data transfer rates. In addition,CPU to memory performance is exceptional due to features like configurable port arbitration priority andqueuing reads ahead of writes.

2.2 Minimizing System CostThe PC109 feature set provides system designers with an array of integrated functionality to assist inlowering overall system cost, such as an integrated Clock Generator with spread-spectrum capabilities,a DDR2-400 Memory Controller, and internal processor and PCI/X bus arbiters.

SwitchFabric

60x/MPX 200-MHz Bus, 64-bit Data, 32/36-bit Address

Two10/100/1GPorts

32-bitFlash &I/O Access

Process andMemory Power

Management

PowerMgmt

Four ExternalInterrupts

InterruptController

Four DMAChannels DMA

Two UARTs UART

IEEE1149.1Boundry

ScanJTAG

Spread-spectrumClock Generator

Clock Generator

Eth

erne

t Con

trol

ler

Connects toSerial PROMs I2C

16-bit I/O Port

GPIO

133-MHz PCI-X Bus66-MHz/64-bit PCI Bus, 64-bit Data

Seven Bus Masters

Host Local Port

80B5020_BK001_04

Processor Interface Arbiter

PCI-X Interface Arbiter

DDR2-400,

8-bit ECC

Mem

ory

Con

trol

ler

20838B–HIREL–04/07


PC109 [Preliminary]

2.3 Simplifying DesignPC109’s flexible configuration options empower designers to develop their systems quickly and effi-ciently. Selection of PCI/PCI-X modes, an integrated Clock Generator, DDR2 support, and the ability toconfigure it as a PCI Host/Agent, all enable the PC109 to be used in a range of applications. The JTAGInterface also simplifies the debug process by allowing access to PC109’s registers without impactingactive transactions.

2.4 Effective Power ManagementThe PC109 is the lowest, power-consuming host bridge on the market. It minimizes active power by dis-abling unused ports and clocks, while its integrated Clock Generator saves power over discrete devices.Its support for DDR2 provides memory power savings of up to 50 percent when compared with DDR. Italso supports precharge power-down and quiet stand-by power reduction modes on memory. In addi-tion, the PC109 conforms to the PCI Bus Power Management Interface Specification.

2.5 Document ConventionsThis document uses a variety of conventions to establish consistency and to help you quickly locateinformation of interest. These conventions are briefly discussed in the following sections.

Non-differential Signal NotationNon-differential signals are either active-low or active-high. An active-low signal has an active state oflogic 0 (or the lower voltage level), and is denoted by a lowercase n. An active-high signal has an activestate of logic 1 (or the higher voltage level), and is not denoted by a special character. The followingtable illustrates the non-differential signal naming convention.

Differential Signal NotationDifferential signals consist of pairs of complement positive and negative signals that are measured at thesame time to determine a signal’s active or inactive state (they are denoted by _P and _N, respectively).The following table illustrates the differential signal naming convention.

State Single-line Signal Multi-line Signal

Active low NAMEn NAMEn[3]

Active high NAME NAME[3]

State Single-line Signal Multi-line Signal

InactiveNAME_P = 0

NAME_N = 1

NAME_P[3] = 0

NAME_N[3] = 1

ActiveNAME_P = 1

NAME_N = 0

NAME_P[3] is 1

NAME_N[3] is 0

30838B–HIREL–04/07


PC109 [Preliminary]

3. General ParametersTable 3-1 provides a summary of the general parameters of the PC109

Table 3-1. Device Parameters

Parameter Description

Technology 130 nm

Die size 8,71 mm x 8,92 mm

Packages 1023 PBGA and HITCE (TBC)

Core power supply 1,2V ± 5%

I/O power supply 3,3V ± 0,3V and 1,8 ± 5%

40838B–HIREL–04/07


PC109 [Preliminary]

4. Signal Description

Figure 4-1. PC109 Microprocessor Signal Groups

PC109

PB_A[0:35]

PB_AACKn

PB_AP[0:4]

PB_ARTRYn

PB_BGn[0:1]

PB_BRn[0:1]

PB_D[0:63]

PB_DBGn[0:1]

PB_DP[0:7]

PB_DRDYn[0:1]

PB_DTI[0:2]

PB_GBLn

PB_HITn[0:1]

PB_INTn[0:3]

PB_QREQn[0:1]

PB_QACKn[0:1]

PB_RSTn

PB_RSTOD

PB_SYSCLK

PB_TAn

PB_TEAn

PB_TBSTn

PB_TSn

PB_TSIZ[0:2]

PB_TT[0:4]

PB_SENSE

Processor Interface

PCI/X Interface Signals

JTAG Interface signals

PLL Power Signals

Memory Controller Signals

Ethernet Controller

Interrupt Controller Signals

HLP Interface Signals

I2C Interface Signals

UART Interface Signals

E_0_TCG[9:0]

E_0_RCG[9:0]

E_0_ PCRS_SDET

E_0_PCOL_R

E_0_ECMDT

E_0_EWRAP

E_0_PRBSEN

E_0_PRBS_PASS

E_0_RXCLK

E_0_TXCLK

E_1_TCG[9:0]

E_1_RCG[9:0]

E_1_PCRS_SDET

E_1_PCOL_RBCM

E_1_ECMDT

E_1_EWRAP

E_1_PRBSEN

E_1_PRBS_PASS

E_1_RXCLK

E_1_TXCLK

E_MDC

E_MDIO

E_REF125

E_GTXCLK[1:0]

SD_SYSCLK

SD_A[15:0]

SD_BA[2:0]

SD_CASn

SD_CLK_P[5:0]/SD_CLK_N[5:0]

SD_CLKEN[1:0]

SD_CLKFBI_PSD_CLKFBI_N

SD_CLKFBO_P/SD_CLKFBO_N

SD_CSn[3:0]

SD_DQ[63:0]

SD_DQS_P[17:0]/SD_DQS_N[17:0]

SD_CB[7:0]

SD_I2C_CLK

SD_I2C_SD

SD_RASn

SD_VREF[1:0]

SD_WEn

SD_ODT[3:0]

SD_DLL_TEST 1:0

PCI_ACK64n

PCI_AD[63:0]

PCI_CBEn[7:0]

PCI_CLK

PCI_DEVSELn

PCI_FRAMEn

PCI_GNTn[7:1]

PCI_IDSEL

PCI_INTAn

PCI_INTBn

PCI_INTCn

PCI_INTDn

PCI_IRDYn

PCI_M66EN

PCI_PAR

PCI_PCIX CAP[1:0]

PCI_PAR64

I_PC

PCI_PERRn

PCI_PMEn

PCI_REQn[7:1]

PCI_REQ64n

PCI_RSTn

PCI_RSTDIR

PCI_SERRn

PCI_STOPn

PCI_TRDYn

PCI_ENUMn

PCI_ES

PCI_HEALTHYn

PCI_HS64ENn

PCI_LEDn

PCI_SENSE

Clock Generator Signals

INT[3:0]

GPIO Interface SignalsGPIO[15:0]

I2C_SCLK

I2C_SD

HLP_AD[31:0]

HLP_CSn[3:0]

HLP_LE

HLP_RDYn

HLP_OEn

HLP_WEn

U_0_RX

U_0_TX

U_1_RX

U_1_TX

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_TRSTn

TEST_ON

TEST_BIDR_CTL

TEST_TM[3:0]

CG_REF

CG_PB_CLKO[2:0]

CG_PCI_CLKO[3:0]

CG_PB_SELECT[2:0]

CG_SD_SELECT[2:0]

Power Supply Signals

Switch Fabric SignalsOCN_RSTn

PB_PLL_AVDD

PB_PLL_AVSS

PCI_PLL_AVDD

PCI_PLL_AVSS

SD_PLL_AVDD

SD_PLL_AVSS

CLKGEN_PLL_AVDD

CLKGEN_PLL_AVDD

CLKGEN_PLL_AVSS

CLKGEN_PLL_AVSS

VDD (50)

VDD_PC (49)

VDD_PB (45)

VDD_SD (39)

VSS (50)

VSS_IO (160)

50838B–HIREL–04/07


PC109 [Preliminary]

5. Detailed SpecificationThis specification describes the specific requirements for the microprocessor PC109 in compliance withe2v standard screening.

6. Applicable Documents1. MIL-STD-883: Test methods and procedures for electronics

2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

The microcircuits are in accordance with the applicable documents and as specified herein.

6.1 Design and Construction

6.1.1 Terminal ConnectionsDepending on the package, the terminal connections are as shown in Table 8-1 on page 10, and Table6-2 on page 7.

6.2 Absolute Maximum RatingsThe following table contains the absolute maximum ratings for the PC109.

Note: 1. The VDD reference is dependent on the input pad supply rail.

Table 6-1. Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Units

TSTG Storage temperature -55 125 °C

Voltage with respect with ground

VDD

VDD_PLL_P

VDD_PLL_SD

VDD_PLL_CG

1.2V DC supply voltage -0.5 2.0 V

VDD_PB1.8V DC supply voltage for Processor Interface

-0.5 2.6 V

VDD_SD1.8V DC supply voltage for Memory Controller

-0.5 2.6 V

VDD_PC

VDD_PLL_PCI3.3V DC supply voltage -0.5 4.1 V

VDD_SD_Vref SDRAM reference voltage 0 VDD_SD V

VIL Minimum signal input voltage -0.5 – V

VIH Maximum signal input voltage - VDD(1) + 0.5 V

60838B–HIREL–04/07


PC109 [Preliminary]

6.3 Recommended Operating ConditionsThe following table contains the recommended operating conditions for the PC109.

Notes: 1. The value of VDD_Vref may be selected by the user to provide optimum noise margin in the system. Typically, the value of VDD_Vref is expected to be (50 ±1)%*VDD_SD of the transmitting device, (for example, Vref min = 0.49*VDD_SD(min) and Vref max = 0.51*VDD_SD(max). VDD_Vref is expected to track variation of VDD_SD.

2. Peak to peak ac noise on VDD_Vref may not exceed ±12% of VDD_Vref.3. Some SDRAMs may further limit the maximum reference voltage.

4. VDD_Vtt is expected to track VDD_Vref of the receiving device.

5. No heat sink, no air flow.

6. Higher ambient temperatures are permissible provided TJUNC is not violated. For heat sink and air flow requirements for higher temperature operation, seeSection 6.4 on page 7.

6.4 Thermal CharacteristicsThe PC109 is specified for operation when the junction temperature (TJUNC) is within the range specifiedby the recommended operating conditions (see Table 6-2 on page 7).

Because the junction temperature is not directly measurable, Case temperature may be used to derivethe junction temperature. Case temperature may be measured in any environment to determine whetherthe part is within the specified operating range. Case temperature is best measured at the center of thetop surface, directly above the die and ballpad.

Table 6-2. Recommended Operating Conditions

Symbol Parameter Minimum Maximum Units Notes

VDD_PC 3.3V DC supply voltage 3.0 3.6 V –

VDD_PB 1.8V supply voltage for Processor Interface 1.71 1.89 V –

VDD_SD 1.8V supply voltage for Memory Controller 1.71 1.89 V –

VDD_Vref Input reference voltage 838 963 mV (1)(2)(3)

VDD_Vtt Termination voltage VDD_Vref - 40 VDD_Vref +40 mV (4)

VDD 1.2V supply voltage 1.14 1.26 V –

VDD_PLL_PB PB_PLL analog supply voltages 1.14 1.26 V –

VDD_PLL_SD SD_PLL analog supply voltage 1.14 1.26 V –

VDD_PLL_CG CG_PLL analog supply voltage 1.14 1.26 V –

VDD_PLL_PCI PCI_PLL analog supply voltage 3.0 3.6 V –

TJUNC

Junction temperature – Military -55 125 °C –

Junction temperature – Industrial -40 110 °C –

Table 6-3. Package Parameters for Thermal Analysis

Package Information FCBGA

Ball Count 1023

Size (mm) 33 x 33

Ball Pitch (mm) 1.00

Ball Matrix (mm) 32 x 32

Signal Ball Row Depth 8

70838B–HIREL–04/07


PC109 [Preliminary]

Note: 1. Bare die, power dissipation of 3.68W.

2. Theta Junction to (package) Ball.

3. 8-layer PCB.

Note: 1. TJUNC as specified in Table 6-2 on page 7.

2. PTOTAL as specified in Table 9-1 on page 16.

3. Calculated as (TJUNC(max) - TA)/Power(max). The required ThetaJA is the maximum allowable ThetaJA to maintain a junction temperature of 125°C.

4. Thermal management of the PC109PC109 is required under these conditions because the required ThetaJA is smaller than the ThetaJA for specified in Table 6-3 on page 7.

Thermal Ball Matrix 10 x 12

Vias 120

Die Size (mm) 8.71 x 8.92

Substrate layers 3 + 2 + 3

Substrate Thickness (mm) 1.2

Power Dissipation (W) 3.68

ThetaJA (°C/W)(1)– Vair = 0.00 m/s 13.6

ThetaJA (°C/W) – Vair = 1.00 12.2

ThetaJA (°C/W) – Vair = 2.00 11.5

ThetaJC (°C/W)(1) 0.08

ThetaJB(2) (°C/W)(3) 10.35

Table 6-4. Sample Thermal Analysis

PCB Conditions

PCB layer count 8

PCB Dimensions (mm) 139.5 x 127

PCB Thickness (mm) 1.6

Environment Conditions

Maximum Junction Temperature (°C)

125(1)

Power Dissipation (W) 3.68(2)

Industrial Commercial

Ambient Temperature (°C) 85 70

Required ThetaJA(3) 10.9(4) 14.9

Table 6-3. Package Parameters for Thermal Analysis (Continued)

Package Information FCBGA

80838B–HIREL–04/07


PC109 [Preliminary]

7. Pin AssignmentFigure 7-1 shows the pinout of the PC109, 1023 BGA expansion package as viewed from the top sur-face. Figure 7-2 shows the side profile of the BGA package to indicate the direction of the top surfaceview.

Figure 7-1. Pinout of the PC109, 1023 BGA Package as Viewed from the Top Surface

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

321 4 5 6 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

151413121110987

90838B–HIREL–04/07


PC109 [Preliminary]

Figure 7-2. Side View of the BGA Package

8. Pinout ListingsTable 8-1 provides the pinout listing for the PC109, 1023 BGA package.

Substrate Assembly

Encapsulant

ViewDie

Table 8-1. Pinout Listing for the PC109, 1023 BGA Package

Signal Name Pin Number I/O

Clock Generator

CG_PB_CLKO[0-2] H32, H31, J32 1.8 Out

CG_PB_SELECT[0-2] J31, E32, H29 1.8 In

CG_PCI_CLKO[0-3] AM18, AM17, AM19, AL18 PCI Out

CG_REF F32 1.8 Out

CG_SD_SELECT[0-2] G29, G32, H28 1.8 In

PLL Power

CLKGEN_PLL_AVDD[0-1] K29 J1 Analog Power

CLKGEN_PLL_AVSS[0-1] K30 J2 Analog Power

DMA

DMAPE_ACK[0-1] AE22, AF23 1.8 Bidir

DMAPE_CLK AL24 1.8 Bidir

DMAPE_CLKO[0-1] AK22, AM23 1.8 Bidir

DMAPE_DATA[0-7] AH21, AG22, AH22, AJ22, AE23, AM22, AH23, AJ23 1.8 Bidir

DMAPE_EOD AL23 1.8 Bidir

Ethernet

E_0_ECMDT AB8 3.3 3-state

E_0_EWRAP AE4 3.3 3-state

E_0_PCOL_RBCM AB5 3.3 Bidir

E_0_PCRS_SDET AD4 3.3 In

E_0_PRBS_PASS AB6 3.3 In

E_0_PRBSEN AC6 3.3 3-state

E_0_RCG[0-9] AC8, AD5, AD6, AD7, AE5, AE6, AE7, AF5, AF6, AG5 3.3 In

E_0_RXCLK AC7 3.3 In

E_0_TCG[0-9] AA7, AA6, AA5, Y8, Y7, Y6, Y5, W8, W6, W5 3.3 3-state

E_0_TXCLK AA8 3.3 In

100838B–HIREL–04/07


PC109 [Preliminary]

E_1_ECMDT AE1 3.3 3-state

E_1_EWRAP AD2 3.3 3-state

E_1_PCOL_RBCM AC3 3.3 Bidir

E_1_PCRS_SDET AC2 3.3 In

E_1_PRBS_PASS AC4 3.3 In

E_1_PRBSEN AE3 3.3 3-state

E_1_RCG[0-9] AE2, AF3, AG1, AG2, AG3, AG4, AH2, AH3, AJ1, AK1 3.3 In

E_1_RXCLK 1AF1 3.3 In

E_1_TCG[0-9] AB4, AB3, AC1, AA4, AA3, AA2, Y3, Y2, AA1, W4 3.3 3-state

E_1_TXCLK AB1 3.3 In

E_GTXCLK[0-1] AD1, AH1 3.3 Out

E_MDC W3 3.3 Out

E_MDIO W1 3.3 Bidir

E_REF125 Y1 3.3 In

GPIO

GPIO[0-9] N5, N6, T4, T5, U6, U7, V4, V5, P3, P5, P6, P7, R3, R5, R6, R7 3.3 Bidir

HLP

HLP_AD[0-31]G1, G2, H2, H3, H5, H6, H7, G5, G6, J3, J4, J5, J6, J7, J8, K1, K3, K4, K5, K6, K8, L1, L2, L3, L4, L6, L7, L8, M6, M7, M8

3.3 Bidir PU

HLP_CSn[0-3] M2, N1, M3, M4 3.3 Out

HLP_LE M5 3.3 3-state

HLP_OEn N4 3.3 Out

HLP_RDYn N3 3.3 In

HLP_WEn M1 3.3 Out

I2C

I2C_SCLK U8 3.3 OD PU

I2C_SD V8 3.3 Bidir OD PU

INT

INT[0-3] R4, U4, T6, V6 3.3 In

JTAG

JTAG_TCK R2 3.3 In

JTAG_TDI P2 3.3 In PU

JTAG_TDO P1 3.3 Out

JTAG_TMS U2 3.3 In PU

JTAG_TRSTn T3 3.3 In PU

Table 8-1. Pinout Listing for the PC109, 1023 BGA Package (Continued)


110838B–HIREL–04/07


PC109 [Preliminary]

NCB4, C17, C23, C28, C30, D30, E4, F3, F4, F5, F6, F8, F12, F25, G27, G30, H8, J30, V7, AE21, AF21

Switch Fabric

OCN_RSTn V3 3.3 In

Processor Bus

PB_A[0-35]J28, T29, M28, T27, K32, V30, K27, R29, K26, R30, J26, W25, T30, V31, R26, AA31, T26, Y30, V27, AA26, U31, U28, V26, R27, T25, AB30, Y31, Y25, Y26, AA32, Y27, AB32, J27, F30, H26, J25

1.8 Bidir

PB_AACKn W26 1.8 3-state PU

PB_AP[0-4] P25, R31, N30, N32, L25 1.8 Bidir

PB_ARTRYn W32 1.8 Bidir PU

PB_BGn[0-1] V29, V28 1.8 3-state PU

PB_BRn[0] N29, N27 1.8 In PU

PB_D[0-63]

AJ29, AK31, AJ30, AL32, AM31, AK29, AG28, AF27, AJ32, AJ31, AH30, AG29, AH29, AK32, AF29, AF28, AH32, AG31, AE29, AC27, AF30, AL26, AG32, AD28, AK24, AJ25, AD29, AG25, AK25, AF31, AF26, AF24, AD31, AC25, AC28, AC29, AE32, AC26, AG26, AB25, AK28, AM25, AL29, AJ27, AM28, AM24, AM27, AL27, AK26, AM30, AM29, AJ28, AH26, AH27, AD32, AL30, AC30, AE26, AD25, AG24, AE25, AH25, AF32, AH24

1.8 Bidir

PB_DBGn[0-1] Y28, Y29 1.8 3-state PU

PB_DP[0-7] AB27, AB26, AB29, AD26, AE27, AC31, AE30 1.8 Bidir

PB_DRDYn[0-1] W29, W27 1.8 In PU

PB_DTI[0-2] U29, W30, Y32 1.8 3-state PU

PB_GBLn R28 1.8 Bidir PU

PB_HITn[0-1] R32, N26 1.8 In PU

PB_INTn[0-3] T32, M25, M26, M27 1.8 3-state PU

PB_PLL_AVDD M30 Analog Power

PB_PLL_AVSS M29 Analog Power

PB_QACKn[0-1] R25, P29 1.8 3-state PU

PB_QREQn[0-1] AA29, AA28 1.8 In PU

PB_RSTn F31 1.8 3-state

PB_RSTOD V32 1.8 In

PB_SENSE AG21 PVT Calibration

PB_SYSCLK P32 1.8 In

PB_TAn U32 1.8 3-state PU

PB_TBSTn P31 1.8 Bidir PU

PB_TEAn V25 1.8 3-state PU

PB_TSIZ[0-2] P26, M31, J29 1.8 Bidir



120838B–HIREL–04/07


PC109 [Preliminary]

PB_TSn U26 1.8 Bidir PU

PB_TT[0-4] L28, L26, P28, K25, L29 1.8 Bidir

PCI Bus

PCI_ACK64n AK15 PCI Bidir

PCI_AD[0-63] PCI Bidir

PCI_CBEn[0-7] AG14, AJ12, AG10, AK9, AH16, AF14, AE14, AM16 PCI Bidir

PCI_CLK AJ21 PCI In

PCI_DEVSELn AE11 PCI Bidir

PCI_ENUMn AK11 PCI OD

PCI_ES AH7 PCI In

PCI_FRAMEn AH10 PCI Bidir

PCI_GNTn[1-7] AL5, AK5, AH5, AM6, AL6, AK6, AJ6 PCI Bidir

PCI_HEALTHYn AM2 PCI In

PCI_HS64ENn AM3 PCI In

PCI_IDSEL AL9 PCI In

PCI_INTAn AK4 PCI Bidir OD

PCI_INTBn AM4 PCI Bidir OD

PCI_INTCn AJ3 PCI Bidir OD

PCI_INTDn AL2 PCI Bidir OD

PCI_IRDYn AL11 PCI Bidir

PCI_LEDn AL3 PCI OD

PCI_M66EN AE12 PCI In

PCI_PAR AH12 PCI Bidir

PCI_PAR64 AJ16 PCI Bidir

PCI_PCIXCAP[0-1] AK3, AJ4 PCI In

PCI_PERRn AG11 PCI Bidir

PCI_PLL_AVDD AM21 Analog Power

PCI_PLL_AVSS AL21 Analog Power

PCI_PMEn AL8 PCI Bidir OD

PCI_REQ64n AL15 PCI Bidir

PCI_REQn[1-7] AK8, AH6, AG6, AM7, AK7, AJ7, AM5 PCI Bidir

PCI_RSTDIR AK2 PCI In

PCI_RSTn AL1 PCI Bidir

PCI_SENSE AH4 PVT Calibration

PCI_SERRn AH11 PCI Bidir OD



130838B–HIREL–04/07


PC109 [Preliminary]

PCI_STOPn AF11 PCI Bidir

PCI_TRDYn AM11 PCI Bidir

PWRUP_PCI_HOST AE20

Memory Controler

SD_A[0-15]G16, G18, G17, H18, G19, H19, F20, H21, G21, G20, G15, G22, H22, G10, G23, G24

SSTL-18 Out

SD_BA[0-2] H15, H16, F23 SSTL_18 Out

SD_CASn G12 SSTL_18 Out

SD_CB[0:7] E18, D18, F15, C14, D19, C19, C15, D15 SSTL_18 Diff Bidir

SD_CLK_N[0-5] B18, A27, A5, A14, A26, A4 SSTL_18 Diff Out

SD_CLK_P[0-5] A17, B27, A6, B14, B26, B5 SSTL_18 Diff Out

SD_CLK_P[1-5] B27, A6, B14, B26, B5

SD_CLKEN[0-1] G25, F26 SSTL_18 Out

SD_CLKFBI_N B17 SSTL_18 Diff Bidir

SD_CLKFBI_P A16 SSTL_18 Diff Bidir

SD_CLKFBO_N A15 SSTL_18 Diff Out

SD_CLKFBO_P B16 SSTL_18 Diff Out

SD_CSn[0-3] G14, F9, H14, G9 SSTL_18 Out

SD_DLL_TEST[0-1] F16, F18 SSTL_18 Out

SD_DQ[0-63]

D31, C32, A29, A28, E31, D32, A30, B29, D29, F28, D25, C25, F29, E29, D26, C26, A24, B23, A19, A18, A25, B24, B20, A20, E23, D23, C20, F19, E24, D24, E20, D20, A12, A11, A7, B7, A13, B13, A8, B8, D13, E13, E10, C9, D14, E14, E11, D10, D8, E8, E5, D4, D9, C8, C5, D5, A2, B2, E2, F1, A3, C3, D3, E1

SSTL_18 Bidir

SD_DQS_N[0-17]A31, D27, B21, E21, B10, C11, C6, D2, D16, B32, E27, A22, C22, A10, D12, E7, C2, D17

SSTL_18 Diff Bidir

SD_DQS_P[0-17]B30, E26, A21, D21, A9, D11, D6, D1, E16, C31, D28, A23, D22, B11, C12, D7, B1, E17

SSTL_18 Diff Bidir

SD_I2C_CLK G3 3.3 OD PU

SD_I2C_SD G4 3.3 Bidir OD PU

SD_ODT[0-3] F11, G8, G11, F7 SSTL_18 Out

SD_PLL_AVDD L31 Analog Power

SD_PLL_AVSS L32 Analog Power

SD_RASn F14 SSTL_18 Out

SD_SYSCLK M32 1.8 In

SD_VREF[0-1] H12, F22SSTL_18

Reference Voltage

SD_WEn G13 SSTL_18 Out



140838B–HIREL–04/07


PC109 [Preliminary]

JTAG

TEST_BIDR_CTL V2 3.3 In PD

TEST_ON U3 3.3 In PD

TEST_TM[0-3] V1, R1, U1, T1 3.3 Bidir

UART

U_0_RX P8 3.3 In

U_0_TX T8 3.3 Out

U_1_RX N8 3.3 In

U_1_TX R8 3.3 Out

VDD

M13, M15, M17, M19, M21, N12, N14, N16, N18, N20, P13, P15, P17, P19, P21, R12, R14, R16, R18, R20, T13, T15, T17, T19, T21, U12, U14, U16, U18, U20, V13, V15, V17, V19, V21, W12, W14, W16, W18, W20, Y13, Y15, Y17, Y19, Y21, AA12, AA14, AA16, AA18, AA20

Core Power

VDD_PB

H27, H30, K24, L23, L24, L27, L30, M23, N23, N24, P23, P27, P30, R23, R24, T23, U23, U24, U27, U30, V23, W23, W24, Y23, AA23, AA24, AA27, AA30, AB23, AC21, AC23, AC24, AD21, AD22, AD23, AD27, AD30, AE24, AG23, AG27, AG30, AK23, AK27, AK30, AM26

PB I/O Power

VDD_PC

J9, K9, K10, L9, L10, M9, M10, N9, N10, P9, P10, R9, R10, T9, T10, U9, U10, V9, V10, W9, W10, Y9, Y10, AA9, AA10, AB9, AB10, AC9, AC10, AC11, AC12, AC13, AC14, AC15, AC16, AC17, AC18, AC19, AD9, AD10, AD11, AD12, AD13, AD14, AD15, AD16, AD17, AD18, AD19

I/O Power

VDD_SD

C4, C7, C10, C13, C16, C18, C21, C24, C27, C29, E28, F10, F13, F17, F21, F24, G26, H10, H11, H23, H24, J11, J13, J15, J17, J19, J21, J23, K12, K13, K14, K15, K16, K17, K18, K19, K20, K21, K22

SD I/O Power

VSS

M12, M14, M16, M18, M20, N13, N15, N17, N19, N21, P12, P14, P16, P18, P20, R13, R15, R17, R19, R21, T12, T14, T16, T18, T20, U13, U15, U17, U19, U21, V12, V14, V16, V18, V20, W13, W15, W17, W19, W21, Y12, Y14, Y16, Y18, Y20, AA13, AA15, AA17, AA19, AA21

Core Ground

VSS_IO

A32, B3, B6, B9, B12, B15, B19, B22, B25, B28, B31, C1, E3, E6, E9, E12, E15, E19, E22, E25, E30, F2, F27, G7, G28, G31, H4, H9, H13, H17, H20, H25, J10, J12, J14, J16, J18, J20, J22, J24, K2, K7, K11, K23, K28, K31, L5, L11, L12, L13, L14, L15, L16, L17, L18, L19, L20, L21, L22, M11, M22, M24, N2, N7, N11, N22, N25, N28, N31, P4, P11, P22, P24, R11, R22, T2, T7, T11, T22, T24, T28, T31, U5, U11, U22, U25, V11, V22, V24, W2, W7, W11, W22, W28, W31, Y4, Y11, Y22, Y24, AA11, AA22, AA25, AB2, AB7, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AB18, AB19, AB20, AB21, AB22, AB24, AB28, AB31, AC5, AC20, AC22, AD3, AD8, AD20, AD24, AE28, AE31, AF2, AF4, AF7, AF10, AF13, AF16, AF19, AF22, AF25, AH8, AH14, AH20, AH28, AH31, AJ2, AJ5, AJ11, AJ17, AJ24, AJ26, AL4, AL7, AL10, AL13, AL16, AL19, AL22, AL25, AL28, AL31, AM1, AM32

I/O Ground



150838B–HIREL–04/07


PC109 [Preliminary]

9. Electrical CharacteristicsThis chapter discusses the following topics about the PC109 electrical characteristics:

• Section 6.2 ”Absolute Maximum Ratings” on page 6

• Section 6.3 ”Recommended Operating Conditions” on page 7

• Section 9.1 ”Power Characteristics” on page 16

• Section 9.2 ”Power Supply Sequencing” on page 17

• Section 9.3 ”DC and Operating Characteristics” on page 18

• Section 9.4 ”AC Timing Specifications” on page 20

• Section 9.5 ”AC Timing Waveforms” on page 39

9.1 Power CharacteristicsThe following table contains power characteristics for the PC109.

Notes: 1. Expected usage model: Clocks operating at maximum frequency; little or low activity for UART, I2C, GPIO, INT, JTAG, TEST, and HLP interfaces; mix of read and write operations on Processor Interface, Memory Controller, and PCI-X Interfaces, DMA operating, both Ethernet ports operating.

2. Maximum chip power is consumed when the PC109 drives all its output; however, it is not possible for the device to continuously drive all outputs all the time. This is why the maximum power, 3.8W, is less than the sum of the maximum current draw on each power rail.

The maximum power specification is a sustained measurement while the maximum current draw is apeak measurement. The PC109 may draw peak currents as high as those specified for each rail underspecific conditions, but the conditions to draw peak current on one rail prevent the possibility of drawingpeak current on the others. Therefore, it is not valid to calculate the power of the device from the peakcurrent draw on each individual rail.

Table 9-1. Power Characteristics

Symbol Parameter Maximum Units Notes

Power Consumption

PTOTAL Total chip power 3.8 W (1)(2)

PCORE Core power including PLLs 1.2 W (1)

PIO I/O power 2.6 W (1)

Supply Currents

IDD_SD VDD_SD current draw 800 mA –

IDD_PB VDD_PB current draw 300 mA –

IDD_PC VDD_PC current draw 875 mA –

IDD VDD current draw 1050 mA –

160838B–HIREL–04/07


PC109 [Preliminary]

9.2 Power Supply SequencingTo ensure proper operation of the PC109, the supply voltages for the device must be sequenced asfollows:

1. The 1.2V supplies, VDD, VDD_PLL_PB, VDD_PLL_SD, and VDD_PLL_CG. must be applied simultaneously.

2. The 3.3V supplies, VDD_PC and VDD_PLL_PC must be applied simultaneously.

3. The VDD_SD, 1.8V, must be applied before the VDD, 1.2V.

4. The VDD_Vref, 0.9V, must track VDD_SD/2.5. The termination voltage, VDD_Vtt, must track VDD_Vref.

6. The VDD_PC must be applied after VDD. There is no restriction on the interval from VDD to VDD_PC.7. The VDD_PB must be applied after VDD. There is no restriction on the interval from VDD to VDD_PB.8. There are no sequencing requirements between VDD_PB and VDD_PC. This is displayed in Figure

9-1 on page 17. VDD_SD is shown in magenta with the solid and dashed lines indicating the window in which VDD_SD must be applied. The VDD_PB is shown in blue, and VDD_PC in green; the solid and dashed lines indicating the window in which these supplies are to be applied. Red shows the 1.2V supplies, VDD, VDD_PLL_PB, VDD_PLL_SD, and VDD_PLL_CG. Cyan shows the refer-ence and termination voltages: VDD_Vref and VDD_Vtt. The ramp of the 1.2V supplies should be used as the time reference for comparing all other supply ramps.

Figure 9-1. Power Supply Sequencing

It is permissible to ramp all supplies simultaneously.

VDD_PB

Time

Vol

tage

3.3

1.8

1.2

0.9

0.0

VDD_SD

VDD_Vref & VDD_Vtt

VDD_PC & VDD_PLL_PC

VDD, VDD_PLL_PB, VDD_PLL_SD, & VDD_PLL_CG

Table 9-2. Power Supply Slew Rate Requirements

Symbol Parameter Minimum Maximum Units

TSLEW_SD Slew rate of VDD_SD 10 1,000,000 V/S

TSLEW_CORE Slew rate VDD, VDD_PLL_PB, VDD_PLL_SD and VDD_PLL_CG 10 1,000,000 V/S

TSLEW_PB Slew rate of VDD_PB 10 1,000,000 V/S

TSLEW_PC Slew rate of VDD_PC 10 1,000,000 V/S

170838B–HIREL–04/07


PC109 [Preliminary]

9.3 DC and Operating CharacteristicsThe following table contains DC and operating characteristics for the PC109.

Table 9-3. DC and Operating Characteristics

Symbol Parameter Condition Minimum Maximum Units Notes

VIL_SDSDRAM Input Low Voltage

– -300 VDD_Vref - 125 mV

VIH_SDSDRAM Input High Voltage

– VDD_Vref + 125 VDD_SD + 300 mV –

VIL_MISCMiscellaneous Input Low Voltage

– -0.3 0.8 V (1)

VIH_MISCMiscellaneous Input High Voltage

– 2.0 VDD_PC+ 0.5 V (1)

VIL_EEthernet Input Low Voltage

– -0.3 0.8 V –

VIH_EEthernet Input High Voltage

– 2.0 VDD_PC+ 0.5 V (2)

VIL_PCI PCI/X Input Low Voltage – -0.5 0.35VDD_PC V (3)

VIH_PCI PCI/X Input High Voltage – 0.5VDD_PC VDD_PC+ 0.5 V (3)

VIH_PB MPX Input High Voltage – 1.2 VDD_PB V (4)

VIL_PB MPX Input Low Voltage – 0 0.6 V –

VIPU MPX Pull-up Voltage – 0.7VDD_PB – V (5)

IILMPX Input leakage current

0<VIN<VDD18 – ± 20.0 µA (6)

VOL_MISC Misc Output Low Voltage IOL = 6 mA – 0.4 V (1)

VOH_MISC Misc Output High Voltage IOH = -6 mA VDD_PC - 0.5 – V (1)(2)(7)

VOL_PB MPX Output Low Voltage IOL = 5 mA – 0.4 V –

VOH_PB MPX Output High Voltage IOH = -5 mA 1.30 – V (7)

VOL_PCI PCI-X Output Low Voltage IOL = 1500 mA – 0.1VDD_PC V (3)

VOH_PCIPCI-X Output High Voltage

IOH = -500 mA 0.9VDD_PC – V (3)

VOL_EEthernet Output Low Voltage

IOL = 12 mA – 0.4 V –

VOH_EEthernet Output High Voltage

IOH = -12 mA VDD_PC - 0.5 – V (2)(7)

IOH_SDSDRAM output minimum source dc current

VDD_SD = 1.7 V; VOUT = 1420

mV-13.4 – mA –

IOL_SDSDRAM output minimum sink dc current

VDD_SD = 1.7 V; VOUT = 280

mV13.4 – mA –

CIN_MISC Input Pin Capacitance – – 5.1 pF (1)

CIN_SD Input Pin Capacitance – – 7.5 pF –

180838B–HIREL–04/07


PC109 [Preliminary]

Notes: 1. Miscellaneous (Misc) signals include all 3.3V signals that are not Processor, Memory, PCI/X, or Ethernet.

2. I/O Power Supply, VDD_PC = 3.3V.

3. As required by the PCI-X Addendum to PCI Local Bus Specification (Revision 1.0a).

4. Processor bus (PB) signals include all 1.8V signals on the Processor Interface (i.e. signal names that begin with PB); the 1.8V signals for the Clock Generator (i.e. signal names that begin with CG, but excluding CG_PCI_CLKO[3:0]); and SD_SYSCLK; All 1.8V signals that begin with DMAPE.

5. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization must insure that input buffer is conducting minimum current at this input voltage.

6. Input leakage current includes tri-state output leakage of the output driver. Pull-ups disabled.

7. VDD = Min, I/O supply = Min.

CIN_PB Input Pin Capacitance – – 8.6 pF –

CIN_PCI Input Pin Capacitance – – 8.8 pF (3)

CIN_E Input Pin Capacitance – – 6.2 pF –

CCLK_SDClock Pin Capacitance SD_SYSCLK

– – 6.4 pF –

CCLK_PBClock Pin Capacitance PB_SYSCLK

– – 6.4 pF –

CCLK_PCIClock Pin Capacitance PCI_CLK

– – 7.5 pF –

LIN_MISC Input Pin Inductance – – 7.7 nH (1)

LIN_SD Input Pin Inductance – – 11.1 nH –

LIN_PB Input Pin Inductance – – 9.5 nH –

LIN_PCI Input Pin Inductance – – 8.3 nH (3)

LIN_E Input Pin Inductance – – 8.8 nH –

LCLK_SDClock Pin Inductance SD_SYSCLK

– – 5.8 nH –

LCLK_PBClock Pin Inductance PB_SYSCLK

– – 6.2 nH –

LCLK_PCIClock Pin Inductance PCI_CLK

– – 4.9 nH (3)

RPU_PB

Pull up resistance of integrated processor interface pull up resistors when enabled

– 4100 8600 Ω –

Table 9-3. DC and Operating Characteristics (Continued)

Symbol Parameter Condition Minimum Maximum Units Notes

190838B–HIREL–04/07


PC109 [Preliminary]

9.4 AC Timing SpecificationsThis section discusses AC timing specifications for the PC109.

9.4.1 Clock Generator AC Signal Timing

Notes: 1. Reference clock frequency must not vary beyond the limits set by the spread spectrum requirements except while reset is active.

2. A 33.33MHz oscillator with ±100ppm accuracy meets the requirements for TF_CG and TFA_CG.

3. Measured from between VIL and VIH.

4. The time difference between a measured cycle period and the ideal cycle period.

5. CG_REF must meet all specified clock input requirements.

Table 9-4. Clock Generator Clock Specifications

Symbol Parameter Min Max Units Notes

TF_CG Reference Clock Frequency (PLL enabled) 11.33 33.33 MHz (1)

TFA_CG Reference clock Frequency accuracy -100 +100 ppm (2)

TC_CG Reference Clock Cycle Period (PLL enabled) 30 – ns –

TCH_CG Reference Clock High Time 10 – ns –

TCL_CG Reference Clock Low Time 10 – ns –

TSR_CG Reference Clock Slew Rate 1 6 V/ns (3)

TJPER_CG Reference Clock period jitter – 1.75 % (4)

TF_NOPLL Reference Clock Frequency (PLL disabled) – 133.333 MHz –

TC_NOPLL Reference Clock Cycle Period (PLL disabled) 7.5 – ns –

TCH_NOPLL Reference Clock High Time (PLL disabled) 3 – ns –

TCL_NOPLL Reference Clock Low Time (PLL disabled) 3 – ns –

TSR_NOPLL Reference Clock Slew Rate (PLL disabled) 1 6 V/ns –

TJPER_NOPLL Reference Clock period jitter (PLL disabled) – 2 % –

TDUTY_CGPB Clock Generator output duty cycle 45 55 % –

TSKEW_CGPB Skew between any two CG_PB_CLKO outputs – 27 ps –

TJPER_CGPB CG_PB_CLKO Clock period jitter -100 100 ps (5)(4)

TDUTY_CGPC Clock Generator output duty cycle 45 55 % –

TSKEW_CGPCI Skew between any two CG_PCI_CLKO outputs – 58 ps –

TJPER_CGPCI CG_PCI_CLKO Clock period jitter -175 175 ps (5)(4)

200838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-2. Clock Generator Interface Timing

9.4.2 Processor Interface AC Signal Timing

Notes: 1. Reference clock frequency must not vary beyond the limits set by the spread-spectrum requirements except while reset is active.

2. The PB_SYSCLK frequency must not exceed 200MHz +100ppm. At lower frequencies, the upper bound on accuracy is not applicable.



5. Spread-spectrum clocks typically use centre spread. The frequency at the highest excursion from nom-inal must not exceed TF_PB.

TSKEW_PCITSKEW_PCI

TSKEW_PBTSKEW_PB

TCL_CG

TC_CG

TCH_CG

CG_REFCLK

CG_PB_CLKO[x]

CG_PB_CLKO[y]

CG_PCI_CLKO[x]

CG_PCI_CLKO[y]

Table 9-5. Processor Interface Input Clock Specification


TF_PB PB_SYSCLK Clock Frequency 100 200 MHz (1)

TC_PB PB_SYSCLK Clock Cycle Time 5 10 ns –

TACC_PB PB_SYSCLK Clock Frequency accuracy – +100 ppm (2)

TCH_PB PB_SYSCLK Clock High Time 2 – ns –

TCL_PB PB_SYSCLK Clock Low Time 2 – ns –

TSR_PB PB_SYSCLK Clock Slew Rate 1 6 V/ns (3)

TJPER_PB PB_SYSCLK Clock period jitter -100 100 ps (4)

Spread Spectrum Requirement

fMOD_PB PB_SYSCLK modulation frequency 30 33 kHz –

fSPREAD_PB PB_SYSCLK Clock frequency spread -0.25 +0.25 % (5)

210838B–HIREL–04/07


PC109 [Preliminary]

Table 9-6 and Table 9-7 list the AC Specifications for the Processor Interface. The AC timing of the Pro-cessor Interface is opt imized for ei ther IBM or Freescale based on the power-up strapPWRUP_PB_CPU.

Notes: 1. Off is detected when the pin sources/sinks < 20 µA.

2. On is detected when the pin sources/sinks > 50 µA.

Notes: 1. Off is detected when the pin sources/sinks < 20 µA.

2. On is detected when the pin sources/sinks > 50 µA.

Table 9-6. AC Specifications for Processor Interface – Freescale Timing


TOV1_PBPB_SYSCLK to output valid for point to point connections

0.075 2.124 ns –

TOV2_PBPB_SYSCLK to output valid for multi-dropped connections

0.075 2.124 ns –

TOZ_PB PB_SYSCLK to output tri-state 2.45 ns (1)

TON_PB PB_SYSCLK to output driven 2.15 ns (2)

TIS_PB Input setup to PB_SYSCLK excluding PB_TSn 1.924 – ns –

TIS_PB_TSn PB_TSn setup to PB_SYSCLK 1.794 – ns –

TIH_PB Input hold from PB_SYSCLK 0.083 – ns –

Table 9-7. AC Specifications for Processor Interface – IBM Timing


TOV1_PBPB_SYSCLK to output valid for point to point connections

0.257 2.524 ns –

TOV2_PBPB_SYSCLK to output valid for multi-dropped connections

0.257 2.524 ns –

TOZ_PB PB_SYSCLK to output tri-state 2.85 ns (1)

TON_PB PB_SYSCLK to output driven 2.55 ns (2)

TIS_PB Input setup to PB_SYSCLK 1.124 – ns –

TIH_PB Input hold from PB_SYSCLK 0.447 – ns –

220838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-3. Processor Interface Timing

Figure 9-4. Processor Interface Overshoot/Undershoot

Table 9-8. AC Overshoot/Undershoot Specification for Processor Interface

Symbol Parameter Max Units Notes

– Maximum allowable peak overshoot above VDD_PB +0.9 V –

– Maximum allowable peak undershoot below ground -0.9 V –

– Maximum area under the overshoot signal above VDD_PB 0.75 V-ns –

– Maximum area above the undershoot signal below VSS 0.75 V-ns –

TIH_PBTIS_PB

TOV2_PB (min)

TOV1_PB (max)TOV1_PB (min)

TCL_PBTCH_PB

TC_PB

PB_SYSCLK

PB output (p-to-p)

PB output (multi-drop)

PB input

VDD_PB

VSS

Areas that contribute tothe undershoot area

Areas that contribute tothe overshoot area

230838B–HIREL–04/07


PC109 [Preliminary]

9.4.3 Memory Controller AC Signal Timing

Notes: 1. Reference clock frequency must not vary beyond the limits set by the spread spectrum requirements except while reset is active.



4. These spreading requirements must be met when using either: the internal Clock Generator frequency spreading function, a spread reference clock, or a spread clock with the Clock Generator in bypass mode.

Notes: 1. Includes duty cycle distortion due to jitter.


Table 9-9. SDRAM Input Clock Specification


TF_SD SD_SYSCLK Clock Frequency 100 200 MHz (1)

TC_SD SD_SYSCLK Clock Cycle Time 5 10 ns –

TCH_SD SD_SYSCLK Clock High Time 1 – ns –

TCL_SD SD_SYSCLK Clock Low Time 1 – ns –

TSR_SD SD_SYSCLK Clock Slew Rate 1 6 V/ns (2)

TJPER_SD SD_SYSCLK Clock period jitter -100 100 ps (3)

Spread Spectrum Requirements

fMOD_SD SD_SYSCLK Clock modulation frequency 30 33 kHz –

fSPREAD_SD SD_SYSCLK Clock frequency spread -0.25 +0.25 % (4)

Table 9-10. DDR SDRAM Output Clock Specification

Symbol Parameter

DDR 400

Units NotesMin Max

TF2_SD DDR SDRAM Clock Frequency 100 200 MHz –

TC2_SD DDR SDRAM Clock Cycle Time 5 10 ns –

TCH2_SD DDR SDRAM Clock High Time 0.45 0.55 TC2_SD(1)

TCL2_SD DDR SDRAM Clock Low Time 0.45 0.55 TC2_SD(1)

TCJIT_SD SD_CLK output period jitter -2.5% +2.5% TC2_SD(2)

TDQSH_SD DDR SDRAM SD_DQS output clock High Time 0.46 0.54 TC2_SD(1)

TDQSL_SD DDR SDRAM SD_DQS output clock Low Time 0.46 0.54 TC2_sd(1)

TCSKW_SD DDR SDRAM Clock Skew for SD_CLK[5:0] and SD_CLK_B[5:0] – 75 ps –

240838B–HIREL–04/07


PC109 [Preliminary]

Table 9-11. AC Specifications for Memory Controller


TADV_SD Internal DLL delay of SD_CLK (ADV_DELAY + 24)/150 TC2_SD(1)

TDQS_SD Internal DLL delay of SD_DQS (input) (DQS_DELAY + 24)/150 TC2_SD(2)

TFBI_SD Internal DLL delay of SD_CLKFBI (FBI_DELAY + 24)/150 TC2_SD(3)

TDQH_SD SD_DQ output high pulse width 0.46 0.54 TC2_SD(9)

TDQL_SD SD_DQ output low pulse width 0.46 0.54 TC2_SD(9)

TDQSS_SDSD_CLK rising edge to rising edge of SD_DQS

(0.19- TADV_SD)*TC2_SD - 0.23

(0.31 - TADV_SD)*TC2_SD + 0.23

ns(4)(5)(6)(

9)

TDSS_SDSD_CLK rising edge to falling edge of SD_DQS

TDQSS_SD(min) + TDQH_SD(min)

TDQSS_SD(max) +TDQH_SD(max)

ns (4)(9)

TDQSON_SD SD_CLK rising edge to SD_DQS driven(0.19 - TADV_SD)*

TC2_SD- 0.09(0.31 - TADV_SD)*TC2_SD + 0.530

ns (4)(7)(9)

TDQSOFF_SD SD_CLK rising edge to SD_DQS tri-state(0.19 - TADV_SD)*TC2_SD + 0.440

(0.31 - TADV_SD)*TC2_SD + 1.590

ns (4)(8)(9)

TOVCMD_SDSD_A & SD_BA and SD_CASn, SD_RASn & SD_WEn output valid from SD_CLK

(0.69 - TADV_SD) *TC2_SD- 0.31

(0.81 - TADV_SD)*TC2_SD + 0.23

ns (4)

TOVCTRL_SDSD_CLKEN, SD_ODT, and SD_CSn output valid from SD_CLK

(0.69 - TADV_SD) * TC2_SD- 0.31

(0.81 - TADV_SD)*TC2_SD + 0.23

ns (4)

TOVDQ_SDSD_DQ/SD_DQM write output valid time from SD_ DQS

0.215 * TC2_SD-0.31 0.285 * TC2_SD + 0.23 ns (9)

TDQON_SD SD_CLK to SD_DQ driven(0.69 - TADV_SD) *

TC2_SD- 0.09(0.81 - TADV_SD) *

TC2_SD + 0.53ns (7)

TDQOFF_SD SD_CLK to SD_DQ tri-state(0.69 - TADV_SD) *

TC2_SD + 0.44(0.81 - TADV_SD) *

TC2_SD + 1.59ns (8)

TOVFBOF_SD SD_CLK to SD_CLKFBO output low(0.19 - TADV_SD)*

TC2_SD- 0.23(0.31 - TADV_SD)*

TC2_SD+ 0.23ns (4)(11)

TOVFBOR_SD SD_CLK to SD_CLKFBO output high(0.69 - TADV_SD) *

TC2_SD- 0.23(0.81- TADV_SD)*

TC2_SD + 0.23ns (4)(11)

TSU_SDSD_DQ & SD_CB read input setup time to SD_ DQS (rising or falling)

(0.035 -TDQS_SD) * TC2_SD + 0.4

– ns (7)(11)

TIH_SDSD_DQ & SD_CB read input hold time From SD_DQS (rising or falling)

(0.035 + TDQS_SD) * TC2_SD + 0.38

– ns (11)

TSUFBI_SDSD_CLKFBI low setup to last SD_DQS falling edge prior to SD_DQS tri-state

(0.05 + TFBI_SD - TDQS_SD) *

TC2_SD + 0.52– ns (11)

TSUFBI2_SDSD_CLKFBI high setup to first SD_DQS rising edge after SD_DQS driven by SDRAM

(0.05 + TFBI_SD - TDQS_SD) * TC2_SD + 1.4

– ns (11)

250838B–HIREL–04/07


PC109 [Preliminary]

Notes: 1. ADV_DELAY is set in SD_ADV_CLK_DELAY[DLL_OFFSET].

2. DQS_DELAY is set in SD_DQS0..17]_DELAY[DLL_OFFSET] for each of the 18 SD_DQS inputs.

3. FBI_DELAY is set in SD_FB_DELAY[DLL_OFFSET].

4. Timing guaranteed with respect to any loaded SD_CLK.

5. Negative numbers mean that SD_DQS transitions before SD_CLK.

6. Falling edges are referenced by TDQSS_SD and TDQH_SD.

7. Measured using a 5 pF load to the 50% point of a rising edge.

8. Measured using a 5 pF load with a 40Ω pull-up to the 10% point of a rising edge.

9. This parameter only applies to write operations where the PC109 is driving SD_DQS, SD_DQ.

10. Negative setup means that SD_DQ must be valid after the transition of SD_DQS.

11. This parameter only applies to read operations where the SDRAM is driving SD_DQS and SD_DQ.

12. CASL is the CAS Latency of the SDRAM and must be programmed in SD_TIMING[CL].

13. REG is either 0 (for unbuffered DIMMs) or 1 (for registered DIMMs) and must be programmed in SD_TIMING[DIMM_TYPE].

TIHFBI_SDSD_CLKFBI low hold from SD_DQS driven on SDRAM read operation

(0.05 - TFBI_SD + TDQS_SD ) * TC2_SD

- 0.11– ns

TIHFBI2_SD

SD_CLKFBI high hold from second last SD_DQS falling edge before SD_DQS tri-state on SDRAM read operation

(0.05 - TFBI_SD + TDQS_SD) *

TC2_SD + 0.12– ns (4)(11)

TCLK2DQS_SD

Round trip delay from rising edge of SD_CLK which is centred on a READ command at the PC109 to first related falling edge of SD_DQS at the PC109

–(3.18 + CASLl + REGm

- TADV_SD - TDQS_SD) * TC2_SD - 8.8

ns (4)

Table 9-11. AC Specifications for Memory Controller (Continued)


260838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-5. Memory Controller Timing(1)

Note: 1. SD Address and Command includes SD_A, SD_BA, SD_RASn, SD_CASn, and SD_WEn. SD Control includes SD_CSn, SD_CKE, and SD_ODT.

Figure 9-6. Memory Controller Timing for TCLK2DQS_SD

TIH_SDTSU_SD

TIHFBI2_SD TSUFBI_SDTSUFBI2_SD

TIHFBI_SD

TTDQL_SDT

TOVDQ_SD (max)TOVDQ_SD (min)

TDQH_SD

TT

T

TDQSH_SD(min)TDQSH_SD (max)

TTDQSL_SD(max)

TDQSL_SD (min)TDSS_SD (min)TDSS_SD(max)

TDQSS_SD(max)TDQSS_SD(min)

TOVFBOF_SD (max)

TOVFBOF_SD (min)TOVFBOR_SD (max)

TOVFBOR_SD (min)

TOVCTRL_SD (max)TOVCTRL_SD (min)

TOVCMD_SD (max)TOVCMD_SD (min)

TCSKW_SDTCSKW_SD

TCL2_SDT

TTCH2_SDTC2_SD

T

T

TCL_SDT

TC_SD

TCH_SD

SD_SYSCLK

SD_CLK_P[x]

SD_CLK_P[y]

SD address & command

SD Control

SD_CLKFBO

SD_DQS_P (output)

SD_DQ (output)

SD_DQS_P (input)

SD_CLKFBI

SD_DQ (input)

Tclk2dqs_sd

READ NOP NOP NOP NOP NOP

SD_CLK @ PC109

SD_A

Command

SD_DQS @ PC109

270838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-7. Memory Controller Overshoot/Undershoot

Table 9-12. AC Overshoot/Undershoot Specification for Memory Controller Address and Control Pins


– Maximum allowable peak overshoot above VDD_SD +0.9 V –


– Maximum area under the overshoot signal above VDD_SD 0.75 V-ns –


VDD_SD

VSS



280838B–HIREL–04/07


PC109 [Preliminary]

9.4.4 PCI/X Interface AC Signal Timing

Notes: 1. The clock frequency may not change beyond the spread-spectrum limits except while device reset is asserted.

2. The minimum clock period must not be violated for any single clock cycle.

3. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform.

Table 9-13. PCI/X Clock (PCI_CLK) Specification

Symbol Parameter

PCI-X PCI

Units NotesMin Max Min Max

TC_PCI PCI Clock Cycle Time 7.5 20 15 40 ns (1)(2)

TF_PCI PCI Clock Frequency 50 133 25 66 MHz (1)

TCH_PCI PCI Clock High Time 3 – 6 – ns –

TCL_PCI PCI Clock Low Time 3 – 6 – ns –

TSR_PCI PCI Clock Slew Rate 1 6 1 6 V/ns (3)

Spread Spectrum Requirements

fMOD_PCI PCI_CLK Clock modulation frequency 30 33 30 33 kHz –

fSPREAD_PCI PCI_CLK Clock frequency spread -1 0 -1 0 % –

Table 9-14. AC Specifications for PCI/X Interface

Symbol Parameter

PCI-X 133 PCI-X 66 PCI 66 PCI 33

Units NotesMin Max Min Max Min Max Min Max

TOV1Clock to Output Valid Delay for bused signals

0.7 3.8 0.7 3.8 1 6 2 11 ns (1)(2)(3)

TOV2

Clock to Output Valid Delay for point to point signals

0.7 3.8 0.7 3.8 2 6 2 12 ns (1)(2)(3)

TOFClock to Output Float Delay

– 7 – 7 – 14 – 28 ns (1)(4)

TIS1Input Setup to clock for bused signals

1.2 – 1.7 – 3 – 7 – ns (3)(5)(6)

TIS2Input Setup to clock for point to point signals

1.2 – 1.7 – 5 – 10,1 2 – ns (3)(4)

TIH1Input Hold time from clock

0.5 – 0.5 – 0 – 0 – ns (4)

TRST Reset Active Time 1 – 1 – 1 – 1 – ms

TRFReset Active to output float delay

– 40 – 40 – 40 – 40 ns (7)(8)

TIS3P[x]_REQ64_B to Reset setup time

10 – 10 – 10 – 10 – clocks –

290838B–HIREL–04/07


PC109 [Preliminary]

Notes: 1. See the timing measurement conditions in Figure 9-18 on page 40.

2. See Figure 9-20 on page 40, Figure 9-21 on page 40 and Figure 9-22 on page 41.

3. Setup time for point-to-point signals applies to P[x]_REQ_B and P[x]_GNT_B only. All other signals are bused.

4. For purposes of Active/Float timing measurements, the HI-Z or Off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.

5. See the timing measurement conditions in Figure 9-17 on page 39.

6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.

7. OCN_RST_B is asserted and de-asserted asynchronously with respect to OCN_CLK (internal Switch Fabric clock signal).

8. All output drivers must be floated when OCN_RST_B is active.

9.4.5 Ethernet Controller AC Signal Timing

Table 9-16 lists the AC specifications for the G/MII and TBI interface of the Ethernet Controller.

TIH2Reset to P[x]_REQ64_B hold time

0 50 0 50 0 50 0 50 ns –

TIS4

PCI-X initialization pattern to Reset setup time

10 – 10 – – – – – clocks –

TIH3

Reset to PCI-X initialization pattern hold time

0 50 0 50 – – – – ns –

Table 9-15. AC Specifications for MII Management Interface

Symbol Parameter Condition Min Max Units

TPERMDC Period of MDC MII Management Clock Output – 60 – ns

TPDMDIO Propagation delay of MDIO output from rising edge of MDC – 10TPERMDC

(max) -10ns

TSUMDIO Input Setup Time of MDIO to rising edge of MDC – 4 – ns

THMDIO Input Hold Time of MDIO after rising edge of MDC – 0 – ns

Table 9-14. AC Specifications for PCI/X Interface (Continued)

Symbol Parameter

PCI-X 133 PCI-X 66 PCI 66 PCI 33

Units NotesMin Max Min Max Min Max Min Max

Table 9-16. Specifications for G/MII and TBI Interface(1)


TCTXCLK Period of E[x]_TXCLK inputs10Mb/s mode 399.98 400.02 ns

100Mb/s mode 39.998 40.002 ns

TCGTXCLK Period of GTX_CLK input 1000Mb/s mode 7.9992 8.0008 ns

TPWTXCLK Pulsewidth of E[x]_TXCLK inputs10Mb/s mode 180 220 ns

100Mb/s mode 18 22 ns

TPWGTXCLK Pulsewidth of GTX_CLK input 1000Mb/s mode 3.2 4.8 ns

300838B–HIREL–04/07


PC109 [Preliminary]

Note: 1. All parameters are valid for both Ethernet Controller ports; that is, E[x] = E0 or E1.

Figure 9-8. Ethernet Controller Overshoot/Undershoot

TCRXCLK Period of E[x]_RXCLK inputs

10Mb/s mode 399.98 400.02 ns

100Mb/s mode 39.998 40.002 ns

1000Mb/s mode 7.9992 8.0008 ns

TCPMARCLK Period of PMA_RX_CLK[x] input 1000Mb/s mode 15.9984 16.0016 ns

TPWRXCLK Pulsewidth of E[x]_RXCLK input



1000Mb/s mode 3.2 4.8 ns

TPWPMARCLK Pulsewidth of PMA_RX_CLK[x] input 1000Mb/s mode 6.4 9.6 ns

TSKPMASkew between PMA_RX_CLK[x] inputs 1000Mb/s mode

7.5 8.5 ns TSKPMA

TPDTXPropagation delay of E[x]_TCG after rising edge of E[x]_TXCLK

10Mb/s or 100Mb/s mode

– 25 ns

TPDGTXPropagation delay of E[x]_TXG after rising edge of GTX_CLK

1000Mb/s mode – 5 ns

TSURXSetup time for E[x]_RCG to rising edge of E[x]_RXCLK

10,100,1000Mb/s modes

2 – ns

THRXHold time for E[x]_RCG to rising edge of E[x]_RXCLK

G/MII modes 0 – ns

TSURXTBI Setup time for E[x]_RCG to PMA_RX_CLK[x] TBI mode 2.5 – ns

THRXTBI Hold time for E[x]_RCG after PMA_RX_CLK[x] TBI mode 0.5 – ns

Table 9-16. Specifications for G/MII and TBI Interface(1) (Continued)


VDD_PC

VSS



310838B–HIREL–04/07


PC109 [Preliminary]

9.4.6 UART Interface AC Signal Timing

Figure 9-9. UART Interface Overshoot/Undershoot

Table 9-17. AC Overshoot/Undershoot Specification for Ethernet Controller


– Maximum allowable peak overshoot above VDD_PC +0.5 V –


– Maximum area under the overshoot signal above VDD_PC 0.75 V-ns –


Table 9-18. AC Overshoot/Undershoot Specification for UART Interface






VDD_PC

VSS



320838B–HIREL–04/07


PC109 [Preliminary]

9.4.7 HLP Interface AC Signal Timing

Notes: 1. Timing may be programmed to multiple integer OCN_CLK clock cycles (internal Switch Fabric clock). Timing specified here assumes the least number of integer clock cycles has been programmed.

2. Minimum allowable number of integer clock cycles is 1.

3. Minimum allowable number of integer clock cycles is 2.

Table 9-19. AC Specifications for HLP Interface


Signal-to-Signal Timing

TSADLE Setup time of HLP_AD (address) to HLP_LE assertion -6 – ns (1)

THADLE Hold time of HLP_AD (address) from HLP_LE assertion 7.2 – ns (1)(2)

TSADCS Setup time of HLP_AD (address) to HLP_CSn assertion -7.5 – ns (1)

TDACSOE Delay time from HLP_CSn assertion to HLP_OEn assertion -1 2.5 ns (1)

TDACSWE Delay time from HLP_CSn assertion to HLP_WEn assertion 0 2.0 ns (1)

THWDCS Hold time from HLP_CSn de-assertion to data release for write data 0.5 – ns –

TDDCSWEDelay time from HLP_CSn de-assertion to HLP_WEn de-assertion

in handshaking mode-2.0 0 ns (1)

TDHWECSDelay time from HLP_WEn de-assertion to HLP_CSn de-assertion

in non-handshaking mode0 2 ns (1)

TDDCSOE Delay time from HLP_CSn de-assertion to HLP_OEn de-assertion -1 2.5 ns –

TVADRDDelay time from HLP_AD (address) valid to read data valid in latchmode

– 2.1 ns (1)(3)

TWVRD Data Valid window 3.7 – ns –

TVADWD Write data valid after address hold in latch mode 4.5 – ns –

TVCSWD Write Data Valid after HLP_CSn assertion in non-latch mode 7.5 – ns –

330838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-10. Address Window Signal Timing Diagram

Figure 9-11. Data Window Signal Timing Diagram

HLP_LE

HLP_AD

HLP_CS_B

HLP_OE_B

HLP_RW

HLP_AD

ADDRESS VALID WRITE DATA VALID

WRITE DATA VALID

tHADLE

tVADWD

tVCSWD

tDACSOE

tDACSWE

tSADCS

tSADLE

HLP_AD

HLP_CS_B

HLP_OE_B

HLP_RW

HLP_AD

ADDRESS VALID

WRITE DATA VALID

tHWDCS

tDDCSWEtDHWECS

tDDCSOE

340838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-12. Address to Read Data Timing Diagram

Figure 9-13. HLP Interface Overshoot/Undershoot

Table 9-20. AC Overshoot/Undershoot Specification for HLP Interface






ADDRESS VALID DATA VALID

tVADRD

HLP_AD

tWVRD

VDD_PC

VSS



350838B–HIREL–04/07


PC109 [Preliminary]

9.4.8 I2C Interface AC Signal TimingThe following table lists the AC specifications for the I2C Interface. The specifications are valid for boththe I2C Interface and the I2C Interface contained within the Memory Controller.

Notes: 1. See Figure 9-14 on page 36.

2. After this period, the first clock pulse is generated.

3. Not tested.

Figure 9-14. I2C Interface Signal Timings

Table 9-21. AC Specifications for I2C Interface


FSCL SD_I2C_CLK/I2C_SCLK Clock Frequency 0 100 kHz –

TBUF Bus Free Time Between STOP and START Condition 4.7 – µs (1)

THDSTA Hold Time (repeated) START condition 4 – µs (1)(2)

TLOW SD_I2C_CLK/I2C_SCLK Clock Low Time 4.7 – µs (1)(3)

THIGH SD_I2C_CLK/I2C_SCLK Clock High Time 4 – µs (1)(3)

TSUSTA Setup Time for a Repeated START condition 4.7 – µs (1)

THDDAT Data Hold Time 0 3.45 µs (1)

TSUDAT Data Setup Time 250 – ns (1)

TSR SD_I2C_CLK, SD_I2C_SD, I2C_SCLK, and I2C_SD Rise Time – 1000 ns (1)

TSF SD_I2C_CLK, SD_I2C_SD, I2C_SCLK, and I2C_SD Fall Time – 300 ns (1)

TSUSTO Setup Time for STOP Condition 4 – µs (1)

Table 9-22. AC Overshoot/Undershoot Specification for I2C Interface






SCL

TBUF TLOW

THDSTATHIGH

TSR

THDDAA

TSF

TSUDAT TSUSTA

THDSTA TSP

Stop

TSUSTO

SDA

Stop Start RepeatedStart

360838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-15. I2C Interface Overshoot/Undershoot

9.4.9 Interrupt Controller Signal TimingThe following table lists the AC specifications for the Interrupt Controller.

Note: 1. INT and GPIO inputs provide only 5 mV hysteresis and a single Switch Fabric clock period of de-bounce.

VDD_PC

VSS



Table 9-23. AC Specifications for Interrupt Controller


TEDGE INT rise/fall time – 0.5Switch Fabric clock period

(1)

Table 9-24. AC Overshoot/Undershoot Specification for Interrupt Controller






370838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-16. Interrupt Controller Overshoot/Undershoot

9.4.10 Boundary Scan Test Signal TimingThe following table lists the test signal timings for the PC109.

Notes: 1. Not tested.

2. See Figure 9-17 on page 39.

3. Outputs precharged to VDD33.

4. See Figure 9-18 on page 40.

5. A float condition occurs when the output current becomes less than ILO. Float delay is not tested (see Figure 9-18 on page 40).

VDD_PC

VSS



Table 9-25. Boundary Scan Test Signal Timings


TBSF JT_TCK Frequency 0 10 MHz –

TBSCH JT_TCK High Time 50 – nsMeasured at 1.5V(1)

TBSCL JT_TCK Low Time 50 – nsMeasured at 1.5V(1)

TBSCR JT_TCK Rise Time – 25 ns0.8V to 2.0V(1)

TBSCF JT_TCK Fall Time – 25 ns2.0V to 0.8V(1)

TSIS1 Input Setup to JT_TCK 10 – ns (2)

TBSIH1 Input Hold from JT_TCK 10 – ns (2)

TBSOV1 JT_TDO Output Valid Delay from falling edge of JT_TCK – 15 ns (3)(4)

TOF1 JT_TDO Output Float Delay from falling edge of JT_TCK – 15 ns (3)(5)

380838B–HIREL–04/07


PC109 [Preliminary]

9.4.11 Reset TimingThe following table lists the reset signal timings for the PC109.

9.5 AC Timing WaveformsThis section contains AC timing waveforms for the PC109.

Figure 9-17. Input Timing Measurement Waveforms

Table 9-26. Reset Timings


TPORPower supplies in recommended operating rage to de-assertion of device reset

100 – ms

Device reset gates PCI_RSTn and the PCI spec requires reset to

remain asserted for 100ms after power supplies are valid

TACTIVE Reset active time 1 – ms –

–CG_REF clock stable to de-assertion of

device reset5 – µs –

–Power-up strapping setup to assertion of

device reset-10 –

CG_REF clock cycles

Power-up straps must not be actively driven before outputs tri-state.

–Power-up strapping setup to de-assertion of

device reset20 –

CG_REF clock cycles

Independent of Clock Generator being bypassed or active.

–Power-up strapping hold from de-assertion

of device reset0 – ns –

THIZ Assertion of reset to outputs tri-state - 10 ns –

–Power hold up after assertion of RESET

during power failure200 400 – Clocks

200 clocks are required for SDRAMs of 2Gbit (or less dense) 400 clocks

required for 4Gbit SDRAMs.

CLK

INPUT Valid VtestVtest

Vtest

TIS

TIH

Vtl

Vth

Vth

Vtl

Vmax

390838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-18. Output Timing Measurement Waveforms

Figure 9-19. AC Test Load for all Signals except PCI/X, DDR2 SDRAM, and Processor Interface

Figure 9-20. PCI/X TOV (max) Rising Edge AC Test Load

Figure 9-21. PCI/X TOV (max) Falling Edge AC Test Load

Vtest

Vtrise

Vtfall

TOV

TOV

TOF

Vtl

Vth

OutputFloat

OutputDelay Rise

OutputDelay Fall

CLK

Output

50 pF

TestPoint

25Ω

Output

10 pF

TestPoint

25Ω

Output

10 pF

VCC33

TestPoint

400838B–HIREL–04/07


PC109 [Preliminary]

Figure 9-22. PCI/X TOV (min) AC Test Load

Figure 9-23. Processor AC Test Load

Figure 9-24. DDR2 SDRAM AC Test Load

Output

10 pF

1 KΩ

1 KΩ

VCC33

TestPoint

2VDD_PBOutputZ0 = 50Ω R = 50Ω

Output VttZ0 = 50Ω R = 50Ω

410838B–HIREL–04/07


PC109 [Preliminary]

9.6 PBGA Mechanical DiagramThe following figure shows the PC109 mechanical diagram

Figure 9-25. PBGA Mechanical Diagram

Note: Capacitor pads for 0306 type capacitors are used on the package but may not have capacitors attached. Please check the actual device and use caution when fitting pick and place devices, or applying additional thermal management products.

PIN #1 CORNER

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 312 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

A

C

E

G

J

L

N

R

U

W

AA

AC

AE

AG

AJ

AL

B

D

F

H

K

M

P

T

V

Y

AB

AD

AF

AH

AK

AM

33.00

32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 231 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

A

C

E

G

J

L

N

R

U

W

AA

AC

AE

AG

AJ

AL

B

D

F

H

K

M

P

T

V

Y

AB

AD

AF

AH

AK

AM

0.60

± 0

.5 M

M

1.6

± 0.

15 M

M

0.81 ± 0.15 MM

0.13~0.38 MM

TYPE 030

6

0.813 Ref1.20 ± 0.15

SE

AT

ING

PLA

NE

-C-

0.25 C

DETAIL : D

0.20C

33.0

0

33.0

0 ±

0.2

0

31.0

0

1.00

-B-

-A-

0.20(4X)

33.00 ± 0.20

31.001.00

420838B–HIREL–04/07


PC109 [Preliminary]

9.7 HITCE Mechanical Diagram (TBC)

10. Board Layout GuidelinesThe PC109 provides a direct connection between a host processor(s) and multiple high-speed periph-eral devices. When implementing a high-speed interconnect system, however, the board designer isconfronted with various challenges regarding layout and performance.

This chapter provides layout guidelines for the PC109 interfaces that connect with high-speed devices. Itshould be used during the schematic capture and layout phases of a board design process.

The following topics are discussed:

• Section 10.1 ”Printed Circuit Board Construction” on page 43

• Section 10.2 ”Device Ballmap” on page 44

• Section 10.3 ”Clocks and PLLs” on page 46

• Section 10.4 ”Processor Bus Layout” on page 47

• Section 10.5 ”Memory Controller” on page 54

• Section 10.6 ”PCI-X Interface” on page 97

• Section 10.7 ”Ethernet Controller” on page 98

• Section 10.8 ”Host Local Port” on page 100

• Section 10.9 ”Power Planes” on page 101

Dimensions in this chapter are given in British imperial units. Use this conversion ratio for Metric units:

• 1 inch = 25.4 mm

• 1 mil = 0.0254 mm

10.1 Printed Circuit Board ConstructionA PCB stackup is described in Figure 10-1 on page 44 (this PCB is used as a reference throughout thisdocument). This PCB construction provides proper impedance control for traces on every layer. It iscomposed of four routing layers and four ground or power planes. It is important to build a PCB that pro-vides controlled impedance layers. Trace impedance is a function of trace geometry and proximity to areference plane (power or ground). This example stack-up is targeted for 60Ω stripline and microstrips.

There are other parameters to consider in order to build a controlled impedance PCB, such as layerthickness, dielectric permittivity, and finished trace width. These parameters, however, are defined bythe PCB manufacturer.

430838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-1. PCB Stackup Example

10.1.1 Transmission Line Terms

• Microstrips – Traces that are adjacent to a continuous reference plane. In the PCB stackup example, the microstrips are on the primary and secondary layers.

• Striplines – Traces routed in inner layers and have two reference planes. In the PCB stack-up example, striplines are on layers 3 and 6.

It is important that one reference plane, power or ground, be continuous under the whole trace length. Areference plane break under a trace will cause impedance discontinuity and degradation of signalquality.

10.2 Device BallmapFigure 10-2 on page 45 shows the orientation of the PC109’s major interfaces. For example, the MemoryController is centered across the north side of the device, while the Processor Interface is located on theright side. The package is a BGA matrix of 32x32 balls on a 1mm grid. The ball grid is fully populatedwith no signals deeper than 8 rows. All balls deeper than eight rows are power and ground.

L01

L02

L03

L04

L05

L06

L07

L08

Layers Cross Section Diagram Type DefinitionLayer Layer Stripline Edge coupled diff

Trace Width Impedance Trace Width Impedancemask

plating.5oz foilprepreg

.5/1 core

.5/1 core

.5/1 core

prepreg

prepreg

prepreg.5 oz foilplatingmask

Secondary

sig

sig

gnd

gnd

Power

Primary

Power

5.0

5.0

4.0

4.0

5.0

5.0

4.0

4.0

60.0 Ω 100.0 Ω

100.0 Ω

100.0 Ω

100.0 Ω

60.0 Ω

60.0 Ω

60.0 Ω

440838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-2. PC109 Ballmap – Top View

For more information about the PC109 pinlist and ballmap, see the Tundra website.

The PC109 can be broken out on four layers using the pad and via dimensions in Figure 10-3 and Figure10-4. The first and second row of the BGA can be escaped on the primary layer. Each internal layer canbe used to escape two other rows.

Figure 10-3. PC109 BGA Pad and Breakout Via Dimension

A1 A32

Clock Gen

SDRAM

HLP

Misc.

Gige

PCI

Processor

PE

.4826 (.0190) - BGA VIA

DIMENSIONS IN MM (INCHES)

.6350 (.250) - BGA PAD SOLDER

.5080 (.0200) - BGA PAD

TRACE WIDTH .2032 (.DOB)

TSI108 BGA BALL BREAKOUT

450838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-4. PC109 Breakout Via Structure

10.3 Clocks and PLLsThe PC109 contains versatile built-in PLLs and clock distribution buffers. Proper use of the PC109 clockoutputs eliminates the need for external clock distribution buffers on the DDR2 devices, the Processorbus, and the PCI/X bus. These clock outputs can be sourced from one single 33.3MHz oscillator, or theycan be sourced from separate clock references. Clock source selection is system dependant. Crystaloscillators or PLL-based programmable clock devices can be used as clock source. Choose a devicethat matches the parameter in Table 10-1.

10.3.1 Supply Noise Causes JitterExcessive clock source jitter may prevent the correct operation of PC109’s internal PLLs. Power supplynoise may affect clock source device output jitter. For this reason, proper power supply filtering is recom-mended. An L-C filter should be connected to the VCC pin of the oscillators or PLL devices. Follow thePLL vendor recommendation for power supply filtering, or implement a circuit similar to the one in Figure10-5.

Figure 10-5. Oscillator Filter Circuit

VIA 19RD 10 STRUCTURE

19 MILS

PRIMARY SIDE

SECONDARY SIDE

10 MILS

ANTIPAD 31 MILS

PCB

Table 10-1. PC109 Clock Sources

Clock SourceMax pk-pk Jitter

(ps) Vin (CMOS) Max Frequency Min. Edge Rate

SDsysclk 100 1.8V 200MHz 1V/ns

PBsysclk 100 1.8V 200MHz 1V/ns

CGref 600 1.8V 33.33MHz 1V/ns

Clock to PC109

Pwr

Vcc

2.2Ω

1 µH0.047 µF

RsOscillatoror

PLL

460838B–HIREL–04/07


PC109 [Preliminary]

10.3.2 Source Clock Lines TerminationTo reduce reflection and improve signal quality, we recommend for you to place a source terminationresistor at the clock source. The clock nets from the clock source and the PC109 should have seriesresistors (Rs). The value of the Rs should be equal to the PCB impedance minus the clock source outputimpedance. Given a PCB impedance of 60Ω, Rs is usually in the range of 10 ~ 30Ω.

10.3.3 Filtering PLL SuppliesBoard designers have to provide a clean voltage supply to the PC109 PLLs. As a result, use a filter cir-cuit on the these PLLs:

• VDD_PLL_SD (1.2V)

• VDD_PLL_PB (1.2V)

• VDD_PLL_PCI (3.3V)

• VDD_PLL_CG (1.2V)

Aim for a maximum of 120 mV peak-to-peak noise if VDD is set exactly at 1.2V. The following supply filtercircuit is recommended for PLL supply filtering. Note that Ferrite bead F2 in Figure 10-6 is optional for1.2V. PLLs and not required for the 3.3V PLL.

Figure 10-6. VDD_PLL Filtering

C1: 0.1 µFC2: 0.01 µF

F1 and F2: 50Ω ferrite bead similar to Murata P/N: BLM31PG500SN or Panasonic P/N:

EXC-CL4532U1

Clocking during Reset

Input clocks must be stable and free running when the PC109 is taken out of reset. If external PLLs areused to generate source clocks, the board reset circuit should monitor the lock status of the PLLs beforede-asserting PC109 reset.

10.4 Processor Bus Layout

10.4.1 Topology DescriptionSignal topology describing the connection between the PC109 and the its end points are broken down inTransmission Line sections (TL):

• Breakout TL – The trace between the PC109 pad and the breakout via, or to the outside limit of the package if the signal is broken out on layer 1.

• Lead-in TL – The trace from the Breakout TL to the processor or to a termination element.

• Proc TL – The trace from the PC109 breakout or a termination element to the processor.

1.2V

VDD_PLL

PC109

VSS_PLL

C2C1F1

F2

470838B–HIREL–04/07


PC109 [Preliminary]

10.4.2 Signal GroupsThree signal groups must be considered on the Processor Interface:

• Clock signals

• Unidirectional point-to-point signals

• Common 60X/MPX signals

10.4.2.1 Clock SignalsClocks to the microprocessors can be sourced from the PC109. The built-in Clock Generator providesthree clock outputs. If the PC109 Clock Generator is used, one clock must be fed back to thePB_SYSCLK input of the PC109.

10.4.2.2 Unidirectional Point-to-point SignalsThe unidirectional signals listed in Table 10-3 on page 48 are part of the 60X/MPX bus. Although theyare part of this bus, they form a separate group from an electrical perspective. If the 60X/MPX interfaceis connected to two processors, the PC109 output driver’s impedance is adjusted accordingly. The point-to-point signals’ output impedance is also adjusted as if they had two loads. In the dual-processor config-uration, point-to-point signals require an impedance matching series element. When connecting thePC109 to a single processor, their routing topology is the same as bi-directional signals.

10.4.2.3 Common 60X/MPX SignalsThese signals do not require any external termination.

Table 10-2. Clock Signals

Signal Name Signal Name Source

CG_PB_CLKO 3 PC109

Table 10-3. Point-to-point Unidirectional Signals

Signal Name Number of Pins Source

PB_BGn 2 PC109

PB_BRn 2 uP

PB_DBGn 2 PC109

PB_DRDYn 2 uP

PB_HITn 2 uP

PB_INTn 4 PC109

PB_QREQn 2 uP

PB_QACKn 2 PC109

Table 10-4. Bi-directional 60X/MPX Bus Signals

Signal Name Number of Pins

PB_A 36

PB_AACKn 1

PB_AP 5

PB_ARTRYn 1

480838B–HIREL–04/07


PC109 [Preliminary]

10.4.3 Clock Signals TopologyClocks are routed point to point with a separate clock signal per processor. The clock input for the Pro-cessor Interface (PB_SYSCLK) should also be routed to match the length of the traces to the processor.The value of Rs is indicated in Table 10-7 on page 50.

Figure 10-7. Processor Bus Clock (PB_CLK) Distribution

Figure 10-8. Clock Signal Topology

PB_D 64

PB_DP 8

PB_DTI 3

PB_GBLn 1

PB_TAn 1

PB_TEAn 1

PB_TBSTn 1

PB_TSn 1

PB_TSIZ 3

PB_TT 5

Table 10-4. Bi-directional 60X/MPX Bus Signals (Continued)

Signal Name Number of Pins

Clock

Generator

Rs

Rs To processor

To processor (optional)Rs

PB_SYSCLK

CG_PB_CLK1

CG_PB_CLK0

CG_PB_CLK2

Controller Processor

Rs

A: Breakout(TL0)

B: Proc(TL1)

490838B–HIREL–04/07


PC109 [Preliminary]

Note: 1. The total trace length must be within the minimum and maximum lengths regardless of the sum of the individual trace subsections.


Table 10-5. Trace Parameters for Clock Signals in Single-processor Configuration

Layers Traces Description

Length (in.)

LayerType

TraceWidth (mil)

MinimumSpacing (mil) Trace

Impedance(Ω)Min Max

WithinGroup

OtherGroups

3,6TL0 Breakout

0 0.5 Stripline 4 4 460

1,8 Microstrip 5 5 5

3,6TL1 Proc

2.5 3.0 Stripline 410 20 60

1,8 2.75 3.3 Microstrip 5

Total(1) (A+B)2.5 3.0 Stripline

Via count = 12.75 3.3 Microstrip

Table 10-6. Trace Parameters for Clock Signals in Dual-processor Configuration


Length (in.)

LayerType

TraceWidth (mil)



WithinGroup

OtherGroups

3,6TL0 Breakout

0 0.5 Stripline 4 4 460


3,6TL1 Proc

3.5 5.0 Stripline 410 20 60

1,8 Microstrip 5

Total(1) (A+B)3.5 5.0 Stripline

Via count = 1Microstrip

Table 10-7. Routing Guidelines for Processor Clocks

Parameter Routing Guideline

Reference Plane Layers All clocks should be referenced to continuous ground planes

Breakout Breakout should be less than 0.5in.

Group SpacingClearance between traces should be 20 mils for all clocks except for the breakout region.

Length MatchingTotal trace lengths should be within the range specified for all other signals but should be matched for all clocks.

Vias Maximum of 1 via for clock routes

Layer Types All clocks should be routed on the same layer.

Rs 33Ω based on a 60Ω PCB

500838B–HIREL–04/07


PC109 [Preliminary]

10.4.4 Single Processor ConfigurationThe processor should be placed on the Processor Interface side (60X side) of the PC109. The maximumdistance between the PC109 and the processor is dictated by the maximum trace length in Table 10-8on page 51.

Figure 10-9. Single Processor Connection Diagram

Figure 10-10. Single Processor 60X Bus and Point-to-point Trace Topology

Procssor


ProcessorInterface

Processor

point-to-point signals

60 X bus

Controller Processor

A: Breakout(TL0)

B: Lead-in(TL1)

Table 10-8. Trace Parameters for 60X Bus and Point-to-point Signals in Single Processor Configuration


Length (in.)

LayerType

TraceWidth (mil)



WithinGroup

OtherGroups

3,6TL0 Breakout 0 0.5

Stripline 4 4 460


3,6TL1 Lead In

2.5 3.0 Stripline 410 20 60

1,8 2.75 3.3 Microstrip 5

Total(1) (A+B) 2.5 3.0 Stripline

Via count = 32.75 3.3 Microstrip

510838B–HIREL–04/07


PC109 [Preliminary]

10.4.5 Dual-processor Y ConfigurationThe two processors sit side by side on the 60X side of the PC109. The maximum distance between thePC109 and the processors is dictated by the maximum trace length in Table 10-10 on page 53.

Depending on the processor’s pin-out, it may be difficult to route the processor bus signals on four track-ing layers. Tundra does not have a reference layout for dual-processor configuration on four trackinglayers.

Figure 10-11. Y topology Connection

Table 10-9. Routing Guidelines for 60X Bus Signals Single Processor Configuration


Reference Plane Layers All signals should be referenced to continuous ground planes

BreakoutBreakout should be less than 0.5in.

Breakout can be on stripline or microstrip

Group Spacing10 mil within group

20 mil to other groups

Length Matching Total trace length should match within 0.5in

ViasMinimize vias where possible. No more than 3 vias should be used in any path from controller to processor.

Layer Types Microstrip or stripline can be used for routing.

PC109

60X

Interface 60 X bus

Processor A

Processor B

Rs

Rs

Rs

Rs


520838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-12. Dual-processor 60X Bus Trace Topology in Y Configuration

Figure 10-13. Point-to-point Signal Topology (Source PC109)

Controller

A: Breakout(TL0)

B: Lead in(TL1)

Processor B

Processor A

C1: Proc A(TL2)

C2: Proc B(TL2)

Table 10-10. Trace Parameters for 60X Bus Signals in Dual-processor Y Configuration


Length (in.)

LayerType

TraceWidth

MinimumSpacing (mil)

ImpedanceMin MaxWithinGroup

OtherGroups


Stripline 4 mil 4 mil 4 mil60Ω

1,8 Microstrip 5 mil 5 mil 5 mil

3,6TL1 Lead in 2.0 3.0

Stripline 4 mil10 mil 20 60Ω

1,8 Microstrip 5 mil

3,6TL2

Proc A and Proc B

1.5 2.5Stripline 4 mil

10 mil 20 mil 60Ω1,8 Microstrip 5 mil

Total(A+B+C1 or

C2)3.5 5.0 Via count = 3

Rs

Controller

A: Breakout(TL0)

B: Lead in(TL1)

Processor

530838B–HIREL–04/07


PC109 [Preliminary]

10.5 Memory Controller

10.5.1 DDR2 Memory TopologiesThe Memory Controller can be connected to DDR2 SDRAM implemented either as soldered-downdevices, or as memory modules. Many configurations are possible, but in order to achieve DDR2-400transfer rates, a design should be limited to one of the following topologies:

• One DIMM or SODIMM connector

• Two DIMM or SODIMMs connectors

• Soldered-down devices with a maximum load of 18 components

The Memory Controller has four signal groups: Clocks, Data, Address + command, and Control. Eachsignal group has specific design requirements with regards to termination and PCB routing rules. Theremainder of this section discusses the specific requirements for these three memory topologies.

Table 10-11. Trace Parameters for Point-to-point Signals


Length (in.)

LayerType

TraceWidth

MinimumSpacing

ImpedanceMin MaxWithinGroup

OtherGroups


Stripline 4 mil 4 mil 4 mil60Ω

1,8 Microstrip 5 mil 5 mil 5 mil

3,6TL1 Lead in 3.5 5.0

Stripline 4 mil10 mil 20 mil 60Ω

1,8 Microstrip 5 mil

Total (A+B) 3.5 5.0Stripline

Via count = 3Microstrip

Table 10-12. Routing Guidelines for 60X Bus Signals in Y Configuration


Reference Plane Layers All signals should be referenced to continuous ground planes

BreakoutBreakout should be less than 0.5in.Breakout can be on stripline or microstrip

Group Spacing10 mil within group20 mil to other groups

Total Trace Length 5.0in for Striplines and microstrips

Length Matching

Total trace length should match within 0.5inSection C1 and C2 of TL2 must be matched within 0.5in

Where practical the three trace segments should be of equal length. When this is not possible, TL1 should be longer than TL2.

ViasMinimize vias where possible. No more than 3 vias should be used in any path from controller to processor.

Layer Types Microstrip or stripline can be used for routing.

Rs 10Ω based on a 60Ω PCB.

540838B–HIREL–04/07


PC109 [Preliminary]

10.5.2 SDRAM ClocksPC109 contains six differential SSTL_18 differential clock outputs for DDR2 SDRAM devices. All sixclocks are identical and can be connected in any order.

10.5.2.1 SDRAM Clock Line LoadingAlthough clock signals are terminated on DIMMs, loading of the module connector and the devices alongthe clock line (on the module) cause signal reflection and clock quality deterioration. Placing a compen-sation capacitor (Cclk) between the positive and negative lines of the clock signal, near the input pin ofthe DIMM, slightly reduces the clock edge rate. The clock signal reflection is therefore reduced. Thecapacitor value is determined by board level signal integrity simulation. The capacitor value is providedin Table 10-13 on page 55.

Figure 10-14. Clock Line Termination

10.5.2.2 Compensation Capacitor and Termination Resistor on Differential ClocksPlace the compensation capacitor between the positive and negative branch of the differential clocksignals.

10.5.2.3 Feedback ClockThe PC109 SDRAM clock feedback is used by PC109 to do internal phase alignment between data (DQsignals), strobe signals (DQS) and clocks. Board designers must route this feedback loop to a specificlength. Based on a PCB impedance of 60Ω, the value of Rf is 22Ω. For more information on the feed-back clock, see Board Layout Recommendation in Section 10.5.7.5 on page 68.

Clock

Source

DIMM

Rs CclkSD_CLK_pSD_CLK_n

Rf

Rf

SDCLK_FB_p

SDCLK_FB_n

PC109

Table 10-13. Cclk Value

Signal Name

Cclk (pF)

DIMM SODIMM

SD_CLK 5.1 5.1

550838B–HIREL–04/07


PC109 [Preliminary]

10.5.3 Termination Requirement for Each Memory Configuration

10.5.3.1 Overview of SSTL_18 Termination1

SSTL_18 is the Input/Output technology used to connect with DDR2 devices (see Figure 10-15 on page56). SSTL_18 uses Vref as a reference level to determine a logic level high or low. An input 250 mVabove Vref is a logic high, an input 250 mV below Vref is a logic low. SSTL_18 signals should be termi-nated with an impedance matching resistor (Rtt) to a termination rail (Vtt). The value of Rtt depends onthe trace length between the driver and the receiver. It is typically between 25Ω and 50Ω. Rs is a sourceimpedance matching resistor. The value depends on the driver output impedance. It is typically 20Ω(Note that Rs is not required with PC109 SSTL drivers). Vtt and Vref are both equal to VDD/2 = 900 mV.

Figure 10-15. Generic SSTL Driver and Receiver Circuit

10.5.3.2 DDR2 Stub TerminationA termination resistor (Rtt) is required on each signal listed in the following tables. Follow the layoutguidelines for each configuration.

Vtt

Vre

f

RsSSTL_18

Driver

SSTL inputRtt

Vref Vdd

Table 10-14. Rtt Values

Signal Name

Rtt Value (Ω)

DIMM SODIMMs

A[15:0] 47 47

BA[2:0] 47 47

ODT[3:0] 47 47

CS[3:0] 47 47

WEn, RAS, CAS 47 47

CLKEN[1:0] 47 47

560838B–HIREL–04/07


PC109 [Preliminary]

10.5.3.3 Series ResistorsSeries resistors are not required with the PC109. The SSTL_18 output drivers feature an Off Chip DriverCalibration mechanism which adjusts the drive strength of signals. An additional series resistor (Rcnt) oncontrol signal is recommended to further improve signal quality. Place a series resistor on each signal inTable 10-15

10.5.3.4 Compensation Capacitors on Address and Command LinesAddress and Command signals are less timing critical than the data groups, but they have potentiallymuch heavier loads in the case of unbuffered DIMMs. A compensation capacitor and termination resistorcan help the signal quality by critically damping the ringing caused by the numerous stubs caused by dis-tributing the signals to all of the chips in the array. Place a compensation capacitor on each signal inTable 10-16.

10.5.3.5 On Die TerminationThe On Die Termination (ODT) feature eliminates the need for on-board resistors on data lines.

The ODT lines are used to activate/dis-activate the termination resistors on the SDRAM components.DDR2 systems provide configurable ODT resistor values: 75Ω or 150Ω.

The configuration set in the Extended Mode Register via I2C on SDRAM and in the SDRAMs ExtendedMode Register in the PC109. The ODT setting varies depending on DIMM stuffing option. For ODT con-figuration information, see the Memory Controller section of the PC109 User Manual.

10.5.4 Vtt/Vref Requirements

10.5.4.1 Vtt Regulator RecommendationThe SSTL_18 termination voltage rail (Vtt) must be supplied by a regulator that can source and sink cur-rent, provide good regulation and very little noise. There are several regulators available that are madespecifically for SSTL_18 termination. Tundra’s reference designs use the LP2997MR from NationalSemiconductor.

Table 10-15. Rcnt Values

Signal Name

Rcnt (Ω)

DIMM SODIMM

CS[3:0] 5.1 5.1

ODT[3:0] 5.1 5.1

CLKEN[1:0] 5.1 5.1

Table 10-16. Ccmd Values

Signal Name

Ccmd (pF)

DIMM SODIMM

A[15:0] 18 18

BA[2:0] 18 18

WEn, RAS, CAS 18 18

570838B–HIREL–04/07


PC109 [Preliminary]

The maximum current source and sink requirement for the 32 signals terminated on Vtt is outlined inTable 10-17. The worst case current flow occurs when all signals are at the same level. The best case iswhen 50% of signals are low and 50% are high.

As several address and command lines switch from one level to another at the same time, the switchingcurrent (di/dt) can become important; therefore, the importance of proper Vtt decoupling. A proper termi-nation circuit design should incorporate a local Vtt plane to connect the regulator to termination resistors(for more information, see layout example in Section 10.5.6.1 on page 60). Low ESR capacitors shoulddecouple the Vtt plane. Use design recommendation from the regulator datasheet, or follow theserecommendation:

• Place several bulk decoupling capacitor – ceramic (X7R) capacitors around the Vtt place totaling ~ 300 µF.

• Place bypass capacitors – 0.01µF ceramic (X7R) as close as possible to Rtt.

• Provide at least 1 capacitor for 3 Rtt.

10.5.4.2 Vref RequirementVtt and Vref must match within ±40 mV. There are two options to supply Vref:

• Use the dedicated Vref output from the SSTL_18 termination voltage regulator.

• Divide SD_VDD by 2 with 1% resistors of the same value: ~ 500Ω.

10.5.4.3 Noise RequirementSSTL_18 systems are sensitive to noise. The difference between a logic high and a logic low is as littleas 325 mV (JEDEC spec VIH(ac) – VIL(dc)). If the overall DDR2 system is noisy, timingmargins areaffected. The noise requirements for Vtt and Vref and SD_VDD is 180 mV peak to peak. Vref must beadequately decoupled to avoid reduction of timing margin due to noise.

10.5.4.4 Vref Decoupling

• Place a 0.01 µF decoupling capacitor as close as possible to each PC109 Vref pin.

• Place a 0.01 µF decoupling capacitor as close as possible to each SDRAM device Vref pin.

• Place a 0.1 µF decoupling capacitor close to DIMM connectors.

Table 10-17. Current Draw on Vtt Plane

Max LevelDelta from

Vtt RttCurrent per

SignalMax # of Signals

Total Current

Draw

VOH 1.8V 900 mV 47Ω -19.1mA 32 -612mA

VOL 0V 900 mV 47Ω 19.1mA 32 612mA

580838B–HIREL–04/07


PC109 [Preliminary]

10.5.5 Signal grouping

10.5.5.1 Data SignalsThe data signal group includes the 64-bit data bus and one byte of ECC. Differential strobes are also inthis group. These signals are the most timing critical signals since they operate at the double data rate.The data bytes are source synchronous signals. They are captured at the memory with their strobe sig-nals. The trace length of strobes and the bits in their group must be closely matched to minimize theskew seen at the receiver. In the PC109 ballmap, each byte is grouped together on either rows 1 and 2,or rows 3 and 4. This allows each byte to breakout on the same layer for every bit within a byte. Data sig-nals should breakout in theproper order to route directly to the destination without crossover of any of thecritical signals.

This minimizes skew from vias and layer changes.

10.5.5.2 Clock SignalsProper routing of the DDR2 clock signals is critical. The clock signals must be routed as differential pairs(see Section 10.5.5.3 on page 60). The PC109 SDRAM PLL feedback signal is provided externally tomatch the board propagation delay of the clock and strobe round trip path. This differential pair shouldbe routed on the same layers as the clocks. Clocks are all on row 5 of the PC109 ballmap. They shouldbe broken out on stripline and should travel on the same layer for the entire route. One via is acceptableto connect to the compensation capacitor.

Table 10-18. Data Signal Group

Byte Group Data Bits DQS DQS (DM)

Byte 0 SD_DQ[7:0] SD_DQS_P/N[0] SD_DQS_P/N[9] (DM[0])








Byte 8 SD_CB[7:0] SD_DQS_P/N[8] SD_DQS_P/N[17] (DM[8])

Table 10-19. Clock Signal Group

Pin Names Number of Pins

SD_CLK_P[0:5]SD_CLK_N[0:5]

66

SD_CLKFBI_PSD_CLKFBI_N

11

SD_CLKFBO_P

SD_CLKFBO_N

1

1

590838B–HIREL–04/07


PC109 [Preliminary]

10.5.5.3 Differential Signal Routing Recommendations

• Route the two traces of a differential pair parallel to each other using the minimum spacing recommendation in the Trace topology table provided in this document after they leave the device to ensure minimal reflection.

• Maintain a constant distance between the two traces of a differential pair over their entire length.

• Keep the electrical length between the two traces of a differential pair the same.

• Minimize the number of vias in order to minimize impedance mismatch and inductance.

10.5.5.4 Address/Command SignalsAddress and command signals are less timing critical than the data groups, but they have potentiallymuch heavier loads in the case of unbuffered DIMM or soldered-down devices. These signals requirestub termination resistors and possibly compensation capacitors.

10.5.5.5 Control DDR SignalsThe control groups, like the address/command group is less timing critical than the data group. Theyrequire stub termination resistors and possibly a series termination element.

10.5.6 Dual DIMM connector Layout

10.5.6.1 ConnectionsThe Memory Controller connects directly to the two DIMM connectors without the need for external gluelogic or clock distribution. Clocks, chip selects and ODT signals have point-to-point connections. Theother signals are daisy-chained from one connector to the other. The Termination resistors Rtt are usedto terminate unidirectional Address and Control signals. Rcnt, Ccmd, and Cclk are recommended toimprove signal quality on heavily loaded lines. A description of the discrete components is provided inSection 10.5.3 on page 56.

Table 10-20. Address and Command Signal Group


SD_A[13:0] 14

SD_BA[2:0] 3

SD_CASn 1

SD_RASn 1

SD_WEn 1

Table 10-21. Control Signal Group


SD_CLKEN[1:0] 2

SD_CSn[3:0] 4

SD_ODT[3:0] 4

600838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-16. Dual DIMM Connection Diagram

10.5.6.2 Component PlacementThe two DIMMs should be positioned across the SDRAM side of the PC109, and the two DIMMs shouldbe parallel to each other and as close together as possible. The distance between the PC109 and theDIMMs is dictated by the minimum and maximum trace length in the trace parameter tables in this sec-tion. The distance between the PC109 and the near connector is usually approximately 0.7 inch to1.5 inch. The recommended distance between pin 1 of each connector is 0.45 inch.

DD

R 2

DIM

M

DD

R 2

DIM

M

SD_CS[3:2]

ODT[3:2]

SD_CS[1:0]

ODT[1:0]

CLKEN[1:0]

DQ[63:0]

DM[8:0]

C

A[13:0]

BA[2:0]

RAS

CAS

WE

SDA

SCLK

CD[7:0]

DSQ[8:0]

SD_CLKB[2:0]

SD_CLK[2:0]

Cclk

Cclk

Ccmd

Ccmd

Ccmd

Ccmd

Ccmd

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rcnt

Rcnt

Rcnt

Rcnt

Rcnt

Vtt

Rtt

Rtt

MemoryController

Vref Vref


Vref Vtt

610838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-17. DDR2 DIMM and PC109 Placement

The minimum and maximum trace length are summarized for each group in Table 10-22. Trace parame-ter details are provided in the sub-section for each signal group.

• The Address/Command group and the Control group trace length from the PC109 to the near connector are the shortest, from a minimum of 1 inch to maximum of 2.5 inches.

• The Clock trace length are the longest with a minimum of 3 inches and a maximum of 5 inches from the PC109 to the near connector. The clock traces must be 2 to 3 inches longer than any address trace.

• DQ/DQS traces must be 2.5 inches to 4.5 inches long from the PC109 to the near connector. The DQ/DQS traces must be 0.5 to 1.0 inch shorter than clock traces.

• The feedback loop is composed of two segments. The first segment matches the clock length, while the second segment matches the DQS length.

• Traces from the near connector to far connector should not exceed 0.5 inch.

Table 10-22. Minimum and Maximum Trace Lengths

Group Absolute Minimum Length

Absolute Maximum Length (to Near

Connector)

Relative Minimum and Maximum

Address/Command/Controls

1 inch 2.5 inch

Clocks 3 inches 5 inches2 to 3 inches longer than

address

DQ/DQS 2.5 inches 4.5 inch0.5 to 1 inch shorter than

clocks

Feedback loop Clocks+DQS

All groups from near connector to far

connector0.25 inch 0.5 inch

240 pin DDR2 DIMM Socket0.45"

PC10933 mm

Approximately 0.7 to 1.5"

620838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-18. Trace Length Per Group from PC109 to the Near Connector

10.5.7 Topology DescriptionSignal topology describing the connection between the PC109 and the DIMM modules are broken downin Transmission Line sections (TL):

• Breakout TL – The trace between the PC109 pad and the breakout via, or to the outside limit of the package if the signal is broken out on layer 1.

• Lead-in TL – The trace from the Breakout TL to the first DIMM pad or to a termination element.

• Term to DIMM TL – The trace from an intermediate termination element to a DIMM connector.

• Stub to DIMM TL – The trace from an intermediate stub termination element to a DIMM connector.

• DIMM to DIMM TL – The trace from the first DIMM to the second DIMM.

• Termination Stub TL – The trace from the last DIMM to Rtt

10.5.7.1 Data SignalsFigure 10-19 on page 63 shows the topology used for routing the data lines. After the breakout escapefrom the pin field of the controller the majority of the routing distance should be on inner stripline layers.

This provides for better propagation delay matching by using common layer types. Vias and layerchanges should be minimized where possible. The recommended trace parameters for DQ signals areoutlined in Table 10-23 on page 64, and DQS signals are in Table 10-24 on page 64. The guidelines forthe data group are summarized in Table 10-25 on page 65.

Figure 10-19. Topology for DQ Signals

Address/Command

Clocks

DQ/DQS 2.5 to 4.5 inches

FB_LOOP_OUT = Clocks FB_LOOP_IN = DQS

Data = clocks -0.5 to -1 inch

Clocks = Address + 2 to 3 inches

1 to 2.5 inches max

3 inches to 5 inches

Controller A: Breakout(TL0)

B: Lead In(TL1)

C: DIMM toDIMM(TL2)

DIMM #1 DIMM #2

630838B–HIREL–04/07


PC109 [Preliminary]


10.5.7.2 DQS SignalFigure 10-20 on page 64 shows the topology recommended for routing DQS lines. The topology is simi-lar to Data Signals. Data strobes should be routed as differential lines.

Figure 10-20. Topology for DQS Signals

Table 10-23. Trace Parameters for DQ Signals


Length (in.)

LayerType

TraceWidth (mil)

MinimumSpacing

Impedance (Ω)Min Max

WithinGroup

OtherGroups

1,3,6,8 TL0 Breakout 0 0.5Stripline 4 4 4

60Microstrip 5 5 5

3,6 TL1 Lead In 2 4 Stripline 4 12 20 60

3,6 TL2DIMM to DIMM

0.25 0.5 Stripline 4 12 20 60

Total(1)Controller to

1st DIMM (A+B)

2.5 4.5

Via count = 1Controller to 2nd DIMM (A+B+C)

3.0 5.0


B: Lead In(TL1)

C: DIMM toDIMM(TL2)

DIMM #1 DIMM #2

Table 10-24. Trace Parameters for DQS Signals


Length (in.)

LayerType

TraceWidth (mil)

MinimumSpacing


WithinGroup

OtherGroups


100Microstrip 5 5 5

3,6 TL1 Lead In 2 4 Stripline 4 4 20 100

640838B–HIREL–04/07


PC109 [Preliminary]


10.5.7.3 DQ and DQS Layout ExampleDQ and DQS are routed on internal signal layers. Each byte group stays on one layer for the distancefrom the PC109 to the near connector. The byte groups are routed on the alternate internal layer to gofrom one connector to the other. Tundra recommends to place adjacent byte groups on alternate layers.Figure 10-21 on page 66 shows all 8 byte groups and ECC routed on two internal layers.

3,6 TL2DIMM to DIMM

0.25 0.5 Stripline 4 4 20 100

Total(1)

Controller to 1st DIMM

(A+B) 2.5 4.5


3.0 5.0

Table 10-24. Trace Parameters for DQS Signals (Continued)


Length (in.)

LayerType

TraceWidth (mil)

MinimumSpacing


WithinGroup

OtherGroups

Table 10-25. Routing Guideline for DQ and DQS Signals


Reference Plane Layers All source synchronous signals should be referenced to solid ground planes.

Breakout

5 mil spacing with other signal groups is acceptable for the breakout section.0.5in is the maximum length of breakout traces.

Microstrip and Stripline can be used for breakout.

Each byte group including bits and strobes must breakout on the same layer.

Group Spacing

DQ to DQ within byte: 12 mil minimum

DQ to other groups: 20 mil minimumDQS to other signals: 20 mil minimum

Total Trace LengthTo 1st DIMM: 2.5in to 4.5inTo 2nd DIMM: 3in to 5.0in

Length Matching

DQS Plus to Minus: As close as routing allows (must be less than ±10 mil)DQ to associated DQS: DQS is +25 mil minimum to +50 mil maximum longer than DQ.

DQ to DQ within group: ±25 mil (to DIMM 1 and DIMM 2)DQS to Clock: DQS is -0.5in to -1.0in to CLK

Vias Maximum of 1 Via for any data or strobe signal.Vias must be matched within a strobe pair and byte group.

Layer Types Breakout can be microstrip or stripline. All other Data/Strobe trace segments must be on stripline.

Within a byte group all signals must be on the same layer.

650838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-21. DQ and DQS on Signal Layers 1 and 2

10.5.7.4 Clock SignalsClock Routing Topology

There are six clock pairs to drive the two DIMM connectors. Each unbuffered DIMM requires threeclocks. The compensation capacitor should be placed close to the DIMM connector. No parallel termina-tion is required on the board because the differential clocks are terminated on the DIMMs. Clocks are allon rows 1 and 2 of the ballmap. They should be broken out on microstrip and should travel on the samelayer for the entire route. One via is acceptable to connect to the capacitor.

Byte 7

DQ[56:63]

DQS7 DQS16

Byte 4

DQ[32:39]

DQS4 DQS13

ECC

CB[0:7]

DQS8 DQS17

Byte 2

DQ [16:23]

DQS2 DQS11

Byte 0

DQ[0:7]

DQS0 DQS9

Byte 1

DQ[8:15]

DQS1 DQS10

Byte 3

DQ[23:31]

DQS3 DQS12

Byte 6

DQ[48:55]

DQS6 DQS15

Byte 5

DQ[40:47]

DQS5 DQS14

660838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-22. Trace Topology for Clock Signals


Cclk

ControllerA: Breakout

(TL0)

B1: Lead In1st DIMM

(TL1)

C: Term toDIMM(TL2)

DIMM #1 DIMM #2

B2: Lead In2nd DIMM

(TL1)

Cclk

Table 10-26. Trace Parameters for Clock Signals


Length (in.)

LayerType

TraceWidth (mil)


Differential Impedance

(Ω)Min MaxWithinGroup

OtherGroups

1 TL0 Breakout 0 0.5 Microstrip 5 mil 5 5 100

1 TL1 B1:Lead In 3.0 5.0 Microstrip 5 mil 5 25 100

1 TL1 B2:Lead In 3.5 5.5 Microstrip 5 mil 5 25 100

1 TL2Termination

to DIMM 0 0.5 Microstrip 5 mil 5 25 100

Total(1)

Controller to 1st DIMM (A+B1+C)

3 5

Via count = 0Controller to 2nd DIMM (A+B2+C)

3.5 5.5

Table 10-27. Routing Guidelines for Clock Signal Group


Reference Plane Layers All clocks should be referenced to solid ground planes

Breakout5 mil spacing with other signal groups is acceptable for the breakout section. 0.5in is the maximum length of breakout spacing. Microstrip should be used for breakout.

Group Spacing Minimum 25 mil to all other signals

Total Trace LengthTo 1st DIMM: 3in to 5inTo 2nd DIMM: 3.5in to 5.5in

670838B–HIREL–04/07


PC109 [Preliminary]

10.5.7.5 Clock Feedback LoopA differential clock feedback pair is provided to track the board propagation delay of the clock and stroberound trip path. The first section of this pair should be routed on the same layers as the clock signals.The second section should be routed on the same layer as the strobe signals. The feedback clock looptrace length should be the average of the clock lines plus the average of data strobe lines. The lengthmatching tolerance is defined in Table 10-28. The position of Rf is defined by the length of TL1and TL2.

Figure 10-23. Trace Topology Clock Feedback loop

10.5.7.6 Clock and Feedback Loop Layout ExampleThe clock signals are routed on the top layer. Cclk capacitors are placed close to the connectors on thetop layer. The clock signals are the longest traces, and require serpentine traces to achieve the required

Length Matching

Clock Plus to Minus: As close as routing allows (must be less than ±10 mil) Clock pair to pair: ±25 mil

Clock to DQS: +0.5in to +1in relative to DQS

Clock to Address/Command: +2in to +3in relative to Address

Vias No vias should be used for clocks

Layer Types All clocks should be routed on microstrip

Table 10-27. Routing Guidelines for Clock Signal Group (Continued)


Table 10-28. Routing Guidelines for Clock Feedback Loop


Routing Route as 100Ω differential pair.

Layers The trace from output to stub (Rf) should be on the same layer as clock traces.The trace from the stub to the input should be on the same layer as strobes (DQS).

Group Spacing 25 mils to other group.

Trace Lengths The trace from output to stub (Rf) should match average clock lengths ±25 mils.The trace from stub to input should match average strobe (DQS) lengths ± 25 mils.

Vias Maximum of 2 vias.

Rf 22Ω


(TL0)

B1: ClockMatching

(TL1)

B2: StrobeMatching

(TL2)

Rf

680838B–HIREL–04/07


PC109 [Preliminary]

length. Rf resistors are on the top layer. The DQS matching section of the feedback loop is on an internallayer (in green).

Figure 10-24. SD_CLOCK and Feedback loop layout examples

10.5.7.7 Address and Command SignalsAlthough SD_CLKEN[0:1] are control signals, their layout topology matches the Address and Commandgroup in the dual DIMM configuration. The capacitor (Ccmd) on address and command lines should beclose to the first DIMM to help match the line impedance to the heavy capacitive loads of the unbufferedDIMMs. The resistor (Rcnt) on SD_CLKEN signals should be placed close to the first DIMM. The paralleltermination (Rtt) is placed as close as possible to the second DIMM.

Figure 10-25. Topology for Address and Command Signals

Figure 10-26. Topology for SD_CLKEN Signals

Rf

Cclk Cclk Cclk

CclkCclk Cclk

SD_CLK3 SD_CLK4

SD_CLK1

SD_CLK2

SD_CLK0

SD_CLK5

Controller

A: Breakout(TL0)

B: Lead In(TL1)

CcmdC: Stub to

DIMM(TL2)

D: DIMM toDIMM(TL3)

E: TerminationStub(TL4)

DIMM #1 DIMM #2

RttVtt

Controller

DIMM #1 DIMM #2

A: Breakout(TL0)

B: Lead In(TL1)

C: Stub toDIMM(TL2)

Rtt


Rcnt

Vtt

D: DIMM toDIMM(TL3)

690838B–HIREL–04/07


PC109 [Preliminary]


10.5.7.8 Control SignalsTermination resistors (Rtt) should be placed as close as possible to DIMM#2.

Table 10-29. Trace Parameters for Address and Command Signal Group


Length (in.)

LayerType

TraceWidth (mil)


Trace Impedance


OtherGroups


Stripline 4 4 4 60


3,6TL1

Lead In 0.5 2.5 Stripline 4 12 25 60

1,8 Microstrip 5

3,6TL2

Stub to DIMM

0 0.5 Stripline 4 12 25 60

1,8 Microstrip 5

3,6TL3

DIMM to DIMM

0.25 0.5 Stripline 4 12 25 60

1,8 Microstrip 5

3,6TL4

Termination stub

0.25 0.5 Stripline 4 12 25 60

1,8 Microstrip 5

Total(1)

Controller to 1st DIMM (A+B+C)

1.0 2.5

Via count = 3Controller to 2nd DIMM

(A+B+C+D) 1.5 3.0

Table 10-30. Routing Guidelines for Address and Command Signal Group


Reference Plane Layers All signals should be referenced to solid ground planes

Breakout5 mil spacing for the breakout is acceptable. 0.5in is the maximum length of breakout spacing.


Total Trace Length To 1st DIMM: 1in to 2.5in To 2nd DIMM: 1.5in to 3in

Length Matching Address to Address: 1in skew Address to Clock: - 2in to - 3in relative to clock

Vias Maximum of 3 Vias

700838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-27. Topology for Control Signals



(TL0)

B1: Lead In(TL1)

B2: Lead In(TL1)

Rcnt

C: Stub toDIMM(TL2)

DIMM #1D: Termination

Stub(TL3)

Rtt

DIMM #2

Rtt

Rcnt

Vtt

Vtt

C: Stub toDIMM(TL2)

D: TerminationStub(TL3)

Table 10-31. Trace Parameters for Control Signal Group


Length (in.)

LayerType

TraceWidth (mil)


Trace Impedance


OtherGroups


Stripline 4 4 460


3,6TL1 B1: Lead In 0.5 2.5

Stripline 412 25 60

1,8 Microstrip 5

3,6TL1 B2: Lead In 1.0 3.0

Stripline 412 25 60

1,8 Microstrip 5

3,6TL2

Stub to 0 0.5

Stripline 412 25 60

1,8 DIMM Microstrip 5

3,6TL3

Termination Stub

0.25 0.5Stripline 4

12 25 601,8 Microstrip 5


1st DIMM (A+B+C)

1.0 2.5


1.5 3.0

Table 10-32. Routing Guidelines for Control Signal Group


Reference Plane Layers All Control signals should be referenced to solid ground planes

710838B–HIREL–04/07


PC109 [Preliminary]

10.5.7.9 Address/Command/Control and Termination Plane Layout ExampleFigure 10-28 on page 73 outlines the Address/Commend group and the CLKEN signals. The Compen-sation capacitors are located just before the near connector. The termination resistors (Rtt) are locatedpass the far connector. The blue traces are address and command signals, while the green traces arethe control signals. All are routed on the bottom layer, but the traces between the near connector and thefar connector are routed on internal layers. The connection from the far connector to Rtt resistors is onthe bottom layer.

The termination plane (Vtt) also is shown in Figure 10-28 on page 73. This copper fill area provides alow-impedance path from the termination resistors to the Vtt regulator (not shown). The plane can be onany layer, but it is preferable to place it on the bottom layer. Using this method, vias are not requiredbetween the termination resistors and the Vtt plane.

Breakout5 mils spacing for the breakout is acceptable. 0.5in is the maximum length of breakout spacing.

Group Spacing Between 25 mils to all other signals

Length Matching Control to Control: 1in skew Control to Clock: - 2in to - 3in relative to clock



720838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-28. Address/Command/Control and Termination Plane Layout

10.5.8 Single DIMM Layout

10.5.8.1 ConnectionsThe Memory Controller connects directly to the DIMM connector as shown in Figure 10-29 on page 74.All signals have a point-to-point connection to the connector. The Termination resistors Rtt are used toterminate unidirectional Address and Control signals. Rcnt and Ccmd and Cclk are recommended toimprove signal quality on heavily loaded lines. A description of the discrete components is provided inSection 10.5.3 on page 56.

VTT Plane

Rtt

Ccmd

Rcnt

Rcnt

730838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-29. Connection Diagram for One DIMM

10.5.8.2 Component PlacementThe single DIMM connector should be positioned across the SDRAM side of the PC109. The distancebetween the PC109 and the DIMM is dictated by the maximum trace length in the trace parameter tablesin this section. The distance between the PC109 and the connector is approximately 0.7 inch to 2 inches.

Figure 10-30. Single DDR2 DIMM and PC109 Placement

The minimum and maximum trace length are summarized for each group in Table 10-33 on page 75.Trace parameter details are provided in the following sub-sections for each signal group.

• The Address/Command group and the control group trace length from the PC109 to the connector are the shortest. from a minimum of 1 inch to a maximum of 3.0 inches.

• The Clock trace length are the longest with a minimum of 3 inches and a maximum of 5.5 inches from the PC109 to the connector. The clock traces must be 2 to 3 inches longer than any address trace.

MemoryController

DD

R2

DIM

M

SD_CLKP[0:2]SD_CLKN[0:2]

SD_CS[0:1]

ODT[0:1]

CLKEN[0:1]

DQ[0:63]

DM[0:8]

C

A[0:13]

BA[0:2]

RAS

CAS

WE

SDA

SCLK

CD[0:7]

Vtt

Cclk

Ccmd

Ccmd

Ccmd

Ccmd

Ccmd

Vref Vref

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rcnt

Rcnt

Rcnt

DSQ[0:8]

PC10933 mm

240 pin DDR2 DIMM Socket

Approximately 0.7 to 2"

740838B–HIREL–04/07


PC109 [Preliminary]

• DQ/DQS traces must be 2.5 inches to 4.5 inches long from the PC109 to the connector. The DQ/DQS traces must be 0.5 to 1.0 inch shorter than clock traces.


Figure 10-31. Trace Length Per Group from PC109 to the Connector

10.5.8.3 Data SignalsFigure 10-32 shows the topology used for routing data lines. After the breakout escape from the pin fieldof the controller the majority of the routing distance should be on inner stripline layers. This provides forbetter propagation delay matching by using common layer types. Vias and layer changes should be min-imized where possible. The recommended trace parameters for DQ signals are outlined in Table 10-35on page 76, and DQS signals are in Table 10-36 on page 77. The guidelines for the data group are sum-marized in Table 10-36 on page 77.

Figure 10-32. Topology for DQ Signals


GroupAbsolute Minimum

LengthAbsolute Max Length (to Near Connector)

Relative Minimum and Maximum

Address/Command /Controls

1 inch 3 inches

Clocks 3 inches 5.5 inches2 to 3 inches longer than

address

DQ/DQS 2.5 inches 4.5 inches 0.5 to 1 inch shorter than

clocks

Feedback loop Clocks+DQS

Clocks = Address + 2 to 3 inches

Address/Command 1.0 to 3.0 inches max

Clocks 3.0 inches to 5.5 inches

DQ/DQS 2.5 to 4.5 inches

FB_LOOP_OUT = Clocks FB_LOOP_IN = DQS

Data = clocks -0.5 to -1 inch


(TL0)B

(TL1)DIMM

750838B–HIREL–04/07


PC109 [Preliminary]

10.5.8.4 DQS SignalFigure 10-33 shows the topology recommended for routing DQS lines. The topology is similar to DataSignals. Data strobes should be routed as differential lines.



Table 10-34. Trace Parameters for DQ Signals


Length (in.)

LayerType

TraceWidth (mil)


Trace Impedance


OtherGroups


60Microstrip 5 5 5

3,6

TL1 Lead In 2 4.5 Stripline 4 12 20 60

TotalController to DIMM (A+B)

2.5 4.5 Via count = 1


(TL0)B

(TL1)DIMM

Table 10-35. Trace Parameters for DQS Signals


Length (in.)

LayerType

TraceWidth (mil)


Trace Impedance


OtherGroups


100Microstrip 5 5 5

3,6

TL1 Lead In 2 4.5 Stripline 4 4 25 100

Total(1) Controller to

DIMM (A+B)2.5 4.5 Via count = 1

760838B–HIREL–04/07


PC109 [Preliminary]


Only three clock pairs are required to drive one DIMM connector. The capacitor should be placed closeto the DIMM connector. No parallel termination is provided on the board because the differential clocksare terminated on the DIMM. Clocks are all on rows 1 and 2 of the ballmap. They should be broken outon microstrip and should travel on the same layer for the entire route.


Table 10-36. Routing Guideline for DQ and DQS Signals


Reference Plane Layers All source synchronous signals should be referenced to solid ground planes

Breakout5 mil spacing for the breakout is acceptable. 0.5in is the maximum length of breakout spacing. Microstrip and Stripline can be used for breakout. Each byte group including bits and strobes must breakout on exactly the same layer.

Group Spacing

DQ to DQ within byte: 12 mil minimum

DQ to other groups: 20 mil minimum

DQS to other signals: 25 mil minimum

Total Trace Length To DIMM: 2.5in to 4.5in

Length Matching

DQS Plus to Minus: As close as routing allows (must be less than ±10 mil) DQ to associated DQS: +25 mil minimum to +50 mil maximumDQ to DQ within group: ±25 mil

DQS to Clock: DQS is -0.5in to -1.0in to CLK

ViasMaximum of 1 vias for any data or strobe signal.

Vias must be matched within a strobe pair and byte group.

Layer TypesBreakout can be microstrip or stripline. All other Data/Strobe trace segments must be on stripline. Within a byte group all signals must be on the same layer.


(TL0)DIMM

Cclk

B1: Lead Into DIMM

(TL1)

C: Term toDIMM(TL2)

770838B–HIREL–04/07


PC109 [Preliminary]


10.5.8.6 Clock Feedback LoopA differential clock feedback pair is provided to track the board propagation delay of the clock and stroberound trip path. The first section of this pair should be routed on the same layers as the clock signals.The second section should be routed on the same layer as the strobe signals.

The feedback clock loop trace length should be the average of the clock lines plus the average of datastrobe lines. The length matching tolerance is defined in Table 10-39 on page 79. The position of Rf isdefined by the length of TL1 and TL2.

Table 10-37. Trace Parameters for Clock Signals


Length (in.)

LayerType

TraceWidth (mil)


Trace Impedance


OtherGroups

1 TL0 Breakout 0 0.5 Microstrip 5 5 5 100

1 TL1 Lead In 2.5 5.5 Microstrip 5 5 25 100

1

TL2Termination

to DIMM0 0.5 Microstrip 5 5 25 100

Total(1) Controller to DIMM (A+B)

3.0 5.5 Via count = 0

Table 10-38. Routing Guidelines for Clock Signal Group



Breakout5 mil spacing for the breakout is acceptable. 0.5in is the maximum length of breakout spacing.



Length MatchingClock Plus to Minus: As close as routing allows (must be less than ±10 mil) Clock pair to pair: ±25 mil Clock to DQS: +0.5in to +1in Clock to Address/Command: +2in to +3in relative to Address

Vias No vias should be used for clocks

Layer Types All clocks should be routed on microstrip.

780838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-35. Trace Topology Clock Feedback Loop

10.5.8.7 Address and Command SignalsThe capacitor (Ccmd) should be close to the DIMM connector to help match the line impedance to theheavy capacitive loads of the unbuffered DIMMs. The parallel termination (Rtt) is placed as close as pos-sible to the DIMM.

Table 10-39. Routing Guidelines for Clock Feedback Loop


Routing Route as 100Ω differential pair.

LayersThe trace from output to stub should match the layer of clock traces.The trace from the stub to the input should match the layer type for strobes.

Group spacing 25 mils to other group

Trace LengthsThe trace from output to stub should match average clock lengths ±25 mils The trace from stub to input should match average strobe lengths ± 25 mils

Vias Maximum of 2 vias

Rf 22Ω

Rf


(TL0)

B1: ClockMatching

(TL1)

B2: StrobeMatching

(TL2)

790838B–HIREL–04/07


PC109 [Preliminary]



Controller

A: Breakout(TL0)

B: Lead In(TL1)

CcmdC: Lead In

(TL2)DIMM


Rtt

Table 10-40. Trace Parameters for Address and Command Signal Group


Length (in.)

LayerType

TraceWidth (mil)


Trace Impedance


OtherGroups


Stripline 4 4 4 60


3,6TL1 Lead In 1 3

Stripline 4 12 20 60

1.8 Microstrip 5

3,6TL2

Stub to DIMM

0 0.5Stripline 4 12 20 60

1,8 Microstrip 5

3,6TL3

Termination stub

0.25 0.5Stripline 4 12 20 60

1,8 Microstrip 5


DIMM (A+B+C)

1.5 3.0 Via count = 3




Breakout5 mil spacing for the breakout is acceptable. 0.5in is the maximum length of breakout spacing



Length Matching Address to Address: 1in skew Address to Clock: - 2in to - 3in relative to clock


800838B–HIREL–04/07


PC109 [Preliminary]

10.5.8.8 Control SignalsTermination resistors (Rtt) should be placed as close as possible to the connector.



Vtt

Controller

A: Breakout(TL0)

B: Lead In(TL1)

RcntC: Stub to

DIMM(TL2)

DIMM


Rtt

Table 10-42. Trace Parameters for Control Signal Group


Length (in.)

LayerType

TraceWidth (mil)


Trace Impedance


OtherGroups


Stripline 4 4 460


3,6TL1 Lead In 1 3

Stripline 412 20 60

1,8 Microstrip 5

3,6TL2

Stub to DIMM

0 0.5Stripline 4


3,6TL3

DIMM to Stub

0.25 0.5Stripline 4



DIMM (A+B+C)

1.5 3.0 Via count = 3



Reference Plane Layers All control signals should be referenced to solid power or ground planes

Breakout5 mil spacing for the breakout is acceptable. 0.5in is the maximum length of breakout spacing

Group Spacing Between 20 mil to all other signals


Length Matching Control to Control: 1in skew Control to Clock: - 2in to - 3in relative to clock


810838B–HIREL–04/07


PC109 [Preliminary]

10.5.9 Dual SODIMM Layout

10.5.9.1 ConnectionsThe Memory Controller connects directly to the two SODIMM connectors without the need for externalglue logic or clock distribution. Clocks, chip selects, and ODT signals have point-to-point connections.The other signals are daisy-chained from one connector to the other. The Termination resistors Rtt areused to terminate unidirectional Address and Control signals. Rcnt, Ccmd, and Cclk are recommendedto improve signal quality on heavily loaded lines. A description of the discrete components is provided inSection 10.5.3 on page 56.

Tundra recommends to use SD_CLK4 and 5 for the far connector and SD_CLK1 and 2 for the near con-nector (connected to CLK0 and CLK1 respectively on the SODIMM connector). This will allow routing ofall four clock pairs on the same layer without crossing.

Figure 10-38. Connection Diagram for Dual SODIMM

MemoryController

SD_CS[2:3]

ODT[2:3]

SD_CS[0:1]

ODT[0:1]

CLKEN[0:1]

DQ[0:63]

A[0:13]

BA[0:2]

RAS

CAS

WE

SDA

SCLK

DSQ[0:7]

Vtt

Cclk

Cclk

Ccmd

Ccmd

Ccmd

Ccmd

Ccmd

Rtt

Rcnt

Rcnt

Rcnt

Rcnt

Rcnt

Vref

SD_CLK_P[4:5]

SD_CLK[1:2]

SD_CLK#[1:2]

SD_CLK_N[4:5]

Vref

Vref Vtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

DD

R2

SO

DIM

M C

onne

ctor

(st

arnd

ard)

DD

R2

SO

DIM

M C

onne

ctor

(re

ve r

sed)

820838B–HIREL–04/07


PC109 [Preliminary]

10.5.9.2 Connector PlacementConnector placement is dictated by minimum and maximum trace lengths, as stated in Section 10.5.9.3on page 83. The following layout parameters assume that both connectors are on the same PCB side asthe PC109. The connectors must be placed on the Memory Controller side of the device. Tundra recom-mends to place the near connector 1.4 inches to the PC109. The recommended distance between pin 1of the near connector and pin 1 of the far connector is approximately 0.4 inch.

Figure 10-39. Dual DDR2 DIMM and PC109 Placement

10.5.9.3 Trace Length SummaryThe Maximum trace length for each signal group (defined in Section 10.5.5 on page 59) is summarizedin Table 10-44 on page 84. Trace parameters details are given in the following sub-sections for each sig-nal group.

• The Address/Command trace length from the PC109 to the near connector should be as short as possible, to a maximum of 2.5 inches.

• The clocks trace length must be at least as long as the longest address line, and cannot exceed the shortest address line by 1.5 inch from the PC109 to the near connector.

• DQ/DQS traces must be 0.5 inch longer than the clock lines and cannot exceed the clock length by more than 2 inches.

• Control traces should match clocks.


• Traces from near connector to far connector should not exceed 0.5 inch.

Approximately

Approximately

Near connector

Far connector

1.4”

0.4”

PC10933 mm

830838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-40. Trace Length Per Group from PC109 to the Near Connector

10.5.9.4 Topology DescriptionSignal topology describing the connection between the PC109 and the DIMM modules are broken downin Transmission Line sections (TL):

• Breakout TL – The trace between the PC109 pad and the breakout via, or to the outside limit of the package if the signal is broken out on the top layer.

• Lead-in TL – The trace from the Breakout TL to the first connector pad or to a termination element.

• Term to Connector TL – The trace from an intermediate termination element to a connector. pad.

• Stub to Connector TL – The trace from an intermediate stub termination element to a connector pad.

• Connector to Connector TL – The trace from the near connector to the far connector.

• Termination Stub TL – The trace from the connector pad to Rtt.

10.5.9.5 Data (DQ) and Data Strobe (DQS) SignalsThe trace topology used for routing data lines and strobe lines is the same. The data bus must be routedin byte groups (see Section 10.5.5.1 on page 59). After the breakout escape from the pin field of theMemory Controller, the majority of the routing distance should be on inner stripline layers. This providesfor better propagation delay matching by using common layer types. Vias and layer changes should beminimized where possible. If a layer change is required, all signals of the same group should changelayer at the same point.


Group Min length Max Length

Address/Command None 2.5 inches

Clocks = Address Address + 1.5 inch

DQ/DQS Clocks + 0.5 inch Clocks + 2 inches

Control = Clocks

Feedback loop Clocks + DQS

All groups from near connector to far connector

0.25 inch 0.5 inch

Address/Command

Clocks

DQ/DQS

Controls

2.5 inches max

Address + 0" to 1.5"

Clocks + 0.5" to 2.0"

Controls = Clocks

FB_LOOP_OUT=Clocks FB_LOOP_IN =DQS

840838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-41. Topology for DQ and DQS Signals

Table 10-45. Routing Guidelines for Data and Strobe Signal Group


Trace impedance

All signals should be referenced to solid ground planes. The target trace impedance is 60Ω for DQ. The target trace impedance is 100Ω for DQS. Recommended trace width is 5 mil for top and bottom layers, 4 mil for inner layers.

Breakout Section0.5 inch long maximum. 5 mil spacing to other traces is acceptable over the breakout section.

Lead-in sectionShould be routed on internal layers. 3 x trace width spacing minimum to traces within the same group. 5 x trace width spacing minimum to traces of other groups.

Connector to Connector section0.5 inch long maximum. Should be routed on internal layers. 5 mil spacing minimum to traces within the same group is acceptable. 3 x trace width spacing minimum to traces of other groups.

Total Trace LengthFrom PC109 ball to pad of near connector: Minimum: Clock traces + 0.5 inch Maximum: Clock traces + 2.0 inches

Length MatchingDQ/DQS within a byte group: ±25 mil to each connector. DQ/DQS all groups: ±0.25 inch to each connector. DQS pair: ±10 mil


PC109

Breakout Lead in

DQpad

DQSpads

Nearconnector Connector to

connector

FarConnector

850838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-42. Internal Layer 2-byte Groups

Byte group 6 Byte group 4 Byte group 2 Byte group 0

860838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-43. Internal Layer 1-byte Groups


Any of the six clock pairs available from PC109, can be connected to any input clock pins of SODIMMconnectors. Each connector requires two clocks. For ease of routing, connect the SD_CLK1 pair and theSD_CLK2 pair to the near connector and the SD_CLK4 pair and the SD_CLK5 pair to the far connector.The compensation capacitor should be placed close to the connector in between the positive and nega-tive signal of each clock pair. No parallel termination is required on the board because the differentialclocks are terminated on the modules. All clocks should be broken out on microstrip and should travel onthe same layer for the entire route. One via is acceptable to connect to the capacitor.

Byte group 7 Byte group 5 Byte group 1Byte group 3

870838B–HIREL–04/07


PC109 [Preliminary]


10.5.9.7 Clock Feedback LoopA differential clock feedback pair is provided to track the board propagation delay of the clock and stroberound trip path. The first section of this pair should be routed on the same layers as the clock signals.The second section should be routed on the same layer as the strobe signals (DQS). The feedback clockloop trace length should be the average of the clock lines plus the average of data strobe lines. The posi-tion of Rf is defined by the length of clock matching section and the DQS matching section.

Table 10-46. Routing Guidelines for the Clock Signal Group


Trace impedanceAll traces should be referenced to solid ground planes. The target trace impedance is 100Ω differential. Recommended trace width is 5 mil.


Lead-in sectionRouted on the top layer. 1 x trace width spacing minimum to traces within the same pair. 5 x trace width spacing minimum to traces of other groups

Stub to Connector section0.5 inch long maximum. Routed on top layer. 5 mil spacing minimum to traces within the same group is acceptable. 5 x trace width spacing minimum to traces of other groups.

Total Trace Length

From PC109 ball to pad of near connector: Minimum = Longest trace length of Address/Command group + 0 inch Maximum =Shortest trace of the Address/Command group + 1.5 inch.

From PC109 ball to pad of far connector: Same as near connector plus 0.5” max

Length Matching Clock pair to Clock pair to the same connector: ±25 mil. Within a pair: ±10 mil

Vias Only one via for Cclk.

PC109SD_CLK pad

Breakout Lead in

Nearconnector

FarConnectorTerm to

connector

Cclk

Cclk

880838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-45. Trace Topology Clock Feedback loop

10.5.9.8 Layout Examples for Clock TracesClock signals are routed on the top layer (in red). Cclk capacitors are placed close to the connector padson the top layer. The clock signals and feedback loop traces are serpentined to achieve required length.Rf resistors are on the top layer. The DQS matching section of the feedback clock is on an internal layer(in green).

Table 10-47. Routing Guidelines for the Feedback loop


Trace impedanceAll traces should be referenced to solid ground planes. The target trace impedance is 100Ω differential. Recommended trace width is 5 mil on top layer and 4 mil in internal layers.


Clock Matching sectionRouted on the top layer. 1 x trace width spacing minimum to traces within the same pair. 5 x trace width spacing minimum to traces of other groups.

DQS Matching sectionRouted on the same layer as DQS signals. 1 x trace width spacing minimum to traces within the same pair. 5 x trace width spacing minimum to traces of other groups.

Length MatchingClock Matching section should be ±25 mil of the average clock traces (including breakout section). DQS Matching section should be ±25 mil of the average DQS traces. (including breakout section).

Vias One pair for Rf. and one pair for breakout of DQS matching section.

Clock Matching

DQS Matching

Breakout

PC109 Feedbackclock out pad

Rf

890838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-46. Clock and Feedback Loop Layout Example

10.5.9.9 Address and Command SignalsAlthough SD_CLKEN[0:1] are control signals, their layout topology matches the Address and Commandgroup. The capacitor (Ccmd) on address and command lines should be close to the near connector tohelp match the line impedance to the heavy capacitive loads of the unbuffered SODIMMs. The resistor(Rcnt) on SD_CLKEN signals should be placed close to the near connector. The parallel termination(Rtt) is placed as close as possible to the far connector.

SD_CLK5 pair

SD_CLK2 pair SD_CLK4 pair

SD_CLK1 pair

Feedback loop

Cclk Cclk

CclkCclk

Rf

900838B–HIREL–04/07


PC109 [Preliminary]


Figure 10-48. Topology for SD_CLKEN Signals



Trace impedance

All signals should be referenced to solid ground planes.The target trace impedance is 60Ω.

Recommended trace width is 5 mil for top and bottom layers, 4 mil for inner layers.

Breakout Section0.5 inch long maximum.

5 mil spacing to other traces is acceptable over the breakout section.

Lead-in section

Can be routed on any layers.

3 x trace width spacing minimum to traces within the same group.5 x trace width spacing minimum to traces of other groups.

Stub to Connector section

0.5 inch long maximum.Can be routed on any layers.

5 mil spacing minimum to traces within the same group is acceptable.

3 x trace width spacing minimum to traces of other groups.

Connector to Connector section

0.5 inch long maximum.

Can be routed on any layers.5 mil spacing minimum to traces within the same group is acceptable.

3 x trace width spacing minimum to traces of other groups.

Termination Stub section0.5 inch long maximum.

Ideally routed on the same layer as Rtt.

Total Trace Length From PC109 ball to pad of near connector: 2.5inches maximum

Length Matching Address to Address: 1inch skew.


PC109Address Pad

Breakout Lead InStub to

connector

Nearconnector

Connector toconnector

Farconnector

TerminationStub

Rtt

Vtt

Ccmd

PC109CLKEN Pad

Breakout Lead In

Rcnt

Stub toconnector

Nearconnector

Connector toconnector

Farconnector

TerminationStub

Rtt

Vtt

910838B–HIREL–04/07


PC109 [Preliminary]

10.5.9.10 Layout Examples for Address LinesFigure 10-49 outlines the Address/Commend group and the CLKEN signals. The blue layer is the bottomof the PCB, the red layer is the top. The Compensation capacitors are located around the near connectorand the termination resistors are located near the far connector. Address signal are route from thePC109 to the near connector on the bottom layer. The connection between the near and far connector ison an internal layer. The connection from the far connector to Rtt resistors is on the bottom layer. The Vttplane is stretched-in towards the near connector to provide connectivity to SD_CS0, SD_ODT0 andsome address lines.

Figure 10-49. Address Signals Layout

VTT plane

Local GND planeand Ccmd

Ccmd

Rtt

RcntCLKEN0CLKEN1

Rtt

920838B–HIREL–04/07


PC109 [Preliminary]

10.5.9.11 Control SignalsControl signals can be routed on any layer. Rcnt should be placed before its related connector. The ter-mination resistors (Rtt) should be placed behind its related connector.




Trace impedanceAll signals should be referenced to solid ground planes. The target trace impedance is 60Ω. Recommended trace width is 5 mil for top and bottom layers, 4 mil for inner layers.


Lead-in sectionCan be routed on any layers. 3 x trace width spacing minimum to traces within the same group. 5 x trace width spacing minimum to traces of other groups.

Stub to Connector section0.5 inch long maximum. Can be routed on any layers. 5 mil spacing minimum to traces within the same group is acceptable. 3 x trace width spacing minimum to traces of other groups.

Termination Stub section 0.5 inch long maximum. Ideally routed on the same layer as Rtt.

Total Trace LengthFrom PC109 ball to pad of connector (including the resistor): matches Clock trace length of the same connector.

Length Matching ±0.75 inch to clock traces


PC109Control

signal pad

Breakout Lead In RcntStub to

Connector

NearConnector

TerminationStub Rtt

FarConnector

Rtt

Rcnt

Vtt

Vtt

930838B–HIREL–04/07


PC109 [Preliminary]

10.5.10 Single SODIMM Layout

Figure 10-51. Single SODIMM Connection Diagram

Designs with a single SODIMM connector should use the same rules as a dual-connector configuration.A standard or reversed connector can be used. From the dual-connector configuration, the connector-to-connector transmission line is no longer required. All other transmission lines and length matching rulesapply.

10.5.11 Soldered-down Devices Layout

10.5.11.1 Soldered-down DevicesThere are several possible soldered-down SDRAM configuration. The approach taken to cover as manyconfiguration as possible is based on JEDEC standard DIMM/SODIMM specifications. A soldered-downmemory configuration should be taken form the JEDEC standards. For information about DDR2 moduledesign specifications, see JEDEC JESD21-C.

Since soldered-down memory topology matches that of a single DIMM/SODIMM, the PC109 connects tothe soldered-down devices using the same topology and the same termination elements as the singleDIMM/SODIMM configuration of Section 10.5.6.1 on page 60.

SD_CS[0:1]

ODT[0:1]

CLKEN[0:1]

DQ[0:63]

A[0:13]

BA[0:2]

RAS

CAS

WE

SDA

SCLK

DSQ[0:7]

Vtt

Cclk

Ccmd

Ccmd

Ccmd

Ccmd

Ccmd

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rtt

Rcnt

Rcnt

Rcnt

MemoryController

VrefVref


DD

R2

SO

DIM

M C

on

nec

tor

(Sta

nd

ard

or

Rev

erse

d)

940838B–HIREL–04/07


PC109 [Preliminary]

10.5.11.2 Layout ApproachThe approach taken to cover as many configurations as possible is based on JEDEC standard DIMM orSODIMM design specifications. Please refer to the following JEDEC 21-C standards for DDR2 moduledesign specifications:

• PC2-4200/PC2-3200 DDR2 Unbuffered SO-DIMM, Reference Design Specification, Revision 0.52, April 26, 2004

• PC2-3200/PC2-4200 DDR2 SDRAM Unbuffered DIMM, Design Specification, Revision 1.0

The layout recommendations of soldered-down devices is a combination of the single DIMM/SODIMMmemory configuration of Section 10.5.8 on page 73 and the JEDEC Layout Standards. The layout topol-ogy outlined in the following sections describe the trace parameters from the PC109 to the beginning oftrace segment TL0 in the JEDEC module specification. Any deviation from the JEDEC standards or fromthis application note should be validated with signal integrity and timing analysis.

10.5.11.3 Data SignalsFigure 10-52 shows the topology used for routing the data lines. After the breakout escape from the pinfield of the controller the majority of the routing distance should be on inner stripline layers. This providesfor better propagation delay matching by using common layer types. Vias and layer changes should beminimized where possible. The recommended trace parameters for DQ signals are outlined in Table 10-23 on page 64, and DQS signals are in Table 10-24 on page 64. The guidelines for the data group areoutlined in Table 10-25 on page 65.

Figure 10-52. Trace Topology for DQ Signals

10.5.11.4 DQS SignalFigure 10-53 shows the topology recommended for routing DQS lines. The topology is similar to DataSignals. Data strobes should be routed as differential lines.


Controller

A: Breakout(TL0)

B: Lead In(TL1)

JEDECstandardmodulelayout


B: Lead In(TL1)


950838B–HIREL–04/07


PC109 [Preliminary]

10.5.11.5 Clock SignalsUse the clock layout configuration from the JEDEC standard to distribute clocks to the memory devices.Depending on the memory configuration, only 2 to 3 clock outputs from the PC109 may be required. Thecapacitor should be placed close to the beginning of the JEDEC layout. If a capacitor is already presentin the JEDEC layout, the two capacitors may be combined. Clocks are all on rows 1 and 2 of the ball-map. They should be broken out on microstrip and should travel on the same layer for the entire route.The trace parameters for clock signals are outlined in Table 10-26 on page 67, and the guidelines are inTable 10-38 on page 78.

Figure 10-54. Trace Topology For Clock Signals

10.5.11.6 Clock Feedback LoopThe feedback loop topology is identical to the single DIMM/SODIMM configuration (for more information,see Section 10.5.7.5 on page 68).

10.5.11.7 Address and Command SignalsThe capacitor (Ccmd) should be close to the beginning of the JEDEC layout. The parallel termination(Rtt) is placed near the capacitor. (It may also be placed within the JEDEC layout). For information ontrace parameters and layout guidelines, see Table 10-40 on page 80 and Table 10-41 on page 80.

Figure 10-55. Trace Topology for Address and Command Signals

Controller

A: Breakout(TL0)

B: Lead In(TL1) JEDEC

standardmodulelayout

C: Term(TL2)

Cclk

Controller

A: Breakout(TL0) B: Lead In

(TL1) JEDECstandard

C: Term(TL2)

Rtt


Ccmd

960838B–HIREL–04/07


PC109 [Preliminary]

10.5.11.8 Control SignalsRcnt should be placed near the beginning of the JEDEC layout. If a series element is present in theJEDEC layout, the two resistors may be combined. Termination resistors (Rtt) should be placed near orwithin the JEDEC layout. For information on trace parameters and layout guidelines, see Table 10-42 onpage 81 and Table 10-43 on page 81.

Figure 10-56. Trace Topology for Control Signals

10.6 PCI-X Interface

10.6.1 PCI-X Loading and Bus SpeedThe PCI-X specification does not provide a maximum load limit on the bus. It is recommended that a sys-tem designer perform rigorous testing to analyze the limitations of bus speed under full load. Based onformal testing,1 the maximum load recommended for reliable 133-MHz bus speed is one connec-tor+add-in card. If the motherboard provides more than one slot, the bus speed should be reduced.

10.6.2 Routing GuidelinesThe PCI connector(s) should be placed near the PCI side of the PC109. Motherboard specification andlayout guidelines are provided in the PCI Local Bus Specification Revision 2.3) and the PCI-X Adden-dum to PCI Local Bus Specification (Revision 1.0a). Follow these additional guidelines for the PCI/XInterface.

Controller

A: Breakout(TL0)

B: Lead In(TL1)


Rcnt

C: Term(TL2)

RttVtt


Table 10-50. Routing Guidelines PCI-X Interface


Reference Plane Layers All signals should be referenced to continuous reference planes

Breakout PC109 Breakout should be less than 0.5in.

Group SpacingClearance between traces should be 15 mils except for the breakout region.

Trace length Keep PCI traces short and match lengths within 1 inch.

Clocks

PCI clocks should be routed from point to point with shortest length possible and match length. Feedback one CG_PCI_CLK back to the PCI_CLK input with matched length to the PCI clocks going to the PCI connectors.

970838B–HIREL–04/07


PC109 [Preliminary]

10.7 Ethernet ControllerThe PC109 User Manual describes the different PC109 to PHY device connections depending on theEthernet mode implemented on the board. Board layout requirements are outlined in Table 10-52 onpage 99 and Table 10-53 on page 99. It is recommended to place a series termination resistor (Rs) nearthe pin of the PC109 unidirectional output signals.

Table 10-51 provides a list of the signals requiring source termination. Refer to the Ethernet PHY vendorspecification to determine if a source termination resistor (Rp) is required.

Figure 10-57. Ethernet Controller Source Termination Resistor

Table 10-51. Ethernet Controller Outputs Requiring Source Termination Resistor

Signal Name Pin Count Rs

E_0_TCG 10

33Ω

E_0_ECMDT 1

E_0_EWRAP 1

E_0_PRBSEN 1

E_0_PCOL_RBCM 1

E_1_TCG 10

E_1_ECMDT 1

E_1_EWRAP 1

E_1_PRBSEN 1

E_1_PCOL_RBCM 1

E_MDC 1

E_GTXCLK 2

Ethernet Rs

Rp


PHY0

Ethernet

PHY1

Rs

Rp

Connectors

E_REF125

PC109GigE

Interfaces

980838B–HIREL–04/07


PC109 [Preliminary]

Maximum Trace Length and trace length mismatch are correlated. Apply the length matching withingroups:

• E0_TCG[9:0], TXCLK0

• E0_RCG[9:0], RXCLK0

• E1_TCG[9:0], TXCLK1

• E1_RCG[9:0], RXCLK1

10.7.1 Hold Time Adjustment on PC109 Receive InputsDue to errata pertaining to hold time on the PC109 GMII receive inputs, attention must be given to thetrace length of E0_RCG[9:0] with respect to RXCLK0, and E1_RCG[9:0] with respect to RXCLK1.

PC109 RCG[9:0] inputs must be held for 700ps after the rising edge of RXCLK. PC109 RCG[9:0] inputsmust be held for 115 ps after the rising edge of RXCLK (for more information, see the PC109 DeviceErrata and Design Notes and the PC109 Device Errata and Design Notes.

Most Ethernet PHYs have a clock-to-valid-data delay of at least 500ps. The clock-to-valid-data delay,combined with the trace skew between RCG[9:0] traces with respect to RXCLK, must provide sufficienthold time on the PC109 GMII receive inputs.

The required skew between RCG[9:0] and RXCLK depends on the missing hold time on the PC109 GMIIreceive inputs and signal propagation delay on the PCB. Propagation delay depends on the PCB dialec-tric constant. It is usually between 140 and 180 ps/inch on FR4 PCBs.

PCBskew = [Tsi10x_setup_time - PHY_clock_to_valid_data] / Propagation delay

Table 10-52. Routing Guidelines Ethernet Controller


Trace Impedance 60Ω

Trace Width 5 mils

Trace Spacing 12 mils

Group Spacing 20 mils to other signal groups

Trace length See Table 10-53

Series resistor Rs 33Ω ±5%

General Guidelines

Rs should be close to driver. Signals should be routed most of the length on either microstrip or stripline for all signals. Vias should be minimized with a maximum of 4 vias. Clocks should have the same number of vias and segments as data lines. Segments lengths should be matched in layers. Breakouts and routing should both be on layers 1, 3, 6, and 8.

Table 10-53. Length Matching for Ethernet Controller

Trace Mismatc Maximum Trace Length

250 mils 6 inches

500 mils 4.5 inches

750 mils 3.5 inches

1 inch 2 inches

990838B–HIREL–04/07


PC109 [Preliminary]

Table 10-54 provides trace skew of E_RCG[9:0] over RXCLK for the PC109 for a PHY with a minimumClock-to-valid-data-delay of 500 ps on a PCB with a propagation delay of 140 ps/inch.

Table 10-55 provides trace skew of E_RCG[9:0] over RXCLK for the PC109 for a PHY with a minimumClock-to-valid-data-delay of 500 ps on a PCB with a propagation delay of 180 ps/inch.

10.8 Host Local PortHost Local Port (HLP) is application specific. General guidelines in Table 10-56 can be used to assurereliability at higher speed.

Table 10-54. PC109 RCG skew for 500 ps clock-to-valid-data – Example

Signal Group Routing Guideline

Ex_RCG[9:0], RXCLKx

PC109 setup time: 700 ps

Minimum Clock to Valid data delay: 500 ps

Missing Hold time (700 ps -500 ps): 200 ps

Trace skew: 200 ps / (140 ps/inch): 1.43 inchAdd 1.43 inch of trace to each E_RCG[9:0] signals over RXCLK

Table 10-55. PC109 RCG skew for 500 ps clock-to-valid-data – Example

Signal Group Routing Guideline

E0_RCG[9:0], RXCLK0

PC109 setup time: 115 ps

Minimum Clock to Valid data delay: 500 ps

Missing Hold time(115 ps -500 ps): -385 psTrace skew: -385 ps / (180 ps/inch): -2.14 inch

RXCLK should not be longer than any E_RCG[9:0] signal by more than 2.14 inches

Table 10-56. Routing Guidelines for HLP Interface


Reference Plane Layers All signals should be referenced to continuous ground planes.

Breakout Breakout should be less than 0.5in. Layer 1, 3, 6, and 8.

Trace spacingTraces should be 12 mils spaced with 20 mils to other interface traces except for breakout.

Total Trace LengthTotal trace lengths should be matched within 1/2 inch across the bus with a maximum of 4 inches for any signal.

Vias Minimize vias where possible with a maximum of 3 vias.

Layer Types All signals should be routed on the same layer type (stripline) either layer 3, 6.

1000838B–HIREL–04/07


PC109 [Preliminary]

10.9 Power Planes

10.9.1 Decoupling RequirementTable 10-57 provides the minimum PC109 decoupling requirement. These recommendation are for thePC109 only. It does not include board-level bulk and bypass decoupling. It does not include the specificPLL filtering requirement and the Vtt rail requirement. Use low ESR, low lead inductance ceramic capac-itors with X7R or X5R rating.

10.9.2 Decoupling Capacitor PlacementFigure 10-58 shows the PC109 via breakout pattern. The vias are oriented in opposite direction on aquadrant by quadrant basic. This breakout pattern creates channels in the center of the chip. Takeadvantage of the breakout channels to place decoupling capacitors. It is possible to place at least 10decoupling capacitors in the channels. Place the decoupling capacitors close to their corresponding VDD

pins in the channel. Place the remaining decoupling capacitors around the PC109 package near theircorresponding VDD pins.

In addition, keep the trace from the decoupling capacitor pad to the via as short as possible and use atrace width of 20 mils.

Table 10-57. Recommended Decoupling

Rail Decoupling

1.8V SDRAM 20 caps at .001 µF 0402 package

1.8V PB 20 caps at .001 µF 0402 package

3.3V 25 caps at .01 µF 0402 package

1.2V Core Supply 10 caps at .01 µF 0402 package

1010838B–HIREL–04/07


PC109 [Preliminary]

Figure 10-58. PC109 Breakout Vias – Secondary Side View

10.9.3 Power Plane SplittingGiven the number of different voltage supplies required on the PC109, it is likely that a board designerwill be forced to split power planes into several power islands. The PC109 power pin distribution isshown in Figure 10-59.

Figure 10-59. PC109 Power Supply Ballmap

At least two separate power planes are required to provide all the required power supplies to the PC109.The example shows VDD_SD, VDD_PC, and VDD_PB on one split plane.

VDD_SD (1.8V)

VDD_PC (3.3V) VDD_PB (1.8V)

1020838B–HIREL–04/07


PC109 [Preliminary]

11. Ordering Information

Notes: 1. For availability of the different versions, contact your local e2v sales office.

2. The letter X in the part number designates a Prototype product that has not been qualified by e2v. Reliability of a PCX part-number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes.

12. Definitions

12.1 Life Support ApplicationsThese products are not designed for use in life support appliances, devices or systems where malfunc-tion of these products can reasonably be expected to result in personal injury. e2v customers using orselling these products for use in such applications do so at their own risk and agree to fully indemnify e2vfor any damages resulting from such improper use or sale.

13. Document Revision HistoryTable 13-1 provides a revision history for this hardware specification.

M: -55˚C, +125˚C

PCX y xxx nnnn xx109

PartIdentifier

ScreeningLevel

109V: -40˚C, +110˚C

ZF: FC-PBGA 200 MHzU: Upscreening test L

ProductCode(1)

PC(X)(2)

Package(1) MaximumBus Speed

RevisionLevel (1)

TemperatureRange Tj (1)

Table 13-1. Document Revision History

Revision Number Date Substantive Change(s)

B 04/07Name change from Atmel to e2v

Ordering information update

A 09/06 Initial revision

1030838B–HIREL–04/07


PC109 [Preliminary]

Table of Contents

Features .................................................................................................... 1

Description ............................................................................................... 1

Scope ........................................................................................................ 2

Screening ................................................................................................. 2

1 Block Diagram .......................................................................................... 2

2 Features .................................................................................................... 2

2.1 Enhancing System Performance .............................................................................2

2.2 Minimizing System Cost ..........................................................................................2

2.3 Simplifying Design ...................................................................................................3

2.4 Effective Power Management .................................................................................3

2.5 Document Conventions ...........................................................................................3

3 General Parameters ................................................................................. 4

4 Signal Description ................................................................................... 5

5 Detailed Specification ............................................................................. 6

6 Applicable Documents ............................................................................ 6

6.1 Design and Construction .........................................................................................6

6.1.1 Terminal Connections .............................................................................6

6.2 Absolute Maximum Ratings .....................................................................................6

6.3 Recommended Operating Conditions .....................................................................7

6.4 Thermal Characteristics ..........................................................................................7

7 Pin Assignment ........................................................................................ 9

8 Pinout Listings ....................................................................................... 10

9 Electrical Characteristics ...................................................................... 16

9.1 Power Characteristics ...........................................................................................16

9.2 Power Supply Sequencing ....................................................................................17

9.3 DC and Operating Characteristics .........................................................................18

9.4 AC Timing Specifications ......................................................................................20

9.4.1 Clock Generator AC Signal Timing ........................................................20

9.4.2 Processor Interface AC Signal Timing ...................................................21

9.4.3 Memory Controller AC Signal Timing ....................................................24

i0838B–HIREL–04/07


PC109 [Preliminary]

9.4.4 PCI/X Interface AC Signal Timing .........................................................29

9.4.5 Ethernet Controller AC Signal Timing ....................................................30

9.4.6 UART Interface AC Signal Timing .........................................................32

9.4.7 HLP Interface AC Signal Timing ............................................................33

9.4.8 I2C Interface AC Signal Timing ..............................................................36

9.4.9 Interrupt Controller Signal Timing ..........................................................37

9.4.10 Boundary Scan Test Signal Timing ......................................................38

9.4.11 Reset Timing ........................................................................................39

9.5 AC Timing Waveforms ..........................................................................................39

9.6 PBGA Mechanical Diagram ...................................................................................42

9.7 HITCE Mechanical Diagram (TBC) .......................................................................43

10 Board Layout Guidelines ...................................................................... 43

10.1 Printed Circuit Board Construction ......................................................................43

10.1.1 Transmission Line Terms ....................................................................44

10.2 Device Ballmap ...................................................................................................44

10.3 Clocks and PLLs .................................................................................................46

10.3.1 Supply Noise Causes Jitter .................................................................46

10.3.2 Source Clock Lines Termination .........................................................47

10.3.3 Filtering PLL Supplies .........................................................................47

10.4 Processor Bus Layout .........................................................................................47

10.4.1 Topology Description ...........................................................................47

10.4.2 Signal Groups ......................................................................................48

10.4.3.1 Clock Signals ...........................................................................48

10.4.4.2 Unidirectional Point-to-point Signals ........................................48

10.4.5.3 Common 60X/MPX Signals .....................................................48

10.4.6 Clock Signals Topology .......................................................................49

10.4.7 Single Processor Configuration ...........................................................51

10.4.8 Dual-processor Y Configuration ..........................................................52

10.5 Memory Controller ...............................................................................................54

10.5.1 DDR2 Memory Topologies ..................................................................54

10.5.2 SDRAM Clocks ....................................................................................55

10.5.3.1 SDRAM Clock Line Loading ....................................................55

10.5.4.2 Compensation Capacitor and Termination Resistor on DifferentialClocks .......................................................................................55

10.5.5.3 Feedback Clock .......................................................................55

ii0838B–HIREL–04/07


PC109 [Preliminary]

10.5.6 Termination Requirement for Each Memory Configuration .................56

10.5.7.1 Overview of SSTL_18 Termination1 .......................................56

10.5.8.2 DDR2 Stub Termination ..........................................................56

10.5.9.3 Series Resistors ......................................................................57

10.5.10.4 Compensation Capacitors on Address and Command Lines .57

10.5.11.5 On Die Termination .................................................................57

10.5.12 Vtt/Vref Requirements .......................................................................57

10.5.13.1 Vtt Regulator Recommendation .............................................57

10.5.14.2 Vref Requirement ...................................................................58

10.5.15.3 Noise Requirement ................................................................58

10.5.16.4 Vref Decoupling .....................................................................58

10.5.17 Signal grouping .................................................................................59

10.5.18.1 Data Signals ..........................................................................59

10.5.19.2 Clock Signals .........................................................................59

10.5.20.3 Differential Signal Routing Recommendations ......................60

10.5.21.4 Address/Command Signals ...................................................60

10.5.22.5 Control DDR Signals ..............................................................60

10.5.23 Dual DIMM connector Layout ............................................................60

10.5.24.1 Connections ...........................................................................60

10.5.25.2 Component Placement ..........................................................61

10.5.26 Topology Description .........................................................................63

10.5.27.1 Data Signals ..........................................................................63

10.5.28.2 DQS Signal ............................................................................64

10.5.29.3 DQ and DQS Layout Example ...............................................65

10.5.30.4 Clock Signals .........................................................................66

10.5.31.5 Clock Feedback Loop ............................................................68

10.5.32.6 Clock and Feedback Loop Layout Example ..........................68

10.5.33.7 Address and Command Signals ............................................69

10.5.34.8 Control Signals ......................................................................70

10.5.35.9 Address/Command/Control and Termination Plane LayoutExample ..................................................................................72

10.5.36 Single DIMM Layout ..........................................................................73

10.5.37.1 Connections ...........................................................................73

10.5.38.2 Component Placement ..........................................................74

10.5.39.3 Data Signals ..........................................................................75

10.5.40.4 DQS Signal ............................................................................76

iii0838B–HIREL–04/07


PC109 [Preliminary]

10.5.41.5 Clock Signals .........................................................................77



10.5.44.8 Control Signals ......................................................................81

10.5.45 Dual SODIMM Layout .......................................................................82

10.5.46.1 Connections ...........................................................................82

10.5.47.2 Connector Placement ............................................................83

10.5.48.3 Trace Length Summary .........................................................83

10.5.49.4 Topology Description .............................................................84

10.5.50.5 Data (DQ) and Data Strobe (DQS) Signals ...........................84

10.5.51.6 Clock Signals .........................................................................87


10.5.53.8 Layout Examples for Clock Traces ........................................89


10.5.55.10 Layout Examples for Address Lines ......................................92

10.5.56.11 Control Signals ......................................................................93

10.5.57 Single SODIMM Layout .....................................................................94

10.5.58 Soldered-down Devices Layout .........................................................94

10.5.59.1 Soldered-down Devices ..........................................................94

10.5.60.2 Layout Approach .....................................................................95

10.5.61.3 Data Signals ...........................................................................95

10.5.62.4 DQS Signal .............................................................................95

10.5.63.5 Clock Signals ..........................................................................96

10.5.64.6 Clock Feedback Loop .............................................................96

10.5.65.7 Address and Command Signals .............................................96

10.5.66.8 Control Signals .......................................................................97

10.6 PCI-X Interface ....................................................................................................97

10.6.1 PCI-X Loading and Bus Speed ...........................................................97

10.6.2 Routing Guidelines ..............................................................................97

10.7 Ethernet Controller ..............................................................................................98

10.7.1 Hold Time Adjustment on PC109 Receive Inputs ...............................99

10.8 Host Local Port ..................................................................................................100

10.9 Power Planes ....................................................................................................101

10.9.1 Decoupling Requirement ...................................................................101

10.9.2 Decoupling Capacitor Placement ......................................................101

iv0838B–HIREL–04/07


PC109 [Preliminary]

10.9.3 Power Plane Splitting ........................................................................102

11 Ordering Information ........................................................................... 103

12 Definitions ............................................................................................ 103

12.1 Life Support Applications ...................................................................................103

13 Document Revision History ................................................................ 103

Table of Contents ...................................................................................... i

v0838B–HIREL–04/07


Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of anyuse thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its stan-dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa-tion contained herein.

How to reach usHome page: www.e2v.com

Sales Office:

United Kingdom

e2v

106 Waterhouse Lane

Chelmsford

Essex CM1 2QU

Tel: +44 (0)1245 493 493

Fax: +44 (0)1245 492 492

USA

e2v

4 Westchester Plaza

Elmsford

NY 10523-1482

Tel: +1 914 592 6050

Fax: +1 914 592 5148

France

e2v

16 Burospace

F-91 572 Bievres Cedex

Tel: +33 (0) 1 6019 5500

Fax: +33 (0) 1 6019 5529

Asia Pacifiq

e2v

Bank of China Tower

30th floor office 7

1 Garden Rd Central

Hong Kong

Tel: +852 2251 8227/8/9

Fax: +852 2251 8383

Product Contact:

e2v

Avenue de Rochepleine

BP 123 - 38521 Saint-Egrève Cedex

France

Tel: +33 (0)4 76 58 30 00

Hotline:

[email protected]

0838B–HIREL–04/07e2v semiconductors SAS 2007