data sheet sky73134-11: wideband pll frequency synthesizer · 2012-01-26 · external vco or...
TRANSCRIPT
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201199F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 14, 2011 1
DATA SHEET
SKY73134-11: Wideband PLL Frequency Synthesizer Applications
• Cellular base station systems: GSM/EDGE, CDMA2000, WCDMA,
TD-SCDMA, LTE
• Other wireless communication systems
Features
• Continuous frequency coverage: 0.35 to 6.2 GHz
• Integer-N frequency synthesizer
• Low phase noise VCO
• Four integrated VCOs with automatic digital frequency
calibration
• Automatic VCO selection based on the target RF output
• Programmable VCO division by 1, 2, 3, 4, or 8
• VCO divide-by-three with 50% duty cycle
• Integrated input/output RF buffer
• Device provides both divided and direct VCO outputs
• Programmable RF output power levels
• Low RF output comparison spurs
• Programmable 18-bit N-counter and 11-bit R-counter
• Dual modulus 7 GHz prescaler (selectable 16/17 or 32/33)
• Programmable charge pump current
• Flexible configuration allows connection to external VCO or PLL
• Bidirectional read/write three-wire serial to parallel interface
• Digital lock detect
• Digital output used as a loop filter component switch
• Optional adjustment of the core, divider, and charge pump
current by external resistor
• Power supply: 3.3 V
• Small, RFLGA (32-pin, 5 x 5 mm) package (MSL3, 260 °C per
JEDEC J-STD-020)
Skyworks Pb-free products are compliant with
all applicable legislation. For additional
information, refer to Skyworks Definition of Lead (Pb)-Free, document number SQ04-0073.
Description The SKY73134-11 is a wideband integer-N frequency synthesizer
with an approximately 6 GHz locking range.
The device includes four differential Voltage Controlled Oscillators
(VCOs), which cover the output frequency range from 2.8 GHz to
6.2 GHz. By applying internal VCO division by 1, 2, 3, 4, or 8, the
output frequency range can be increased from 0.35 GHz to
6.2 GHz, monitored at the RF output.
The direct, non-divided internal VCO frequency can also be
monitored at the bidirectional VCO pins. The VCO selection can be
automatic based on the target RF output. The flexible
SKY73134-11 configuration allows the loop to be locked by an
external VCO or external Phase Locked Loop (PLL), or the device
can use the divider chain only. The SKY73134-11 is controlled by
a bidirectional read/write serial to parallel interface.
The SKY73134-11 frequency synthesizer is manufactured with a
BiCMOS 0.18 μm SiGe process and provided in a compact,
32-pin RF Land Grid Array (RFLGA). The pin configuration and
package are shown in Figure 1. A functional block diagram is
shown in Figure 2. Signal pin assignments and functional pin
descriptions are provided in Table 1.
S1839
1
2
3
4
5
6
7
8
9
25
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
32 31 30 29 28 27 26
VCC_VCO
VCC_CAP
VCO_RES
OUT_BUFP
OUT_BUFN
VCC_OBUF
DIV_CAP
DIV_RES
VCC_DIV
CLK
DATA
LE
EXT_VCON
EXT_VCOP
PLL_RES
REF_CLK
GND_REF
VCC_REF
VC
TR
L
VCC
_P
LL
VC
O_C
P
CP
_O
UT
LF_C
TR
L
LD_
OU
T
VCC
_D
IG
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Figure 1. SKY73134-11 Pinout – 32-Pin RFLGA (Top View)
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S1838
OutputBuffer
Digital Frequency ControlVCO Calibration
N-Divider
VCOOut
VCOBuffer
PLLBuffer
VCOIn
RefBuffer
÷ 1
VCO1
OUT_BUFP
OUT_BUFN
VC
TR
L
CP
_O
UT
LD_
OU
T
÷ 2
÷ 3
÷ 4
÷ 8
EXT_VCON
CLK
DATA
LE
EXT_VCOP
REF_CLK
VCO2
VCO3
VCO4
Phase Detector
Read/WriteSPI
Charge Pump Lock Detect
R-Divider
Figure 2. SKY73134-11 Block Diagram
Table 1. SKY73134-11 Signal Descriptions
Pin # Name Description Pin # Name Description
1 VCC_VCO Supply for VCO 17 VCC_REF Supply for reference buffer
2 VCC_CAP External capacitor for VCO bias connected
to VCC_VCO pin
18 GND_REF Reference buffer ground
3 VCO_RES External 15 kΩ resistor to set VCO bias 19 REF_CLK Reference clock input
4 OUT_BUFP Positive LO output 20 PLL_RES External 20 kΩ resistor for the PLL/charge
pump bias
5 OUT_BUFN Negative LO output 21 EXT_VCOP Positive, external VCO input
6 VCC_OBUF Supply for output buffer 22 EXT_VCON Negative, external VCO input
7 DIV_CAP External capacitor for the divider bias
connected to the VCC_DIV pin
23 LE Latch enable input for the SPI
8 DIV_RES External 60 kΩ resistor to set the divider
bias
24 DATA Data input for the SPI
9 VCC_DIV Supply for dividers 25 CLK Clock input for the SPI
10 VCTRL VCO tuning voltage 26 N/C No connection
11 VCC_PLL PLL supply 27 N/C No connection
12 VCC_CP Supply for charge pump 28 N/C No connection
13 CP_OUT Charge pump output 29 N/C No connection
14 LF_CTRL Loop filter component switch control 30 N/C No connection
15 LD_OUT Lock detect output 31 N/C No connection
16 VCC_DIG Supply for digital blocks 32 N/C No connection
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Functional Description The SKY73134-11 is comprised of seven main functional blocks:
1. N-divider
2. R-divider
3. Phase detector
4. Charge pump
5. VCO and digital frequency VCO calibration
6. VCO dividers
7. Lock detect
N-Divider
The N-divider consists of a selectable 16/17 or 32/33 prescaler,
13-bit main counter, and 5-bit swallow counter. The 18-bit N-
divider ratio is calculated as:
N = P × M + S
Where: P = Prescaler value
M = Main counter value
S = Swallow counter value
The N-divider range is from P2 to 218. For a 32/33 prescaler, the
N-divider range varies from 1024 to 262144.
R-Divider
The 11-bit programmable R-divider divides the reference input
frequency and generates the reference input for the phase
detector. The R-divider range varies from 1 to 211 (2048).
Phase Detector
The phase detector is an edge-controlled digital circuit. The
circuit has two inputs: the reference signal (Ref) and the N-divider
output. There are two digital outputs (Up and Dn) that drive the
charge pump.
When the input phase difference is positive, the Up output is
pulled up to VDD. When the input phase difference is negative,
the Dn output is pulled down to ground. This type of phase
detector acts only on the positive edges of the input signals.
Charge Pump
The charge pump is used to convert the logic levels of the Up and
Dn pulses, carrying the phase error between the reference and
the divided signal into analog quantities/current pulses.
The output of the SKY73134-11 charge pump is programmable
and varies between 0.9 mA and 5.4 mA. Additional adjustment of
the charge pump current can be accomplished by changing the
value of the external PLL bias resistor.
VCO and Digital Frequency VCO Calibration
The SKY73134-11 incorporates four VCOs. Each VCO covers a
different frequency range between 2.8 and 6.2 GHz.
The VCOs are designed to generate the LO signal with the tuning
function controlled by the synthesizer. Each VCO uses a switch
capacitor array and an analog varactor for digital tuning. The
digital auto-tuning loop provides the proper coarse tuning setting
for the VCO switch capacitors. This sets the oscillation frequency
as close to target as possible before starting fine analog tuning.
When VCO auto-tuning is enabled, the PLL performs a successive
approximation process to digitally tune the VCO close to the final
programmed frequency. Once that is complete, analog tuning is
enabled to lock the VCO to the programmed frequency.
The auto-tuning loop is designed to compensate process variation
so that the VCO fine tuning range can be reduced to cover
temperature variation only. This ensures that the PLL is always
locked.
VCO Dividers
The divider chain consists of dividers and LO drivers. Any VCO can
be divided by 2, 3, 4, or 8, which improves the LO phase noise by
6 dB, 9.5 dB, 12 dB, and 18 dB, respectively.
Using frequency division, the overall VCO range of the device is
widened from 0.35 to 6.2 GHz.
The output RF buffer has a programmable current that provides
variation in the output RF level. The direct non-divided VCO output
can be monitored at the additional bidirectional internal/external
VCO pins. The divider chain and the internal PLL can be locked by
an external VCO.
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Lock Detect
The lock detect circuit is activated when the phase difference
between the Up and Dn phase detector signals for a given number
of comparison cycles is shorter than a fixed delay. The CMOS
output is active high when the loop is locked.
Bidirectional Digital Interface
A three-wire Serial Programmable Interface (SPI) with read/write
capability provides mode and bias control, and control of the PLL.
The serial interface consists of three signals: the bus clock (CLK),
latch enable (LE), and the serial, bidirectional data line (DATA).
Write Mode. A write data stream consists of 25 bits:
Bits[15:0] provide the 16-bit data block.
Bits[20:16] provide the register address.
Bit[21] is the read/write bit (0 = read, 1 = write).
Bits[24:22] provide the device address (the SKY73134-11 is
011b).
Read Mode. The read data stream is almost identical to the write
data stream. Following the 5-bit register address, a “turn around”
cycle is inserted so the baseband can disable its drive of the data
line and the addressed device on the bus can activate its data
output driver.
When the baseband addresses a device connected to the serial
bus, the bus enable signal (LE) goes low half a clock cycle before
the CLK signal becomes active. Data on the DATA line is clocked
into the SKY73134-11 on the rising edge of the clock.
Data from the SKY73134-11 to the baseband is clocked at the
falling edge of the clock. The enable line goes high at the end of
the data transfer.
A timing diagram for the SPI read/write cycle is shown in
Figure 3.
Serial Bus Timing
The SPI bus speed is programmable. Timing requirements for the
CLK, DATA, and LE signals are provided in Table 2. A serial data
input timing diagram is shown in Figure 4.
24 23 22 21 20 19 18 17 16
24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK
DATA
LE
CLK
Write Cycle
Read Cycle
DATA
LE
S2433
Turn-Around
Figure 3. Read/Write SPI Cycles
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Table 2. SPI Timing Requirements
Timing Description Minimum Time (ns)
tperiod Clock period 25
thigh Clock high time 10
tsu Data setup to clock rise 5
thld Data hold from clock rise 5
telch Enable low to clock rise 10
twidth Enable high width 10
tefeh Clock fall to enable high 20
DATA
CLK
tsuLE
S2434
telch
thld
thigh
tcfeh twidth
tperiod
Figure 4. SPI Timing Diagram
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PLL Control Registers (R-Divider and N-Divider)
There are three digital PLL control registers that are used to store
the R-divider and N-divider values: PLL R-Divider, PLL N-Divider
1, and PLL N-Divider 2. By default, all registers are 25 bits wide.
Bit[21] is the read/write bit, cleared when writing to the device.
Bits[20:16] are the address bits of the registers. The 16 least
significant bits (LSBs) represent the data bits.
Three values are needed to calculate the three PLL dividers,
R_DIV, N_DIV1 and N_DIV2: the desired frequency (FRF), the VCO
divider (D), and the frequency step size (FSTEP).
The VCO frequency (FVCO) has a range of 2.8 GHz to 6.2 GHz, and
is defined by the product of the desired frequency (FRF) and the
VCO divider, D:
DFF RFVCO ×=
(1)
The VCO divider (equal to 1, 2, 3, 4, or 8) is chosen so that the
product of FRF × D is within the specified VCO range.
The frequency step size (FSTEP) is a user defined value. Given FSTEP
and D, the comparison frequency (FCOMP) can be calculated by:
DFF STEPCOMP ×=
(2)
The PLL R-Divider register stores the value of the 11-bit R-divider
that produces the desired comparison frequency (FCOMP) for the RF
PLL according to the following equation:
COMP
REF
F
FR = (3)
Where FREF is the reference frequency provided to the device.
The PLL N-Divider 1 and PLL N-Divider 2 registers store the value
of the N-divider according to the following equation:
COMP
VCO
F
FN = (4)
Bits[1:0] of the PLL N-Divider 2 register are the most significant
bits (MSBs) of the 18-bit representation of the N number.
Bits[15:0] of the PLL N-Divider 1 register are the LSBs of the 18-
bit binary representation of the N number.
The calculated R-divider and N-divider values are programmed
into the SKY73134-11 using the SPI interface.
Additional programming information is provided in the document,
Skyworks Wideband Integer-N, Phase-Locked Loop Programming Guide, document number 201322.
Example:
A desired RF output frequency of 2000 MHz is required using a
reference frequency of 38.4 MHz and a desired frequency step
size of 100 kHz. If the VCO divider is equal to 2, the VCO
frequency is 4000 MHz from Equation 1 and the comparison
frequency is equal to 200 kHz from Equation 2.
From Equations 3 and 4, the R and N values become:
R = 192 = 11000000b
N = 20000 = 100111000100000b
These values would be programmed through the SPI interface.
Figure 5 represents the bits of the PLL R-Divider register with the
value of R = 192. Figures 6 and 7 represent the bits of the PLL N-
Divider 1 and PLL N-Divider 2 registers, respectively, with the
value of N = 20000.
Electrical and Mechanical Specifications The absolute maximum ratings of the SKY73134-11 are provided
in Table 3. The recommended operating conditions are specified
in Table 4 and electrical specifications are provided in Tables 5
through 7.
Open-loop VCO phase noise measurements are illustrated in
Figures 8 to 11. Closed-loop VCO phase noise measurements are
illustrated in Figures 12 to 19. An Agilent E5052 signal source
analyzer was used for all phase noise measurements.
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
001 xxx 0x 00 1 01 0 00 00x00 1 1 0 0
16-Bit R-Divider Value3-Bit Device
Address5-Bit Register
Address
1-Bit Read/Write FlagS1847
Note: Value of bits [13:11] can vary. Refer to Skyworks Wideband Integer-N, Phase-Locked Loop Programming Guide, document number 201199.
Figure 5. PLL R-Divider Register Showing an R-Divider Value of 192
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LSBs of 18-BitN-Divider Value
S1849
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
010 010 11 01 0 10 0 00 00000 1 1 0 0
3-Bit DeviceAddress
5-Bit RegisterAddress
1-Bit Read/Write Flag
Figure 6. PLL N-Divider 1 Register Showing an N-Divider Value of 20000 (LSBs)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
110 xxx xx xx x xx x xx 00x00 1 1 0 0
3-Bit DeviceAddress
5-Bit RegisterAddress
1-Bit Read/Write Flag
Note: Value of bits [15:2] can vary. Refer to Skyworks Wideband Integer-N, Phase-Locked Loop Programming Guide, document number 201322.
MSBs of 18-BitN-Divider Value
S1848
Figure 7. PLL N-Divider 2 Register Showing an N-Divider Value of 20000 (MSBs)
Table 3. SKY73134-11 Absolute Maximum Ratings
Parameter Symbol Minimum Maximum Units
Supply voltage (VCC_VCO, VCC_OBUF, VCC_DIV, VCC_PLL, VCC_CP,
VCC_DIG, and VCC_REF pins)
VCC 3.6 V
Supply current ICC 150 mA
Operating case temperature TC –40 +85 °C
Junction temperature TJ +150 °C
Storage case temperature TSTG –40 +125 °C
Notes: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION: Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times. The SKY73134-11 is rated as a Class 1B device using Human Body Model (HBM) testing, Class 2 device using Charged Device Model (CDM) testing, and as a Class A device using Man-Machine (MM) testing.
Table 4. SKY73134-11 Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Units
Supply voltage (VCC_VCO, VCC_OBUF,
VCC_DIV, VCC_PLL, VCC_CP, VCC_DIG, and
VCC_REF pins)
VCC 3.0 3.3 3.6 V
Supply current ICC 120 130 mA
Operating case temperature TC –40 +85 °C
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Table 5. SKY73134-11 Electrical Specifications: Reference Input and Charge Pump (Note 1) (TC = +25 °C, Unless Otherwise Noted)
Parameter Symbol Test Condition Min Typical Max Units
Reference input frequency FREF 10 200 MHz
Reference input sensitivity 200 900 mVp-p
Comparison frequency FCOMP FRF x 103 x
D/218
(Note 2)
FRF x 103 x
D/210
(Note 2)
kHz
Frequency step FSTEP FRF x 103/218 FRF x 103/210 kHz
Charge pump current ICP Step size = 0.6 mA 0.9 2.7 5.4 mA
Output voltage compliance range 0.4 VDD – 0.4 V
Comparison spurs –70 –65 dBc
Locking time 20 kHz bandwidth, 1 ppm
frequency error
1 ms
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Table 6. SKY73134-11 Electrical Specifications: VCO and RF Output Characteristics (Note 1) (TC = +25 °C, Unless Otherwise Noted)
Parameter Symbol Test Condition Min Typical Max Units
RF output frequency FRF 350 6000 MHz
VCO frequency 2.8 6.2 GHz
VCO sensitivity KVCO 12 20 38 MHz/V
VCO pushing 5 10 MHz/V
VCO control voltage VCTRL 0.4 VDD – 0.4 V
RF power –8 +2 +4 dBm
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Table 7. SKY73134-11 Electrical Specifications: Phase Noise Performance (1 of 3) (Note 1) (TC = +25 °C, Unless Otherwise Noted)
Parameter Symbol Test Condition Min Typical Max Units
In-Band Phase Noise, Closed Loop
Normalized in-band phase noise floor with
internal VCO
ICP = 3.6 mA, PLL
bandwidth = 30 kHz
–213 dBc/Hz
In-band phase noise floor divide-by-1 ICP = 3.6 mA, PLL
bandwidth = 30 kHz
–213 + 20 x logN + 10log(FCOMP) dBc/Hz
In-band phase noise floor divide-by-2 ICP = 3.6 mA, PLL
bandwidth = 30 kHz
–219 + 20 x logN + 10log(FCOMP) dBc/Hz
In-band phase noise floor divide-by-3 ICP = 3.6 mA, PLL
bandwidth = 30 kHz
–222 + 20 x logN + 10log(FCOMP) dBc/Hz
In-band phase noise floor divide-by-4 ICP = 3.6 mA, PLL
bandwidth = 30 kHz
–225 + 20 x logN + 10log(FCOMP) dBc/Hz
In-band phase noise floor divide-by-8 ICP = 3.6 mA, PLL
bandwidth = 30 kHz
–231 + 20 x logN + 10log(FCOMP) dBc/Hz
PLL Integrated Phase Noise
Integrated phase noise (1 kHz to 10 MHz) PLL bandwidth = 30 MHz,
RF output = 1 GHz,
FSTEP = 400 kHz
–45 dBc
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Table 7. SKY73134-11 Electrical Specifications: Phase Noise Performance (2 of 3) (Note 1) (TC = +25 °C, Unless Otherwise Noted)
Parameter Symbol Test Condition Min Typical Max Units
Open Loop VCO Phase Noise @ 2.7 GHz
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 3 MHz
@ 10 MHz
–45
–77
–108
–134
–145
–154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Open Loop VCO Phase Noise @ 3.3 GHz
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 3 MHz
@ 10 MHz
–44
–76
–106
–132
–143
–152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Open Loop VCO Phase Noise @ 4.0 GHz
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 3 MHz
@ 10 MHz
–42
–75
–105
–131
–142
–152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Open Loop VCO Phase Noise @ 5.0 GHz
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 3 MHz
@ 10 MHz
–41
–73
–104
–131
–142
–150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
VCO Divided by 2
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
VCO – 6
VCO – 6
VCO – 6
VCO – 6
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
VCO Divided by 3
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
VCO – 9.5
VCO – 9.5
VCO – 9.5
VCO – 9.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
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Table 7. SKY73134-11 Electrical Specifications: Phase Noise Performance (3 of 3) (Note 1) (TC = +25 °C, Unless Otherwise Noted)
Parameter Symbol Test Condition Min Typical Max Units
VCO Divided by 4
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
VCO – 12
VCO – 12
VCO – 12
VCO – 12
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
VCO Divided by 8
Phase noise:
@ 1 kHz
@ 10 kHz
@ 100 kHz
VCO – 18
VCO – 18
VCO – 18
dBc/Hz
dBc/Hz
dBc/Hz
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Open-Loop Phase Noise Measurements
Figure 8. Open-Loop VCO Phase Noise @ 2.7 GHz
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Figure 9. Open-Loop VCO Phase Noise @ 3.3 GHz
Figure 10. Open-Loop VCO Phase Noise @ 4.0 GHz
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Figure 11. Open-Loop VCO Phase Noise @ 5.0 GHz
Closed-Loop Phase Noise Measurements Closed-loop phase noise is measured with a 76.8 MHz external
reference clock. The values of the loop filter components for
Figures 12 to 15 are shown on the schematic diagram in
Figure 22: C33 = 2.2 nF, C32 = C34 = 100 pF, R15 = 2.2 kΩ,
and R18 = 10 kΩ. For Figures 16 to 19, the loop filter components are:
C33 = 4.4 nF, C32 = C34 = 200 pF, R15 = 1.1 kΩ, and
R18 = 5 kΩ. The following parameters characterize the phase
noise measurements:
RFOUT = measured output frequency
FSTEP = the frequency step (channel spacing)
VCO_Div = the VCO frequency divider
FCOMP = the comparison (phase detector) frequency
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Figure 12. Closed-Loop Phase Noise Performance For RFOUT = 900 MHz (FSTEP = 400 kHz, VCO_Div = 4, FCOMP = 1.6 MHz)
Figure 13. Closed-Loop Phase Noise Performance For RFOUT = 1.3 GHz (FSTEP = 400 kHz, VCO_Div = 4, FCOMP = 1.6 MHz)
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
14 December 14, 2011 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201199F
Figure 14. Closed-Loop Phase Noise Performance For RFOUT = 1.8 GHz (FSTEP = 400 kHz, VCO_Div = 3, FCOMP = 1.2 MHz)
Figure 15. Closed-Loop Phase Noise Performance For RFOUT = 2.2 GHz (FSTEP = 800 kHz, VCO_Div = 2, FCOMP = 1.6 MHz)
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
201199F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 14, 2011 15
Figure 16. Closed-Loop Phase Noise Performance For RFOUT = 2.8 GHz (FSTEP = 1600 kHz, VCO_Div = 1, FCOMP = 1.6 MHz)
Figure 17. Closed-Loop Phase Noise Performance For RFOUT = 4.2 GHz (FSTEP = 1600 kHz, VCO_Div = 1, FCOMP = 1.6 MHz)
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
16 December 14, 2011 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201199F
Figure 18. Closed-Loop Phase Noise Performance For RFOUT = 5.2 GHz (FSTEP = 1600 kHz, VCO_Div = 1, FCOMP = 1.6 MHz)
Figure 19. Closed-Loop Phase Noise Performance For RFOUT = 6.0 GHz (FSTEP = 1600 kHz, VCO_Div = 1, FCOMP = 1.6 MHz)
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
201199F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 14, 2011 17
Evaluation Board Description The SKY73134-11 Evaluation Board is used to test the
performance of the SKY73134-11 frequency synthesizer. An
assembly drawing for the Evaluation Board is shown in Figure 20
and the layer detail is provided in Figure 21. A schematic diagram
of the SKY73134-11 Evaluation Board is shown in Figure 22.
Circuit Design Configurations
The following design considerations are general in nature and
must be followed regardless of final use or configuration:
1. Paths to ground should be made as short as possible.
2. The ground pad of the SKY73134-11 has special electrical
and thermal grounding requirements. This pad is the main
thermal conduit for heat dissipation. Since the circuit board
acts as the heat sink, it must shunt as much heat as possible
from the device. Therefore, design the connection to the
ground pad to dissipate the maximum wattage produced by
the circuit board.
3. Skyworks recommends including external bypass capacitors
on the VCC voltage inputs of the device.
Package Dimensions The PCB layout footprint for the SKY73134-11 is provided in
Figure 23. Figure 24 shows the package dimensions for the
25-pin RFLGA and Figure 25 provides the tape and reel
dimensions.
Package and Handling Information Since the device package is sensitive to moisture absorption, it is
baked and vacuum packed before shipping. Instructions on the
shipping container label regarding exposure to moisture after the
container seal is broken must be followed. Otherwise, problems
related to moisture absorption may occur when the part is
subjected to high temperature during solder assembly.
THE SKY73134-11 is rated to Moisture Sensitivity Level 3 (MSL3)
at 260 °C. It can be used for lead or lead-free soldering. For
additional information, refer to the Skyworks Application Note,
PCB Design & SMT Assembly/Rework Guidelines for RFLGA Packages, document number 103147.
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format.
S1851
Figure 20. SKY73134-11 Evaluation Board Assembly Diagram
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
18 December 14, 2011 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201199F
Layer 1: Top – Metal
Layer 2: Ground
Layer 3: Power Plane
Layer 4: Solid Ground Plane
S1852
Figure 21. SKY73134-11 Evaluation Board Layer Detail
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
201199F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 14, 2011 19
VCC =
2.8
V
VCC =
5 V
LD, 5
V
LD
VCC TC
XO
VC
O 3
.3 V
VCC
Supply
50
Ω t
race
50
Ω t
race
50
Ω t
race
50
Ω t
race
50
Ω t
race
20
0 Ω
diffe
rential
tra
ces
10
0 Ω
diffe
rential
tra
ces
R5
5 is
mar
ked as
L20
on la
yout
VCC
_VC
O1
1
2 3 4 5 6 7 8 9
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
11
10
12
13
14
15
16
VC
O_C
AP
VC
O_
RES
OU
T_
BU
FP
3.3
V VCC
VTu
ne
VC
O T
unin
g V
olta
ge
OU
T_
BU
FN
VCC
_O
BU
F
DIV
_C
AP
DIV
_R
ES
VCC
_D
IV
VCTRL
VCC_PLL
VCC_CP
LF_CTRL
LD_OUT
CP_OUT
VCC_DIG
CLK
DAT
A LE
EX
T_
VC
ON
EX
T_
VC
OP
PLL
_R
ES
REF_C
LK
GN
D_
REF
VCC
_R
EF
N/C
N/C
N/C
N/C
N/C
N/C
N/C
J1
4 H
EA
DER1 2 3 4
KT3
22
25
P3
84
00
DC
V2
8P
N0
OU
T3
VC
ON
1VCC
4
GN
D2
NC
7S
Z0
8P
5X B A
2 1
Y4
VCC
5
GN
D3
JTI_
Bal
un-5
50
0B
L15
U0
10
0
GN
D2
2
UN
BA
L1
BA
L–6
BA
L+4
GN
D5
5
GN
D3
3
GN
D2
SU
PP
LY3
OU
TP
UT
4EN
AB
LE6
GN
D5
GN
D8
GN
D7
CO
NTR
OL
1
C7
10
00
pF
L2 10
0 n
H0
80
5 W
W
L11
10
0 n
H0
80
5 W
WL6 DN
I
L15
DN
I
R9
DN
I
C6
33
pF
R8
15
kΩ
1%
06
03
R6
DN
I
C8
DN
ITC
M4
-25
L31
00
pF
L14
10
0 p
F
R7
0 Ω
R5
10
Ω
R1
31
20
kΩ
R1
7D
NI
R1
52
.2 k
Ω
R1
81
0 k
ΩR
19
DN
I
R1
4D
NI
R1
12
0 k
Ω
R2
3D
NI
C1
71
00
0 p
F
C2
33
3 p
F
C2
44
.7 μ
F
R1
21
20
kΩ
R5
20
Ω
J4C
ON
1
1
J8C
ON
1
C5
1 μ
F
+
SEC
CT
2
SEC
1P
RIM
DO
T6
PR
IM4
N/C
5
SEC
DO
T3
MC
74
LCX
12
5D
1Y
32 5
6 8
7
11
2Y
3Y
4Y
1A
2A
3A
4A
10
E
VCC
GND
20
E3
0E
40
E
J5S
MA
1
J3S
MA
1
J6 SM
A
1
C3
DN
IC
21
μF
C1
1 μ
F
C4
DN
I
TC
XO
Out
C1
2D
NI
C1
4D
NI
L51
00
pF
L41
00
pF
L17
DN
I
C2
13
3 p
FC
22
1 μ
F
C2
01
μF
C26
33
pF
C2
51
00
nF
C3
03
3 p
F
C4
41
μF
C4
51
μF
C32
10
0 p
FC
33
2.2
nF
C3
41
00
pF
C29
1 μ
F
C2
74
.7 μ
F
+
LP29
85
AIM
5-3
.3
VIN
1
GN
D2
ON
/OFF
3
VO
UT
5
BYPASS
4
Lock
Det
ect
Voltage
Reg
ula
tors
Pow
er S
upply
Filt
ers
Lock
Det
ect
Outp
ut
Ser
ial I
/O In
terf
ace
Pull-
Dow
n R
esis
tors
1
J7C
ON
1
L19
Ferr
ite
6 H
EA
DER
J2
1 2 3 4 5 6
L7 DN
IR1
0D
NI
R5
40
Ω
R5
30
Ω
C9
DN
I
C1
3D
NI
C1
1D
NI
C1
0D
NI
R1
10
kΩ
R46
DN
IR
47
DN
I
R49
DN
I
R2
10
kΩ
R3
0 Ω
Ref
eren
ce C
lock
L1 10
0 n
HL8
10
0 n
H
L91
00
nH
R5
DN
I
L10
10
0 n
HL26
10
0 n
H
L13
10
0 p
F
L18
DN
IL16
DN
I
L12
10
0 n
HR
efer
ence
Clo
ck
VC
O VCC
VCC
TC
XO
VC
O VCC
Ext
VC
O VCC
Ext
Latc
h E
nab
le
Data
Clo
ck
DAT
A_
PC
VCC S
upply
+5 V
Supply
CLK
_PC
LE_
PC
DAT
A_
REA
D_
+5V
REA
D_
EN
LD_
+5V
R4
DN
I
Con
trol
Vol
tage
Note
: So
me
com
pone
nt la
bels
may
be
diffe
rent
than
the
co
rresp
ondi
ng c
ompo
nent
sym
bol s
how
n he
re.
Co
mpo
nent
val
ues,
how
ever
, are
acc
urat
e as
of t
he
date
of t
his
Data
She
et.
Co
mpo
nent
R8
is a
pos
itive
Tem
pera
ture
Coe
ffici
ent
of
Res
ista
nce
(TCR
) the
rmis
tor r
ated
at 1
500
ppm
/°C.
×
××
××
××
×
×
C1
81
μF
C1
51
μF
C2
83
3 p
F
C19
33
pF
C3
51
μF
C16
33
pF
C3
14
.7 μ
F
+
C36
4.7
μF
C3
71
00
0 p
F
+
R5
51
.1 k
Ω
VC
O, 3
.3 V
DAT
A
CLK
Q1
Q2
PLL
, 3.3
V
VCC VC
O
VCC D
iv
C4
31
μF
C5
11
μF
C4
21
μF
C39
0.1
μF
C3
81
μF
C5
01
μF
R3
10
Ω R3
5D
NI
R3
21
Ω
R36
10
kΩ
R2
20
Ω
R2
5D
NI
R3
81
0 k
ΩR
40
1 Ω
VCC P
LLC
56
1 μ
FC
55
1 μ
F
R4
21
Ω
VCC C
P
C6
01
μF
C6
11
μF
R4
31
Ω
VCC D
ig
C6
51
μF
C6
41
μF
R4
51
Ω
VCC R
efC6
71
μF
C66
1 μ
F
R4
81
Ω
VCC 0
Buf, 3
.3 V
C69
1 μ
FC6
81
μF
R5
01
Ω
VCC =
2.8
VVCC2
p 8
V
VCC2
p 8
V
VCC2
p 8
V
VCC2
p 8
V
Data
Rea
d, 5
V
LE, PC
VCC =
5 V
C4
81
μF
C49
1 μ
F
L22
0 n
H
VCC =
2.8
VVCC VC
O E
xtC
52
1 μ
FC
53
1 μ
F
L23
0 n
H
+5
V S
upply
VCC +
5 V
C6
21
μF
C6
31
μF
L25
0 n
H
PLL
3.3
V
VCC
Supply
R3
7D
NI
LP29
85
AIM
5-3
.3
VIN
1
GN
D2
ON
/OFF
3
VO
UT
5
BYPASS
4L2
1Fe
rrite
C4
11
μF
C4
04
.7 μ
F
+
C46
4.7
μF
C4
71
00
0 p
F
+
VCC
2.8
V
+5 V
Supply
R4
4D
NI
LP29
85
AIM
5-3
.3
VIN
1
GN
D2
ON
/OFF
3
VO
UT
5
BYPASS
4L2
4Fe
rrite
C5
71
μF
C5
44
.7 μ
F
+
C5
84
.7 μ
FC
59
10
00
pF
+
S201
6
LE
DAT
A
CLK LE
R39
10
kΩ
R2
02
kΩ
R2
40
Ω
R2
10
Ω
DAT
A, PC
DAT
A
Rea
d E
nab
le
R29
0 Ω
R2
7D
NI
R3
0D
NI
R16
2 k
Ω
R26
2 k
Ω
R2
82
kΩ
Rea
d E
nab
le
R4
11
0 k
Ω
9 12 1 4 10
13
14
CLK
, PC
R3
30
Ω
R3
4D
NI
Figure 22. SKY73134-11 Evaluation Board Schematic
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
20 December 14, 2011 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201199F
S2748All dimensions are in millimeters
5.34
5.34
32X 0.57
Pin 1
Pin 32
32X 0.30
0.5 Typ.
Package Outline
0.5 Typ.
31X 0.57
31X 0.30
0.6 Pitch
32X 0.67
32X 0.40
0.6 Pitch
0.25 Typ.
5.34
0.5 Typ.
5.34
5.44
5.44
ø1.41 mm stencil aperture,50% of center pad opening.
Pin 1 Indicator(ø0.15)
ø2
Stencil ApertureTop View
MetallizationTop View
Solder Mask OpeningTop View
Package Outline
Package Outline
Pin 1
Pin 32
Pin 1
Pin 32
Thermal via array Ø0.3 mm on0.6 mm pitch will improve
thermal performance.NOTE: thermal vias should be tented
and filled with solder mask, 30-35 μmCu plating recommended.
Figure 23. PCB Layout Footprint for the SKY73134-11 5 x 5 mm RFLGA
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
201199F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 14, 2011 21
S2747
5.04 B
C
CBA
A
Pin 1Indicator
5.04
(2X R0.05)
32X SMT Pad
1 ± 0.1
0.38 ± 0.1
(0.37)
0.4 ± 0.05
0.3 ± 0.05
(0.04)Solder Mask to Package Edge
(0.05)Pad to Package Edge
R1.0
0.15
A
Detail ASMT PadScale: 3X
7X This Rotation7X Rotated 180°
9X Rotated 90° CW9X Rotated 90° CCW
Top View Side View Bottom View
0.2 A B C
0.1 A B C
0.1
Pin 1 Indicator(∅0.15)
Pin 32
Pin 1
Solder Mask Opening
All measurements are in millimetersDimensioning and tolerancing according to ASME Y14.5M-1994
20
X 2
.48
18
X 2
.47
16X 2.48
4X
0.5 4X
0.5
4X
1
2.3
5
2.35
0
0
14X 2.47
4X 1.5
4X 1
4X 2
4X 0.5
Figure 24. SKY73134-11 32-Pin RFLGA Package Dimensions
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
22 December 14, 2011 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201199F
S461b
Notes:1. Carrier tape: black conductive polystyrene2. Cover tape material: transparent conductive PSA3. Cover tape size: 9.3 mm width4. ESD surface resistivity is ≤1 x 1010 Ohms/Square according to EIA, JEDIC TNR specification.5. P0/P1 10 pitches cumulative tolerance on tape: ±0.20 mm6. Ao and Bo measurement points are 0.30 mm from bottom pocket.7. All dimensions are in millimeters
A
B
2.00 ± 0.05
∅1.55 ± 0.05
0.30 ± 0.05
5o Max.
5o Max.
5.3
5 (
Bo)
1.75 ± 0.10
∅1.50 Min.
5.5
0 ±
0.0
5
8.00 (P1) 4.00 (P0)
A
B
B
A
1.30 (Ko)
12
.00
± 0
.30
5.35 (Ao)
Pin #1Indicator
Figure 25. SKY73134-11 Tape and Reel Dimensions
DATA SHEET • SKY73134-11 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
201199F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 14, 2011 23
Ordering Information Model Name Manufacturing Part Number Evaluation Board Part Number
SKY73134-11 Frequency Synthesizer SKY73134-11 TW18-D170
Copyright © 2009, 2010, 2011 Skyworks Solutions, Inc. All Rights Reserved.
Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by
Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the
information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to
update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.
No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or
information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks Terms and Conditions
of Sale.
THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A
PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY
DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS
SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION,
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POSSIBILITY OF SUCH DAMAGE.
Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury,
death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any
damages resulting from such improper use or sale.
Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of
products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for
applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of stated published specifications or parameters.
Skyworks, the Skyworks symbol, and “Breakthrough Simplicity” are trademarks or registered trademarks of Skyworks Solutions, Inc., in the United States and other countries. Third-party brands
and names are for identification purposes only, and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com,
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