data logger - ck electronic · this reaches a complete circuit and conclusion of the data logging...

Data Logger by

Carsten KristiansenNapier University

November 2004

Title page

• Author: Carsten Kristiansen.

• Napier No: 04007712.

• Assignment title: Data Logger.

• Education: Electronic and Computer Engineering.

• Module: Engineering Applications SE32101.

• Place of education: Napier University Edinburgh10 Colinton RoadEdinburgh EH10 5DT

• Lecturer: Dr. T.D. Binnie.

• Assignment period: 2. November 2004 - 14. January 2005.

1. AbstractThis report describes how an data logger are designed and simulated. The data logger mustmemorise a analogue signal from an electrical model of an ultrasonic transducer, where the valuesmust be presented visually at a display. These values are be stored when the memory has beentriggered from a digital sequence. The data logger are designed in blocks, where each block aresimulated individually. This reaches a complete circuit and conclusion of the data logging system.

Contents1. Abstract........................................................................................................................................... 42. Introduction.................................................................................................................................... 6

2.1. Analogue source........................................................................................................................62.2. Digital source............................................................................................................................ 7

3. Assignment specifications.............................................................................................................. 83.1. Block diagram........................................................................................................................... 8

4. Amplifier..........................................................................................................................................94.1. Calculations...............................................................................................................................94.2. Simulation of the instrumentation amplifier............................................................................ 114.3. Offset correction..................................................................................................................... 124.4. Offset calculations...................................................................................................................124.5. Simulation of the amplifier...................................................................................................... 13

5. Sequence detector......................................................................................................................... 155.1. State diagram:......................................................................................................................... 155.2. State table:.............................................................................................................................. 155.3. State assignment:.................................................................................................................... 165.4. Next state logic....................................................................................................................... 165.5. Simulation of the sequence detector....................................................................................... 17

6. Counter..........................................................................................................................................186.1. Counter setup:.........................................................................................................................186.2. Simulation of the counter........................................................................................................19

7. A/D converter................................................................................................................................207.1. Simulation of the A/D converter............................................................................................. 20

8. Memory and display.....................................................................................................................218.1. Memory...................................................................................................................................218.2. Display.................................................................................................................................... 218.3. Simulation of the memory and display.................................................................................... 22

9. Schematic of the data logger........................................................................................................239.1. Schematic of the data logger using macros.............................................................................24

10. Conclusion................................................................................................................................... 2511. References....................................................................................................................................26

11.1. Internet..................................................................................................................................2611.2. Literature...............................................................................................................................2611.3. Software tools....................................................................................................................... 26

Data Logger Carsten Kristiansen – Napier No.: 04007712

2. IntroductionThe assignment of the design and simulation of this data logger, are done by designing each block foritself, simulating these individually which in the final stage will lead to a complete data loggingsystem. With the use of the TINA Pro software, the circuits and simulations can be carried out. Thedesign procedure for this is to build each of the circuits, simulate their behaviour and then save themindividually as macros. The electrical models of the Analogue and digital sources that are used forthe assignment are analysed below.

2.1. Analogue sourceThe analogue source is a predefined part of the assignment, which is the electronic model of aultrasonic transducer. The figure 1 below illustrates the schematic symbol of the analogue source.The output is connected to an impedance meter which in the simulation will measure the outputimpedance of the analogue source.

The impedance are in the simulation measured to be 159,69Ω, which should be taken inconsideration when the amplifier circuit are designed, because it can have a great effect on the inputof the amplifier as a load resistance. A good solution for this can be by using an instrumentationamplifier for the analogue signal.

As the simulation result in figure 2 illustrates, the signal from the analogue source has a amplitude of±100μV. After a period of 400μS, the analogue source will generate a square signal with a timeperiod of 400μS. This will give a frequency of 1

400=2,5 kHz.

6 Napier University Edinburgh

Fig. 1: Analogue Source

Analogue SourceVs

U1

Output

+Z ZM1

Fig. 2: Analogue source simulation result

T

Time (s)0.00 500.00u 1.00m 1.50m 2.00m

Vs

-100.00u

100.00u

Carsten Kristiansen – Napier No.: 04007712 Data Logger

2.2. Digital sourceThe digital source has two independent outputs, one that is a serial digital test source (Signal) whichgenerates the sequence 1011. The other output is a clock source (Clock), which generates a clocksignal for the following sequence detector.

Fig. 3: Digital source

Fig. 4: Digital source simulation result

The clock in the digital source as shown in figure 4 generates a square signal with a period of 10μS,

which gives a frequency of 1

10=100kHz. The generation of the signal out, illustrates the serial

sequence 1011.

Napier University Edinburgh 7

Digital Source SignalClock

U1

Signal outClock out

T

Time (s)

0.00 50.00u 100.00u 150.00u 200.00u

Clock out

L

H

Signal out

L

H


3. Assignment specifications

• The first part is to design an analogue amplifier for the transducer signal. The sourcetransducer is non-ideal – it has a finite bandwidth and an internal impedance.

• The signal from the transducer has a peak voltage of ~100µV. The 8-bit analogue-to-digitalconverter to be used for the system has a maximum input voltage level of 1,02V which willproduce the maximum output of 11111111. The transducer signal must be amplified tomatch the input of the analogue to digital converter.

• The transducer signal has to be converted and ´captured´ and stored in a digital memorywhen triggered by a digital source. Specifically, when the serial digital data sequence 1011is received three times from an external source, then the analogue transducer signal will becaptured and stored in a memory. The digital bit rate is 100kHz. The circuit will count thenumber of individual (non-overlapping) sequences up to a value of three. At this value itwill trigger the analogue-to-digital converter and the memory storage.

• Use TINA simulation package to design and simulate a non-ideal mixed signal data loggingcircuit which records a digital representation of the analogue output from an ultrasonictransducer.

3.1. Block diagramFrom the specifications a general block diagram can be presented. The block diagram below in figure5 indicates what the desired options for the assignment are.

Fig. 5: Data Logger block diagram


DigitalSource

Analogue Source

Sequence Detector

Amplifier

CounterCLK CLK

A/DConverter Memory

Display


4. AmplifierFor amplification between the analogue source and the A/D converter, an instrumentation amplifiercircuit are used. This type of amplifier can amplify a very low input voltage to a desired outputvoltage with a low noise level. The figure 6 below, illustrates how the general instrumentationamplifier looks like. Look aside from the component values, which will be calculated. The OP-ampchosen for the circuit is the TL074 from Texas Instruments. This chip consists of 4 single, low noiseOP-amps, which can be supplied with a ± voltage. The supply voltage which will be used for theamplifier is ±12V.

Fig. 6: General instrumentation amplifier circuit

With this circuit, the values of the resistors has to be calculated from some chosen requirements,which is the amplification of the OP-Amp's. In the first part that includes the OP1 and OP2 theamplification are chosen to be high compared to the amplification with OP3. This is desired to usethe excellent qualities of the Common Mode Rejection Ratio (CMRR), that the OP-Amp's canprovide. But first it is needed to calculate how great the amplification between the input/output mustbe.

4.1. CalculationsKnown:• U in=±100V• U out max=1,02V

Total amplification:

Au total=U out max

U in= 1,02

200=5100 V /V

The total amplification are then split up so that the first part which is OP1 and OP2 provides anamplification of 100 V/V, and the second part with OP3 is set to 51 V/V.


V+

V-

V+

V+

V-

V-

-

+ + OP1 TL074

-

+ +OP2 TL074

-

+ +OP3 TL074

R1 1k

R2 1k

R3 1k

R4 1k

R5 1k

R6 1k

R7 1k

Input

Output


Chosen:• R1=100 k• R2=R1• Au1=100V /V• R3=10 k • R6=R3• Au2=51V /V

R7 is calculated:

Au1=1 2⋅R2R7

⇒ R7= 2⋅R2Au1−1

=2⋅100 k100−1

⇒ R7=2,02 k~2 k (E12 value)

Due to tolerance variations of the resistors the value of R7 are changed to 1,8kΩ, and apotentiometer (P1) with a value of 470Ω is inserted in series, so if the circuit where to be buildpractically, it would be possible to adjust the amplification to the precise value that is needed. Thepotentiometer is inserted in a way, so that if the glider should attempt to stop working, theinstrumentation amplifier would still work, but with a difference in the amplification. The adjustablearea of the amplification resistance (R7+P1) will be from 1,8kΩ to 2,27kΩ. The minimum tomaximum relationship of the amplification with the potentiometer inserted are calculated below.

Minimum to maximum amplification of OP1 and OP2:

Au1 min=1 2⋅R2R7P1max

=1 2⋅100 k1,8 k470

~ 88V /V

Au1 max=1 2⋅R2R7P1min

=1 2⋅100 k1,8 k0

~ 111V /V

R3 is calculated:

Au=R4R3

⇒ R4=Au⋅R3=51⋅10 k ⇒ R4=510 k (E24 value)

-And R5 = R4

Voltage output calculations:The output voltage of the instrumentation amplifier, can with the values of the resistors and the inputvoltage from the analogue source now be calculated. The calculated voltages below are the ideal (theresistor R7 and the potentiometer P1 has a total value of 2,02kΩ), the minimum and the maximumoutput voltages with the P1 potentiometer inserted.

U out ideal=U OP1+−U OP2+⋅12⋅R2

R7P1ideal⋅R4

R3=200−0⋅1 2⋅100 k

1,8 k220⋅510 k

10 k=1,0201V

U out min=U OP1+−U OP2+⋅12⋅R2

R7P1max⋅R4

R3=200−0⋅1 2⋅100 k

1,8 k470⋅510 k

10 k=0,9089V

U out max=U OP1+−U OP2+⋅12⋅R2

R7P1min⋅R4

R3=200−0⋅1 2⋅100 k

1,8 k0⋅510 k

10 k=1,1435V



4.2. Simulation of the instrumentation amplifierThe instrumentation amplifier with the calculated values above are simulated with the ideal valueswhere the potentiometer P1 are in its ideal position, which is at 220Ω. The figure 7 below illustratesthe simulation circuit of the instrumentation amplifier, with the analogue source connected to theinput.

Fig. 7: Instrumentation amplifier simulation circuit

Fig. 8: Instrumentation amplifier simulation result

The simulation output of the instrumentation amplifier indicates that the output are phase shifted 180degrees compared to the input as shown in figure 8 above, because of the inverting amplifier OP3.The output voltage derived from the simulation in TINA has a peak to peak value of -507,42mV to538,23mV. The absolute voltage on the output are the two voltages added together which gives avalue of 1,045V.


V+

V-

V+

V+

V-

V-

-

+ + OP1 TL074

-

+ + OP2 TL074

-

+ +OP3 TL074

R1 100k

R2 100k

R3 10k

R4 510k

R5 510k

R6 10k

R7 1,8k

P1 470

Analogue SourceVs

U1

Output

Input

T

Time (s)0.00 500.00u 1.00m 1.50m 2.00m

Input

-200.00u

200.00u

Output

-600.00m

600.00m


4.3. Offset correctionAs illustrated in the figure 8 with the simulation of the instrumentation amplifier the voltage level ofthe output are not as desired from 0V to 1,02V, which can be adjusted to the right level by insertinganother amplifier on the output of the OP3. The amplifier used for this is an inverting amplifier wherethere is used offset voltage on the positive input. There are more advantages of inserting thisamplifier, than the offset correction. The input to output phase shift of the complete amplifier will be0 degrees, and since it is a TL074 that is being used for the circuit, all of the OP-amps in the packagewill be used. If the amplifier where to be build in practical, this would be a preferred choice of use,considering temperature and component variations. The general circuit for the offset correction isillustrated below in figure 9. The values of the resistors will be calculated.

Fig. 9: Offset correction circuit

4.4. Offset calculationsKnown:• U out min=507,42 mV

Chosen:• Au=1V /V

• R8=R9=10 k• R10=1 k

Offset voltage are calculated:

U offset=U out min

Au1=507,42 m

2=253,71 mV


V+

V-

V+

-

+ +OP4 TL074

InputOutput

R8 1k

R9 1k

P2 1k

R10 1k

R11 1k


R11+P2 are calculated:

R11P2=R10⋅ V+U offset

−1=1 k⋅ 12253,71 m

−1=46,298 k

R11 are chosen to be 33kΩ, where the potentiometer P2 then can be calculated to be:P2=R11P2−R11chosen=46,298 k−33 k=13,298 k ~ 15 k (E12 value)

With the potentiometer P2 adjusted to the correct value of 13,298kΩ, the output should be able todeliver an approximate voltage from 0 to 1,02V.

4.5. Simulation of the amplifierThe complete circuit of the amplifier are illustrated in the figure 10 below. The amplifier aresimulated with the analogue source on the input. The potentiometers P1 and P2 are adjusted to thecorrect values as calculated previously to get the best performance of the amplifier.

Fig. 10: Amplifier simulation circuit


V+

V-

V+

V+

V-

V-

V+

V-

V+

-

+ + OP1 TL074

-

+ +OP2 TL074

-

+ +OP3 TL074

R1 100k

R2 100k

R3 10k

R4 510k

R5 510k

R6 10k

Analogue SourceVs

U1 Input

P1 470

R7 1,8k

-

+ +OP4 TL074

R8 10k

R9 10k

R10 1k

Output

P2 15k

R11 33k


Transient analysis of the amplifier:

Fig. 11: Transient simulation result of the amplifier

From the figure 11 above the transient simulation result of the amplifier indicates that the phase shiftbetween the input to output are 0 degrees, and the output voltage levels are as desired. The levelsare measured to be from -30mV to 1,01V. However the following A/D converters analogue inputwill only display levels from 0V to 1,01V digitally on the output.

AC transfer analysis of the amplifier:

Fig. 12: AC transfer simulation result of the amplifier

The AC transfer simulation of the amplifier shows the best working condition of the amplifier infrequency vs. Gain. Note that the best results of the gain can be derived at frequencies between200Hz to 3kHz.


T

Time (s)0.00 500.00u 1.00m 1.50m 2.00m

Input

-100.00u

100.00u

Output

0.00

1.00

T

Frequency (Hz)

10 100 1k 10k 100k

Input

-20.00

0.00

Output

40.00

80.00


5. Sequence detectorWith the digital source at the input, the sequence detector has to detect at the serial digital sequence1011. By using D-type Flip-Flops a circuit for the detector can be designed. The output of the Flip-Flops must be added together which will give a detect signal at the output.

5.1. State diagram:The state diagram can give a good overview at the functions that is desired in the sequence detector.There are 4 bits in the sequence 1011, which are put into the diagram below in figure 13. The A to Dindicates each of the stages of the 4 bits, where E is the output that has to be set to a logical highwhen the sequence 1011 is received.

Fig. 13: Sequence detector state diagram

5.2. State table:From the state diagram the functions of the sequence detector can be derived and written into a statetable as shown below. The table shows the present and next state logic, which are used for the D-type Flip-Flops, where the x+, y+ and z+ are the inputs on the Flip-Flops. Din are the data-input on theFlip-Flops.


State table

Present Din = 0 Din = 1A A BB C BC A DD C EE A B ←Output

Next state x+ y+ z+


5.3. State assignment:To minimize faults in the sequence, there will be used gray code for the present state in the stateassignment table as shown below. To find the next state logic, the common known state table for theD-type Flip-Flop have been used.

5.4. Next state logicBy deriving the next state logic from the state assignment table, it can be written into Karnaughmaps. For each of the 3 outputs there are made a map, where the logical gates for the sequencedetector can be found.

y zDin x 0 0 0 1 1 1 1 0

0 0 0 0 0 00 1 X X X 01 1 X X X 01 0 0 0 0 1

x+ Output

x+=Din⋅x⋅y⋅z

y zDin x 0 0 0 1 1 1 1 0

0 0 0 1 0 10 1 X X X 01 1 X X X 01 0 0 0 1 1

y+ Output

y+=Din⋅x⋅y⋅zDin⋅x⋅yx⋅y⋅z

y zDin x 0 0 0 1 1 1 1 0

0 0 0 1 0 10 1 X X X 01 1 X X X 11 0 1 1 0 0

z+ Output

z+=x⋅y⋅zDin⋅x⋅y⋅zDin⋅x⋅yDin⋅x⋅y⋅z


State assignment

State Din = 0 Din = 1A 000 000 001B 001 011 001C 011 000 010D 010 011 110E 110 000 001 ←Detect

Presentx y z

Next state x+ y+ z+


The expressions for each of the outputs have been tried reducing with boolean algebra, but theresults could not make the use of gates for the circuit be more optimized than the expressionsderived from the Karnaugh map, so the results from the Karnaugh maps are used for the design ofthe circuit.

5.5. Simulation of the sequence detector

Fig. 14: Sequence detector simulation circuitThe sequence detector are simulated with the Digital source on the input to verify the correct outputfunctions. The result of the digital timing analysis are illustrated below.

Fig. 15: Digital timing analysis of the sequence detector


D

C Q

QP

U1 SN7474

D

C Q

QP

U2 SN7474

D

C Q

QP

U3 SN7474

+U4

+ U5

+U6

+ U7

+U8

+ U9

U10 SN7421

U12 SN7411

U13 SN7421U14 SN7404

U16 SN7411

U17 SN7421

U18 SN7411

U19 SN7411

U11 4075

U20 SN7411

U15 4072

U21 SN7421

Digital Source SignalClock

U1 CLKDin

Detect

X Y Z

X Y Z

T

Time (s)0.00 100.00u 200.00u 300.00u

CLK0.00

5.00

Detect0.00

4.00

Din0.00

5.00

X0.00

4.00

Y0.00

4.00

Z0.00

4.00


6. CounterTo read the detected sequence from the sequence detector every time there has been a correctsequence 3 times from the digital source, a counter is needed to trigger the memory. The counterthat is chosen for this job is the SN74190, which is a 4 bit synchronous up/down BCD counter. Theschematic symbol of the counter are shown below with a description of the pin connections.

Pin connections:• CTEN=Count enable control input• D /U=Down/Up control line input• CLK=Clock input• LOAD=Load control line input• A to D=4 bit data input lines• M /m=Maximum/minimumcount output• RCO=Ripple clock output• QA to QD=4bit data output

By examin the datasheet for the SN74190 counter from Texas Instruments, a circuit for the countercan be designed. The counter must count binary up to three from the previous detect signal, on theCLK input. When this is fulfilled, the counter needs to be reset again to zero and keep counting tothree. The counter should at the binary number of three be able to give a logical high trigger signalat the output.

6.1. Counter setup:• CLK :Connected to the clock detect output from the sequence detector.• CTEN : Connected to ground - counter enabled.• D /U : Connected to ground - counter direction up.•

LOAD :Connected to the output on the trigger gate through an inverter - counter resetswhen trigger output is high.

•A to D : Connected to ground - with a low level at the LOAD input, the counter are presetto 0000 on the data output lines.

•QA and QB : Connected to a AND-gate - when the counter reaches the binary number 3, theoutput on the AND-gate will give a trigger signal.


Fig. 16: Counter

CTEND/UCLKLOADABCD

M/mRCO

QAQBQCQD

U22 SN74190


6.2. Simulation of the counterThe counter is in the simulation connected to a 10kHz clock signal to verify its use. In the finalcircuit it is connected as described in the counter setup. The circuit used for the simulation of thecounter are illustrated below in figure 17.

Fig. 17: Counter simulation circuit

Fig. 18: Transient simulation result of the counter

The counter will when running, deliver a trigger signal on every third of the clock ticks at the CLKinput, except the first counting sequence where it will be at the fourth clock tick. This is because thecounter is not reset when it starts counting, which means that when the first clock pulse arrives, thecounter will count from binary zero to three.


CTEND/UCLKLOADABCD

M/mRCO

QAQBQCQD

U22 SN74190

U23 SN7408

U1 SN7404

Output

U2CLK

T

Time (s)0.00 250.00u 500.00u 750.00u 1.00m

CLK

0.00

5.00

Output

0.00

4.00


7. A/D converterTo convert the analogue signal from the amplifier to digital levels that can be used for the memorycircuit, an A/D converter is inserted. The component that is chosen is a standard 8 bit A/D converterfrom TINA. The analogue input must be a voltage level from 0 to 1,02V, which at the outputs woulddeliver a 8 bit digital output from 0000 to FFFF. The reference voltage input on the converter areconnected to ground. To verify the correct operations of the A/D conversion with the signal from theamplifier, a 8 bit digital to analogue converter are used for this purpose.

7.1. Simulation of the A/D converter

Fig. 19: A/D converter simulation circuitThe voltage generator are set to deliver a sinusoidal signal of ±510mV with a offset at 510mV,which will give a voltage level of 0V to 1,02V on the input of the A/D converter, that is similar tothe output from the amplifier.

Fig. 20: Transient simulation result of the A/D converter


A 0

7

U1

0

7

EA

R0Ri

Gnd

U2

Output+

VG1

Input +U3

0 1 2 3 4 5 6 7

T

Time (s)0.00 200.00u 400.00u 600.00u

00.004.00

10.004.00

20.004.00

30.004.00

40.004.00

50.004.00

60.004.00

70.004.00

Input0.002.00

Output0.001.00


8. Memory and displayThe values from the analogue source that is amplified and converted to the 8 bit digital signal, needsto be stored in a memory device, and then displayed visually on a display device. The values from thememory can be viewed at the display by the use of addressing.

8.1. MemoryThe memory chosen for the data logger is a 8 bit static CMOS RAM (SRAM), which is a standardRAM component in TINA. This memory can be addressed from the hex values 00 to FF which givesa total memory allocation of 2048 bytes. To address the memory, the 12 bit binary counter 14040 isinserted in the circuit. The counter will be reset with a high level on the MR pin every time thecounter has reached a decimal value of 2048. In the simulation of the memory and display, the outputfrom the counter are connected to both the address and data input lines on the RAM. The clocksignal used at the input on the counter are similar to the clock output from the digital source. Thesetup description below for the memory is the one used for the simulation.

Memory setup:• CS :Chip select=Connected to ground - chip enabled.•

R /W : Read /Write=Connected to the clock - when a high level the memory reads dataon the data input, when low the memory writes data on the data output lines.

• OD:Output Disable=Connected to ground - memory device enabled.

8.2. DisplayThe display chosen for the data logger is an ascii display. This display has an 8 bit input an candisplay characters from common known ascii table as illustrated in figure 21. The table is only asmall part of the complete ascii table, where the entire table can be found at the Internet address inthe references.

Fig. 21: Part of the ascii table



8.3. Simulation of the memory and display

Fig. 22: Digital step by step analysis of the memory and display

The figure above illustrates a running simulation of the memory and display, where the displayreceives a 8 bit digital signal of 01000010, which as a decimal number is 64. In the ascii table thisnumber represents the character B, which the ascii display also indicates.

Fig. 23: Digital timing analysis of the memory and display


T

Time (s)0.00 250.00u 500.00u 750.00u 1.00m

CLK

DO1

DO2

DO3

DO4

DO5

DO6

DO7

DO8


9. Schematic of the data logger



9.1. Schematic of the data logger using macros



10. ConclusionThe design and simulation assignment of a data logger has been completed with some difficulty in thesimulation part of the complete data logging system. It has been learned that the TINA simulationsoftware surprisingly not where able to simulate the final and complete circuit of the data logger,which was a big disappointment, not to be able to see the final simulation results with the entirecircuit. Different approaches where tried to figure out if it could be possible in some way to get asuccessful simulation result with the final schematic, but without any luck. By reading closely at thehomepage of the TINA software it was found that the desired simulation was not possible.

If the data logger where to be build in practical, the circuits could be reduced even further by the useof a microcontroller. This controller could be a PSoC mixed-signal controller from Cypress, whichwould be able to replace roughly all the circuits that has been designed for the system.

There where some problems when the sequence detector where designed and simulated. It was atfirst tried setting up the present states in the state assignment table with binary code, which in thesimulations didn't work, so instead the Gray code was used and the outcome of the simulations thenwhere as expected.

The assignment of designing the data logger has been a very interesting assignment, cause of theexperiences it has given by the use of the TINA software, and the combination of both analogue anddigital electronic.

________________________________Carsten Kristiansen



11. References

11.1. Internet• Instrumentation amplifiers, www.analog.com• TL074, www.ti.com• Counter SN74190, www.ti.com• ascii table, www.asciitable.com

11.2. Literature• Introduction to electrical engineering, Mulukutla S. Sarma.• Handout notes for Sequential synchronous circuits, Jay Hoy.• Digital Teknik, Leif Møller Andersen.

11.3. Software tools• TINA Pro for Windows, www.designsoft.com


data logger - ck electronic · this reaches a complete circuit and conclusion of the data logging...

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