data flow modelling

8/3/2019 Data Flow Modelling

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DATA FLOW MODELLING


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Concurrent Statements

Concurrent statements are executed at

the same time, independent of the order in

which they appear


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architecture

Begin

A


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Process model for this

Architecture..

Begin

process (B)A


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Three inverting buffersentity INV is

port (A:in bit;B:out bit);end INV;

architecture DELAY of INV is

signal B,C:bit;begin

Z


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A

C

Z

B


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RS Latch

Entity RS_LATCH is

Port (A,B:in bit; Q ,QBAR :inout bit);

End RS_LATCH;

architecture DELTA of RS_LATCH is

begin

QBAR


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S

R

QBAR

Q


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Multiple Drivers

Entity TWO-DR is

port (A,B,C :in bit: Z: out bit);

End TWO-DR;

Architecture MULTI of TWO-Dr is

Begin

Z


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Architecture EXA of EXAMPLE is

begin

Z


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Conditional Signal Assignment

Condition is a boolean expression

Mandatory else path, unless unconditional

assignment

conditions may overlap

priority

Equivalent of if ..., elsif ..., else constructs


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TARGET


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entity CONDITIONAL_ASSIGNMENT is

port (A, B, C, X : in bit_vector (3 downto 0);

Z_CONC : out bit_vector (3 downto 0);

Z_SEQ : out bit_vector (3 downto 0));

end CONDITIONAL_ASSIGNMENT;

architecture EXAMPLE of CONDITIONAL_ASSIGNMENT

isbegin

-- Concurrent version of conditional signal assignment

Z_CONC "1000" elseA;


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-- Equivalent sequential statements

process (A, B, C, X)

beginif (X = "1111") then

Z_SEQ "1000") then

Z_SEQ


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Selected Signal Assignment

with EXPRESSION select

TARGET


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entity SELECTED_ASSIGNMENT is

port (A, B, C, X : in integer range 0 to 15;

Z_CONC : out integer range 0 to 15;Z_SEQ : out integer range 0 to

15);

end SELECTED_ASSIGNMENT;


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architecture EXAMPLE ofSELECTED_ASSIGNMENT is

begin

-- Concurrent version of selected signalassignmentwith X select

Z_CONC


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-- Equivalent sequential statements

process (A, B, C, X)

begin

case X is

when 0 => Z_SEQ Z_SEQ Z_SEQ Z_SEQ


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Copyright 1995- SCRA1999

Methodology

ReinventingElectronic

DesignArchitecture Infrastructure

DARPA Tri-Service

RASSP

Blocks and Guards

l Blocks are concurrent statements and provide amechanism to partition an architecturedescription

m Items declared in declarative region of block are visible

only inside the block, e.g. :q signals, subprograms

l Blocks may be nested to define a hierarchicalpartitioning of the architectural description


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Block label:block (guard expression)

Block header

Block declarationsBegin

concurrent statements

End block;


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Blocks may be used to define apartitioning and a hierarchy within adesign and to group together signal

assignments and other concurrentstatements which may share somecommon locally declared objects.


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Copyright 1995- SCRA1999

Methodology

ReinventingElectronic

DesignArchitecture Infrastructure

DARPA Tri-Service

RASSP

Blocks and Guards

l Unique to blocks is the GUARD construct

mAguardedsignal assignment statement schedules anassignment to the signal driver only if the GUARDexpression is true. If the GUARD is false, the

corresponding signal drivers are disconnectedmExample

ARCHITECTURE guarded_assignments OF n_ _mux IS1BEGINbi: FOR j IN iRANGE GENERATEbj: BLOCK (s(j)= OR s(j)=Z)1

BEGINx


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A conditional GUARD can be included inthe BLOCK declaration. If such a GUARD

expression exists, then any signalassignment statement in the block whichhas the keyword GUARDED willdisconnect the corresponding signal driver

if the GUARD expression evaluates tofalse.

This is one mechanism which can be usedto guarantee that there be only one activedriver on any signal at any one time.

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